Attachment 23987 Details for Bug 20723 – reg_dumper_pre_s3

reg_dumper_pre_s3

reg_dumper_pre_S3 (text/plain), 8.71 KB, created by liuhaien on 2009-03-17 22:29:26 UTC

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Creator: liuhaien

Created: 2009-03-17 22:29:26 UTC

Size: 8.71 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x000f0401 (dual channel asymmetric, XOR randomization: disabled, XOR bit: 11)
>(II):            CHDECMISC: 0x22b97828 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0401 (0x0401)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x01080000 (0x0000)
>(II):               C1DRB0: 0x05040302 (0x0302)
>(II):               C1DRB1: 0x07060504 (0x0504)
>(II):               C1DRB2: 0x09080706 (0x0706)
>(II):               C1DRB3: 0x0b0a0908 (0x0908)
>(II):              C0DRA01: 0x04020108 (0x0108)
>(II):              C0DRA23: 0x00000402 (0x0402)
>(II):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II):           PGETBL_CTL: 0x4ffc0001
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II):              SDVOUDI: 0x000000ff
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc0000300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000000 (power target: off)
>(II):            PP_STATUS: 0x40000000 (off, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00fa09c4
>(II):        PP_OFF_DELAYS: 0x00fa09c4
>(II):           PP_DIVISOR: 0x00270f02
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II):             DSPABASE: 0x00c00000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II):            PIPEASTAT: 0x04040203 (status: SVBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):                 FPA0: 0x00031305 (n = 3, m1 = 19, m2 = 5)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94020000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II):             DSPBBASE: 0x00c00000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00030e09 (n = 3, m1 = 14, m2 = 9)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>(II):             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>(II):              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>(II):             VTOTAL_B: 0x032502ff (768 active, 806 total)
>(II):             VBLANK_B: 0x032502ff (768 start, 806 end)
>(II):              VSYNC_B: 0x03080302 (771 start, 777 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00800080
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x800c0c00
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x0332012d
>(II):            TV_CSC_Y2: 0x07d30104
>(II):             TV_CSC_U: 0x0733052d
>(II):            TV_CSC_U2: 0x05c70300
>(II):             TV_CSC_V: 0x0340030c
>(II):            TV_CSC_V2: 0x06d00300
>(II):         TV_CLR_KNOBS: 0x00606000
>(II):         TV_CLR_LEVEL: 0x010b00e1
>(II):           TV_H_CTL_1: 0x00400359
>(II):           TV_H_CTL_2: 0x80480022
>(II):           TV_H_CTL_3: 0x007c0344
>(II):           TV_V_CTL_1: 0x00f01415
>(II):           TV_V_CTL_2: 0x00060607
>(II):           TV_V_CTL_3: 0x80120001
>(II):           TV_V_CTL_4: 0x000900f0
>(II):           TV_V_CTL_5: 0x000a00f0
>(II):           TV_V_CTL_6: 0x000900f0
>(II):           TV_V_CTL_7: 0x000a00f0
>(II):          TV_SC_CTL_1: 0xc1710088
>(II):          TV_SC_CTL_2: 0x4e2d1dc8
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00360024
>(II):          TV_WIN_SIZE: 0x02640198
>(II):      TV_FILTER_CTL_1: 0x80000d63
>(II):      TV_FILTER_CTL_2: 0x0001e1e2
>(II):      TV_FILTER_CTL_3: 0x0000f0f1
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0xb1403000
>(II):         TV_H_LUMA_59: 0x0000b060
>(II):        TV_H_CHROMA_0: 0xb1403000
>(II):       TV_H_CHROMA_59: 0x0000b060
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II): pipe A dot 107520 n 3 m1 19 m2 5 p1 2 p2 10
>(II): pipe B dot 65000 n 3 m1 14 m2 9 p1 2 p2 14
>(II): DumpRegsEnd

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Attachments on bug 20723: 23986 | 23987

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