Attachment 34279 Details for Bug 27220 – inte_reg_dump with drm-intel-next branch

inte_reg_dump with drm-intel-next branch

intel_reg_dump_drm_intel_next (text/plain), 7.08 KB, created by Jan-Hendrik Zab on 2010-03-21 05:49:03 UTC

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Creator: Jan-Hendrik Zab

Created: 2010-03-21 05:49:03 UTC

Size: 7.08 KB

patch

obsolete

>        CPU_VGACNTRL: 0x80000000 (disabled)
>DIGITAL_PORT_HOTPLUG: 0x00000000
>           RR_HW_CTL: 0x00000000 (low 0, high 0)
>      FDI_PLL_BIOS_0: 0x082b3019
>      FDI_PLL_BIOS_1: 0x00000000
>      FDI_PLL_BIOS_2: 0x00000000
>DISPLAY_PORT_PLL_BIO: 0x0807012b
>DISPLAY_PORT_PLL_BIO: 0x00000000
>DISPLAY_PORT_PLL_BIO: 0x00000000
>    FDI_PLL_FREQ_CTL: 0x00053687
>           PIPEACONF: 0xc0000010 (enabled, active, 8bpc)
>            HTOTAL_A: 0x07b0063f (1600 active, 1969 total)
>            HBLANK_A: 0x07b0063f (1600 start, 1969 end)
>             HSYNC_A: 0x06bf067f (1664 start, 1728 end)
>            VTOTAL_A: 0x03920383 (900 active, 915 total)
>            VBLANK_A: 0x03920383 (900 start, 915 end)
>             VSYNC_A: 0x03890386 (903 start, 906 end)
>        VSYNCSHIFT_A: 0x00000000
>            PIPEASRC: 0x063f0383 (1600, 900)
>       PIPEA_DATA_M1: 0x7e26657d (TU 64, val 0x26657d 2516349)
>       PIPEA_DATA_N1: 0x00800000 (val 0x800000 8388608)
>       PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>       PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>       PIPEA_LINK_M1: 0x0003331f (val 0x3331f 209695)
>       PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
>       PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>       PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>            DSPACNTR: 0xd8004000 (enabled)
>            DSPABASE: 0x00000000
>          DSPASTRIDE: 0x00001900 (100)
>            DSPASURF: 0x08020000
>         DSPATILEOFF: 0x00000000 (0, 0)
>           PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
>            HTOTAL_B: 0x031f027f (640 active, 800 total)
>            HBLANK_B: 0x03170287 (648 start, 792 end)
>             HSYNC_B: 0x02ef028f (656 start, 752 end)
>            VTOTAL_B: 0x020c01df (480 active, 525 total)
>            VBLANK_B: 0x020401e7 (488 start, 517 end)
>             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>        VSYNCSHIFT_B: 0x00000000
>            DSPBCNTR: 0x00000000 (disabled)
>            DSPBBASE: 0x00000000
>          DSPBSTRIDE: 0x00000000 (0)
>            DSPBSURF: 0x00000000
>         DSPBTILEOFF: 0x00000000 (0, 0)
>            PIPEBSRC: 0x027f01df (640, 480)
>       PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>       PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
>       PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>       PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>           PFA_CTL_1: 0x00800000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel (null),chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>           PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>         PFA_WIN_POS: 0x00000000 (0, 0)
>         PFB_WIN_POS: 0x00000000 (0, 0)
>        PFA_WIN_SIZE: 0x00000000 (0, 0)
>        PFB_WIN_SIZE: 0x00000000 (0, 0)
>    PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>     PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>    PCH_DPLL_TMR_CFG: 0x0271186a
>      PCH_SSC4_PARMS: 0x00000000
>  PCH_SSC4_AUX_PARMS: 0x00000000
>          PCH_DPLL_A: 0xc4020002 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>          PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
>            PCH_FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>            PCH_FPA1: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>            PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>            PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>      TRANS_HTOTAL_A: 0x07b0063f (1600 active, 1969 total)
>      TRANS_HBLANK_A: 0x07b0063f (1600 start, 1969 end)
>       TRANS_HSYNC_A: 0x06bf067f (1664 start, 1728 end)
>      TRANS_VTOTAL_A: 0x03920383 (900 active, 915 total)
>      TRANS_VBLANK_A: 0x03920383 (900 start, 915 end)
>       TRANS_VSYNC_A: 0x03890386 (903 start, 906 end)
>      TRANSA_DATA_M1: 0x7e04f182 (TU 64, val 0x4f182 323970)
>      TRANSA_DATA_N1: 0x0004f1a0 (val 0x4f1a0 324000)
>      TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>      TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_M1: 0x0001a5d6 (val 0x1a5d6 107990)
>   TRANSA_DP_LINK_N1: 0x000278d0 (val 0x278d0 162000)
>   TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>      TRANS_HTOTAL_B: 0x031f027f (640 active, 800 total)
>      TRANS_HBLANK_B: 0x03170287 (648 start, 792 end)
>       TRANS_HSYNC_B: 0x02ef028f (656 start, 752 end)
>      TRANS_VTOTAL_B: 0x020c01df (480 active, 525 total)
>      TRANS_VBLANK_B: 0x020401e7 (488 start, 517 end)
>       TRANS_VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>      TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>      TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>      TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>      TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>          TRANSACONF: 0xc0000000 (enable, active)
>          TRANSBCONF: 0x00000000 (disable, inactive)
>         FDI_TXA_CTL: 0xb01c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>         FDI_TXB_CTL: 0x00044000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>         FDI_RXA_CTL: 0xb0182050 (enable, train pattern not train, port width X4, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>         FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>        FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>        FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>     FDI_RXA_TUSIZE1: 0x7e000000
>     FDI_RXA_TUSIZE2: 0x7e000000
>     FDI_RXB_TUSIZE1: 0x7e000000
>     FDI_RXB_TUSIZE2: 0x7e000000
>       FDI_PLL_CTL_1: 0x33505248
>       FDI_PLL_CTL_2: 0x00000000
>         FDI_RXA_IIR: 0x00000000
>         FDI_RXA_IMR: 0x000000ff
>         FDI_RXB_IIR: 0x00000000
>         FDI_RXB_IMR: 0x000000ff
>            PCH_ADPA: 0x00f40018 (disabled, transcoder A, +hsync, +vsync)
>               HDMIB: 0x0000089c
>               HDMIC: 0x0000001c
>               HDMID: 0x0000001c
>            PCH_LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel)
>           PCH_eDP_A: 0x00000018
>            PCH_DP_B: 0x0000001c
>            PCH_DP_C: 0x0000001c
>            PCH_DP_D: 0xb00c001c

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Attachments on bug 27220: 34274 | 34275 | 34276 | 34277 | 34278 | 34279 | 35846 | 35847 | 35888 | 35889 | 35908 | 35909 | 36377 | 37558 | 37559 | 38402

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