Attachment 44345 Details for Bug 35183 – initial minimal patch to fix hangs.

[patch] initial minimal patch to fix hangs.

0001-drm-radeon-try-and-fix-hangs-with-pageflip-g-s-kde.patch (text/plain), 2.29 KB, created by Dave Airlie on 2011-03-11 03:14:56 UTC

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Creator: Dave Airlie

Created: 2011-03-11 03:14:56 UTC

Size: 2.29 KB

patch

obsolete

>From be35a9e5ed3072ae3a6a9cd63659c0ec7b8b5286 Mon Sep 17 00:00:00 2001
>From: Dave Airlie <airlied@redhat.com>
>Date: Fri, 11 Mar 2011 21:17:41 +1000
>Subject: [PATCH] drm/radeon: try and fix hangs with pageflip + g-s/kde.
>
>This is my first attempt at a minimal patch.
>
>Signed-off-by: Dave Airlie <airlied@redhat.com>
>---
> drivers/gpu/drm/radeon/r100.c               |   17 -----------------
> drivers/gpu/drm/radeon/radeon_legacy_crtc.c |    3 ++-
> 2 files changed, 2 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
>index 93fa735..79de991 100644
>--- a/drivers/gpu/drm/radeon/r100.c
>+++ b/drivers/gpu/drm/radeon/r100.c
>@@ -70,23 +70,6 @@ MODULE_FIRMWARE(FIRMWARE_R520);
> 
> void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
> {
>-	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
>-	u32 tmp;
>-
>-	/* make sure flip is at vb rather than hb */
>-	tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
>-	tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
>-	/* make sure pending bit is asserted */
>-	tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
>-	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
>-
>-	/* set pageflip to happen as late as possible in the vblank interval.
>-	 * same field for crtc1/2
>-	 */
>-	tmp = RREG32(RADEON_CRTC_GEN_CNTL);
>-	tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
>-	WREG32(RADEON_CRTC_GEN_CNTL, tmp);
>-
> 	/* enable the pflip int */
> 	radeon_irq_kms_pflip_irq_get(rdev, crtc);
> }
>diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>index 9ae599e..66c9af1 100644
>--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>@@ -443,7 +443,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
> 		       (target_fb->bits_per_pixel * 8));
> 	crtc_pitch |= crtc_pitch << 16;
> 
>-
>+	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
> 	if (tiling_flags & RADEON_TILING_MACRO) {
> 		if (ASIC_IS_R300(rdev))
> 			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
>@@ -502,6 +502,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
> 	gen_cntl_val = RREG32(gen_cntl_reg);
> 	gen_cntl_val &= ~(0xf << 8);
> 	gen_cntl_val |= (format << 8);
>+	gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
> 	WREG32(gen_cntl_reg, gen_cntl_val);
> 
> 	crtc_offset = (u32)base;
>-- 
>1.7.3.2
>

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