Attachment 47868 Details for Bug 31676 – dmesg efi + nouveau drm + video=eDP-1:1366x768e + debug

dmesg efi + nouveau drm + video=eDP-1:1366x768e + debug

dmesg.efi.nouveau (text/plain), 669.90 KB, created by Benoit Gschwind on 2011-06-12 07:35:55 UTC

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Filename:

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Creator: Benoit Gschwind

Created: 2011-06-12 07:35:55 UTC

Size: 669.90 KB

patch

obsolete

>Linux version 2.6.39.1.efi.nouveau (root@gobelin) (gcc version 4.4.5 (Gentoo 4.4.5 p1.2, pie-0.4.5) ) #7 SMP PREEMPT Sun Jun 12 15:32:16 CEST 2011
>Command line: BOOT_IMAGE=(hd0,gpt2)/boot/vmlinuz-2.6.39.1.efi.nouveau drm.debug=0xff video=eDP-1:1366x768e root=/dev/sda2
>BIOS-provided physical RAM map:
> BIOS-e820: 0000000000000000 - 000000000008f000 (usable)
> BIOS-e820: 000000000008f000 - 0000000000090000 (ACPI NVS)
> BIOS-e820: 0000000000090000 - 00000000000a0000 (usable)
> BIOS-e820: 0000000000100000 - 00000000af000000 (usable)
> BIOS-e820: 00000000af000000 - 00000000bf000000 (reserved)
> BIOS-e820: 00000000bf000000 - 00000000bf719000 (usable)
> BIOS-e820: 00000000bf719000 - 00000000bf939000 (ACPI NVS)
> BIOS-e820: 00000000bf939000 - 00000000bf954000 (usable)
> BIOS-e820: 00000000bf954000 - 00000000bf96b000 (ACPI data)
> BIOS-e820: 00000000bf96b000 - 00000000bf96d000 (usable)
> BIOS-e820: 00000000bf96d000 - 00000000bf99b000 (reserved)
> BIOS-e820: 00000000bf99b000 - 00000000bf9b0000 (usable)
> BIOS-e820: 00000000bf9b0000 - 00000000bf9db000 (reserved)
> BIOS-e820: 00000000bf9db000 - 00000000bfef9000 (usable)
> BIOS-e820: 00000000bfef9000 - 00000000bff00000 (reserved)
> BIOS-e820: 00000000d3200000 - 00000000d3201000 (reserved)
> BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved)
> BIOS-e820: 0000000100000000 - 0000000140000000 (usable)
>NX (Execute Disable) protection: active
>EFI v1.10 by Apple
> ACPI=0xbf96a000  ACPI 2.0=0xbf96a014  SMBIOS=0xbf71a000 
>Kernel-defined memdesc doesn't match the one from EFI!
>EFI: mem00: type=7, attr=0xf, range=[0x0000000000000000-0x000000000008f000) (0MB)
>EFI: mem01: type=10, attr=0xf, range=[0x000000000008f000-0x0000000000090000) (0MB)
>EFI: mem02: type=7, attr=0xf, range=[0x0000000000090000-0x00000000000a0000) (0MB)
>EFI: mem03: type=2, attr=0xf, range=[0x0000000000100000-0x00000000003f0000) (2MB)
>EFI: mem04: type=7, attr=0xf, range=[0x00000000003f0000-0x0000000081526000) (2065MB)
>EFI: mem05: type=2, attr=0xf, range=[0x0000000081526000-0x00000000ac921000) (691MB)
>EFI: mem06: type=4, attr=0xf, range=[0x00000000ac921000-0x00000000ac9a1000) (0MB)
>EFI: mem07: type=7, attr=0xf, range=[0x00000000ac9a1000-0x00000000ac9ea000) (0MB)
>EFI: mem08: type=4, attr=0xf, range=[0x00000000ac9ea000-0x00000000aca0a000) (0MB)
>EFI: mem09: type=7, attr=0xf, range=[0x00000000aca0a000-0x00000000aca5e000) (0MB)
>EFI: mem10: type=4, attr=0xf, range=[0x00000000aca5e000-0x00000000aca5f000) (0MB)
>EFI: mem11: type=7, attr=0xf, range=[0x00000000aca5f000-0x00000000aca6c000) (0MB)
>EFI: mem12: type=4, attr=0xf, range=[0x00000000aca6c000-0x00000000aca6d000) (0MB)
>EFI: mem13: type=7, attr=0xf, range=[0x00000000aca6d000-0x00000000aca85000) (0MB)
>EFI: mem14: type=4, attr=0xf, range=[0x00000000aca85000-0x00000000aca8a000) (0MB)
>EFI: mem15: type=7, attr=0xf, range=[0x00000000aca8a000-0x00000000aca8b000) (0MB)
>EFI: mem16: type=4, attr=0xf, range=[0x00000000aca8b000-0x00000000aca8f000) (0MB)
>EFI: mem17: type=7, attr=0xf, range=[0x00000000aca8f000-0x00000000aca91000) (0MB)
>EFI: mem18: type=4, attr=0xf, range=[0x00000000aca91000-0x00000000aca96000) (0MB)
>EFI: mem19: type=7, attr=0xf, range=[0x00000000aca96000-0x00000000aca99000) (0MB)
>EFI: mem20: type=4, attr=0xf, range=[0x00000000aca99000-0x00000000acaaa000) (0MB)
>EFI: mem21: type=7, attr=0xf, range=[0x00000000acaaa000-0x00000000acab0000) (0MB)
>EFI: mem22: type=4, attr=0xf, range=[0x00000000acab0000-0x00000000acab2000) (0MB)
>EFI: mem23: type=7, attr=0xf, range=[0x00000000acab2000-0x00000000acab4000) (0MB)
>EFI: mem24: type=4, attr=0xf, range=[0x00000000acab4000-0x00000000acac6000) (0MB)
>EFI: mem25: type=7, attr=0xf, range=[0x00000000acac6000-0x00000000acaca000) (0MB)
>EFI: mem26: type=4, attr=0xf, range=[0x00000000acaca000-0x00000000acae1000) (0MB)
>EFI: mem27: type=7, attr=0xf, range=[0x00000000acae1000-0x00000000acae2000) (0MB)
>EFI: mem28: type=4, attr=0xf, range=[0x00000000acae2000-0x00000000acae3000) (0MB)
>EFI: mem29: type=7, attr=0xf, range=[0x00000000acae3000-0x00000000acae4000) (0MB)
>EFI: mem30: type=4, attr=0xf, range=[0x00000000acae4000-0x00000000acaea000) (0MB)
>EFI: mem31: type=7, attr=0xf, range=[0x00000000acaea000-0x00000000acaed000) (0MB)
>EFI: mem32: type=4, attr=0xf, range=[0x00000000acaed000-0x00000000acaf1000) (0MB)
>EFI: mem33: type=7, attr=0xf, range=[0x00000000acaf1000-0x00000000acb0f000) (0MB)
>EFI: mem34: type=4, attr=0xf, range=[0x00000000acb0f000-0x00000000acb13000) (0MB)
>EFI: mem35: type=7, attr=0xf, range=[0x00000000acb13000-0x00000000acb14000) (0MB)
>EFI: mem36: type=4, attr=0xf, range=[0x00000000acb14000-0x00000000acb16000) (0MB)
>EFI: mem37: type=7, attr=0xf, range=[0x00000000acb16000-0x00000000acb18000) (0MB)
>EFI: mem38: type=4, attr=0xf, range=[0x00000000acb18000-0x00000000acb1f000) (0MB)
>EFI: mem39: type=7, attr=0xf, range=[0x00000000acb1f000-0x00000000acb20000) (0MB)
>EFI: mem40: type=4, attr=0xf, range=[0x00000000acb20000-0x00000000acb21000) (0MB)
>EFI: mem41: type=7, attr=0xf, range=[0x00000000acb21000-0x00000000acb22000) (0MB)
>EFI: mem42: type=4, attr=0xf, range=[0x00000000acb22000-0x00000000acb44000) (0MB)
>EFI: mem43: type=7, attr=0xf, range=[0x00000000acb44000-0x00000000acb46000) (0MB)
>EFI: mem44: type=4, attr=0xf, range=[0x00000000acb46000-0x00000000acb4c000) (0MB)
>EFI: mem45: type=7, attr=0xf, range=[0x00000000acb4c000-0x00000000acb50000) (0MB)
>EFI: mem46: type=4, attr=0xf, range=[0x00000000acb50000-0x00000000acb51000) (0MB)
>EFI: mem47: type=7, attr=0xf, range=[0x00000000acb51000-0x00000000acb52000) (0MB)
>EFI: mem48: type=4, attr=0xf, range=[0x00000000acb52000-0x00000000acb58000) (0MB)
>EFI: mem49: type=7, attr=0xf, range=[0x00000000acb58000-0x00000000acb59000) (0MB)
>EFI: mem50: type=4, attr=0xf, range=[0x00000000acb59000-0x00000000acb6e000) (0MB)
>EFI: mem51: type=7, attr=0xf, range=[0x00000000acb6e000-0x00000000acb83000) (0MB)
>EFI: mem52: type=4, attr=0xf, range=[0x00000000acb83000-0x00000000acbb2000) (0MB)
>EFI: mem53: type=7, attr=0xf, range=[0x00000000acbb2000-0x00000000acbb6000) (0MB)
>EFI: mem54: type=4, attr=0xf, range=[0x00000000acbb6000-0x00000000acbc3000) (0MB)
>EFI: mem55: type=7, attr=0xf, range=[0x00000000acbc3000-0x00000000acfc4000) (4MB)
>EFI: mem56: type=4, attr=0xf, range=[0x00000000acfc4000-0x00000000acffe000) (0MB)
>EFI: mem57: type=7, attr=0xf, range=[0x00000000acffe000-0x00000000acfff000) (0MB)
>EFI: mem58: type=4, attr=0xf, range=[0x00000000acfff000-0x00000000af000000) (32MB)
>EFI: mem59: type=4, attr=0xf, range=[0x00000000bf000000-0x00000000bf6af000) (6MB)
>EFI: mem60: type=7, attr=0xf, range=[0x00000000bf6af000-0x00000000bf719000) (0MB)
>EFI: mem61: type=10, attr=0xf, range=[0x00000000bf719000-0x00000000bf939000) (2MB)
>EFI: mem62: type=7, attr=0xf, range=[0x00000000bf939000-0x00000000bf954000) (0MB)
>EFI: mem63: type=9, attr=0xf, range=[0x00000000bf954000-0x00000000bf96b000) (0MB)
>EFI: mem64: type=7, attr=0xf, range=[0x00000000bf96b000-0x00000000bf96d000) (0MB)
>EFI: mem65: type=6, attr=0x800000000000000f, range=[0x00000000bf96d000-0x00000000bf99b000) (0MB)
>EFI: mem66: type=7, attr=0xf, range=[0x00000000bf99b000-0x00000000bf9b0000) (0MB)
>EFI: mem67: type=5, attr=0x800000000000000f, range=[0x00000000bf9b0000-0x00000000bf9db000) (0MB)
>EFI: mem68: type=7, attr=0xf, range=[0x00000000bf9db000-0x00000000bfaea000) (1MB)
>EFI: mem69: type=3, attr=0xf, range=[0x00000000bfaea000-0x00000000bfd5f000) (2MB)
>EFI: mem70: type=7, attr=0xf, range=[0x00000000bfd5f000-0x00000000bfe5f000) (1MB)
>EFI: mem71: type=1, attr=0xf, range=[0x00000000bfe5f000-0x00000000bfeef000) (0MB)
>EFI: mem72: type=7, attr=0xf, range=[0x00000000bfeef000-0x00000000bfef3000) (0MB)
>EFI: mem73: type=2, attr=0xf, range=[0x00000000bfef3000-0x00000000bfef9000) (0MB)
>EFI: mem74: type=0, attr=0xf, range=[0x00000000bfef9000-0x00000000bfeff000) (0MB)
>EFI: mem75: type=6, attr=0x800000000000000f, range=[0x00000000bfeff000-0x00000000bff00000) (0MB)
>EFI: mem76: type=7, attr=0xf, range=[0x0000000100000000-0x0000000140000000) (1024MB)
>EFI: mem77: type=0, attr=0x8000000000000000, range=[0x00000000af000000-0x00000000bf000000) (256MB)
>EFI: mem78: type=11, attr=0x8000000000000000, range=[0x00000000d3200000-0x00000000d3201000) (0MB)
>EFI: mem79: type=11, attr=0x8000000000000000, range=[0x00000000ffc00000-0x00000000ffc80000) (0MB)
>EFI: mem80: type=11, attr=0x8000000000000000, range=[0x00000000ffc80000-0x00000000ffca8000) (0MB)
>EFI: mem81: type=11, attr=0x8000000000000000, range=[0x00000000ffca8000-0x00000000ffcca000) (0MB)
>EFI: mem82: type=11, attr=0x8000000000000000, range=[0x00000000ffcca000-0x00000000ffffc000) (3MB)
>EFI: mem83: type=11, attr=0x8000000000000000, range=[0x00000000ffffc000-0x0000000100000000) (0MB)
>DMI 2.4 present.
>DMI: Apple Inc. MacBookAir3,1/Mac-942452F5819B1C1B, BIOS    MBA31.88Z.0061.B01.1011181342 11/18/10
>e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
>e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
>No AGP bridge found
>last_pfn = 0x140000 max_arch_pfn = 0x400000000
>MTRR default type: write-back
>MTRR fixed ranges enabled:
>  00000-9FFFF write-back
>  A0000-FFFFF uncachable
>MTRR variable ranges enabled:
>  0 base 0C0000000 mask FC0000000 uncachable
>  1 base 0BFF00000 mask FFFF00000 uncachable
>  2 disabled
>  3 disabled
>  4 disabled
>  5 disabled
>  6 disabled
>  7 disabled
>x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
>last_pfn = 0xbfef9 max_arch_pfn = 0x400000000
>initial memory mapped : 0 - 20000000
>Base memory trampoline at [ffff88000009a000] 9a000 size 20480
>init_memory_mapping: 0000000000000000-00000000bfef9000
> 0000000000 - 00bfe00000 page 2M
> 00bfe00000 - 00bfef9000 page 4k
>kernel direct mapping tables up to bfef9000 @ bfef4000-bfef9000
>init_memory_mapping: 0000000100000000-0000000140000000
> 0100000000 - 0140000000 page 2M
>kernel direct mapping tables up to 140000000 @ 13fffa000-140000000
>ACPI: RSDP 00000000bf96a014 00024 (v02 APPLE )
>ACPI: XSDT 00000000bf96a1c0 00084 (v01 APPLE   Apple00 00000061      01000013)
>ACPI: FACP 00000000bf968000 000F4 (v04 APPLE   Apple00 00000061 Loki 0000005F)
>ACPI: DSDT 00000000bf95b000 0572C (v01 APPLE  MacBookA 00030001 INTL 20061109)
>ACPI: FACS 00000000bf71e000 00040
>ACPI: HPET 00000000bf967000 00038 (v01 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: APIC 00000000bf966000 00068 (v01 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: APIC 00000000bf965000 00068 (v02 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: ASF! 00000000bf963000 000A5 (v32 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: SBST 00000000bf962000 00030 (v01 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: ECDT 00000000bf961000 00053 (v01 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: SSDT 00000000bf958000 00107 (v01 APPLE  SataAhci 00001000 INTL 20061109)
>ACPI: SSDT 00000000bf957000 00024 (v01 APPLE     Apple 00001000 INTL 20061109)
>ACPI: SSDT 00000000bf955000 0008A (v01 APPLE  NoSDCard 00001000 INTL 20061109)
>ACPI: SSDT 00000000bf954000 004DC (v01  APPLE    CpuPm 00003000 INTL 20061109)
>ACPI: MCFG 00000000bf964000 0003C (v01 APPLE   Apple00 00000001 Loki 0000005F)
>ACPI: BIOS bug: multiple APIC/MADT found, using 0
>ACPI: If "acpi_apic_instance=2" works better, notify linux-acpi@vger.kernel.org
>ACPI: Local APIC address 0xfee00000
>Zone PFN ranges:
>  DMA      0x00000010 -> 0x00001000
>  DMA32    0x00001000 -> 0x00100000
>  Normal   0x00100000 -> 0x00140000
>Movable zone start PFN for each node
>early_node_map[9] active PFN ranges
>    0: 0x00000010 -> 0x0000008f
>    0: 0x00000090 -> 0x000000a0
>    0: 0x00000100 -> 0x000af000
>    0: 0x000bf000 -> 0x000bf719
>    0: 0x000bf939 -> 0x000bf954
>    0: 0x000bf96b -> 0x000bf96d
>    0: 0x000bf99b -> 0x000bf9b0
>    0: 0x000bf9db -> 0x000bfef9
>    0: 0x00100000 -> 0x00140000
>On node 0 totalpages: 982008
>  DMA zone: 56 pages used for memmap
>  DMA zone: 7 pages reserved
>  DMA zone: 3920 pages, LIFO batch:0
>  DMA32 zone: 14280 pages used for memmap
>  DMA32 zone: 701601 pages, LIFO batch:31
>  Normal zone: 3584 pages used for memmap
>  Normal zone: 258560 pages, LIFO batch:31
>ACPI: PM-Timer IO Port: 0x408
>ACPI: Local APIC address 0xfee00000
>ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
>ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
>ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>IOAPIC[0]: apic_id 1, version 17, address 0xfec00000, GSI 0-23
>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>ACPI: IRQ0 used by override.
>ACPI: IRQ2 used by override.
>ACPI: IRQ9 used by override.
>Using ACPI (MADT) for SMP configuration information
>ACPI: HPET id: 0x10de8201 base: 0xfed00000
>SMP: Allowing 2 CPUs, 0 hotplug CPUs
>nr_irqs_gsi: 40
>Allocating PCI resources starting at d3201000 (gap: d3201000:2c9ff000)
>setup_percpu: NR_CPUS:2 nr_cpumask_bits:2 nr_cpu_ids:2 nr_node_ids:1
>PERCPU: Embedded 25 pages/cpu @ffff88013fc00000 s73216 r8192 d20992 u1048576
>pcpu-alloc: s73216 r8192 d20992 u1048576 alloc=1*2097152
>pcpu-alloc: [0] 0 1 
>Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 964081
>Kernel command line: reboot=pci acpi_backlight=vendor BOOT_IMAGE=(hd0,gpt2)/boot/vmlinuz-2.6.39.1.efi.nouveau drm.debug=0xff video=eDP-1:1366x768e root=/dev/sda2
>PID hash table entries: 4096 (order: 3, 32768 bytes)
>Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
>Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
>xsave/xrstor: enabled xstate_bv 0x3, cntxt size 0x240
>Checking aperture...
>No AGP bridge found
>Memory: 3748092k/5242880k available (4537k kernel code, 1314848k absent, 179940k reserved, 1644k data, 416k init)
>SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
>Preemptable hierarchical RCU implementation.
>NR_IRQS:320
>Extended CMOS year: 2000
>Console: colour dummy device 80x25
>console [tty0] enabled
>hpet clockevent registered
>Fast TSC calibration using PIT
>Detected 1596.749 MHz processor.
>Calibrating delay loop (skipped), value calculated using timer frequency.. 3193.49 BogoMIPS (lpj=1596749)
>pid_max: default: 32768 minimum: 301
>Mount-cache hash table entries: 256
>CPU: Physical Processor ID: 0
>CPU: Processor Core ID: 0
>mce: CPU supports 6 MCE banks
>CPU0: Thermal monitoring enabled (TM2)
>using mwait in idle threads.
>ACPI: Core revision 20110316
>Setting APIC routing to flat
>..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>CPU0: Intel(R) Core(TM)2 Duo CPU     U9600  @ 1.60GHz stepping 0a
>Performance Events: PEBS fmt0+, Core2 events, Intel PMU driver.
>... version:                2
>... bit width:              40
>... generic registers:      2
>... value mask:             000000ffffffffff
>... max period:             000000007fffffff
>... fixed-purpose events:   3
>... event mask:             0000000700000003
>Booting Node   0, Processors  #1 Ok.
>smpboot cpu 1: start_ip = 9a000
>Brought up 2 CPUs
>Total of 2 processors activated (6386.87 BogoMIPS).
>NET: Registered protocol family 16
>ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>ACPI: bus type pci registered
>PCI: MMCONFIG for domain 0000 [bus 00-02] at [mem 0xf0000000-0xf02fffff] (base 0xf0000000)
>PCI: not using MMCONFIG
>PCI: Using configuration type 1 for base access
>bio: create slab <bio-0> at 0
>ACPI: EC: EC description table is found, configuring boot EC
>[Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
>ACPI: SSDT 00000000bf71dc98 0023D (v01  APPLE  Cpu0Ist 00003000 INTL 20061109)
>ACPI: Dynamic OEM Table Load:
>ACPI: SSDT           (null) 0023D (v01  APPLE  Cpu0Ist 00003000 INTL 20061109)
>ACPI: SSDT 00000000bf71c618 005A6 (v01  APPLE  Cpu0Cst 00003001 INTL 20061109)
>ACPI: Dynamic OEM Table Load:
>ACPI: SSDT           (null) 005A6 (v01  APPLE  Cpu0Cst 00003001 INTL 20061109)
>ACPI: SSDT 00000000bf71df18 000C8 (v01  APPLE  Cpu1Ist 00003000 INTL 20061109)
>ACPI: Dynamic OEM Table Load:
>ACPI: SSDT           (null) 000C8 (v01  APPLE  Cpu1Ist 00003000 INTL 20061109)
>ACPI: SSDT 00000000bf71bf18 00085 (v01  APPLE  Cpu1Cst 00003000 INTL 20061109)
>ACPI: Dynamic OEM Table Load:
>ACPI: SSDT           (null) 00085 (v01  APPLE  Cpu1Cst 00003000 INTL 20061109)
>ACPI: Interpreter enabled
>ACPI: (supports S0 S3 S5)
>ACPI: Using IOAPIC for interrupt routing
>PCI: MMCONFIG for domain 0000 [bus 00-02] at [mem 0xf0000000-0xf02fffff] (base 0xf0000000)
>PCI: MMCONFIG at [mem 0xf0000000-0xf02fffff] reserved in ACPI motherboard resources
>ACPI: EC: GPE = 0x57, I/O: command/status = 0x66, data = 0x62
>PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
>pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000c0000-0x000c3fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000c4000-0x000c7fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000c8000-0x000cbfff]
>pci_root PNP0A08:00: host bridge window [mem 0x000cc000-0x000cffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
>pci_root PNP0A08:00: host bridge window [mem 0x000dc000-0x000dffff]
>pci_root PNP0A08:00: host bridge window [mem 0x000e0000-0x000e3fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000e4000-0x000e7fff]
>pci_root PNP0A08:00: host bridge window [mem 0x000e8000-0x000ebfff]
>pci_root PNP0A08:00: host bridge window [mem 0x000ec000-0x000effff]
>pci_root PNP0A08:00: host bridge window [mem 0x000f0000-0x000fffff]
>pci_root PNP0A08:00: host bridge window [mem 0xc0000000-0xfebfffff]
>pci 0000:00:00.0: [10de:0d60] type 0 class 0x000600
>pci 0000:00:00.1: [10de:0d68] type 0 class 0x000500
>pci 0000:00:01.0: [10de:0d6d] type 0 class 0x000500
>pci 0000:00:01.1: [10de:0d6e] type 0 class 0x000500
>pci 0000:00:01.2: [10de:0d6f] type 0 class 0x000500
>pci 0000:00:01.3: [10de:0d70] type 0 class 0x000500
>pci 0000:00:02.0: [10de:0d71] type 0 class 0x000500
>pci 0000:00:02.1: [10de:0d72] type 0 class 0x000500
>pci 0000:00:03.0: [10de:0d80] type 0 class 0x000601
>pci 0000:00:03.0: reg 10: [io  0x2100-0x21ff]
>pci 0000:00:03.1: [10de:0d7b] type 0 class 0x000500
>pci 0000:00:03.2: [10de:0d79] type 0 class 0x000c05
>pci 0000:00:03.2: reg 10: [io  0x2000-0x20ff]
>pci 0000:00:03.2: reg 14: [mem 0xd3286000-0xd3287fff]
>pci 0000:00:03.2: reg 20: [io  0x2240-0x227f]
>pci 0000:00:03.2: reg 24: [io  0x2200-0x223f]
>pci 0000:00:03.2: PME# supported from D3hot D3cold
>pci 0000:00:03.2: PME# disabled
>pci 0000:00:03.3: [10de:0d69] type 0 class 0x000500
>pci 0000:00:03.4: [10de:0d7a] type 0 class 0x000b40
>pci 0000:00:03.4: reg 10: [mem 0xd3200000-0xd327ffff]
>pci 0000:00:04.0: [10de:0d9c] type 0 class 0x000c03
>pci 0000:00:04.0: reg 10: [mem 0xd328a000-0xd328afff]
>pci 0000:00:04.0: supports D1 D2
>pci 0000:00:04.0: PME# supported from D0 D1 D2 D3hot D3cold
>pci 0000:00:04.0: PME# disabled
>pci 0000:00:04.1: [10de:0d9d] type 0 class 0x000c03
>pci 0000:00:04.1: reg 10: [mem 0xd328b100-0xd328b1ff]
>pci 0000:00:04.1: supports D1 D2
>pci 0000:00:04.1: PME# supported from D0 D1 D2 D3hot D3cold
>pci 0000:00:04.1: PME# disabled
>pci 0000:00:06.0: [10de:0d9c] type 0 class 0x000c03
>pci 0000:00:06.0: reg 10: [mem 0xd3289000-0xd3289fff]
>pci 0000:00:06.0: supports D1 D2
>pci 0000:00:06.0: PME# supported from D0 D1 D2 D3hot D3cold
>pci 0000:00:06.0: PME# disabled
>pci 0000:00:06.1: [10de:0d9d] type 0 class 0x000c03
>pci 0000:00:06.1: reg 10: [mem 0xd328b000-0xd328b0ff]
>pci 0000:00:06.1: supports D1 D2
>pci 0000:00:06.1: PME# supported from D0 D1 D2 D3hot D3cold
>pci 0000:00:06.1: PME# disabled
>pci 0000:00:08.0: [10de:0d94] type 0 class 0x000403
>pci 0000:00:08.0: reg 10: [mem 0xd3280000-0xd3283fff]
>pci 0000:00:08.0: PME# supported from D3hot D3cold
>pci 0000:00:08.0: PME# disabled
>pci 0000:00:0a.0: [10de:0d88] type 0 class 0x000106
>pci 0000:00:0a.0: reg 10: [io  0x2298-0x229f]
>pci 0000:00:0a.0: reg 14: [io  0x22a4-0x22a7]
>pci 0000:00:0a.0: reg 18: [io  0x2290-0x2297]
>pci 0000:00:0a.0: reg 1c: [io  0x22a0-0x22a3]
>pci 0000:00:0a.0: reg 20: [io  0x2280-0x228f]
>pci 0000:00:0a.0: reg 24: [mem 0xd3284000-0xd3285fff]
>pci 0000:00:0b.0: [10de:0d75] type 0 class 0x000500
>pci 0000:00:0b.0: reg 10: [mem 0xd3288000-0xd3288fff]
>pci 0000:00:15.0: [10de:0d9b] type 1 class 0x000604
>pci 0000:00:15.0: PME# supported from D0 D1 D2 D3hot D3cold
>pci 0000:00:15.0: PME# disabled
>pci 0000:00:17.0: [10de:0d76] type 1 class 0x000604
>pci 0000:00:17.0: PME# supported from D0 D3hot D3cold
>pci 0000:00:17.0: PME# disabled
>pci 0000:01:00.0: [14e4:4353] type 0 class 0x000280
>pci 0000:01:00.0: reg 10: [mem 0xd3100000-0xd3103fff 64bit]
>pci 0000:01:00.0: supports D1 D2
>pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
>pci 0000:01:00.0: PME# disabled
>pci 0000:00:15.0: PCI bridge to [bus 01-01]
>pci 0000:00:15.0:   bridge window [io  0xfffffffffffff000-0x0000] (disabled)
>pci 0000:00:15.0:   bridge window [mem 0xd3100000-0xd31fffff]
>pci 0000:00:15.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>pci 0000:02:00.0: [10de:08a2] type 0 class 0x000300
>pci 0000:02:00.0: reg 10: [mem 0xd2000000-0xd2ffffff]
>pci 0000:02:00.0: reg 14: [mem 0xc0000000-0xcfffffff 64bit pref]
>pci 0000:02:00.0: reg 1c: [mem 0xd0000000-0xd1ffffff 64bit pref]
>pci 0000:02:00.0: reg 24: [io  0x1000-0x107f]
>pci 0000:02:00.0: reg 30: [mem 0xd3000000-0xd301ffff pref]
>pci 0000:00:17.0: PCI bridge to [bus 02-02]
>pci 0000:00:17.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:00:17.0:   bridge window [mem 0xd2000000-0xd30fffff]
>pci 0000:00:17.0:   bridge window [mem 0xc0000000-0xd1ffffff 64bit pref]
>pci_bus 0000:00: on NUMA node 0
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.IXVE._PRT]
> pci0000:00: Requesting ACPI _OSC control (0x1d)
> pci0000:00: ACPI _OSC control (0x1d) granted
>ACPI: PCI Interrupt Link [LNK1] (IRQs *16 17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LNK2] (IRQs 16 *17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LNK3] (IRQs 16 17 *18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LNK4] (IRQs 16 17 18 *19 20 21 22 23)
>ACPI: PCI Interrupt Link [Z00J] (IRQs 16 17 18 19 20 *21 22 23)
>ACPI: PCI Interrupt Link [Z00K] (IRQs 16 17 18 19 20 *21 22 23)
>ACPI: PCI Interrupt Link [Z00L] (IRQs 16 17 18 19 20 *21 22 23)
>ACPI: PCI Interrupt Link [Z00M] (IRQs 16 17 18 19 20 *21 22 23)
>ACPI: PCI Interrupt Link [LSMB] (IRQs 16 17 18 19 20 21 *22 23)
>ACPI: PCI Interrupt Link [LUS0] (IRQs 16 *17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LUS2] (IRQs 16 *17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LMAC] (IRQs 16 *17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LAZA] (IRQs 16 17 18 19 *20 21 22 23)
>ACPI: PCI Interrupt Link [LGPU] (IRQs *16 17 18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [LPID] (IRQs 16 17 18 19 20 21 22 23) *0, disabled.
>ACPI: PCI Interrupt Link [LSI0] (IRQs 16 17 *18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [Z000] (IRQs 16 17 *18 19 20 21 22 23)
>ACPI: PCI Interrupt Link [Z001] (IRQs 16 17 18 19 20 21 *22 23)
>ACPI: PCI Interrupt Link [LPMU] (IRQs 16 17 18 19 20 21 22 23) *0, disabled.
>vgaarb: device added: PCI:0000:02:00.0,decodes=io+mem,owns=none,locks=none
>vgaarb: loaded
>SCSI subsystem initialized
>libata version 3.00 loaded.
>usbcore: registered new interface driver usbfs
>usbcore: registered new interface driver hub
>usbcore: registered new device driver usb
>PCI: Using ACPI for IRQ routing
>PCI: pci_cache_line_size set to 64 bytes
>reserve RAM buffer: 000000000008f000 - 000000000008ffff 
>reserve RAM buffer: 00000000af000000 - 00000000afffffff 
>reserve RAM buffer: 00000000bf719000 - 00000000bfffffff 
>reserve RAM buffer: 00000000bf954000 - 00000000bfffffff 
>reserve RAM buffer: 00000000bf96d000 - 00000000bfffffff 
>reserve RAM buffer: 00000000bf9b0000 - 00000000bfffffff 
>reserve RAM buffer: 00000000bfef9000 - 00000000bfffffff 
>Bluetooth: Core ver 2.16
>NET: Registered protocol family 31
>Bluetooth: HCI device and connection manager initialized
>Bluetooth: HCI socket layer initialized
>Bluetooth: L2CAP socket layer initialized
>Bluetooth: SCO socket layer initialized
>HPET: 4 timers in total, 0 timers will be used for per-cpu timer
>hpet0: at MMIO 0xfed00000, IRQs 2, 8, 31, 31
>hpet0: 4 comparators, 64-bit 25.000000 MHz counter
>Switching to clocksource hpet
>pnp: PnP ACPI init
>ACPI: bus type pnp registered
>pnp 00:00: [bus 00-ff]
>pnp 00:00: [io  0x0cf8-0x0cff]
>pnp 00:00: [io  0x0000-0x0cf7 window]
>pnp 00:00: [io  0x0d00-0xffff window]
>pnp 00:00: [mem 0x000a0000-0x000bffff window]
>pnp 00:00: [mem 0x000c0000-0x000c3fff window]
>pnp 00:00: [mem 0x000c4000-0x000c7fff window]
>pnp 00:00: [mem 0x000c8000-0x000cbfff window]
>pnp 00:00: [mem 0x000cc000-0x000cffff window]
>pnp 00:00: [mem 0x000d0000-0x000d3fff window]
>pnp 00:00: [mem 0x000d4000-0x000d7fff window]
>pnp 00:00: [mem 0x000d8000-0x000dbfff window]
>pnp 00:00: [mem 0x000dc000-0x000dffff window]
>pnp 00:00: [mem 0x000e0000-0x000e3fff window]
>pnp 00:00: [mem 0x000e4000-0x000e7fff window]
>pnp 00:00: [mem 0x000e8000-0x000ebfff window]
>pnp 00:00: [mem 0x000ec000-0x000effff window]
>pnp 00:00: [mem 0x000f0000-0x000fffff window]
>pnp 00:00: [mem 0xc0000000-0xfebfffff window]
>pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
>pnp 00:01: [mem 0x00000000-0xffffffffffffffff disabled]
>pnp 00:01: [mem 0xf0000000-0xf3ffffff]
>system 00:01: [mem 0xf0000000-0xf3ffffff] has been reserved
>system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:02: [io  0x0300-0x031f]
>pnp 00:02: [irq 6]
>pnp 00:02: Plug and Play ACPI device, IDs APP0001 (active)
>pnp 00:03: [io  0x0000-0x0008]
>pnp 00:03: [io  0x000a-0x000f]
>pnp 00:03: [io  0x0081-0x0083]
>pnp 00:03: [io  0x0087]
>pnp 00:03: [io  0x0089-0x008b]
>pnp 00:03: [io  0x008f]
>pnp 00:03: [io  0x00c0-0x00d1]
>pnp 00:03: [io  0x00d4-0x00df]
>pnp 00:03: [dma 4]
>pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active)
>pnp 00:04: [irq 0 disabled]
>pnp 00:04: [irq 8]
>pnp 00:04: [mem 0xfed00000-0xfed003ff]
>system 00:04: [mem 0xfed00000-0xfed003ff] has been reserved
>system 00:04: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active)
>pnp 00:05: [io  0x00f0-0x00f1]
>pnp 00:05: [irq 13]
>pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active)
>pnp 00:06: [io  0x0400-0x047f]
>pnp 00:06: [io  0x0480-0x04ff]
>pnp 00:06: [io  0x0500-0x057f]
>pnp 00:06: [io  0x0580-0x05ff]
>pnp 00:06: [io  0x0800-0x087f]
>pnp 00:06: [io  0x0880-0x08ff]
>pnp 00:06: [io  0x0010-0x001f]
>pnp 00:06: [io  0x0022-0x003f]
>pnp 00:06: [io  0x0044-0x005f]
>pnp 00:06: [io  0x0063]
>pnp 00:06: [io  0x0065]
>pnp 00:06: [io  0x0067-0x006f]
>pnp 00:06: [io  0x0072-0x0073]
>pnp 00:06: [io  0x0074-0x007f]
>pnp 00:06: [io  0x0091-0x0093]
>pnp 00:06: [io  0x0097-0x009f]
>pnp 00:06: [io  0x00a2-0x00bf]
>pnp 00:06: [io  0x00e0-0x00ef]
>pnp 00:06: [io  0x04d0-0x04d1]
>pnp 00:06: [io  0x0080]
>pnp 00:06: [io  0x0295-0x0296]
>system 00:06: [io  0x0400-0x047f] has been reserved
>system 00:06: [io  0x0480-0x04ff] has been reserved
>system 00:06: [io  0x0500-0x057f] has been reserved
>system 00:06: [io  0x0580-0x05ff] has been reserved
>system 00:06: [io  0x0800-0x087f] has been reserved
>system 00:06: [io  0x0880-0x08ff] has been reserved
>system 00:06: [io  0x04d0-0x04d1] has been reserved
>Switched to NOHz mode on CPU #0
>system 00:06: [io  0x0295-0x0296] has been reserved
>system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>pnp 00:07: [io  0x0070-0x0077]
>pnp 00:07: Plug and Play ACPI device, IDs PNP0b00 (active)
>Switched to NOHz mode on CPU #1
>pnp: PnP ACPI: found 8 devices
>ACPI: ACPI bus type pnp unregistered
>pci 0000:00:15.0: PCI bridge to [bus 01-01]
>pci 0000:00:15.0:   bridge window [io  disabled]
>pci 0000:00:15.0:   bridge window [mem 0xd3100000-0xd31fffff]
>pci 0000:00:15.0:   bridge window [mem pref disabled]
>pci 0000:00:17.0: PCI bridge to [bus 02-02]
>pci 0000:00:17.0:   bridge window [io  0x1000-0x1fff]
>pci 0000:00:17.0:   bridge window [mem 0xd2000000-0xd30fffff]
>pci 0000:00:17.0:   bridge window [mem 0xc0000000-0xd1ffffff 64bit pref]
>pci 0000:00:15.0: power state changed by ACPI to D0
>pci 0000:00:15.0: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [Z00J] enabled at IRQ 21
>pci 0000:00:15.0: PCI INT A -> Link[Z00J] -> GSI 21 (level, low) -> IRQ 21
>pci 0000:00:15.0: setting latency timer to 64
>pci 0000:00:17.0: setting latency timer to 64
>pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
>pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
>pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
>pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff]
>pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff]
>pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff]
>pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff]
>pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff]
>pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff]
>pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff]
>pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff]
>pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff]
>pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff]
>pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff]
>pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff]
>pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff]
>pci_bus 0000:00: resource 20 [mem 0xc0000000-0xfebfffff]
>pci_bus 0000:01: resource 1 [mem 0xd3100000-0xd31fffff]
>pci_bus 0000:02: resource 0 [io  0x1000-0x1fff]
>pci_bus 0000:02: resource 1 [mem 0xd2000000-0xd30fffff]
>pci_bus 0000:02: resource 2 [mem 0xc0000000-0xd1ffffff 64bit pref]
>NET: Registered protocol family 2
>IP route cache hash table entries: 131072 (order: 8, 1048576 bytes)
>TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
>TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>TCP: Hash tables configured (established 262144 bind 65536)
>TCP reno registered
>UDP hash table entries: 2048 (order: 4, 65536 bytes)
>UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
>PCI: CLS 256 bytes, default 64
>PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>Placing 64MB software IO TLB between ffff8800a8921000 - ffff8800ac921000
>software IO TLB at phys 0xa8921000 - 0xac921000
>Btrfs loaded
>msgmni has been set to 7320
>alg: No test for stdrng (krng)
>Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
>io scheduler noop registered (default)
>pcieport 0000:00:15.0: setting latency timer to 64
>pcieport 0000:00:15.0: irq 40 for MSI/MSI-X
>intel_idle: MWAIT substates: 0x3122220
>intel_idle: does not run on family 6 model 23
>ACPI: AC Adapter [ADP1] (on-line)
>input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
>ACPI: Lid Switch [LID0]
>input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input1
>ACPI: Power Button [PWRB]
>input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input2
>ACPI: Sleep Button [SLPB]
>input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
>ACPI: Power Button [PWRF]
>ACPI: acpi_idle registered with cpuidle
>Monitor-Mwait will be used to enter C-1 state
>Monitor-Mwait will be used to enter C-2 state
>Monitor-Mwait will be used to enter C-3 state
>Marking TSC unstable due to TSC halts in idle
>[drm] Initialized drm 1.1.0 20060810
>[drm:drm_pci_init], 
>[drm:drm_get_pci_dev], 
>nouveau 0000:02:00.0: enabling device (0006 -> 0007)
>ACPI: PCI Interrupt Link [LGPU] enabled at IRQ 16
>nouveau 0000:02:00.0: PCI INT A -> Link[LGPU] -> GSI 16 (level, low) -> IRQ 16
>nouveau 0000:02:00.0: setting latency timer to 64
>[drm:drm_get_minor], 
>[drm:drm_get_minor], new minor assigned 64
>[drm:drm_get_minor], 
>[drm:drm_get_minor], new minor assigned 0
>[drm] nouveau 0000:02:00.0: nouveau_load:892 - vendor: 0x10DE device: 0x8A2 class: 0x30000
>[drm] nouveau 0000:02:00.0: nouveau_load:909 - regs mapped ok at 0xd2000000
>[drm] nouveau 0000:02:00.0: Detected an NV50 generation card (0x0af100a2)
>[drm] nouveau 0000:02:00.0: Attempting to load BIOS image from PRAMIN
>ACPI: Battery Slot [BAT0] (battery present)
>[drm] nouveau 0000:02:00.0: ... appears to be valid
>[drm] nouveau 0000:02:00.0: BIT BIOS found
>[drm] nouveau 0000:02:00.0: Bios version 70.89.13.00
>[drm] nouveau 0000:02:00.0: Pointer to BIT loadval table invalid
>[drm] nouveau 0000:02:00.0: TMDS table version 2.0
>[drm] nouveau 0000:02:00.0: Found Display Configuration Block version 4.0
>[drm] nouveau 0000:02:00.0: Raw DCB entry 0: 040001b6 0f220010
>[drm] nouveau 0000:02:00.0: Raw DCB entry 1: 020112a6 0f220010
>[drm] nouveau 0000:02:00.0: Raw DCB entry 2: 02011262 00020010
>[drm] nouveau 0000:02:00.0: Raw DCB entry 3: 0000000e 00000000
>[drm] nouveau 0000:02:00.0: DCB connector table: VHER 0x40 5 16 4
>[drm] nouveau 0000:02:00.0:   0: 0x00002047: type 0x47 idx 0 tag 0x08
>[drm] nouveau 0000:02:00.0:   1: 0x00101146: type 0x46 idx 1 tag 0x07
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table 0 at offset 0x6A0C
>[drm] nouveau 0000:02:00.0: 0x6A0C: ------ Executing following commands ------
>[drm] nouveau 0000:02:00.0: 0x6A0C: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A0C: Reg: 0x00614008, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614008, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614008, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A19: Reg: 0x00088090, Mask: 0xFFFFFFFC, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00088090, Data: 0x03000007
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00088090, Data: 0x03000007
>[drm] nouveau 0000:02:00.0: 0x6A26: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A26: Reg: 0x00088200, Mask: 0xFFFF7F7F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00088200, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00088200, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6A33: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A33: Reg: 0x00020060, Mask: 0xFFC0FFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00020060, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 0x6A40: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A40: Reg: 0x0002004C, Mask: 0xFDFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0002004C, Data: 0x4407220B
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0002004C, Data: 0x4407220B
>[drm] nouveau 0000:02:00.0: 0x6A4D: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4D: Repeating following segment 20 times
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A4F: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6A5C: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A5D: Reg: 0x00020060, Mask: 0xFFC0FFFF, Data: 0x00040000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00020060, Data: 0x00040000
>[drm] nouveau 0000:02:00.0: 0x6A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A6A: Reg: 0x0002004C, Mask: 0xFDFFFFFF, Data: 0x02000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0002004C, Data: 0x4407220B
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0002004C, Data: 0x4607220B
>[drm] nouveau 0000:02:00.0: 0x6A77: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A77: Reg: 0x00020064, Mask: 0xFFFFFFC0, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00020064, Data: 0x40400002
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00020064, Data: 0x40400002
>[drm] nouveau 0000:02:00.0: 0x6A84: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000200, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6A8D: [ (0x8C) - INIT_8C ]
>[drm] nouveau 0000:02:00.0: 0x6A8E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A8E: Reg: 0x00022210, Mask: 0xFFFFFFFE, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00022210, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6A9B: [ (0x33) - INIT_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9B: Repeating following segment 20 times
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6A9D: Reg: 0x00000000, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000000, Data: 0x0AF100A2
>[drm] nouveau 0000:02:00.0: 0x6AAA: [ (0x36) - INIT_END_REPEAT ]
>[drm] nouveau 0000:02:00.0: 0x6AAB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6AAB: Reg: 0x0000C040, Mask: 0xCFFFEFFF, Data: 0x30001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000C040, Data: 0x30001000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000C040, Data: 0x30001000
>[drm] nouveau 0000:02:00.0: 0x6AB8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000200, Data: 0xC0010111
>[drm] nouveau 0000:02:00.0: 0x6AC1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6AC1: Reg: 0x00022210, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00022210, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6ACE: [ (0x8D) - INIT_8D ]
>[drm] nouveau 0000:02:00.0: 0x6ACF: [ (0x69) - INIT_IO ]
>[drm] nouveau 0000:02:00.0: 0x6ACF: Port: 0x03C3, Mask: 0x00, Data: 0x01
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614100, Data: 0x50000603
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614100, Data: 0x00800603
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614900, Data: 0x00800100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000200, Data: 0xC0912111
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000200, Data: 0x80912111
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00000200, Data: 0xC0912111
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000200, Data: 0xC0912111
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614100, Data: 0x00800018
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614900, Data: 0x00800018
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614100, Data: 0x10000018
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614900, Data: 0x10000018
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614280, Data: 0x04840484
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614280, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615280, Data: 0x04840484
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615280, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614380, Data: 0x00800484
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614380, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614B80, Data: 0x00800484
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614B80, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615380, Data: 0x00800484
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615380, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614108, Data: 0x0000FE14
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614108, Data: 0x0000FE14
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614908, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6AD4: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x3F, Head: 0x00, Data: 0x57
>[drm] nouveau 0000:02:00.0: 0x6AD7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6AD7: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00001084, Data: 0x00001C69
>[drm] nouveau 0000:02:00.0: 0x6AE4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6AE4: Reg: 0x0000E108, Mask: 0xFFFFFF7F, Data: 0x00000080
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E108, Data: 0x000004C8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E108, Data: 0x000004C8
>[drm] nouveau 0000:02:00.0: 0x6AF1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6AF1: Reg: 0x0000E300, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E300, Data: 0x00000300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E300, Data: 0x00000300
>[drm] nouveau 0000:02:00.0: 0x6AFE: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x6AFE: Condition: 0x0F
>[drm] nouveau 0000:02:00.0: 0x6AFE: Cond: 0x0F, Reg: 0x000211A8, Mask: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x000211A8, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6AFE: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6AFE: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x6B00: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B00: Reg: 0x0002000C, Mask: 0xBFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0002000C, Data: 0x40009C40
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0002000C, Data: 0x00009C40
>[drm] nouveau 0000:02:00.0: 0x6B0D: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:02:00.0: 0x6B0D: ------ Skipping following commands  ------
>[drm] nouveau 0000:02:00.0: 0x6B0E: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:02:00.0: 0x6B1C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B25: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B2E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B37: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B40: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:02:00.0: 0x6B5E: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:02:00.0: 0x6B6C: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:02:00.0: 0x6B7A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B87: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B90: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6B99: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BA2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BAB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BB8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BC1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BCA: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BD7: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x6BD7: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x6BD8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E548, Data: 0x0000FFFF
>[drm] nouveau 0000:02:00.0: 0x6BE1: [ (0x8E) - INIT_GPIO ]
>[drm] nouveau 0000:02:00.0: 0x6BE1: Entry: 0x700007E1
>[drm] nouveau 0000:02:00.0: 0x6BE1: set gpio 0x07, state 0
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 0x6BE1: Entry: 0xA40021E2
>[drm] nouveau 0000:02:00.0: 0x6BE1: set gpio 0x21, state 0
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 0x6BE1: Entry: 0x210001E3
>[drm] nouveau 0000:02:00.0: 0x6BE1: set gpio 0x01, state 1
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 0x6BE1: Entry: 0x240000E4
>[drm] nouveau 0000:02:00.0: 0x6BE1: set gpio 0x00, state 0
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 0x6BE1: Entry: 0x700008F3
>[drm] nouveau 0000:02:00.0: 0x6BE1: set gpio 0x08, state 0
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E28C, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E28C, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 0x6BE2: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00009220, Data: 0x00000412
>[drm] nouveau 0000:02:00.0: 0x6BEB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00009200, Data: 0x00000804
>[drm] nouveau 0000:02:00.0: 0x6BF4: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00009210, Data: 0x00000271
>[drm] nouveau 0000:02:00.0: 0x6BFD: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6BFD: Reg: 0x00614200, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614200, Data: 0x00800040
>[drm] nouveau 0000:02:00.0: 0x6C0A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C0A: Reg: 0x00614A00, Mask: 0xFFFFFFF0, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614A00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 0x6C17: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C17: Reg: 0x00614A80, Mask: 0xF8F8F8F8, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614A80, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 0x6C24: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C24: Reg: 0x00614300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614300, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 0x6C31: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C31: Reg: 0x00614B00, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614B00, Data: 0x00800080
>[drm] nouveau 0000:02:00.0: 0x6C3E: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C3E: Reg: 0x00615300, Mask: 0xFFFFF8F8, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 0x6C4B: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C4B: Reg: 0x00101000, Mask: 0xF0FFFFFF, Data: 0x8F000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00101000, Data: 0x8FC088C0
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00101000, Data: 0x8FC088C0
>[drm] nouveau 0000:02:00.0: 0x6C58: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C58: Reg: 0x0010100C, Mask: 0xFFFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0010100C, Data: 0x80010010
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0010100C, Data: 0x80010010
>[drm] nouveau 0000:02:00.0: 0x6C65: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C65: SrcReg: 0x00614004, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x00610184, DstMask: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00614004, Data: 0x07200000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00610184, Data: 0x07200000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00610184, Data: 0x07200000
>[drm] nouveau 0000:02:00.0: 0x6C7B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619F00, Data: 0x00000009
>[drm] nouveau 0000:02:00.0: 0x6C84: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C84: Reg: 0x00001540, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00001540, Data: 0xF7030003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00001540, Data: 0xF7030003
>[drm] nouveau 0000:02:00.0: 0x6C91: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E18C, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 0x6C9A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6C9A: Reg: 0x00004714, Mask: 0x00000001, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004714, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004714, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CA7: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x6CA7: Condition: 0x07, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x6CA7: Cond: 0x07, Reg: 0x00004718, Mask: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004718, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CA7: Checking if 0x00000001 equals 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CA7: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x6CA7: Cond: 0x07, Reg: 0x00004718, Mask: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004718, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CA7: Checking if 0x00000001 equals 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CAA: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x6CAA: Condition: 0x05, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x6CAA: Cond: 0x05, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CAA: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:02:00.0: 0x6CAA: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x6CAA: Cond: 0x05, Reg: 0x0000E820, Mask: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CAA: Checking if 0x00010000 equals 0x00010000
>[drm] nouveau 0000:02:00.0: 0x6CAD: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x6CAE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CAE: Reg: 0x0000E820, Mask: 0xFFFFFFEE, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010105
>[drm] nouveau 0000:02:00.0: 0x6CBB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CBB: Reg: 0x0000E830, Mask: 0x80000000, Data: 0x00211701
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E830, Data: 0x00211701
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E830, Data: 0x00211701
>[drm] nouveau 0000:02:00.0: 0x6CC8: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x6CC8: Condition: 0x06, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x6CC8: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CC8: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:02:00.0: 0x6CC8: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:02:00.0: 0x6CC8: Cond: 0x06, Reg: 0x0000E820, Mask: 0x00020000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CC8: Checking if 0x00000000 equals 0x00020000
>[drm] nouveau 0000:02:00.0: 0x6CC8: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:02:00.0: 0x6CCB: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x6CCB: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x6CCC: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CCC: Reg: 0x0000E820, Mask: 0xFFFFFFFB, Data: 0x00000004
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CD9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CD9: Reg: 0x0000E820, Mask: 0xFFFFFFE7, Data: 0x00000010
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x6CE6: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CE6: Reg: 0x0000E82C, Mask: 0xFFFFFFF7, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6CF3: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6CF3: Reg: 0x0000E830, Mask: 0x7FFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E830, Data: 0x00211701
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E830, Data: 0x00211701
>[drm] nouveau 0000:02:00.0: 0x6D00: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6D00: Reg: 0x0000E82C, Mask: 0xFFFFFFFB, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E82C, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 0x6D0D: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004194, Data: 0x1E1C0121
>[drm] nouveau 0000:02:00.0: 0x6D16: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004190, Data: 0x001C0121
>[drm] nouveau 0000:02:00.0: 0x6D1F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041A0, Data: 0x00080121
>[drm] nouveau 0000:02:00.0: 0x6D28: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004164, Data: 0x00020121
>[drm] nouveau 0000:02:00.0: 0x6D31: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004160, Data: 0x3E060121
>[drm] nouveau 0000:02:00.0: 0x6D3A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004168, Data: 0x1E060121
>[drm] nouveau 0000:02:00.0: 0x6D43: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004180, Data: 0x00060121
>[drm] nouveau 0000:02:00.0: 0x6D4C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004184, Data: 0x00060121
>[drm] nouveau 0000:02:00.0: 0x6D55: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041A4, Data: 0x00060121
>[drm] nouveau 0000:02:00.0: 0x6D5E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041B0, Data: 0x00180121
>[drm] nouveau 0000:02:00.0: 0x6D67: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041B4, Data: 0x00080121
>[drm] nouveau 0000:02:00.0: 0x6D70: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6D70: Reg: 0x00004190, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004190, Data: 0x001C3121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004190, Data: 0x001C3121
>[drm] nouveau 0000:02:00.0: 0x6D7D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6D7D: Reg: 0x000041A0, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x000041A0, Data: 0x00083121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041A0, Data: 0x00083121
>[drm] nouveau 0000:02:00.0: 0x6D8A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6D8A: Reg: 0x00004164, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004164, Data: 0x00023121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004164, Data: 0x00023121
>[drm] nouveau 0000:02:00.0: 0x6D97: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6D97: Reg: 0x00004160, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004160, Data: 0x3E063121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004160, Data: 0x3E063121
>[drm] nouveau 0000:02:00.0: 0x6DA4: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DA4: Reg: 0x00004168, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004168, Data: 0x1E063121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004168, Data: 0x1E063121
>[drm] nouveau 0000:02:00.0: 0x6DB1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DB1: Reg: 0x00004180, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004180, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004180, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 0x6DBE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DBE: Reg: 0x00004184, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004184, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004184, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 0x6DCB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DCB: Reg: 0x000041A4, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x000041A4, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041A4, Data: 0x00063121
>[drm] nouveau 0000:02:00.0: 0x6DD8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DD8: Reg: 0x000041B0, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x000041B0, Data: 0x00183121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041B0, Data: 0x00183121
>[drm] nouveau 0000:02:00.0: 0x6DE5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DE5: Reg: 0x000041B4, Mask: 0xFFFFCFFF, Data: 0x00003000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x000041B4, Data: 0x00083121
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x000041B4, Data: 0x00083121
>[drm] nouveau 0000:02:00.0: 0x6DF2: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DF2: Reg: 0x00004200, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004200, Data: 0x00010008
>[drm] nouveau 0000:02:00.0: 0x6DFF: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6DFF: Reg: 0x00004220, Mask: 0xFFFFFFF7, Data: 0x00000008
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00004220, Data: 0x00010008
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004220, Data: 0x00010008
>[drm] nouveau 0000:02:00.0: 0x6E0C: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004120, Data: 0x001C3021
>[drm] nouveau 0000:02:00.0: 0x6E15: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004124, Data: 0x001C3021
>[drm] nouveau 0000:02:00.0: 0x6E1E: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004140, Data: 0x001C0100
>[drm] nouveau 0000:02:00.0: 0x6E27: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00004144, Data: 0x001C0100
>[drm] nouveau 0000:02:00.0: 0x6E30: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614100, Data: 0x10000100
>[drm] nouveau 0000:02:00.0: 0x6E39: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614900, Data: 0x10000100
>[drm] nouveau 0000:02:00.0: 0x6E42: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000C044, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6E4B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00000200, Data: 0xC0110111
>[drm] nouveau 0000:02:00.0: 0x6E54: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6E54: Reg: 0x00100268, Mask: 0xFFFCFFFF, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00100268, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00100268, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 0x6E61: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C0E8, Data: 0x6888D110
>[drm] nouveau 0000:02:00.0: 0x6E6A: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C8E8, Data: 0xE887D10C
>[drm] nouveau 0000:02:00.0: 0x6E73: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D0E8, Data: 0xE887D10C
>[drm] nouveau 0000:02:00.0: 0x6E7C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table 1 at offset 0x6E7D
>[drm] nouveau 0000:02:00.0: 0x6E7D: ------ Executing following commands ------
>[drm] nouveau 0000:02:00.0: 0x6E7D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table 2 at offset 0x6E7F
>[drm] nouveau 0000:02:00.0: 0x6E7F: ------ Executing following commands ------
>[drm] nouveau 0000:02:00.0: 0x6E7F: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000108C, Data: 0x000000D1
>[drm] nouveau 0000:02:00.0: 0x6E88: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xF0, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 0x6E8B: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:02:00.0: 0x6E8B: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x08, Count: 0x02
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x08
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x09
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:02:00.0: 0x6E92: [ (0x51) - INIT_CR_INDEX_ADDRESS_LATCHED ]
>[drm] nouveau 0000:02:00.0: 0x6E92: Index1: 0xA0, Index2: 0xA1, BaseAddr: 0x18, Count: 0x02
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x006194A0, Data: 0x10000019
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x18
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA1, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xA0, Head: 0x00, Data: 0x19
>[drm] nouveau 0000:02:00.0: 0x6E99: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:02:00.0: 0x6E99: Index: 0x88, Mask: 0xBF, Data: 0x40
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000040
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x40
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x88, Head: 0x00, Data: 0x40
>[drm] nouveau 0000:02:00.0: 0x6E9D: [ (0x52) - INIT_CR ]
>[drm] nouveau 0000:02:00.0: 0x6E9D: Index: 0x8A, Mask: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619488, Data: 0x00000040
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x8A, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 0x6EA1: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E200, Data: 0x0003103C
>[drm] nouveau 0000:02:00.0: 0x6EAA: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x30, Head: 0x00, Data: 0x10
>[drm] nouveau 0000:02:00.0: 0x6EAD: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x31, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 0x6EB0: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0xAA, Head: 0x00, Data: 0x00
>[drm] nouveau 0000:02:00.0: 0x6EB3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table 3 at offset 0x6EB4
>[drm] nouveau 0000:02:00.0: 0x6EB4: ------ Executing following commands ------
>[drm] nouveau 0000:02:00.0: 0x6EB4: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x6EB4: Executing subroutine at 0x5E4E
>[drm] nouveau 0000:02:00.0: 0x5E4E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x6EB4: End of 0x5E4E subroutine
>[drm] nouveau 0000:02:00.0: 0x6EB7: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x6EB7: Executing subroutine at 0x6E7E
>[drm] nouveau 0000:02:00.0: 0x6E7E: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x6EB7: End of 0x6E7E subroutine
>[drm] nouveau 0000:02:00.0: 0x6EBA: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00612000, Data: 0x10000210
>[drm] nouveau 0000:02:00.0: 0x6EC3: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614000, Data: 0x10000210
>[drm] nouveau 0000:02:00.0: 0x6ECC: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614100, Data: 0x50000000
>[drm] nouveau 0000:02:00.0: 0x6ED5: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614118, Data: 0x00230122
>[drm] nouveau 0000:02:00.0: 0x6EDE: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061411C, Data: 0x000017D7
>[drm] nouveau 0000:02:00.0: 0x6EE7: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614120, Data: 0x00210124
>[drm] nouveau 0000:02:00.0: 0x6EF0: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00614124, Data: 0x00001C51
>[drm] nouveau 0000:02:00.0: 0x6EF9: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x6EF9: Condition: 0x09
>[drm] nouveau 0000:02:00.0: 0x6EF9: Cond: 0x09, Reg: 0x00021218, Mask: 0x000000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00021218, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6EF9: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6EF9: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x6EFB: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061A868, Data: 0x4C006A22
>[drm] nouveau 0000:02:00.0: 0x6F04: [ (0x38) - INIT_NOT ]
>[drm] nouveau 0000:02:00.0: 0x6F04: ------ Skipping following commands  ------
>[drm] nouveau 0000:02:00.0: 0x6F05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6F12: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6F28: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x6F28: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x6F29: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061A830, Data: 0x000415F1
>[drm] nouveau 0000:02:00.0: 0x6F32: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C080, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6F3B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C084, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x6F44: [ (0x53) - INIT_ZM_CR ]
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x85, Head: 0x00, Data: 0xFF
>[drm] nouveau 0000:02:00.0: 0x6F47: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6F47: Reg: 0x00001084, Mask: 0xFFFFF7FF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00001084, Data: 0x00001469
>[drm] nouveau 0000:02:00.0: 0x6F54: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6F54: SrcReg: 0x00088078, Shift: 0x00, SrcMask: 0xFFFFFFFF, Xor: 0x00000000, DstReg: 0x0010A4F4, DstMask: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00088078, Data: 0x00000320
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0010A4F4, Data: 0x00000320
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0010A4F4, Data: 0x00000320
>[drm] nouveau 0000:02:00.0: 0x6F6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6F6A: Reg: 0x00100B18, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00100B18, Data: 0x000A3400
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00100B18, Data: 0x000A3400
>[drm] nouveau 0000:02:00.0: 0x6F77: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table 4 at offset 0x6F78
>[drm] nouveau 0000:02:00.0: 0x6F78: ------ Executing following commands ------
>[drm] nouveau 0000:02:00.0: 0x6F78: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Parsing VBIOS init table at offset 0x6FDD
>[drm] nouveau 0000:02:00.0: 0x6FDD: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x6FDD: Condition: 0x00, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x6FDD: Cond: 0x00, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 0x6FDD: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:02:00.0: 0x6FDD: Condition not met, sleeping for 20ms
>[drm] nouveau 0000:02:00.0: 0x6FDD: Cond: 0x00, Reg: 0x0061000C, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 0x6FDD: Checking if 0x00000000 equals 0x80000000
>[drm] nouveau 0000:02:00.0: 0x6FDD: Condition still not met after 20ms, skipping following opcodes
>[drm] nouveau 0000:02:00.0: 0x6FE0: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x6FE0: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x6FE1: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6FE1: SrcReg: 0x00610000, Shift: 0x00, SrcMask: 0x0000FFFF, Xor: 0x00000000, DstReg: 0x0061000C, DstMask: 0xFFFF0000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00610000, Data: 0x857D0150
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 0x6FF7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x6FF7: Reg: 0x0061000C, Mask: 0xBFFFFFFF, Data: 0x40000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061000C, Data: 0x40000150
>[drm] nouveau 0000:02:00.0: 0x7004: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x7004: Condition: 0x01, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x7004: Cond: 0x01, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 0x7004: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x7004: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x7004: Cond: 0x01, Reg: 0x0061000C, Mask: 0x40000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061000C, Data: 0x00000150
>[drm] nouveau 0000:02:00.0: 0x7004: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x7007: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x7008: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:02:00.0: 0x5CAC: parsing output script 0
>[drm] nouveau 0000:02:00.0: 0x5CAC: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5CAC: subop 0x00
>[drm] nouveau 0000:02:00.0: 0x5CAC: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x5CAF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D080, Data: 0x0000B42D
>[drm] nouveau 0000:02:00.0: 0x5CB8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D084, Data: 0xC000B42D
>[drm] nouveau 0000:02:00.0: 0x5CC1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CC1: Reg: 0x0000E1E4, Mask: 0xFFFFFFFC, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E1E4, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E1E4, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 0x5CCE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CCE: Reg: 0x0000E100, Mask: 0xFFFFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E100, Data: 0x00140300
>[drm] nouveau 0000:02:00.0: 0x5CDB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CDB: Reg: 0x6061C140, Mask: 0xFFFFFFFE, Data: 0x00000001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5CE8: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 2
>[drm] nouveau 0000:02:00.0: 0x5CAC: parsing output script 0
>[drm] nouveau 0000:02:00.0: 0x5CAC: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5CAC: subop 0x00
>[drm] nouveau 0000:02:00.0: 0x5CAC: skipping following commands
>[drm] nouveau 0000:02:00.0: 0x5CAF: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CB8: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CC1: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CCE: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CDB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5CE8: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Searching for output entry for 2 0 2
>[drm] nouveau 0000:02:00.0: 0x596C: parsing output script 0
>[drm] nouveau 0000:02:00.0: 0x596C: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00101000, Data: 0x8FC088C0
>[drm] nouveau 0000:02:00.0: nouveau_volt_init:183 - vid bit 0 has no gpio tag
>[drm] nouveau 0000:02:00.0: nouveau_i2c_identify:310 - Probing monitoring devices on I2C bus: 2
>[drm] nouveau 0000:02:00.0: nouveau_i2c_identify:320 - No devices found.
>[drm] nouveau 0000:02:00.0: 4 available performance level(s)
>[drm] nouveau 0000:02:00.0: 0: memory 405MHz core 405MHz shader 405MHz voltage 900mV
>[drm] nouveau 0000:02:00.0: 1: memory 450MHz core 450MHz shader 810MHz voltage 900mV
>[drm] nouveau 0000:02:00.0: 2: memory 450MHz core 450MHz shader 810MHz voltage 900mV
>[drm] nouveau 0000:02:00.0: 3: memory 450MHz core 450MHz shader 950MHz voltage 900mV
>[drm] nouveau 0000:02:00.0: Loading PLL limits for register 0x00004200
>[drm] nouveau 0000:02:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:02:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_inputfreq: 14000
>[drm] nouveau 0000:02:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_n: 8
>[drm] nouveau 0000:02:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:02:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:02:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:02:00.0: pll.min_p: 1
>[drm] nouveau 0000:02:00.0: pll.max_p: 63
>[drm] nouveau 0000:02:00.0: pll.refclk: 100000
>[drm] nouveau 0000:02:00.0: Loading PLL limits for register 0x00004220
>[drm] nouveau 0000:02:00.0: pll.vco1.minfreq: 1000000
>[drm] nouveau 0000:02:00.0: pll.vco1.maxfreq: 2000000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_inputfreq: 25000
>[drm] nouveau 0000:02:00.0: pll.vco1.max_inputfreq: 100000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_n: 8
>[drm] nouveau 0000:02:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:02:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:02:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:02:00.0: pll.min_p: 1
>[drm] nouveau 0000:02:00.0: pll.max_p: 63
>[drm] nouveau 0000:02:00.0: pll.refclk: 100000
>[drm] nouveau 0000:02:00.0: c: memory 0MHz core 550MHz shader 1400MHz
>[TTM] Zone  kernel: Available graphics memory: 1874046 kiB.
>[TTM] Initializing pool allocator.
>[drm] nouveau 0000:02:00.0: Detected 256MiB VRAM
>[drm] nouveau 0000:02:00.0: Stolen system memory at: 0x00af000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_init:242 - 
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000003
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b02bf60
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=131072 align=4096 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00010200 vinst=0x0000050200 size=0x00004000 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88013b19c060
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x00014200 vinst=0x0000054200 size=0x00000100 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88013b19c0c0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c120
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c1e0
>[drm] nouveau 0000:02:00.0: 64 MiB GART (aperture)
>[drm] nouveau 0000:02:00.0: nv50_fb_create:59 - 4095 tags available
>[drm] nouveau 0000:02:00.0: nv50_graph_init:179 - 
>[drm] nouveau 0000:02:00.0: nv50_graph_init_reset:44 - 
>[drm] nouveau 0000:02:00.0: nv50_graph_init_regs__nv:68 - 
>[drm] nouveau 0000:02:00.0: nv50_graph_init_zcull:103 - 
>[drm] nouveau 0000:02:00.0: nv50_graph_init_ctxctl:143 - 
>[drm] nouveau 0000:02:00.0: nv50_graph_init_intr:53 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_init:166 - 
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c2a0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=512 align=4096 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c300
>[drm] nouveau 0000:02:00.0: nv50_fifo_init_reset:99 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_init_intr:108 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_init_context_table:121 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch1
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch2
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch3
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch4
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch5
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch6
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch7
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch8
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch9
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch10
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch11
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch12
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch13
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch14
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch15
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch16
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch17
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch18
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch19
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch20
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch21
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch22
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch23
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch24
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch25
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch26
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch27
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch28
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch29
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch30
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch31
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch32
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch33
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch34
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch35
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch36
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch37
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch38
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch39
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch40
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch41
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch42
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch43
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch44
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch45
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch46
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch47
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch48
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch49
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch50
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch51
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch52
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch53
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch54
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch55
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch56
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch57
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch58
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch59
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch60
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch61
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch62
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch63
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch64
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch65
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch66
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch67
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch68
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch69
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch70
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch71
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch72
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch73
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch74
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch75
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch76
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch77
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch78
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch79
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch80
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch81
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch82
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch83
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch84
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch85
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch86
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch87
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch88
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch89
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch90
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch91
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch92
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch93
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch94
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch95
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch96
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch97
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch98
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch99
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch100
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch101
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch102
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch103
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch104
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch105
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch106
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch107
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch108
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch109
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch110
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch111
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch112
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch113
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch114
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch115
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch116
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch117
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch118
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch119
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch120
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch121
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch122
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch123
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch124
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch125
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_disable:85 - ch126
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:02:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_init_regs__nv:136 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_init_regs:144 - 
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_enable:68 - ch0
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_enable:68 - ch127
>[drm] nouveau 0000:02:00.0: nv50_display_create:282 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_create:729 - 
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c4e0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=1048576 align=4096 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c540
>[drm] nouveau 0000:02:00.0: nv50_crtc_create:729 - 
>[drm] nouveau 0000:02:00.0: nouveau_connector_create:784 - 
>[drm:drm_sysfs_connector_add], adding "eDP-1" to sysfs
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm] nouveau 0000:02:00.0: nv50_sor_create:287 - 
>[drm] nouveau 0000:02:00.0: nouveau_connector_create:784 - 
>[drm:drm_sysfs_connector_add], adding "DP-1" to sysfs
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm] nouveau 0000:02:00.0: nv50_sor_create:287 - 
>[drm] nouveau 0000:02:00.0: nouveau_connector_create:784 - 
>[drm] nouveau 0000:02:00.0: nv50_sor_create:287 - 
>[drm] nouveau 0000:02:00.0: nv50_display_init:74 - 
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=32768 align=65536 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c660
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=16 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c6c0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=4096 align=0 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c720
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c780
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000d30: h=0xcafe0000, c=0x00800000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c7e0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000200
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000200: h=0x01000000, c=0x00808000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c840
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000218: h=0x01000003, c=0x00810000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c8a0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000210: h=0x01000002, c=0x00818000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c900
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch0 handle=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch0 0x00000208: h=0x01000001, c=0x00820000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c960
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000d38: h=0xcafe0000, c=0x10828001
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19c9c0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000220: h=0x01000003, c=0x10830001
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19ca20
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000228: h=0x01000002, c=0x10838001
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19ca80
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000208: h=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000210: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000220: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch1 0x00000228: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000230: h=0x01000001, c=0x10840001
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cae0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000d30
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d30: h=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000d38: h=0xcafe0000
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000d40: h=0xcafe0000, c=0x20848002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cb40
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000218
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000238: h=0x01000003, c=0x20850002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cba0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000210
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000240: h=0x01000002, c=0x20858002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch0 size=24 align=32 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cc00
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch2 handle=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000208
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000208: h=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000210: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000218: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000220: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000228: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000230: h=0x01000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000238: h=0x01000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:144 - collision ch2 0x00000240: h=0x01000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch2 0x00000248: h=0x01000001, c=0x20860002
>[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[drm] No driver support for vblank timestamp query.
>[drm:drm_irq_install], irq=16
>[drm] nouveau 0000:02:00.0: nouveau_channel_alloc:158 - initialising channel 1
>[drm] nouveau 0000:02:00.0: nouveau_sgdma_populate:30 - num_pages = 16
>[drm] nouveau 0000:02:00.0: nouveau_sgdma_populate:30 - num_pages = 1
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_channel_init:788 - ch1 vram=0x80000002 tt=0x80000003
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_channel_init_pramin:743 - ch1
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=415744 align=4096 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cd20
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:337 - pinst=0x0023a200 vinst=0x000028d200 size=0x00004000 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new_fake:342 - gpuobj ffff88013b19cd80
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=32768 align=16 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cde0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19ce40
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000010
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000480
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000480: h=0x80000010, c=0x00000e00
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cea0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000011
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000488
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000488: h=0x80000011, c=0x00000e02
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cf00
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000002
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000410
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000410: h=0x80000002, c=0x00000e04
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013b19cf60
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000003
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000418
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000418: h=0x80000003, c=0x00000e06
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce000
>[drm] nouveau 0000:02:00.0: nv50_fifo_create_context:236 - ch1
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=256 align=256 flags=0x00000006
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce060
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=4096 align=1024 flags=0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce0c0
>[drm] nouveau 0000:02:00.0: nv50_fifo_channel_enable:68 - ch1
>[drm] nouveau 0000:02:00.0: nv50_fifo_playlist_update:41 - 
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_gr_new:640 - ch1 class=0x5039
>[drm] nouveau 0000:02:00.0: nv50_graph_create_context:253 - ch1
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=349184 align=0 flags=0x00000006
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce120
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000006
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce180
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000001
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000408
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000408: h=0x80000001, c=0x00106480
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce1e0
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000006
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000430
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000430: h=0x80000006, c=0x00006482
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_gr_new:640 - ch1 class=0x506e
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x8000000e
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000470
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000470: h=0x8000000e, c=0x00000004
>[drm] nouveau 0000:02:00.0: nouveau_channel_alloc:222 - channel 1 initialised
>[drm:drm_fb_helper_connector_parse_command_line], cmdline mode for connector eDP-1 1366x768@60Hz
>[drm] forcing eDP-1 connector ON
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 16:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 14:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 13:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 12:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>No connectors reported connected with modes
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch-1 size=65536 align=4096 flags=0x00000002
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce2a0
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_gr_new:640 - ch1 class=0x502d
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:179 - ch1 size=24 align=16 flags=0x00000006
>[drm] nouveau 0000:02:00.0: nouveau_gpuobj_new:184 - gpuobj ffff88013a8ce300
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:39 - ch1 handle=0x80000007
>[drm] nouveau 0000:02:00.0: nouveau_ramht_hash_handle:50 - hash=0x00000438
>[drm] nouveau 0000:02:00.0: nouveau_ramht_insert:135 - insert ch1 0x00000438: h=0x80000007, c=0x00106484
>[drm] nouveau 0000:02:00.0: allocated 1368x768 fb: 0x40000000, bo ffff88013a8af000
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], modes are different, full mode set
>[drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm:drm_vblank_get], enabling vblank on crtc 0, ret: 0
>[drm:drm_update_vblank_count], enabling vblank interrupts on crtc 0, missed 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004150FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004150FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03854040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004150FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000010
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000010
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:607 - 0x610030: 0x000002e0
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:627 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:627 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:627 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:650 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:650 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk10_handler:650 - SOR-2 mc: 0x00023841
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:02:00.0: 0x5CE9: parsing output script 1
>[drm] nouveau 0000:02:00.0: 0x5CE9: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000020
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000020
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:730 - 0x610030: 0x000002f0
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:02:00.0: 0x5CEA: parsing output script 2
>[drm] nouveau 0000:02:00.0: 0x5CEA: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: Loading PLL limits for register 0x00614100
>[drm] nouveau 0000:02:00.0: pll.vco1.minfreq: 500000
>[drm] nouveau 0000:02:00.0: pll.vco1.maxfreq: 1000000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_inputfreq: 25000
>[drm] nouveau 0000:02:00.0: pll.vco1.max_inputfreq: 75000
>[drm] nouveau 0000:02:00.0: pll.vco1.min_n: 8
>[drm] nouveau 0000:02:00.0: pll.vco1.max_n: 255
>[drm] nouveau 0000:02:00.0: pll.vco1.min_m: 1
>[drm] nouveau 0000:02:00.0: pll.vco1.max_m: 255
>[drm] nouveau 0000:02:00.0: pll.min_p: 1
>[drm] nouveau 0000:02:00.0: pll.max_p: 63
>[drm] nouveau 0000:02:00.0: pll.refclk: 27000
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_clock:294 - pclk 85885 out 8588 N 34 fN 0x0f9e M 1 P 11
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:759 - DAC-0 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:759 - DAC-1 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:759 - DAC-2 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:782 - SOR-0 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:782 - SOR-1 mc: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_unk20_handler:782 - SOR-2 mc: 0x00051801
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:02:00.0: 0x5CA8: parsing clock script 0
>[drm] nouveau 0000:02:00.0: 0x5CA8: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5CA8: Executing subroutine at 0x5AC2
>[drm] nouveau 0000:02:00.0: 0x5AC2: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5AC2: Executing subroutine at 0x5D44
>[drm] nouveau 0000:02:00.0: 0x5D44: [ (0x58) - INIT_ZM_REG_SEQUENCE ]
>[drm] nouveau 0000:02:00.0: 0x5D44: BaseReg: 0x4061C040, Count: 0x10
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D040, Data: 0x000010C8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D044, Data: 0x0040A000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D048, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D04C, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D050, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D054, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D058, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D05C, Data: 0x00408000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D060, Data: 0x00002000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D064, Data: 0x000090C8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D068, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D06C, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D070, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D074, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D078, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D07C, Data: 0x00008000
>[drm] nouveau 0000:02:00.0: 0x5D8A: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5AC2: End of 0x5D44 subroutine
>[drm] nouveau 0000:02:00.0: 0x5AC5: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5AC5: Reg: 0x6061C128, Mask: 0xFBFFFFFF, Data: 0x04000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5AD2: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5CA8: End of 0x5AC2 subroutine
>[drm] nouveau 0000:02:00.0: 0x5CAB: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000040
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000040
>[drm] nouveau 0000:02:00.0: nv50_display_unk40_handler:879 - 0x610030: 0x000002f0
>[drm] nouveau 0000:02:00.0: Searching for output entry for 6 0 4
>[drm] nouveau 0000:02:00.0: 0x5AD3: parsing clock script 1
>[drm] nouveau 0000:02:00.0: 0x5AD3: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nv50_display_bh:902 - PDISPLAY_INTR_BH 0x00000000 0x00000000
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>Console: switching to colour frame buffer device 171x48
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_lut_load:48 - 
>fb0: nouveaufb frame buffer device
>drm: registered panic notifier
>[drm] Initialized nouveau 0.0.16 20090420 for 0000:02:00.0 on minor 0
>ahci 0000:00:0a.0: version 3.0
>ahci 0000:00:0a.0: power state changed by ACPI to D0
>ahci 0000:00:0a.0: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [LSI0] enabled at IRQ 18
>ahci 0000:00:0a.0: PCI INT A -> Link[LSI0] -> GSI 18 (level, low) -> IRQ 18
>ahci 0000:00:0a.0: irq 41 for MSI/MSI-X
>ahci 0000:00:0a.0: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
>ahci 0000:00:0a.0: flags: 64bit ncq sntf pm led pio slum part apst 
>ahci 0000:00:0a.0: setting latency timer to 64
>scsi0 : ahci
>ata1: SATA max UDMA/133 abar m8192@0xd3284000 port 0xd3284100 irq 41
>ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>ehci_hcd 0000:00:04.1: power state changed by ACPI to D0
>ehci_hcd 0000:00:04.1: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [LUS2] enabled at IRQ 17
>ehci_hcd 0000:00:04.1: PCI INT B -> Link[LUS2] -> GSI 17 (level, low) -> IRQ 17
>ehci_hcd 0000:00:04.1: setting latency timer to 64
>ehci_hcd 0000:00:04.1: EHCI Host Controller
>ehci_hcd 0000:00:04.1: new USB bus registered, assigned bus number 1
>ehci_hcd 0000:00:04.1: disable lpm/ppcd for nvidia mcp89
>ehci_hcd 0000:00:04.1: debug port 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>ehci_hcd 0000:00:04.1: cache line size of 256 is not supported
>ehci_hcd 0000:00:04.1: irq 17, io mem 0xd328b100
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>ehci_hcd 0000:00:04.1: USB 2.0 started, EHCI 1.10
>hub 1-0:1.0: USB hub found
>hub 1-0:1.0: 6 ports detected
>ehci_hcd 0000:00:06.1: power state changed by ACPI to D0
>ehci_hcd 0000:00:06.1: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [Z001] enabled at IRQ 22
>ehci_hcd 0000:00:06.1: PCI INT B -> Link[Z001] -> GSI 22 (level, low) -> IRQ 22
>ehci_hcd 0000:00:06.1: setting latency timer to 64
>ehci_hcd 0000:00:06.1: EHCI Host Controller
>ehci_hcd 0000:00:06.1: new USB bus registered, assigned bus number 2
>ehci_hcd 0000:00:06.1: disable lpm/ppcd for nvidia mcp89
>ehci_hcd 0000:00:06.1: debug port 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>ehci_hcd 0000:00:06.1: cache line size of 256 is not supported
>ehci_hcd 0000:00:06.1: irq 22, io mem 0xd328b000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>ehci_hcd 0000:00:06.1: USB 2.0 started, EHCI 1.10
>hub 2-0:1.0: USB hub found
>hub 2-0:1.0: 6 ports detected
>ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>ohci_hcd 0000:00:04.0: power state changed by ACPI to D0
>ohci_hcd 0000:00:04.0: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [LUS0] enabled at IRQ 23
>ohci_hcd 0000:00:04.0: PCI INT A -> Link[LUS0] -> GSI 23 (level, low) -> IRQ 23
>ohci_hcd 0000:00:04.0: setting latency timer to 64
>ohci_hcd 0000:00:04.0: OHCI Host Controller
>ohci_hcd 0000:00:04.0: new USB bus registered, assigned bus number 3
>ohci_hcd 0000:00:04.0: irq 23, io mem 0xd328a000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>hub 3-0:1.0: USB hub found
>hub 3-0:1.0: 6 ports detected
>ohci_hcd 0000:00:06.0: power state changed by ACPI to D0
>ohci_hcd 0000:00:06.0: power state changed by ACPI to D0
>ACPI: PCI Interrupt Link [Z000] enabled at IRQ 20
>ohci_hcd 0000:00:06.0: PCI INT A -> Link[Z000] -> GSI 20 (level, low) -> IRQ 20
>ohci_hcd 0000:00:06.0: setting latency timer to 64
>ohci_hcd 0000:00:06.0: OHCI Host Controller
>ohci_hcd 0000:00:06.0: new USB bus registered, assigned bus number 4
>ohci_hcd 0000:00:06.0: irq 20, io mem 0xd3289000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>hub 4-0:1.0: USB hub found
>hub 4-0:1.0: 6 ports detected
>i8042: PNP: No PS/2 controller found. Probing ports directly.
>i8042: No controller found
>mousedev: PS/2 mouse device common for all mice
>Bluetooth: Generic Bluetooth USB driver ver 0.6
>usbcore: registered new interface driver btusb
>cpuidle: using governor ladder
>cpuidle: using governor menu
>TCP cubic registered
>Bluetooth: RFCOMM TTY layer initialized
>Bluetooth: RFCOMM socket layer initialized
>Bluetooth: RFCOMM ver 1.11
>Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>Bluetooth: BNEP filters: protocol multicast
>Bluetooth: HIDP (Human Interface Emulation) ver 1.2
>Registering the dns_resolver key type
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>ata1.00: ATA-8: APPLE SSD TS128C, CJAA0201, max UDMA/100
>ata1.00: 236978176 sectors, multi 16: LBA48 
>ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>ata1.00: configured for UDMA/100
>scsi 0:0:0:0: Direct-Access     ATA      APPLE SSD TS128C CJAA PQ: 0 ANSI: 5
>sd 0:0:0:0: [sda] 236978176 512-byte logical blocks: (121 GB/113 GiB)
>sd 0:0:0:0: Attached scsi generic sg0 type 0
>sd 0:0:0:0: [sda] Write Protect is off
>sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
> sda: sda1 sda2 sda3 sda4
>sd 0:0:0:0: [sda] Attached SCSI disk
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>EXT4-fs (sda2): mounted filesystem without journal. Opts: (null)
>VFS: Mounted root (ext2 filesystem) readonly on device 8:2.
>Freeing unused kernel memory: 416k freed
>usb 1-1: new high speed USB device number 2 using ehci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>NET: Registered protocol family 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>udev[134]: starting version 164
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 1-6: new high speed USB device number 5 using ehci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>rtc_cmos 00:07: RTC can wake from S4
>rtc_cmos 00:07: rtc core: registered rtc_cmos as rtc0
>rtc0: alarms up to one year, y3k, 242 bytes nvram, hpet irqs
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>HDA Intel 0000:00:08.0: power state changed by ACPI to D0
>HDA Intel 0000:00:08.0: power state changed by ACPI to D0
>HDA Intel 0000:00:08.0: enabling device (0000 -> 0002)
>ACPI: PCI Interrupt Link [LAZA] enabled at IRQ 19
>HDA Intel 0000:00:08.0: PCI INT A -> Link[LAZA] -> GSI 19 (level, low) -> IRQ 19
>hda_intel: Disable MSI for Nvidia chipset
>HDA Intel 0000:00:08.0: setting latency timer to 64
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-3: new full speed USB device number 2 using ohci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>input: bcm5974 as /devices/pci0000:00/0000:00:04.0/usb3/3-3/3-3:1.2/input/input4
>usbcore: registered new interface driver bcm5974
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>input: Apple Inc. Apple Internal Keyboard / Trackpad as /devices/pci0000:00/0000:00:04.0/usb3/3-3/3-3:1.0/input/input5
>apple 0003:05AC:0242.0001: input,hidraw0: USB HID v1.11 Keyboard [Apple Inc. Apple Internal Keyboard / Trackpad] on usb-0000:00:04.0-3/input0
>apple 0003:05AC:0242.0002: hidraw1: USB HID v1.11 Device [Apple Inc. Apple Internal Keyboard / Trackpad] on usb-0000:00:04.0-3/input1
>usbcore: registered new interface driver usbhid
>usbhid: USB HID core driver
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5: new full speed USB device number 3 using ohci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>hub 3-5:1.0: USB hub found
>hub 3-5:1.0: 3 ports detected
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>asix 1-1:1.0: eth0: register 'asix' at usb-0000:00:04.1-1, ASIX AX88772 USB 2.0 Ethernet, 00:80:c8:3c:f1:93
>usbcore: registered new interface driver asix
>udev[140]: renamed network interface eth0 to eth2
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5.1: new full speed USB device number 4 using ohci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>input: HID 05ac:820a as /devices/pci0000:00/0000:00:04.0/usb3/3-5/3-5.1/3-5.1:1.0/input/input6
>generic-usb 0003:05AC:820A.0003: input,hidraw2: USB HID v1.11 Keyboard [HID 05ac:820a] on usb-0000:00:04.0-5.1/input0
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5.2: new full speed USB device number 5 using ohci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>input: HID 05ac:820b as /devices/pci0000:00/0000:00:04.0/usb3/3-5/3-5.2/3-5.2:1.0/input/input7
>generic-usb 0003:05AC:820B.0004: input,hidraw3: USB HID v1.11 Mouse [HID 05ac:820b] on usb-0000:00:04.0-5.2/input0
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5.3: new full speed USB device number 6 using ohci_hcd
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5.1: USB disconnect, device number 4
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>usb 3-5.2: USB disconnect, device number 5
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>EXT4-fs (sda2): re-mounted. Opts: (null)
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>EXT4-fs (sda4): mounted filesystem with ordered data mode. Opts: (null)
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>asix 1-1:1.0: eth2: link down
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>asix 1-1:1.0: eth2: link up, 100Mbps, full-duplex, lpa 0x45E1
>NET: Registered protocol family 17
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:vblank_disable_fn], disabling vblank on crtc 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>NET: Registered protocol family 10
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm:drm_vblank_get], enabling vblank on crtc 0, ret: 0
>[drm:drm_update_vblank_count], enabling vblank interrupts on crtc 0, missed 0
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>eth2: no IPv6 routers present
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nv50_crtc_commit:498 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - unblanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_calc_timestamping_constants], crtc 5: hwmode: htotal 1800, vtotal 795, vdisplay 768
>[drm:drm_calc_timestamping_constants], crtc 5: clock 85885 kHz framedur 16661610 linedur 20958, pixeldur 11
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:7:eDP-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:6] [NOFB]
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01114000
>[drm:output_poll_execute], [CONNECTOR:7:eDP-1] status updated from 1 to 2
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:output_poll_execute], [CONNECTOR:9:DP-1] status updated from 2 to 2
>[drm:drm_sysfs_hotplug_event], generating hotplug event
>[drm:drm_fb_helper_hotplug_event], 
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:eDP-1]
>[drm] nouveau 0000:02:00.0: nouveau_connector_native_mode:545 - native mode from largest: 0x0@0
>[drm:drm_mode_debug_printmodeline], Modeline 12:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm:drm_mode_prune_invalid], Not using 1368x768 mode -3
>[drm:drm_mode_debug_printmodeline], Modeline 19:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 1024x768 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 18:"848x480" 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 848x480 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 17:"800x600" 0 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 16:"800x600" 0 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[drm:drm_mode_prune_invalid], Not using 800x600 mode 15
>[drm:drm_mode_debug_printmodeline], Modeline 15:"640x480" 0 25175 640 656 752 800 480 489 492 525 0x40 0xa
>[drm:drm_mode_prune_invalid], Not using 640x480 mode 15
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 0 cmd 4 addr 0x50 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:DP-1] disconnected
>[drm:drm_setup_crtcs], 
>[drm:drm_enable_connectors], connector 7 enabled? yes
>[drm:drm_enable_connectors], connector 9 enabled? no
>[drm:drm_target_preferred], looking for cmdline mode on connector 7
>[drm:drm_target_preferred], found mode 1368x768
>[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs], desired mode 1368x768 set on crtc 5
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:5] [FB:14] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:7:eDP-1] to [CRTC:5]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 13:"1368x768" 0 85885 1368 1440 1584 1800 768 769 772 795 0x0 0x6
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_fixup:154 - or 2
>[drm:drm_crtc_helper_set_mode], [CRTC:5]
>[drm] nouveau 0000:02:00.0: nv50_crtc_prepare:485 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:71 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_blank:72 - blanked
>[drm] nouveau 0000:02:00.0: nv50_cursor_hide:79 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_mode_set:608 - index 0
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_dither:141 - 
>[drm] nouveau 0000:02:00.0: nv50_crtc_set_scale:194 - 
>[drm] nouveau 0000:02:00.0: No native mode, forcing panel scaling
>[drm] nouveau 0000:02:00.0: nv50_crtc_do_mode_set_base:526 - index 0
>[drm:drm_crtc_helper_set_mode], [ENCODER:8:TMDS-8] set [MODE:13:1368x768]
>[drm] nouveau 0000:02:00.0: nv50_sor_mode_set:194 - or 2 type 6 -> crtc 0
>[drm] nouveau 0000:02:00.0: nv50_sor_dpms:76 - or 2 type 6 mode 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x600 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000001
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01118000
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:283 - link training!!
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:301 - SOR-2: running DP script 0
>[drm] nouveau 0000:02:00.0: 0x59D8: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x59D8: subop 0x01
>[drm] nouveau 0000:02:00.0: 0x59D8: continuing to execute
>[drm] nouveau 0000:02:00.0: 0x59DB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59DB: Reg: 0x0000E820, Mask: 0xFFFFFEFF, Data: 0x00000100
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0000E820, Data: 0x01010115
>[drm] nouveau 0000:02:00.0: 0x59E8: [ (0x3C) - INIT_OP_3C ]
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Indexed IO read:  Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Indexed IO write: Port: 0x03D4, Index: 0x86, Head: 0x00, Data: 0x04
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00619484, Data: 0x0004FF00
>[drm] nouveau 0000:02:00.0: 0x59EA: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x59EB: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59EB: Reg: 0x6061C10C, Mask: 0xFFFFBFFE, Data: 0x00004001
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x59F8: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x59F8: Reg: 0x6061C128, Mask: 0x7FFFFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D128, Data: 0x95052512
>[drm] nouveau 0000:02:00.0: 0x5A05: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A05: Reg: 0x40614300, Mask: 0xFCFFFFFF, Data: 0x03000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A12: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D00C, Data: 0x01000300
>[drm] nouveau 0000:02:00.0: 0x5A1B: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 0x5A24: [ (0x7A) - INIT_ZM_REG ]
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D014, Data: 0x00020000
>[drm] nouveau 0000:02:00.0: 0x5A2D: [ (0x5B) - INIT_SUB_DIRECT ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: Executing subroutine at 0x498D
>[drm] nouveau 0000:02:00.0: 0x498D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x498D: Reg: 0x0061C814, Mask: 0xFFBFFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C814, Data: 0x00840000
>[drm] nouveau 0000:02:00.0: 0x499A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x499A: Reg: 0x0061C930, Mask: 0xFF7FFFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C930, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 0x49A7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49A7: Reg: 0x0061C810, Mask: 0xFFFFE1FF, Data: 0x00001000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00031000
>[drm] nouveau 0000:02:00.0: 0x49B4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49B4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49B7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49B7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 0x49B7: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49B7: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x49B9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49B9: Reg: 0x0061C810, Mask: 0xFFFFEFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00039000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038000
>[drm] nouveau 0000:02:00.0: 0x49C6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49C7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49C7: Reg: 0x0061C810, Mask: 0xFFFFF7FF, Data: 0x00000800
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030000
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49D4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49D7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49D7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 0x49D7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49D7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49D9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E6: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x49E6: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x49E7: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x49E7: Reg: 0x0061C810, Mask: 0xFFFFFBFF, Data: 0x00000400
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030800
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F4: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x49F4: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x49F7: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x49F7: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 0x49F7: Checking if 0x00000000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x49F7: Condition not fulfilled -- skipping following commands
>[drm] nouveau 0000:02:00.0: 0x49F9: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A06: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A06: ---- Executing following commands ----
>[drm] nouveau 0000:02:00.0: 0x4A07: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A07: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000200
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00030E00
>[drm] nouveau 0000:02:00.0: 0x4A14: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x4A14: Sleeping for 0x0064 microseconds
>[drm] nouveau 0000:02:00.0: 0x4A17: [ (0x75) - INIT_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition: 0x0E
>[drm] nouveau 0000:02:00.0: 0x4A17: Cond: 0x0E, Reg: 0x0061C810, Mask: 0x00008000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 0x4A17: Checking if 0x00008000 equals 0x00008000
>[drm] nouveau 0000:02:00.0: 0x4A17: Condition fulfilled -- continuing to execute
>[drm] nouveau 0000:02:00.0: 0x4A19: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A19: Reg: 0x0061C810, Mask: 0xFFFFFDFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00038E00
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061C810, Data: 0x00038C00
>[drm] nouveau 0000:02:00.0: 0x4A26: [ (0x72) - INIT_RESUME ]
>[drm] nouveau 0000:02:00.0: 0x4A27: [ (0x5F) - INIT_COPY_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x4A27: SrcReg: 0x0061C810, Shift: 0x00, SrcMask: 0x00001E00, Xor: 0x00000000, DstReg: 0x0061D010, DstMask: 0xFFFFE1FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061C810, Data: 0x00030C00
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D010, Data: 0x0030152F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D010, Data: 0x00300D2F
>[drm] nouveau 0000:02:00.0: 0x4A3D: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: 0x5A2D: End of 0x498D subroutine
>[drm] nouveau 0000:02:00.0: 0x5A30: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A30: Reg: 0x40614300, Mask: 0xFFFCFFFF, Data: 0x00010000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x00615300, Data: 0x03814040
>[drm] nouveau 0000:02:00.0: 0x5A3D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A3D: Reg: 0x6061C130, Mask: 0xFFBFFF00, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 0x5A4A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A4A: Reg: 0x6061C034, Mask: 0x7FEEFFFF, Data: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D034, Data: 0x800013E8
>[drm] nouveau 0000:02:00.0: 0x5A57: [ (0x74) - INIT_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A57: Sleeping for 0x000A microseconds
>[drm] nouveau 0000:02:00.0: 0x5A5A: [ (0x56) - INIT_CONDITION_TIME ]
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition: 0x0B, Retries: 0x64
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5A: Condition met, continuing
>[drm] nouveau 0000:02:00.0: 0x5A5A: Cond: 0x0B, Reg: 0x4061C034, Mask: 0x80000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D034, Data: 0x000013E8
>[drm] nouveau 0000:02:00.0: 0x5A5A: Checking if 0x00000000 equals 0x00000000
>[drm] nouveau 0000:02:00.0: 0x5A5D: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A5D: Reg: 0x6061C130, Mask: 0xFFFFFF0F, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D130, Data: 0x004000FF
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D130, Data: 0x0040000F
>[drm] nouveau 0000:02:00.0: 0x5A6A: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A6A: Reg: 0x6061C10C, Mask: 0xFCFFCFFF, Data: 0x00000000
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D10C, Data: 0x004140FD
>[drm] nouveau 0000:02:00.0: 0x5A77: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x102 len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A7F: [ (0x3A) - INIT_DP_CONDITION ]
>[drm] nouveau 0000:02:00.0: 0x5A7F: subop 0x05
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0xd len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: 0x5A7F: auxch rd fail: -16
>[drm] nouveau 0000:02:00.0: 0x5A82: [ (0x6E) - INIT_NV_REG ]
>[drm] nouveau 0000:02:00.0: 0x5A82: Reg: 0x6061C140, Mask: 0xFFFFFFFD, Data: 0x00000002
>[drm] nouveau 0000:02:00.0: 	Read:  Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 	Write: Reg: 0x0061D140, Data: 0x00000003
>[drm] nouveau 0000:02:00.0: 0x5A8F: [ (0x98) - INIT_AUXCH ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 9 addr 0x10a len 1
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: expected bit 16 == 0, got 0x01119000
>[drm] nouveau 0000:02:00.0: INIT_AUXCH: rd auxch fail -16
>[drm] nouveau 0000:02:00.0: 0x5A97: [ (0x71) - INIT_DONE ]
>[drm] nouveau 0000:02:00.0: nouveau_dp_link_train:311 - 	begin train: bw 0, lanes 0
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:487 - ch 1 cmd 8 addr 0x100 len 1
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 0: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 1: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 2: 0x00000000
>[drm] nouveau 0000:02:00.0: nouveau_dp_auxch:513 - wr 3: 0x00000000
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004
>[drm] nouveau 0000:02:00.0: nv50_display_isr:952 - PDISPLAY_INTR 0x00000000 0x00000004

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Attachments on bug 31676: 40329 | 40330 | 40331 | 41174 | 41176 | 44747 | 47868

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