Attachment 60605 Details for Bug 44006 – Periodically sanity check powermanagement

[patch] Periodically sanity check powermanagement

0001-drm-i915-Periodically-sanity-check-power-management.patch (text/plain), 4.93 KB, created by Chris Wilson on 2012-04-26 02:18:27 UTC

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Creator: Chris Wilson

Created: 2012-04-26 02:18:27 UTC

Size: 4.93 KB

patch

obsolete

>From 9abdcdf185d27344153c3a16af7618aed67bf618 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Thu, 26 Apr 2012 09:33:16 +0100
>Subject: [PATCH] drm/i915: Periodically sanity check power management
>
>Every time we use the device after a period of idleness, check that the
>power management setup is still sane. This is to workaround a bug
>whereby it seems that we begin suppressing power management interrupts,
>preventing SandyBridge+ from going into turbo mode.
>
>References: https://bugs.freedesktop.org/show_bug.cgi?id=44006
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_drv.h      |    1 +
> drivers/gpu/drm/i915/intel_display.c |    8 +++----
> drivers/gpu/drm/i915/intel_drv.h     |    2 ++
> drivers/gpu/drm/i915/intel_pm.c      |   38 ++++++++++++++++++++++++++++++++++
> 4 files changed, 44 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 6b6eb49..bf34316 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -240,6 +240,7 @@ struct drm_i915_display_funcs {
> 	void (*update_wm)(struct drm_device *dev);
> 	void (*update_sprite_wm)(struct drm_device *dev, int pipe,
> 				 uint32_t sprite_width, int pixel_size);
>+	void (*sanitize_pm)(struct drm_device *dev);
> 	int (*crtc_mode_set)(struct drm_crtc *crtc,
> 			     struct drm_display_mode *mode,
> 			     struct drm_display_mode *adjusted_mode,
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 05c6e66..40fac16 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -4982,9 +4982,6 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
> 		else
> 			i9xx_update_cursor(crtc, base);
> 	}
>-
>-	if (visible)
>-		intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
> }
> 
> static int intel_crtc_cursor_set(struct drm_crtc *crtc,
>@@ -5697,9 +5694,10 @@ void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
> 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
> 		return;
> 
>-	if (!dev_priv->busy)
>+	if (!dev_priv->busy) {
>+		intel_sanitize_pm(dev);
> 		dev_priv->busy = true;
>-	else
>+	} else
> 		mod_timer(&dev_priv->idle_timer, jiffies +
> 			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
> 
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index b4d39f2..a57f0fb 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -351,6 +351,8 @@ void intel_plane_cleanup(struct intel_plane *plane);
> extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
> 				      enum plane plane);
> 
>+void intel_sanitize_pm(struct drm_device *dev);
>+
> /* intel_panel.c */
> extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
> 				   struct drm_display_mode *adjusted_mode);
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 3b05ba3..ee44889 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2938,6 +2938,42 @@ void intel_init_clock_gating(struct drm_device *dev)
> 		dev_priv->display.init_pch_clock_gating(dev);
> }
> 
>+static void gen6_sanitize_pm(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	u32 limits, delay, old;
>+
>+	gen6_gt_force_wake_get(dev_priv);
>+
>+	old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
>+	/* Make sure we continue to get interrupts
>+	 * until we hit the minimum or maximum frequencies.
>+	 */
>+	limits &= ~(0x3f << 16 | 0x3f << 24);
>+	delay = dev_priv->cur_delay;
>+	if (delay < dev_priv->max_delay)
>+		limits |= (dev_priv->max_delay & 0x3f) << 24;
>+	if (delay > dev_priv->min_delay)
>+		limits |= (dev_priv->min_delay & 0x3f) << 16;
>+
>+	if (old != limits) {
>+		DRM_ERROR("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS expected %08x, was %08x\n",
>+			  limits, old);
>+		I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
>+	}
>+
>+	gen6_gt_force_wake_put(dev_priv);
>+}
>+
>+void intel_sanitize_pm(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
>+	if (dev_priv->display.sanitize_pm)
>+		dev_priv->display.sanitize_pm(dev);
>+}
>+
> /* Set up chip specific power management-related functions */
> void intel_init_pm(struct drm_device *dev)
> {
>@@ -3014,6 +3050,7 @@ void intel_init_pm(struct drm_device *dev)
> 				dev_priv->display.update_wm = NULL;
> 			}
> 			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
>+			dev_priv->display.sanitize_pm = gen6_sanitize_pm;
> 		} else if (IS_IVYBRIDGE(dev)) {
> 			/* FIXME: detect B0+ stepping and use auto training */
> 			if (SNB_READ_WM0_LATENCY()) {
>@@ -3025,6 +3062,7 @@ void intel_init_pm(struct drm_device *dev)
> 				dev_priv->display.update_wm = NULL;
> 			}
> 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
>+			dev_priv->display.sanitize_pm = gen6_sanitize_pm;
> 		} else
> 			dev_priv->display.update_wm = NULL;
> 	} else if (IS_VALLEYVIEW(dev)) {
>-- 
>1.7.10
>

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Attachments on bug 44006: 54669 | 54671 | 54695 | 54696 | 54781 | 54782 | 58796 | 58797 | 58798 | 60586 | 60601 | 60602 | 60603 | 60605 | 60664

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