Attachment 70400 Details for Bug 57388 – dmesg info with testdisplay

dmesg info with testdisplay

dmesg20121122ivb4.log (text/plain), 605.79 KB, created by Guang Yang on 2012-11-22 03:06:30 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Guang Yang

Created: 2012-11-22 03:06:30 UTC

Size: 605.79 KB

patch

obsolete

><7>[   55.305154] [drm:i915_driver_open], 
><7>[   55.305184] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
><7>[   55.305190] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   55.305192] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   55.305194] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   55.305197] [drm:intel_crtc_set_config], [CRTC:5] [FB:102] #connectors=1 (x y) (0 0)
><7>[   55.305200] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   55.305201] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   55.305203] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   55.305205] [drm:intel_crtc_set_config], [CRTC:7] [FB:102] #connectors=1 (x y) (0 0)
><7>[   55.305208] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   55.305210] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   55.305211] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   55.305216] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   55.305218] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   55.305220] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[   55.305223] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   55.305225] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   55.305226] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[   55.305229] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   55.305231] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   55.305232] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[   55.305244] [drm:i915_driver_open], 
><7>[   55.305920] [drm:i915_driver_open], 
><7>[   55.306070] [drm:i915_driver_open], 
><7>[   55.306174] [drm:i915_driver_open], 
><7>[   55.306203] [drm:i915_driver_open], 
><7>[   55.306298] [drm:i915_driver_open], 
><7>[   55.306343] [drm:i915_driver_open], 
><7>[   55.306375] [drm:i915_driver_open], 
><7>[   55.306453] [drm:i915_driver_open], 
><7>[   55.306656] [drm:i915_driver_open], 
><7>[   55.306722] [drm:i915_driver_open], 
><7>[   55.306767] [drm:i915_driver_open], 
><7>[   55.306790] [drm:i915_driver_open], 
><7>[   55.306860] [drm:i915_driver_open], 
><7>[   55.306945] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.306988] [drm:i915_driver_open], 
><7>[   55.307015] [drm:i915_driver_open], 
><7>[   55.307088] [drm:i915_driver_open], 
><7>[   55.307156] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.307193] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.307233] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.307276] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.307393] [drm:i915_driver_open], 
><7>[   55.307503] [drm:i915_driver_open], 
><7>[   55.307542] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.307590] [drm:i915_driver_open], 
><7>[   55.307625] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.309220] [drm:i915_driver_open], 
><7>[   55.309419] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.309593] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   55.309728] [drm:i915_gem_context_create_ioctl], HW context 1 created
><7>[   56.192916] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.198479] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.208571] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.223186] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.224482] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.228543] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.229190] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.229872] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.232606] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.239987] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
><7>[   56.602605] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
><7>[   56.602618] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   56.602622] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   56.602626] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   56.602630] [drm:intel_crtc_set_config], [CRTC:5] [FB:102] #connectors=1 (x y) (0 0)
><7>[   56.602634] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   56.602637] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   56.602640] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   56.602644] [drm:intel_crtc_set_config], [CRTC:7] [FB:102] #connectors=1 (x y) (0 0)
><7>[   56.602647] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[   56.602650] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[   56.602653] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[   56.602661] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   56.602664] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   56.602667] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[   56.602671] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   56.602674] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   56.602676] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[   56.602680] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[   56.602683] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[   56.602686] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  623.014452] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  623.014458] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[  623.014462] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[  623.014468] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  623.014472] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  623.014475] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  623.014479] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  623.014482] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  623.014485] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  623.014487] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  623.014489] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  623.029855] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  623.064167] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 2, on? 1) for crtc 5
><7>[  623.064377] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  623.064379] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  623.064381] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  623.064387] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  623.064393] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[  623.064398] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  623.064402] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  623.064405] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  623.064409] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  623.064412] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  623.064415] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  623.064417] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  623.064419] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  623.066097] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  623.100120] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 7
><7>[  623.100122] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[  623.100534] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  623.100537] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  623.100539] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  623.100545] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  623.100552] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  623.100555] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  623.100559] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  623.100562] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  623.100566] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  623.100568] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  623.100570] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  623.100572] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  943.366568] [drm:i915_driver_open], 
><7>[  943.366597] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
><7>[  943.366603] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  943.366605] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  943.366607] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  943.366610] [drm:intel_crtc_set_config], [CRTC:5] [FB:102] #connectors=1 (x y) (0 0)
><7>[  943.366613] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  943.366614] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  943.366616] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  943.366618] [drm:intel_crtc_set_config], [CRTC:7] [FB:102] #connectors=1 (x y) (0 0)
><7>[  943.366621] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  943.366623] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  943.366624] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  943.366629] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  943.366631] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  943.366633] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  943.366635] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  943.366637] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  943.366639] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  943.366642] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  943.366643] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  943.366645] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  943.366656] [drm:i915_driver_open], 
><7>[  943.366836] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
><7>[  943.366845] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
><7>[  943.366855] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
><7>[  943.366859] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
><7>[  943.366864] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x82f40010, result 1
><7>[  943.366866] [drm:intel_crt_detect], CRT detected via hotplug
><7>[  943.404299] [drm:drm_edid_to_eld], ELD: no CEA Extension found
><7>[  943.404352] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
><7>[  943.404355] [drm:drm_mode_debug_printmodeline], Modeline 22:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
><7>[  943.404361] [drm:drm_mode_debug_printmodeline], Modeline 51:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[  943.404365] [drm:drm_mode_debug_printmodeline], Modeline 45:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[  943.404369] [drm:drm_mode_debug_printmodeline], Modeline 44:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
><7>[  943.404374] [drm:drm_mode_debug_printmodeline], Modeline 50:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[  943.404378] [drm:drm_mode_debug_printmodeline], Modeline 29:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  943.404382] [drm:drm_mode_debug_printmodeline], Modeline 24:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  943.404386] [drm:drm_mode_debug_printmodeline], Modeline 47:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[  943.404390] [drm:drm_mode_debug_printmodeline], Modeline 46:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
><7>[  943.404394] [drm:drm_mode_debug_printmodeline], Modeline 42:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[  943.404399] [drm:drm_mode_debug_printmodeline], Modeline 49:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
><7>[  943.404403] [drm:drm_mode_debug_printmodeline], Modeline 43:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[  943.404407] [drm:drm_mode_debug_printmodeline], Modeline 41:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[  943.404411] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
><7>[  943.404415] [drm:drm_mode_debug_printmodeline], Modeline 23:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[  943.404419] [drm:drm_mode_debug_printmodeline], Modeline 39:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[  943.404423] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
><7>[  943.404427] [drm:drm_mode_debug_printmodeline], Modeline 30:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[  943.404431] [drm:drm_mode_debug_printmodeline], Modeline 37:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[  943.404435] [drm:drm_mode_debug_printmodeline], Modeline 31:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[  943.404440] [drm:drm_mode_debug_printmodeline], Modeline 48:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[  943.404444] [drm:drm_mode_debug_printmodeline], Modeline 35:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[  943.404448] [drm:drm_mode_debug_printmodeline], Modeline 32:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[  943.404452] [drm:drm_mode_debug_printmodeline], Modeline 25:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[  943.404456] [drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[  943.404460] [drm:drm_mode_debug_printmodeline], Modeline 36:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[  943.404464] [drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
><7>[  943.404468] [drm:drm_mode_debug_printmodeline], Modeline 26:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[  943.404473] [drm:drm_mode_debug_printmodeline], Modeline 27:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[  943.404477] [drm:drm_mode_debug_printmodeline], Modeline 28:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[  943.404494] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
><7>[  943.563082] [drm:drm_mode_addfb], [FB:138]
><7>[  943.563127] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  943.563134] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  943.563136] [drm:intel_crtc_set_config], [CRTC:3] [FB:138] #connectors=1 (x y) (0 0)
><7>[  943.563140] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  943.563142] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  943.563144] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  943.566660] [drm:ironlake_update_plane], Writing base 0085C000 00000000 0 0 6720
><7>[  943.578791] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  948.620964] [drm:drm_mode_addfb], [FB:141]
><7>[  948.620993] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  948.620999] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  948.621002] [drm:intel_crtc_set_config], [CRTC:3] [FB:141] #connectors=1 (x y) (0 0)
><7>[  948.621005] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  948.621007] [drm:drm_mode_debug_printmodeline], Modeline 56:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
><7>[  948.621010] [drm:drm_mode_debug_printmodeline], Modeline 146:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[  948.621013] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  948.621016] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  948.621018] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  948.621019] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  948.621021] [drm:drm_mode_debug_printmodeline], Modeline 146:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[  948.621024] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  948.621027] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  948.634432] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  948.668451] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  948.668458] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  948.668877] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  948.668880] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  948.668883] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  948.668921] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  948.668924] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  948.668926] [drm:drm_mode_debug_printmodeline], Modeline 146:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[  948.668931] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  948.668934] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  948.669249] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  948.719343] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  948.723654] [drm:ironlake_update_plane], Writing base 00F17000 00000000 0 0 6720
><7>[  948.775258] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  948.775276] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  948.775279] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  948.775281] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  948.775285] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:146:1680x945]
><7>[  948.775289] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  948.775292] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  948.775294] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  948.827257] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  948.879193] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  948.879354] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  948.880016] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  948.880020] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  948.880679] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  948.880683] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  948.880686] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  948.880688] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  948.880692] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  948.898516] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  948.900136] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  948.900156] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  948.900161] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  948.900166] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  948.900170] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  948.900174] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  948.900178] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  948.900181] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  948.900183] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  953.371236] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x82f40010, result 1
><7>[  953.371241] [drm:intel_crt_detect], CRT detected via hotplug
><7>[  953.371244] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 1 to 1
><7>[  953.443144] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[  953.443150] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-1] status updated from 1 to 1
><7>[  953.515069] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[  953.515075] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 1 to 1
><7>[  953.517631] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.521603] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.525620] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.527040] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[  953.527046] [drm:output_poll_execute], [CONNECTOR:18:DP-1] status updated from 2 to 2
><7>[  953.529600] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.533591] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.537576] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[  953.539018] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[  953.539022] [drm:output_poll_execute], [CONNECTOR:20:DP-2] status updated from 2 to 2
><7>[  953.938648] [drm:drm_mode_addfb], [FB:146]
><7>[  953.938676] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  953.938683] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  953.938685] [drm:intel_crtc_set_config], [CRTC:3] [FB:146] #connectors=1 (x y) (0 0)
><7>[  953.938688] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  953.938690] [drm:drm_mode_debug_printmodeline], Modeline 146:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[  953.938693] [drm:drm_mode_debug_printmodeline], Modeline 147:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[  953.938697] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  953.938699] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  953.938701] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  953.938702] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  953.938704] [drm:drm_mode_debug_printmodeline], Modeline 147:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[  953.938707] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  953.938710] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  953.954842] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  953.989546] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  953.989552] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  953.989966] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  953.989969] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  953.989972] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  953.990009] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  953.990013] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  953.990015] [drm:drm_mode_debug_printmodeline], Modeline 147:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[  953.990020] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  953.990023] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  953.990338] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  954.041513] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  954.045431] [drm:ironlake_update_plane], Writing base 01526000 00000000 0 0 5632
><7>[  954.096434] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  954.096441] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  954.096445] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  954.096448] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  954.096452] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:147:1400x1050]
><7>[  954.096457] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  954.096460] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  954.096463] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  954.148396] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  954.200354] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  954.200526] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  954.201187] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  954.201191] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  954.201849] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  954.201853] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  954.201856] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  954.201858] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  954.201863] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  954.216468] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  954.217333] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  954.217342] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  954.217347] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  954.217351] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  954.217366] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  954.217371] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  954.217375] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  954.217377] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  954.217380] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  959.254086] [drm:drm_mode_addfb], [FB:147]
><7>[  959.254114] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  959.254120] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  959.254122] [drm:intel_crtc_set_config], [CRTC:3] [FB:147] #connectors=1 (x y) (0 0)
><7>[  959.254125] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  959.254127] [drm:drm_mode_debug_printmodeline], Modeline 147:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[  959.254130] [drm:drm_mode_debug_printmodeline], Modeline 148:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
><7>[  959.254134] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  959.254136] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  959.254138] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  959.254140] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  959.254141] [drm:drm_mode_debug_printmodeline], Modeline 148:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
><7>[  959.254144] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  959.254147] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  959.259874] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  959.287761] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  959.287768] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  959.288181] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  959.288184] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  959.288187] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  959.288224] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  959.288227] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  959.288230] [drm:drm_mode_debug_printmodeline], Modeline 148:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
><7>[  959.288234] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  959.288237] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  959.288552] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  959.339697] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  959.343057] [drm:ironlake_update_plane], Writing base 01ACA000 00000000 0 0 5632
><7>[  959.393611] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  959.393618] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  959.393622] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  959.393625] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  959.393629] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:148:1400x1050]
><7>[  959.393634] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  959.393637] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  959.393640] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  959.445589] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  959.497525] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  959.497686] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  959.498348] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  959.498352] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  959.499010] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  959.499015] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  959.499017] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  959.499020] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  959.499024] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  959.516982] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  959.518487] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  959.518506] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  959.518511] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  959.518516] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  959.518520] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  959.518524] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  959.518528] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  959.518531] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  959.518534] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  964.556496] [drm:drm_mode_addfb], [FB:148]
><7>[  964.556524] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  964.556530] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  964.556532] [drm:intel_crtc_set_config], [CRTC:3] [FB:148] #connectors=1 (x y) (0 0)
><7>[  964.556536] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  964.556538] [drm:drm_mode_debug_printmodeline], Modeline 148:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
><7>[  964.556541] [drm:drm_mode_debug_printmodeline], Modeline 149:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[  964.556545] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  964.556547] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  964.556549] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  964.556551] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  964.556552] [drm:drm_mode_debug_printmodeline], Modeline 149:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[  964.556555] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  964.556558] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  964.556868] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  964.590942] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  964.590948] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  964.591362] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  964.591365] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  964.591368] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  964.591404] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  964.591408] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  964.591410] [drm:drm_mode_debug_printmodeline], Modeline 149:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[  964.591415] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  964.591418] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  964.591732] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  964.642866] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  964.647433] [drm:ironlake_update_plane], Writing base 0206E000 00000000 0 0 6400
><7>[  964.698825] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  964.698832] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  964.698836] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  964.698839] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  964.698843] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:149:1600x900]
><7>[  964.698848] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  964.698851] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  964.698854] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  964.750760] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  964.802678] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  964.802839] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  964.803500] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  964.803504] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  964.804161] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  964.804165] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  964.804167] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  964.804169] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  964.804174] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  964.822156] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  964.823677] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  964.823687] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  964.823692] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  964.823697] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  964.823701] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  964.823705] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  964.823709] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  964.823711] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  964.823714] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  969.860370] [drm:drm_mode_addfb], [FB:149]
><7>[  969.860397] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  969.860403] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  969.860406] [drm:intel_crtc_set_config], [CRTC:3] [FB:149] #connectors=1 (x y) (0 0)
><7>[  969.860409] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  969.860411] [drm:drm_mode_debug_printmodeline], Modeline 149:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[  969.860414] [drm:drm_mode_debug_printmodeline], Modeline 150:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  969.860417] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  969.860419] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  969.860421] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  969.860423] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  969.860425] [drm:drm_mode_debug_printmodeline], Modeline 150:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  969.860428] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  969.860431] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  969.871050] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  969.906092] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  969.906098] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  969.906511] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  969.906514] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  969.906517] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  969.906554] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  969.906557] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  969.906560] [drm:drm_mode_debug_printmodeline], Modeline 150:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  969.906565] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  969.906567] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  969.906882] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  969.958029] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  969.961521] [drm:ironlake_update_plane], Writing base 025ED000 00000000 0 0 5120
><7>[  970.012966] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  970.012973] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  970.012977] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  970.012980] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  970.012984] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:150:1280x1024]
><7>[  970.012989] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  970.012992] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  970.012995] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  970.064911] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  970.116854] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  970.117015] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  970.117677] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  970.117681] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  970.118339] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  970.118343] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  970.118346] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  970.118348] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  970.118353] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  970.132947] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  970.133842] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  970.133852] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  970.133857] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  970.133862] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  970.133865] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  970.133871] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  970.133878] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  970.133883] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  970.133886] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  975.171947] [drm:drm_mode_addfb], [FB:150]
><7>[  975.171971] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  975.171977] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  975.171980] [drm:intel_crtc_set_config], [CRTC:3] [FB:150] #connectors=1 (x y) (0 0)
><7>[  975.171982] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  975.171984] [drm:drm_mode_debug_printmodeline], Modeline 150:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  975.171987] [drm:drm_mode_debug_printmodeline], Modeline 151:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  975.171990] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  975.171992] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  975.171994] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  975.171996] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  975.171998] [drm:drm_mode_debug_printmodeline], Modeline 151:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  975.172001] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  975.172004] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  975.179048] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  975.207267] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  975.207273] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  975.207686] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  975.207689] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  975.207692] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  975.207714] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  975.207718] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  975.207720] [drm:drm_mode_debug_printmodeline], Modeline 151:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  975.207725] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  975.207728] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  975.208043] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  975.259204] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  975.263326] [drm:ironlake_update_plane], Writing base 02AED000 00000000 0 0 5120
><7>[  975.315108] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  975.315116] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  975.315119] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  975.315122] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  975.315126] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:151:1280x1024]
><7>[  975.315132] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  975.315135] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  975.315137] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  975.367085] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  975.419028] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  975.419189] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  975.419850] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  975.419854] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  975.420511] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  975.420516] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  975.420518] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  975.420521] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  975.420525] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  975.438446] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  975.439970] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  975.439981] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  975.439986] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  975.439990] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  975.439995] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  975.439999] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  975.440003] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  975.440005] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  975.440008] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  980.484071] [drm:drm_mode_addfb], [FB:151]
><7>[  980.484104] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  980.484112] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  980.484114] [drm:intel_crtc_set_config], [CRTC:3] [FB:151] #connectors=1 (x y) (0 0)
><7>[  980.484118] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  980.484120] [drm:drm_mode_debug_printmodeline], Modeline 151:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[  980.484123] [drm:drm_mode_debug_printmodeline], Modeline 152:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[  980.484127] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  980.484129] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  980.484131] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  980.484134] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  980.484135] [drm:drm_mode_debug_printmodeline], Modeline 152:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[  980.484139] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  980.484142] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  980.497800] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  980.532374] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  980.532380] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  980.532794] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  980.532797] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  980.532801] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  980.532839] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  980.532843] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  980.532845] [drm:drm_mode_debug_printmodeline], Modeline 152:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[  980.532851] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  980.532853] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  980.533168] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  980.584313] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  980.586998] [drm:ironlake_update_plane], Writing base 02FED000 00000000 0 0 5760
><7>[  980.638256] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  980.638268] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  980.638272] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  980.638275] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  980.638280] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:152:1440x900]
><7>[  980.638286] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  980.638289] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  980.638292] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  980.690200] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  980.742139] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  980.742301] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  980.742963] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  980.742967] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  980.743634] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  980.743639] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  980.743641] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  980.743644] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  980.743649] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  980.758235] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  980.760131] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  980.760142] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  980.760147] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  980.760152] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  980.760156] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  980.760160] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  980.760165] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  980.760168] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  980.760170] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  985.798945] [drm:drm_mode_addfb], [FB:152]
><7>[  985.798974] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  985.798981] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  985.798983] [drm:intel_crtc_set_config], [CRTC:3] [FB:152] #connectors=1 (x y) (0 0)
><7>[  985.798987] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  985.798989] [drm:drm_mode_debug_printmodeline], Modeline 152:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[  985.798992] [drm:drm_mode_debug_printmodeline], Modeline 153:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
><7>[  985.798996] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  985.798998] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  985.799000] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  985.799002] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  985.799003] [drm:drm_mode_debug_printmodeline], Modeline 153:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
><7>[  985.799007] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  985.799010] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  985.802978] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  985.830593] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  985.830600] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  985.831013] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[  985.831016] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  985.831019] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  985.831043] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  985.831047] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  985.831049] [drm:drm_mode_debug_printmodeline], Modeline 153:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
><7>[  985.831054] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  985.831057] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  985.831372] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  985.882496] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  985.885560] [drm:ironlake_update_plane], Writing base 034DF000 00000000 0 0 5760
><7>[  985.937468] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  985.937476] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[  985.937480] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  985.937483] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  985.937487] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:153:1440x900]
><7>[  985.937493] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[  985.937496] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  985.937498] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  985.989413] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  986.041356] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  986.041516] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  986.042178] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  986.042182] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  986.042839] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  986.042844] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  986.042846] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  986.042849] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  986.042853] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  986.060784] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  986.062341] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  986.062351] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  986.062356] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  986.062360] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  986.062365] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  986.062369] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  986.062373] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  986.062375] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  986.062378] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  991.097901] [drm:drm_mode_addfb], [FB:153]
><7>[  991.097927] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  991.097932] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  991.097934] [drm:intel_crtc_set_config], [CRTC:3] [FB:153] #connectors=1 (x y) (0 0)
><7>[  991.097937] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  991.097939] [drm:drm_mode_debug_printmodeline], Modeline 153:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
><7>[  991.097942] [drm:drm_mode_debug_printmodeline], Modeline 154:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[  991.097945] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  991.097947] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  991.097949] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  991.097951] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  991.097952] [drm:drm_mode_debug_printmodeline], Modeline 154:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[  991.097955] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  991.097958] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  991.106762] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  991.141757] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  991.141764] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  991.142176] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[  991.142179] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  991.142182] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  991.142205] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  991.142208] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  991.142211] [drm:drm_mode_debug_printmodeline], Modeline 154:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[  991.142216] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  991.142218] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  991.142533] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  991.193695] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  991.196660] [drm:ironlake_update_plane], Writing base 039D1000 00000000 0 0 5120
><7>[  991.248601] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  991.248609] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  991.248612] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  991.248615] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  991.248619] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:154:1280x960]
><7>[  991.248624] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  991.248627] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  991.248630] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  991.300578] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  991.352521] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  991.352682] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  991.353344] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  991.353348] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  991.354006] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  991.354010] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  991.354012] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  991.354015] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  991.354020] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  991.371946] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  991.373505] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  991.373515] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  991.373520] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  991.373525] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  991.373529] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  991.373533] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  991.373537] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  991.373540] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  991.373542] [drm:intel_modeset_check_state], [CRTC:7]
><7>[  996.409955] [drm:drm_mode_addfb], [FB:154]
><7>[  996.409979] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[  996.409985] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[  996.409987] [drm:intel_crtc_set_config], [CRTC:3] [FB:154] #connectors=1 (x y) (0 0)
><7>[  996.409990] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[  996.409991] [drm:drm_mode_debug_printmodeline], Modeline 154:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[  996.409995] [drm:drm_mode_debug_printmodeline], Modeline 155:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
><7>[  996.409998] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[  996.410000] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[  996.410002] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[  996.410004] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[  996.410005] [drm:drm_mode_debug_printmodeline], Modeline 155:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
><7>[  996.410008] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[  996.410011] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[  996.416368] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  996.449926] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[  996.449932] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[  996.450345] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[  996.450348] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  996.450351] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  996.450373] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[  996.450376] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[  996.450379] [drm:drm_mode_debug_printmodeline], Modeline 155:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
><7>[  996.450384] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[  996.450387] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[  996.450701] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[  996.501830] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  996.504196] [drm:ironlake_update_plane], Writing base 03E81000 00000000 0 0 5504
><7>[  996.555801] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  996.555809] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[  996.555812] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  996.555815] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  996.555820] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:155:1366x768]
><7>[  996.555825] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[  996.555828] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[  996.555831] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[  996.607746] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  996.659689] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[  996.659850] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[  996.660512] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[  996.660516] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[  996.661174] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[  996.661178] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[  996.661181] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[  996.661183] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[  996.661188] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[  996.679086] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[  996.680674] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[  996.680684] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[  996.680689] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[  996.680693] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[  996.680697] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[  996.680701] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[  996.680705] [drm:intel_modeset_check_state], [CRTC:3]
><7>[  996.680708] [drm:intel_modeset_check_state], [CRTC:5]
><7>[  996.680710] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1001.715156] [drm:drm_mode_addfb], [FB:155]
><7>[ 1001.715180] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1001.715186] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1001.715188] [drm:intel_crtc_set_config], [CRTC:3] [FB:155] #connectors=1 (x y) (0 0)
><7>[ 1001.715191] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1001.715192] [drm:drm_mode_debug_printmodeline], Modeline 155:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
><7>[ 1001.715195] [drm:drm_mode_debug_printmodeline], Modeline 156:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1001.715199] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1001.715201] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1001.715203] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1001.715204] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1001.715206] [drm:drm_mode_debug_printmodeline], Modeline 156:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1001.715209] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1001.715212] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1001.715264] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1001.749102] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1001.749108] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1001.749521] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1001.749524] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1001.749527] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1001.749563] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1001.749566] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1001.749569] [drm:drm_mode_debug_printmodeline], Modeline 156:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1001.749573] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1001.749576] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1001.749889] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1001.801041] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1001.803405] [drm:ironlake_update_plane], Writing base 04289000 00000000 0 0 5440
><7>[ 1001.854979] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1001.854986] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1001.854990] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1001.854993] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1001.854997] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:156:1360x768]
><7>[ 1001.855002] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1001.855005] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1001.855008] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1001.906895] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1001.958868] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1001.959029] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1001.959690] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1001.959694] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1001.960352] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1001.960357] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1001.960359] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1001.960361] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1001.960366] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1001.978287] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1001.979851] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1001.979861] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1001.979866] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1001.979871] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1001.979875] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1001.979879] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1001.979883] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1001.979886] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1001.979888] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1007.016239] [drm:drm_mode_addfb], [FB:156]
><7>[ 1007.016283] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1007.016289] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1007.016291] [drm:intel_crtc_set_config], [CRTC:3] [FB:156] #connectors=1 (x y) (0 0)
><7>[ 1007.016297] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1007.016300] [drm:drm_mode_debug_printmodeline], Modeline 156:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1007.016305] [drm:drm_mode_debug_printmodeline], Modeline 157:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1007.016309] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1007.016311] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1007.016313] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1007.016315] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1007.016316] [drm:drm_mode_debug_printmodeline], Modeline 157:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1007.016319] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1007.016322] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1007.021435] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1007.056271] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1007.056278] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1007.056691] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1007.056694] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1007.056697] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1007.056719] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1007.056722] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1007.056725] [drm:drm_mode_debug_printmodeline], Modeline 157:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1007.056730] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1007.056733] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1007.057047] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1007.108209] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1007.110523] [drm:ironlake_update_plane], Writing base 04685000 00000000 0 0 5120
><7>[ 1007.162148] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1007.162155] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1007.162159] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1007.162162] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1007.162166] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:157:1280x800]
><7>[ 1007.162171] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1007.162174] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1007.162177] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1007.214093] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1007.266036] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1007.266198] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1007.266860] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1007.266864] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1007.267522] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1007.267526] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1007.267528] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1007.267531] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1007.267535] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1007.282124] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1007.283053] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1007.283064] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1007.283069] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1007.283074] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1007.283078] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1007.283082] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1007.283086] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1007.283089] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1007.283091] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1012.319782] [drm:drm_mode_addfb], [FB:157]
><7>[ 1012.319806] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1012.319811] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1012.319813] [drm:intel_crtc_set_config], [CRTC:3] [FB:157] #connectors=1 (x y) (0 0)
><7>[ 1012.319816] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1012.319817] [drm:drm_mode_debug_printmodeline], Modeline 157:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1012.319821] [drm:drm_mode_debug_printmodeline], Modeline 158:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
><7>[ 1012.319824] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1012.319826] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1012.319828] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1012.319830] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1012.319831] [drm:drm_mode_debug_printmodeline], Modeline 158:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
><7>[ 1012.319834] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1012.319837] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1012.326406] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1012.353451] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1012.353458] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1012.353870] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1012.353873] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1012.353876] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1012.353911] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1012.353915] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1012.353917] [drm:drm_mode_debug_printmodeline], Modeline 158:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
><7>[ 1012.353922] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1012.353925] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1012.354239] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1012.405361] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1012.407672] [drm:ironlake_update_plane], Writing base 04A6D000 00000000 0 0 5120
><7>[ 1012.459327] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1012.459335] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1012.459339] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1012.459342] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1012.459346] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:158:1280x800]
><7>[ 1012.459351] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1012.459354] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1012.459357] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1012.511272] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1012.563215] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1012.563376] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1012.564038] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1012.564041] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1012.564699] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1012.564703] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1012.564706] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1012.564708] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1012.564712] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1012.582707] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1012.584167] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1012.584178] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1012.584183] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1012.584187] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1012.584192] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1012.584196] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1012.584200] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1012.584202] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1012.584205] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1017.621431] [drm:drm_mode_addfb], [FB:158]
><7>[ 1017.621455] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1017.621460] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1017.621462] [drm:intel_crtc_set_config], [CRTC:3] [FB:158] #connectors=1 (x y) (0 0)
><7>[ 1017.621465] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1017.621467] [drm:drm_mode_debug_printmodeline], Modeline 158:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
><7>[ 1017.621470] [drm:drm_mode_debug_printmodeline], Modeline 159:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1017.621473] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1017.621475] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1017.621478] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1017.621479] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1017.621481] [drm:drm_mode_debug_printmodeline], Modeline 159:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1017.621484] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1017.621487] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1017.624857] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1017.658594] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1017.658600] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1017.659012] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1017.659015] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1017.659018] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1017.659040] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1017.659043] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1017.659046] [drm:drm_mode_debug_printmodeline], Modeline 159:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1017.659051] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1017.659054] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1017.659368] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1017.710560] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1017.713090] [drm:ironlake_update_plane], Writing base 04E55000 00000000 0 0 4608
><7>[ 1017.764498] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1017.764505] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1017.764509] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1017.764512] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1017.764516] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:159:1152x864]
><7>[ 1017.764521] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1017.764524] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1017.764527] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1017.816443] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1017.868359] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1017.868520] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1017.869181] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1017.869185] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1017.869843] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1017.869847] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1017.869849] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1017.869852] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1017.869856] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1017.884455] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1017.885375] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1017.885385] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1017.885394] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1017.885399] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1017.885403] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1017.885407] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1017.885411] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1017.885414] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1017.885416] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1022.920167] [drm:drm_mode_addfb], [FB:159]
><7>[ 1022.920191] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1022.920197] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1022.920199] [drm:intel_crtc_set_config], [CRTC:3] [FB:159] #connectors=1 (x y) (0 0)
><7>[ 1022.920202] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1022.920204] [drm:drm_mode_debug_printmodeline], Modeline 159:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1022.920207] [drm:drm_mode_debug_printmodeline], Modeline 160:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1022.920210] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1022.920212] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1022.920214] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1022.920216] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1022.920218] [drm:drm_mode_debug_printmodeline], Modeline 160:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1022.920221] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1022.920224] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1022.932183] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1022.959799] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1022.959805] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1022.960218] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1022.960221] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1022.960224] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1022.960260] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1022.960263] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1022.960265] [drm:drm_mode_debug_printmodeline], Modeline 160:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1022.960270] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1022.960273] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1022.960588] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1023.011735] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1023.014036] [drm:ironlake_update_plane], Writing base 05221000 00000000 0 0 5120
><7>[ 1023.065674] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1023.065681] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1023.065685] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1023.065688] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1023.065692] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:160:1280x768]
><7>[ 1023.065697] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1023.065700] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1023.065703] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1023.117618] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1023.169561] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1023.169722] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1023.170384] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1023.170387] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1023.171045] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1023.171050] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1023.171052] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1023.171054] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1023.171059] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1023.185709] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1023.186554] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1023.186566] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1023.186573] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1023.186580] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1023.186589] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1023.186597] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1023.186603] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1023.186608] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1023.186612] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1028.222611] [drm:drm_mode_addfb], [FB:160]
><7>[ 1028.222634] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1028.222640] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1028.222642] [drm:intel_crtc_set_config], [CRTC:3] [FB:160] #connectors=1 (x y) (0 0)
><7>[ 1028.222645] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1028.222646] [drm:drm_mode_debug_printmodeline], Modeline 160:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1028.222649] [drm:drm_mode_debug_printmodeline], Modeline 161:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
><7>[ 1028.222653] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1028.222655] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1028.222657] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1028.222659] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1028.222660] [drm:drm_mode_debug_printmodeline], Modeline 161:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
><7>[ 1028.222663] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1028.222666] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1028.226289] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1028.253981] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1028.253988] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1028.254400] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1028.254403] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1028.254406] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1028.254442] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1028.254445] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1028.254448] [drm:drm_mode_debug_printmodeline], Modeline 161:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
><7>[ 1028.254452] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1028.254455] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1028.254770] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1028.305918] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1028.308216] [drm:ironlake_update_plane], Writing base 055E1000 00000000 0 0 5120
><7>[ 1028.359834] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1028.359841] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1028.359845] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1028.359848] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1028.359853] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:161:1280x768]
><7>[ 1028.359858] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1028.359861] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1028.359864] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1028.411802] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1028.463744] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1028.463906] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1028.464567] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1028.464571] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1028.465228] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1028.465233] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1028.465235] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1028.465238] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1028.465242] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1028.483196] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1028.484728] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1028.484738] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1028.484743] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1028.484748] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1028.484752] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1028.484756] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1028.484760] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1028.484763] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1028.484765] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1033.518003] [drm:drm_mode_addfb], [FB:161]
><7>[ 1033.518027] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1033.518033] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1033.518035] [drm:intel_crtc_set_config], [CRTC:3] [FB:161] #connectors=1 (x y) (0 0)
><7>[ 1033.518038] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1033.518039] [drm:drm_mode_debug_printmodeline], Modeline 161:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
><7>[ 1033.518042] [drm:drm_mode_debug_printmodeline], Modeline 162:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1033.518046] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1033.518048] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1033.518050] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1033.518052] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1033.518053] [drm:drm_mode_debug_printmodeline], Modeline 162:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1033.518056] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1033.518059] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1033.521852] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1033.557153] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1033.557159] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1033.557572] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1033.557575] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1033.557578] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1033.557601] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1033.557604] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1033.557606] [drm:drm_mode_debug_printmodeline], Modeline 162:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1033.557611] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1033.557614] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1033.557929] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1033.609090] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1033.610902] [drm:ironlake_update_plane], Writing base 059A1000 00000000 0 0 4096
><7>[ 1033.661999] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1033.662006] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1033.662010] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1033.662013] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1033.662017] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:162:1024x768]
><7>[ 1033.662023] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1033.662025] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1033.662028] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1033.713976] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1033.765919] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1033.766080] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1033.766742] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1033.766745] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1033.767403] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1033.767408] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1033.767410] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1033.767413] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1033.767417] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1033.781969] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1033.782908] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1033.782917] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1033.782922] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1033.782927] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1033.782931] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1033.782939] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1033.782946] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1033.782948] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1033.782951] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1038.821644] [drm:drm_mode_addfb], [FB:162]
><7>[ 1038.821675] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1038.821683] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1038.821685] [drm:intel_crtc_set_config], [CRTC:3] [FB:162] #connectors=1 (x y) (0 0)
><7>[ 1038.821699] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1038.821702] [drm:drm_mode_debug_printmodeline], Modeline 162:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1038.821705] [drm:drm_mode_debug_printmodeline], Modeline 163:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1038.821709] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1038.821711] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1038.821713] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1038.821715] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1038.821717] [drm:drm_mode_debug_printmodeline], Modeline 163:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1038.821720] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1038.821724] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1038.825062] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1038.853303] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1038.853309] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1038.853723] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1038.853726] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1038.853729] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1038.853767] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1038.853770] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1038.853773] [drm:drm_mode_debug_printmodeline], Modeline 163:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1038.853778] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1038.853781] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1038.854096] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1038.905231] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1038.906778] [drm:ironlake_update_plane], Writing base 05CA1000 00000000 0 0 4096
><7>[ 1038.958171] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1038.958179] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1038.958183] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1038.958186] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1038.958191] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:163:1024x768]
><7>[ 1038.958197] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1038.958200] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1038.958203] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1039.010114] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1039.062060] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1039.062222] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1039.062883] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1039.062887] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1039.063564] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1039.063568] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1039.063571] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1039.063573] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1039.063578] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1039.079060] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1039.081043] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1039.081054] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1039.081059] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1039.081064] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1039.081068] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1039.081072] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1039.081076] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1039.081079] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1039.081082] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1044.115174] [drm:drm_mode_addfb], [FB:163]
><7>[ 1044.115202] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1044.115209] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1044.115212] [drm:intel_crtc_set_config], [CRTC:3] [FB:163] #connectors=1 (x y) (0 0)
><7>[ 1044.115215] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1044.115217] [drm:drm_mode_debug_printmodeline], Modeline 163:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1044.115220] [drm:drm_mode_debug_printmodeline], Modeline 164:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1044.115224] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1044.115226] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1044.115228] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1044.115230] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1044.115231] [drm:drm_mode_debug_printmodeline], Modeline 164:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1044.115234] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1044.115237] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1044.125670] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1044.154510] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1044.154516] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1044.154930] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1044.154933] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1044.154936] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1044.154959] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1044.154963] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1044.154965] [drm:drm_mode_debug_printmodeline], Modeline 164:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1044.154970] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1044.154973] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1044.155287] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1044.206447] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1044.208571] [drm:ironlake_update_plane], Writing base 05FA1000 00000000 0 0 4096
><7>[ 1044.260354] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1044.260362] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1044.260366] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1044.260369] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1044.260373] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:164:1024x768]
><7>[ 1044.260378] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1044.260381] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1044.260383] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1044.312331] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1044.364275] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1044.364436] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1044.365098] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1044.365102] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1044.365760] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1044.365764] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1044.365767] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1044.365769] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1044.365774] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1044.383722] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1044.385258] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1044.385268] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1044.385273] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1044.385278] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1044.385282] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1044.385286] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1044.385290] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1044.385293] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1044.385295] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1049.418419] [drm:drm_mode_addfb], [FB:164]
><7>[ 1049.418443] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1049.418448] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1049.418450] [drm:intel_crtc_set_config], [CRTC:3] [FB:164] #connectors=1 (x y) (0 0)
><7>[ 1049.418453] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1049.418455] [drm:drm_mode_debug_printmodeline], Modeline 164:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1049.418458] [drm:drm_mode_debug_printmodeline], Modeline 165:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1049.418461] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1049.418463] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1049.418465] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1049.418467] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1049.418468] [drm:drm_mode_debug_printmodeline], Modeline 165:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1049.418471] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1049.418474] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1049.426667] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1049.461678] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1049.461685] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1049.462098] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1049.462101] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1049.462104] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1049.462126] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1049.462129] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1049.462132] [drm:drm_mode_debug_printmodeline], Modeline 165:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1049.462137] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1049.462140] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1049.462454] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1049.513587] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1049.515161] [drm:ironlake_update_plane], Writing base 062A1000 00000000 0 0 4096
><7>[ 1049.566556] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1049.566563] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1049.566567] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1049.566570] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1049.566574] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:165:1024x576]
><7>[ 1049.566579] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1049.566582] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1049.566585] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1049.618500] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1049.670445] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1049.670606] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1049.671268] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1049.671272] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1049.671930] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1049.671935] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1049.671937] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1049.671939] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1049.671944] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1049.689915] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1049.691385] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1049.691394] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1049.691399] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1049.691404] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1049.691408] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1049.691412] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1049.691416] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1049.691419] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1049.691421] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1054.723565] [drm:drm_mode_addfb], [FB:165]
><7>[ 1054.723588] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1054.723594] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1054.723596] [drm:intel_crtc_set_config], [CRTC:3] [FB:165] #connectors=1 (x y) (0 0)
><7>[ 1054.723599] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1054.723600] [drm:drm_mode_debug_printmodeline], Modeline 165:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1054.723603] [drm:drm_mode_debug_printmodeline], Modeline 166:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1054.723607] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1054.723609] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1054.723611] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1054.723613] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1054.723614] [drm:drm_mode_debug_printmodeline], Modeline 166:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1054.723617] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1054.723620] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1054.732572] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1054.766850] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1054.766856] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1054.767268] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1054.767271] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1054.767274] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1054.767296] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1054.767300] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1054.767302] [drm:drm_mode_debug_printmodeline], Modeline 166:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1054.767307] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1054.767310] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1054.767624] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1054.818754] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1054.820003] [drm:ironlake_update_plane], Writing base 064E1000 00000000 0 0 3200
><7>[ 1054.871726] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1054.871733] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1054.871737] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1054.871740] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1054.871744] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:166:800x600]
><7>[ 1054.871750] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1054.871753] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1054.871755] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1054.923672] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1054.975616] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1054.975777] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1054.976438] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1054.976442] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1054.977100] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1054.977104] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1054.977107] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1054.977109] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1054.977114] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1054.992308] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1054.992602] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1054.992612] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1054.992617] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1054.992622] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1054.992626] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1054.992630] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1054.992635] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1054.992637] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1054.992640] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1060.025646] [drm:drm_mode_addfb], [FB:166]
><7>[ 1060.025670] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1060.025675] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1060.025677] [drm:intel_crtc_set_config], [CRTC:3] [FB:166] #connectors=1 (x y) (0 0)
><7>[ 1060.025680] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1060.025682] [drm:drm_mode_debug_printmodeline], Modeline 166:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1060.025685] [drm:drm_mode_debug_printmodeline], Modeline 167:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1060.025688] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1060.025690] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1060.025693] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1060.025694] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1060.025696] [drm:drm_mode_debug_printmodeline], Modeline 167:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1060.025699] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1060.025702] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1060.030255] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1060.059035] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1060.059041] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1060.059454] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1060.059457] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1060.059460] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1060.059482] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1060.059485] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1060.059488] [drm:drm_mode_debug_printmodeline], Modeline 167:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1060.059493] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1060.059495] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1060.059810] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1060.110972] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1060.112226] [drm:ironlake_update_plane], Writing base 066B6000 00000000 0 0 3200
><7>[ 1060.163910] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1060.163917] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1060.163921] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1060.163924] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1060.163929] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:167:800x600]
><7>[ 1060.163934] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1060.163937] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1060.163939] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1060.215857] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1060.267799] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1060.267960] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1060.268622] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1060.268626] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1060.269284] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1060.269288] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1060.269290] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1060.269292] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1060.269297] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1060.283835] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1060.284793] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1060.284805] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1060.284812] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1060.284818] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1060.284824] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1060.284836] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1060.284842] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1060.284847] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1060.284851] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1065.318668] [drm:drm_mode_addfb], [FB:167]
><7>[ 1065.318692] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1065.318697] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1065.318699] [drm:intel_crtc_set_config], [CRTC:3] [FB:167] #connectors=1 (x y) (0 0)
><7>[ 1065.318702] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1065.318704] [drm:drm_mode_debug_printmodeline], Modeline 167:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1065.318707] [drm:drm_mode_debug_printmodeline], Modeline 168:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1065.318710] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1065.318712] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1065.318714] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1065.318716] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1065.318718] [drm:drm_mode_debug_printmodeline], Modeline 168:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1065.318720] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1065.318723] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1065.323092] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1065.350227] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1065.350233] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1065.350646] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1065.350650] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1065.350653] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1065.350675] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1065.350678] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1065.350681] [drm:drm_mode_debug_printmodeline], Modeline 168:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1065.350685] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1065.350688] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1065.351003] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1065.401160] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1065.402622] [drm:ironlake_update_plane], Writing base 0688B000 00000000 0 0 3200
><7>[ 1065.454099] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1065.454106] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1065.454110] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1065.454113] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1065.454117] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:168:800x600]
><7>[ 1065.454123] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1065.454126] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1065.454128] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1065.506011] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1065.557986] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1065.558147] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1065.558809] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1065.558813] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1065.559471] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1065.559475] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1065.559477] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1065.559480] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1065.559485] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1065.577294] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1065.578969] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1065.578980] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1065.578985] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1065.578989] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1065.578993] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1065.578998] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1065.579001] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1065.579004] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1065.579006] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1070.612960] [drm:drm_mode_addfb], [FB:168]
><7>[ 1070.612983] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1070.612989] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1070.612991] [drm:intel_crtc_set_config], [CRTC:3] [FB:168] #connectors=1 (x y) (0 0)
><7>[ 1070.612994] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1070.612996] [drm:drm_mode_debug_printmodeline], Modeline 168:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1070.612999] [drm:drm_mode_debug_printmodeline], Modeline 169:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1070.613002] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1070.613004] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1070.613006] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1070.613008] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1070.613010] [drm:drm_mode_debug_printmodeline], Modeline 169:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1070.613013] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1070.613016] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1070.628368] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1070.662383] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1070.662389] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1070.662801] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1070.662804] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1070.662807] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1070.662843] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1070.662846] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1070.662849] [drm:drm_mode_debug_printmodeline], Modeline 169:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1070.662854] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1070.662856] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1070.663169] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1070.714321] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1070.715578] [drm:ironlake_update_plane], Writing base 06A60000 00000000 0 0 3200
><7>[ 1070.767261] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1070.767268] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1070.767272] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1070.767275] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1070.767279] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:169:800x600]
><7>[ 1070.767284] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1070.767287] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1070.767290] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1070.819213] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1070.871120] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1070.871281] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1070.871943] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1070.871947] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1070.872609] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1070.872614] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1070.872616] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1070.872618] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1070.872623] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1070.891656] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1070.892141] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1070.892152] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1070.892157] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1070.892161] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1070.892165] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1070.892169] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1070.892173] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1070.892176] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1070.892179] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1075.924557] [drm:drm_mode_addfb], [FB:169]
><7>[ 1075.924580] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1075.924585] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1075.924587] [drm:intel_crtc_set_config], [CRTC:3] [FB:169] #connectors=1 (x y) (0 0)
><7>[ 1075.924590] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1075.924591] [drm:drm_mode_debug_printmodeline], Modeline 169:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1075.924594] [drm:drm_mode_debug_printmodeline], Modeline 170:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1075.924598] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1075.924600] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1075.924602] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1075.924603] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1075.924605] [drm:drm_mode_debug_printmodeline], Modeline 170:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1075.924608] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1075.924611] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1075.934964] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1075.970551] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1075.970557] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1075.970970] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1075.970974] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1075.970976] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1075.971012] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1075.971015] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1075.971018] [drm:drm_mode_debug_printmodeline], Modeline 170:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1075.971023] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1075.971026] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1075.971340] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1076.022489] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1076.023571] [drm:ironlake_update_plane], Writing base 06C35000 00000000 0 0 3392
><7>[ 1076.075397] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1076.075404] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1076.075408] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1076.075412] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1076.075416] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:170:848x480]
><7>[ 1076.075421] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1076.075424] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1076.075426] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1076.127374] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1076.179316] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1076.179477] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1076.180139] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1076.180143] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1076.180801] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1076.180805] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1076.180808] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1076.180810] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1076.180815] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1076.198736] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1076.200258] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1076.200268] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1076.200273] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1076.200277] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1076.200281] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1076.200286] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1076.200289] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1076.200292] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1076.200295] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1081.227016] [drm:drm_mode_addfb], [FB:170]
><7>[ 1081.227039] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1081.227044] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1081.227046] [drm:intel_crtc_set_config], [CRTC:3] [FB:170] #connectors=1 (x y) (0 0)
><7>[ 1081.227049] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1081.227050] [drm:drm_mode_debug_printmodeline], Modeline 170:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1081.227053] [drm:drm_mode_debug_printmodeline], Modeline 171:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
><7>[ 1081.227056] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1081.227058] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1081.227061] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1081.227062] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1081.227064] [drm:drm_mode_debug_printmodeline], Modeline 171:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
><7>[ 1081.227067] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1081.227070] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1081.243098] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1081.276721] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1081.276727] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1081.277141] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1081.277144] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1081.277147] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1081.277182] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1081.277185] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1081.277188] [drm:drm_mode_debug_printmodeline], Modeline 171:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
><7>[ 1081.277193] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1081.277195] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1081.277509] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1081.328655] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1081.329431] [drm:ironlake_update_plane], Writing base 06DC3000 00000000 0 0 2560
><7>[ 1081.380599] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1081.380606] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1081.380610] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1081.380613] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1081.380617] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:171:640x480]
><7>[ 1081.380622] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1081.380625] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1081.380628] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1081.432544] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1081.484487] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1081.484648] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1081.485310] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1081.485314] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1081.485971] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1081.485975] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1081.485978] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1081.485980] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1081.485985] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1081.500978] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1081.501500] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1081.501512] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1081.501519] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1081.501525] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1081.501533] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1081.501545] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1081.501550] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1081.501555] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1081.501559] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1086.529109] [drm:drm_mode_addfb], [FB:171]
><7>[ 1086.529132] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1086.529137] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1086.529139] [drm:intel_crtc_set_config], [CRTC:3] [FB:171] #connectors=1 (x y) (0 0)
><7>[ 1086.529142] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1086.529143] [drm:drm_mode_debug_printmodeline], Modeline 171:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
><7>[ 1086.529146] [drm:drm_mode_debug_printmodeline], Modeline 172:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1086.529150] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1086.529152] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1086.529154] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1086.529155] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1086.529157] [drm:drm_mode_debug_printmodeline], Modeline 172:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1086.529160] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1086.529163] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1086.535981] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1086.564910] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1086.564916] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1086.565329] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1086.565332] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1086.565335] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1086.565371] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1086.565374] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1086.565377] [drm:drm_mode_debug_printmodeline], Modeline 172:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1086.565381] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1086.565384] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1086.565699] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1086.616848] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1086.617741] [drm:ironlake_update_plane], Writing base 06EEF000 00000000 0 0 2560
><7>[ 1086.668789] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1086.668796] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1086.668800] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1086.668803] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1086.668807] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:172:640x480]
><7>[ 1086.668813] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1086.668815] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1086.668818] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1086.720737] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1086.772645] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1086.772806] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1086.773468] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1086.773471] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1086.774130] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1086.774135] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1086.774138] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1086.774140] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1086.774145] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1086.788739] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1086.789666] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1086.789676] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1086.789681] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1086.789687] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1086.789691] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1086.789696] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1086.789701] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1086.789704] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1086.789706] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1091.816235] [drm:drm_mode_addfb], [FB:172]
><7>[ 1091.816259] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1091.816264] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1091.816266] [drm:intel_crtc_set_config], [CRTC:3] [FB:172] #connectors=1 (x y) (0 0)
><7>[ 1091.816269] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1091.816271] [drm:drm_mode_debug_printmodeline], Modeline 172:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1091.816274] [drm:drm_mode_debug_printmodeline], Modeline 173:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1091.816277] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1091.816279] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1091.816281] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1091.816283] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1091.816284] [drm:drm_mode_debug_printmodeline], Modeline 173:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1091.816287] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1091.816290] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1091.823118] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1091.850103] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1091.850110] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1091.850523] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1091.850526] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1091.850529] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1091.850578] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1091.850581] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1091.850584] [drm:drm_mode_debug_printmodeline], Modeline 173:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1091.850588] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1091.850591] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1091.850906] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1091.902041] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1091.902818] [drm:ironlake_update_plane], Writing base 0701B000 00000000 0 0 2560
><7>[ 1091.953981] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1091.953988] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1091.953992] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1091.953995] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1091.954000] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:173:640x480]
><7>[ 1091.954005] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1091.954008] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1091.954011] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1092.005926] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1092.057837] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1092.057998] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1092.058659] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1092.058663] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1092.059327] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1092.059331] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1092.059334] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1092.059336] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1092.059341] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1092.077243] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1092.078854] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1092.078864] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1092.078869] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1092.078873] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1092.078878] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1092.078882] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1092.078885] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1092.078888] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1092.078890] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1097.103142] [drm:drm_mode_addfb], [FB:173]
><7>[ 1097.103172] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1097.103180] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
><7>[ 1097.103183] [drm:intel_crtc_set_config], [CRTC:3] [FB:173] #connectors=1 (x y) (0 0)
><7>[ 1097.103186] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1097.103188] [drm:drm_mode_debug_printmodeline], Modeline 173:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1097.103192] [drm:drm_mode_debug_printmodeline], Modeline 174:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1097.103195] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1097.103198] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1097.103200] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1097.103202] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1097.103204] [drm:drm_mode_debug_printmodeline], Modeline 174:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1097.103207] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1097.103210] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1097.104982] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1097.140248] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1097.140255] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1097.140668] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1097.140671] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1097.140674] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1097.140726] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1097.140730] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1097.140733] [drm:drm_mode_debug_printmodeline], Modeline 174:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1097.140737] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1097.140740] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1097.141055] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1097.192187] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1097.192766] [drm:ironlake_update_plane], Writing base 07147000 00000000 0 0 2880
><7>[ 1097.244130] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1097.244141] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1097.244146] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1097.244149] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1097.244154] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:174:720x400]
><7>[ 1097.244160] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1097.244163] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1097.244166] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1097.296077] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1097.348017] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1097.348179] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1097.348841] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1097.348845] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1097.349519] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1097.349523] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1097.349526] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1097.349528] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1097.349533] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1097.365081] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1097.367007] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1097.367020] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1097.367028] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1097.367034] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1097.367040] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1097.367046] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1097.367052] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1097.367057] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1097.367061] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1102.361678] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
><7>[ 1102.361687] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [NOCRTC]
><7>[ 1102.361690] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1102.361694] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1102.361697] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1102.361700] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1102.361703] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
><7>[ 1102.375009] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1102.405473] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1102.405480] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1102.405893] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1102.405896] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1102.405899] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1102.405913] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1102.405918] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1102.405922] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1102.405927] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1102.405931] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1102.405935] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1102.405937] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1102.405940] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1102.405954] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1102.405957] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set
><7>[ 1102.405971] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
><7>[ 1102.405977] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI-A-1]
><7>[ 1102.477423] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1102.549444] [drm:drm_edid_to_eld], ELD monitor VE228
><4>[ 1102.549451] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
><7>[ 1102.549453] [drm:drm_edid_to_eld], ELD size 7, SAD count 1
><7>[ 1102.549545] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI-A-1] probed modes :
><7>[ 1102.549548] [drm:drm_mode_debug_printmodeline], Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1102.549553] [drm:drm_mode_debug_printmodeline], Modeline 101:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1102.549558] [drm:drm_mode_debug_printmodeline], Modeline 54:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1102.549562] [drm:drm_mode_debug_printmodeline], Modeline 100:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1102.549566] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1102.549571] [drm:drm_mode_debug_printmodeline], Modeline 63:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1102.549575] [drm:drm_mode_debug_printmodeline], Modeline 64:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1102.549579] [drm:drm_mode_debug_printmodeline], Modeline 90:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1102.549583] [drm:drm_mode_debug_printmodeline], Modeline 86:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1102.549587] [drm:drm_mode_debug_printmodeline], Modeline 85:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1102.549591] [drm:drm_mode_debug_printmodeline], Modeline 89:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1102.549595] [drm:drm_mode_debug_printmodeline], Modeline 72:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1102.549599] [drm:drm_mode_debug_printmodeline], Modeline 60:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1102.549604] [drm:drm_mode_debug_printmodeline], Modeline 87:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1102.549608] [drm:drm_mode_debug_printmodeline], Modeline 62:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1102.549612] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1102.549616] [drm:drm_mode_debug_printmodeline], Modeline 55:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1102.549620] [drm:drm_mode_debug_printmodeline], Modeline 84:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1102.549624] [drm:drm_mode_debug_printmodeline], Modeline 83:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1102.549628] [drm:drm_mode_debug_printmodeline], Modeline 82:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1102.549632] [drm:drm_mode_debug_printmodeline], Modeline 59:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1102.549636] [drm:drm_mode_debug_printmodeline], Modeline 81:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1102.549641] [drm:drm_mode_debug_printmodeline], Modeline 80:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1102.549645] [drm:drm_mode_debug_printmodeline], Modeline 99:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1102.549649] [drm:drm_mode_debug_printmodeline], Modeline 93:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1102.549653] [drm:drm_mode_debug_printmodeline], Modeline 73:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1102.549657] [drm:drm_mode_debug_printmodeline], Modeline 74:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1102.549661] [drm:drm_mode_debug_printmodeline], Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1102.549665] [drm:drm_mode_debug_printmodeline], Modeline 88:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1102.549669] [drm:drm_mode_debug_printmodeline], Modeline 76:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1102.549673] [drm:drm_mode_debug_printmodeline], Modeline 78:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1102.549677] [drm:drm_mode_debug_printmodeline], Modeline 77:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1102.549682] [drm:drm_mode_debug_printmodeline], Modeline 65:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1102.549686] [drm:drm_mode_debug_printmodeline], Modeline 66:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1102.549690] [drm:drm_mode_debug_printmodeline], Modeline 98:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1102.549694] [drm:drm_mode_debug_printmodeline], Modeline 79:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1102.549698] [drm:drm_mode_debug_printmodeline], Modeline 95:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1102.549702] [drm:drm_mode_debug_printmodeline], Modeline 68:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1102.549706] [drm:drm_mode_debug_printmodeline], Modeline 67:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1102.549710] [drm:drm_mode_debug_printmodeline], Modeline 69:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1102.549714] [drm:drm_mode_debug_printmodeline], Modeline 70:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1102.549718] [drm:drm_mode_debug_printmodeline], Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1102.549722] [drm:drm_mode_debug_printmodeline], Modeline 71:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1102.549737] [drm:drm_mode_getconnector], [CONNECTOR:12:?]
><7>[ 1102.608335] [drm:drm_mode_addfb], [FB:173]
><7>[ 1102.608364] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1102.608370] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1102.608373] [drm:intel_crtc_set_config], [CRTC:3] [FB:173] #connectors=1 (x y) (0 0)
><7>[ 1102.608375] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
><7>[ 1102.608377] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1102.608379] [drm:drm_mode_debug_printmodeline], Modeline 174:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1102.608382] [drm:drm_mode_debug_printmodeline], Modeline 174:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1102.608385] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1102.608387] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1102.608389] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1102.608391] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1102.608392] [drm:drm_mode_debug_printmodeline], Modeline 174:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1102.608395] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
><7>[ 1102.608400] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1102.608423] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1102.608425] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1102.608427] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1102.608428] [drm:drm_mode_debug_printmodeline], Modeline 174:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1102.608433] [drm:intel_get_pch_pll], CRTC:3 sharing existing PCH PLL c6018 (refcount 1, ative 0)
><7>[ 1102.608435] [drm:intel_get_pch_pll], using pll 1 for pipe 0
><7>[ 1102.608437] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1102.608750] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1102.660220] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1102.665563] [drm:ironlake_update_plane], Writing base 07261000 00000000 0 0 7680
><7>[ 1102.665570] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1102.665574] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1102.665578] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:174:1920x1080]
><7>[ 1102.665582] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1102.665585] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1102.665589] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1102.665592] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1102.665602] [drm:ironlake_write_eld], ELD size 7
><7>[ 1102.665629] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1102.665632] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1102.718157] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1102.770099] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1102.770260] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1102.770922] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1102.770926] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1102.771584] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1102.771588] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1102.771590] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1102.771593] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1102.771597] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1102.789530] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1102.791043] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1102.791053] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1102.791058] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1102.791062] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1102.791066] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1102.791071] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1102.791074] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1102.791077] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1102.791079] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1107.847273] [drm:drm_mode_addfb], [FB:174]
><7>[ 1107.847301] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1107.847308] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1107.847310] [drm:intel_crtc_set_config], [CRTC:3] [FB:174] #connectors=1 (x y) (0 0)
><7>[ 1107.847313] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1107.847315] [drm:drm_mode_debug_printmodeline], Modeline 174:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1107.847318] [drm:drm_mode_debug_printmodeline], Modeline 175:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1107.847321] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1107.847323] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1107.847325] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1107.847327] [drm:drm_mode_debug_printmodeline], Modeline 175:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1107.847330] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1107.847333] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1107.850556] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1107.884485] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1107.884491] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1107.884905] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1107.884908] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1107.884944] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1107.884946] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1107.884950] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1107.884952] [drm:drm_mode_debug_printmodeline], Modeline 175:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1107.884957] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1107.884960] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1107.885274] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1107.936423] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1107.941734] [drm:ironlake_update_plane], Writing base 07A4A000 00000000 0 0 7680
><7>[ 1107.993359] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1107.993366] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1107.993370] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1107.993374] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:175:1920x1080]
><7>[ 1107.993378] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1107.993381] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1107.993385] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1107.993389] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1107.993419] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1107.993422] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1108.045304] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1108.097247] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1108.097408] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1108.098069] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1108.098074] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1108.098732] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1108.098736] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1108.098739] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1108.098741] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1108.098746] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1108.120002] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1108.120230] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1108.120240] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1108.120245] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1108.120250] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1108.120254] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1108.120258] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1108.120262] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1108.120264] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1108.120267] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1112.492400] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x2f40010, result 1
><7>[ 1112.492407] [drm:intel_crt_detect], CRT detected via hotplug
><7>[ 1112.492410] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 1 to 1
><7>[ 1112.564311] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1112.564318] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-1] status updated from 1 to 1
><7>[ 1112.636235] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1112.636242] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 1 to 1
><7>[ 1112.638801] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.642771] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.646766] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.648210] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1112.648217] [drm:output_poll_execute], [CONNECTOR:18:DP-1] status updated from 2 to 2
><7>[ 1112.650774] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.654757] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.658760] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1112.660197] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1112.660203] [drm:output_poll_execute], [CONNECTOR:20:DP-2] status updated from 2 to 2
><7>[ 1113.174502] [drm:drm_mode_addfb], [FB:175]
><7>[ 1113.174529] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1113.174536] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1113.174538] [drm:intel_crtc_set_config], [CRTC:3] [FB:175] #connectors=1 (x y) (0 0)
><7>[ 1113.174541] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1113.174543] [drm:drm_mode_debug_printmodeline], Modeline 175:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1113.174546] [drm:drm_mode_debug_printmodeline], Modeline 176:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1113.174549] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1113.174551] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1113.174553] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1113.174554] [drm:drm_mode_debug_printmodeline], Modeline 176:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1113.174557] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1113.174560] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1113.194391] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1113.235605] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1113.235611] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1113.236024] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1113.236027] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1113.236063] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1113.236065] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1113.236068] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1113.236071] [drm:drm_mode_debug_printmodeline], Modeline 176:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1113.236076] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1113.236079] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1113.236393] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1113.287545] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1113.293655] [drm:ironlake_update_plane], Writing base 08233000 00000000 0 0 7680
><7>[ 1113.345476] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1113.345484] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1113.345488] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1113.345492] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:176:1920x1080]
><7>[ 1113.345496] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1113.345499] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1113.345503] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1113.345507] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1113.345537] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1113.345540] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1113.397423] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1113.449365] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1113.449526] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1113.450188] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1113.450192] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1113.450849] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1113.450854] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1113.450856] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1113.450859] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1113.450863] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1113.468857] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1113.470350] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1113.470360] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1113.470364] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1113.470368] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1113.470373] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1113.470377] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1113.470381] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1113.470383] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1113.470386] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1118.522426] [drm:drm_mode_addfb], [FB:176]
><7>[ 1118.522453] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1118.522459] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1118.522461] [drm:intel_crtc_set_config], [CRTC:3] [FB:176] #connectors=1 (x y) (0 0)
><7>[ 1118.522464] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1118.522466] [drm:drm_mode_debug_printmodeline], Modeline 176:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1118.522469] [drm:drm_mode_debug_printmodeline], Modeline 177:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1118.522472] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1118.522474] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1118.522476] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1118.522478] [drm:drm_mode_debug_printmodeline], Modeline 177:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1118.522481] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1118.522484] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1118.532581] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1118.566748] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1118.566754] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1118.567167] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1118.567170] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1118.567206] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1118.567208] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1118.567211] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1118.567214] [drm:drm_mode_debug_printmodeline], Modeline 177:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1118.567219] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1118.567221] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1118.567536] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1118.618653] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1118.623983] [drm:ironlake_update_plane], Writing base 08A1C000 00000000 0 0 7680
><7>[ 1118.675621] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1118.675628] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1118.675632] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1118.675637] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:177:1920x1080i]
><7>[ 1118.675640] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1118.675644] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1118.675647] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1118.675651] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1118.675681] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1118.675684] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1118.727533] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1118.779511] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1118.779672] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1118.780334] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1118.780338] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1118.780996] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1118.781000] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1118.781003] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1118.781005] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1118.781010] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1118.802281] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1118.802495] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1118.802504] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1118.802513] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1118.802517] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1118.802522] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1118.802529] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1118.802532] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1118.802535] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1118.802538] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1123.855101] [drm:drm_mode_addfb], [FB:177]
><7>[ 1123.855129] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1123.855135] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1123.855137] [drm:intel_crtc_set_config], [CRTC:3] [FB:177] #connectors=1 (x y) (0 0)
><7>[ 1123.855140] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1123.855141] [drm:drm_mode_debug_printmodeline], Modeline 177:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1123.855144] [drm:drm_mode_debug_printmodeline], Modeline 178:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1123.855148] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1123.855150] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1123.855152] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1123.855153] [drm:drm_mode_debug_printmodeline], Modeline 178:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1123.855156] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1123.855159] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1123.856672] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1123.896891] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1123.896897] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1123.897310] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1123.897313] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1123.897349] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1123.897352] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1123.897355] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1123.897358] [drm:drm_mode_debug_printmodeline], Modeline 178:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1123.897363] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1123.897365] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1123.897680] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1123.948828] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1123.954070] [drm:ironlake_update_plane], Writing base 09205000 00000000 0 0 7680
><7>[ 1124.005765] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1124.005772] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1124.005776] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1124.005780] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:178:1920x1080i]
><7>[ 1124.005784] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1124.005788] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1124.005791] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1124.005795] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1124.005824] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1124.005827] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1124.057709] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1124.109652] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1124.109813] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1124.110475] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1124.110479] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1124.111136] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1124.111141] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1124.111143] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1124.111146] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1124.111150] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1124.129090] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1124.130639] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1124.130648] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1124.130653] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1124.130658] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1124.130662] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1124.130666] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1124.130670] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1124.130673] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1124.130676] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1129.185130] [drm:drm_mode_addfb], [FB:178]
><7>[ 1129.185155] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1129.185161] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1129.185163] [drm:intel_crtc_set_config], [CRTC:3] [FB:178] #connectors=1 (x y) (0 0)
><7>[ 1129.185166] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1129.185168] [drm:drm_mode_debug_printmodeline], Modeline 178:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1129.185171] [drm:drm_mode_debug_printmodeline], Modeline 179:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1129.185174] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1129.185176] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1129.185178] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1129.185180] [drm:drm_mode_debug_printmodeline], Modeline 179:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1129.185183] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1129.185186] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1129.190154] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1129.225036] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1129.225043] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1129.225456] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1129.225459] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1129.225481] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1129.225484] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1129.225487] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1129.225490] [drm:drm_mode_debug_printmodeline], Modeline 179:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1129.225495] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1129.225497] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1129.225812] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1129.276950] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1129.281961] [drm:ironlake_update_plane], Writing base 099EE000 00000000 0 0 6400
><7>[ 1129.333910] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1129.333917] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1129.333921] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1129.333926] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:179:1600x1200]
><7>[ 1129.333929] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1129.333933] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1129.333936] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1129.333940] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1129.333970] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1129.333973] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1129.385822] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1129.437797] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1129.437958] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1129.438620] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1129.438624] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1129.439282] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1129.439286] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1129.439289] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1129.439291] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1129.439296] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1129.457221] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1129.458783] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1129.458793] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1129.458798] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1129.458802] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1129.458807] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1129.458811] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1129.458815] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1129.458817] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1129.458820] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1134.511207] [drm:drm_mode_addfb], [FB:179]
><7>[ 1134.511244] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1134.511251] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1134.511253] [drm:intel_crtc_set_config], [CRTC:3] [FB:179] #connectors=1 (x y) (0 0)
><7>[ 1134.511256] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1134.511258] [drm:drm_mode_debug_printmodeline], Modeline 179:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1134.511261] [drm:drm_mode_debug_printmodeline], Modeline 180:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1134.511264] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1134.511266] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1134.511268] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1134.511270] [drm:drm_mode_debug_printmodeline], Modeline 180:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1134.511273] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1134.511276] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1134.518254] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1134.553182] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1134.553188] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1134.553601] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1134.553605] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1134.553640] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1134.553643] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1134.553646] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1134.553648] [drm:drm_mode_debug_printmodeline], Modeline 180:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1134.553653] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1134.553656] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1134.553971] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1134.605121] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1134.609648] [drm:ironlake_update_plane], Writing base 0A141000 00000000 0 0 6720
><7>[ 1134.661025] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1134.661032] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1134.661036] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1134.661041] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:180:1680x1050]
><7>[ 1134.661044] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1134.661048] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1134.661051] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1134.661055] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1134.661085] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1134.661088] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1134.713001] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1134.764945] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1134.765105] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1134.765767] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1134.765771] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1134.766430] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1134.766434] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1134.766437] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1134.766439] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1134.766444] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1134.784476] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1134.785929] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1134.785939] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1134.785944] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1134.785949] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1134.785953] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1134.785957] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1134.785961] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1134.785964] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1134.785966] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1139.836056] [drm:drm_mode_addfb], [FB:180]
><7>[ 1139.836081] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1139.836087] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1139.836089] [drm:intel_crtc_set_config], [CRTC:3] [FB:180] #connectors=1 (x y) (0 0)
><7>[ 1139.836092] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1139.836093] [drm:drm_mode_debug_printmodeline], Modeline 180:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1139.836096] [drm:drm_mode_debug_printmodeline], Modeline 181:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1139.836100] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1139.836102] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1139.836104] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1139.836106] [drm:drm_mode_debug_printmodeline], Modeline 181:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1139.836108] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1139.836111] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1139.843292] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1139.877332] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1139.877338] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1139.877751] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1139.877755] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1139.877790] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1139.877793] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1139.877796] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1139.877798] [drm:drm_mode_debug_printmodeline], Modeline 181:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1139.877803] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1139.877806] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1139.878120] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1139.929271] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1139.933359] [drm:ironlake_update_plane], Writing base 0A7FC000 00000000 0 0 6720
><7>[ 1139.985179] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1139.985186] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1139.985190] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1139.985194] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:181:1680x945]
><7>[ 1139.985198] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1139.985201] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1139.985205] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1139.985208] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1139.985238] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1139.985241] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1140.037153] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1140.089094] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1140.089254] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1140.089915] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1140.089919] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1140.090577] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1140.090581] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1140.090584] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1140.090586] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1140.090591] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1140.108448] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1140.110037] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1140.110045] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1140.110050] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1140.110055] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1140.110059] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1140.110063] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1140.110067] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1140.110070] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1140.110072] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1145.159793] [drm:drm_mode_addfb], [FB:181]
><7>[ 1145.159819] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1145.159824] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1145.159826] [drm:intel_crtc_set_config], [CRTC:3] [FB:181] #connectors=1 (x y) (0 0)
><7>[ 1145.159829] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1145.159831] [drm:drm_mode_debug_printmodeline], Modeline 181:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1145.159834] [drm:drm_mode_debug_printmodeline], Modeline 182:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1145.159837] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1145.159839] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1145.159841] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1145.159843] [drm:drm_mode_debug_printmodeline], Modeline 182:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1145.159846] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1145.159849] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1145.164747] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1145.199457] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1145.199464] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1145.199876] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1145.199879] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1145.199915] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1145.199918] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1145.199921] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1145.199923] [drm:drm_mode_debug_printmodeline], Modeline 182:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1145.199928] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1145.199931] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1145.200245] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1145.251423] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1145.255277] [drm:ironlake_update_plane], Writing base 0AE0B000 00000000 0 0 5632
><7>[ 1145.306360] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1145.306367] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1145.306371] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1145.306375] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:182:1400x1050]
><7>[ 1145.306379] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1145.306383] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1145.306386] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1145.306390] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1145.306420] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1145.306423] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1145.358272] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1145.410248] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1145.410410] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1145.411072] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1145.411076] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1145.411734] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1145.411739] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1145.411741] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1145.411743] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1145.411748] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1145.426371] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1145.427238] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1145.427248] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1145.427253] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1145.427257] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1145.427261] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1145.427265] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1145.427269] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1145.427272] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1145.427275] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1150.475599] [drm:drm_mode_addfb], [FB:182]
><7>[ 1150.475634] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1150.475639] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1150.475642] [drm:intel_crtc_set_config], [CRTC:3] [FB:182] #connectors=1 (x y) (0 0)
><7>[ 1150.475655] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1150.475657] [drm:drm_mode_debug_printmodeline], Modeline 182:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1150.475660] [drm:drm_mode_debug_printmodeline], Modeline 183:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1150.475663] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1150.475666] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1150.475668] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1150.475669] [drm:drm_mode_debug_printmodeline], Modeline 183:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1150.475675] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1150.475681] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1150.483113] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1150.511647] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1150.511654] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1150.512067] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1150.512070] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1150.512106] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1150.512108] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1150.512112] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1150.512114] [drm:drm_mode_debug_printmodeline], Modeline 183:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1150.512119] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1150.512122] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1150.512436] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1150.563557] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1150.567471] [drm:ironlake_update_plane], Writing base 0B3AF000 00000000 0 0 5632
><7>[ 1150.618523] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1150.618531] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1150.618534] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1150.618539] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:183:1400x1050]
><7>[ 1150.618542] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1150.618546] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1150.618549] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1150.618553] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1150.618583] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1150.618586] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1150.670468] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1150.722382] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1150.722544] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1150.723206] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1150.723209] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1150.723867] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1150.723871] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1150.723874] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1150.723876] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1150.723881] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1150.741824] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1150.743364] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1150.743373] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1150.743378] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1150.743383] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1150.743387] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1150.743391] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1150.743395] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1150.743398] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1150.743400] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1155.794934] [drm:drm_mode_addfb], [FB:183]
><7>[ 1155.794959] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1155.794964] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1155.794966] [drm:intel_crtc_set_config], [CRTC:3] [FB:183] #connectors=1 (x y) (0 0)
><7>[ 1155.794969] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1155.794971] [drm:drm_mode_debug_printmodeline], Modeline 183:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1155.794974] [drm:drm_mode_debug_printmodeline], Modeline 184:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1155.794977] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1155.794979] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1155.794981] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1155.794982] [drm:drm_mode_debug_printmodeline], Modeline 184:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1155.794985] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1155.794988] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1155.807293] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1155.840792] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1155.840798] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1155.841211] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1155.841214] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1155.841250] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1155.841253] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1155.841256] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1155.841258] [drm:drm_mode_debug_printmodeline], Modeline 184:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1155.841263] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1155.841266] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1155.841580] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1155.892730] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1155.897137] [drm:ironlake_update_plane], Writing base 0B953000 00000000 0 0 6400
><7>[ 1155.948666] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1155.948674] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1155.948678] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1155.948682] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:184:1600x900]
><7>[ 1155.948686] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1155.948689] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1155.948692] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1155.948696] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1155.948725] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1155.948728] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1156.000612] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1156.052555] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1156.052716] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1156.053378] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1156.053382] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1156.054040] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1156.054045] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1156.054047] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1156.054050] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1156.054055] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1156.072050] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1156.073560] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1156.073570] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1156.073575] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1156.073579] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1156.073584] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1156.073588] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1156.073592] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1156.073594] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1156.073597] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1161.127119] [drm:drm_mode_addfb], [FB:184]
><7>[ 1161.127151] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1161.127157] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1161.127160] [drm:intel_crtc_set_config], [CRTC:3] [FB:184] #connectors=1 (x y) (0 0)
><7>[ 1161.127163] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1161.127165] [drm:drm_mode_debug_printmodeline], Modeline 184:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1161.127168] [drm:drm_mode_debug_printmodeline], Modeline 185:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1161.127172] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1161.127174] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1161.127176] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1161.127178] [drm:drm_mode_debug_printmodeline], Modeline 185:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1161.127181] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1161.127184] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1161.137640] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1161.172939] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1161.172956] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1161.173369] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1161.173372] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1161.173409] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1161.173412] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1161.173415] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1161.173417] [drm:drm_mode_debug_printmodeline], Modeline 185:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1161.173422] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1161.173425] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1161.173740] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1161.224871] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1161.227586] [drm:ironlake_update_plane], Writing base 0BED2000 00000000 0 0 5120
><7>[ 1161.278786] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1161.278794] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1161.278798] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1161.278802] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:185:1280x1024]
><7>[ 1161.278806] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1161.278810] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1161.278813] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1161.278817] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1161.278847] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1161.278849] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1161.330728] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1161.381666] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1161.381827] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1161.382488] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1161.382492] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1161.383156] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1161.383160] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1161.383163] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1161.383165] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1161.383170] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1161.397742] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1161.398666] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1161.398675] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1161.398679] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1161.398683] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1161.398690] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1161.398694] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1161.398697] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1161.398699] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1161.398702] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1166.450657] [drm:drm_mode_addfb], [FB:185]
><7>[ 1166.450686] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1166.450693] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1166.450695] [drm:intel_crtc_set_config], [CRTC:3] [FB:185] #connectors=1 (x y) (0 0)
><7>[ 1166.450699] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1166.450701] [drm:drm_mode_debug_printmodeline], Modeline 185:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1166.450704] [drm:drm_mode_debug_printmodeline], Modeline 186:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1166.450707] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1166.450709] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1166.450711] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1166.450713] [drm:drm_mode_debug_printmodeline], Modeline 186:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1166.450716] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1166.450719] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1166.457122] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1166.484099] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1166.484105] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1166.484518] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1166.484521] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1166.484545] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1166.484547] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1166.484550] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1166.484553] [drm:drm_mode_debug_printmodeline], Modeline 186:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1166.484558] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1166.484561] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1166.484875] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1166.536006] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1166.539420] [drm:ironlake_update_plane], Writing base 0C3D2000 00000000 0 0 5120
><7>[ 1166.590973] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1166.590980] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1166.590984] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1166.590988] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:186:1280x1024]
><7>[ 1166.590992] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1166.590996] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1166.590999] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1166.591003] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1166.591033] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1166.591036] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1166.642918] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1166.694829] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1166.694990] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1166.695652] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1166.695656] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1166.696314] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1166.696319] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1166.696321] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1166.696323] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1166.696328] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1166.714235] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1166.715815] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1166.715824] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1166.715829] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1166.715833] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1166.715838] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1166.715842] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1166.715846] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1166.715849] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1166.715851] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1171.766311] [drm:drm_mode_addfb], [FB:186]
><7>[ 1171.766336] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1171.766342] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1171.766344] [drm:intel_crtc_set_config], [CRTC:3] [FB:186] #connectors=1 (x y) (0 0)
><7>[ 1171.766347] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1171.766348] [drm:drm_mode_debug_printmodeline], Modeline 186:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1171.766351] [drm:drm_mode_debug_printmodeline], Modeline 187:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1171.766355] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1171.766357] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1171.766359] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1171.766360] [drm:drm_mode_debug_printmodeline], Modeline 187:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1171.766363] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1171.766367] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1171.773643] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1171.808248] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1171.808255] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1171.808668] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1171.808671] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1171.808707] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1171.808709] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1171.808712] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1171.808715] [drm:drm_mode_debug_printmodeline], Modeline 187:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1171.808720] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1171.808722] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1171.809037] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1171.860153] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1171.863594] [drm:ironlake_update_plane], Writing base 0C8D2000 00000000 0 0 5760
><7>[ 1171.915123] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1171.915130] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1171.915134] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1171.915138] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:187:1440x900]
><7>[ 1171.915142] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1171.915145] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1171.915149] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1171.915152] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1171.915182] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1171.915185] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1171.967068] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1172.018978] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1172.019140] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1172.019800] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1172.019804] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1172.020465] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1172.020469] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1172.020471] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1172.020474] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1172.020478] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1172.035070] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1172.036014] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1172.036025] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1172.036032] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1172.036038] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1172.036045] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1172.036056] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1172.036062] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1172.036067] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1172.036072] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1177.084109] [drm:drm_mode_addfb], [FB:187]
><7>[ 1177.084134] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1177.084139] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1177.084141] [drm:intel_crtc_set_config], [CRTC:3] [FB:187] #connectors=1 (x y) (0 0)
><7>[ 1177.084144] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1177.084146] [drm:drm_mode_debug_printmodeline], Modeline 187:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1177.084149] [drm:drm_mode_debug_printmodeline], Modeline 188:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1177.084152] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1177.084154] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1177.084156] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1177.084158] [drm:drm_mode_debug_printmodeline], Modeline 188:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1177.084161] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1177.084164] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1177.093138] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1177.121410] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1177.121416] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1177.121829] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1177.121832] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1177.121868] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1177.121871] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1177.121874] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1177.121876] [drm:drm_mode_debug_printmodeline], Modeline 188:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1177.121881] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1177.121884] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1177.122198] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1177.173315] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1177.177302] [drm:ironlake_update_plane], Writing base 0CDC4000 00000000 0 0 5760
><7>[ 1177.229284] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1177.229291] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1177.229295] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1177.229299] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:188:1440x900]
><7>[ 1177.229303] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1177.229306] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1177.229310] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1177.229314] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1177.229343] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1177.229346] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1177.281230] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1177.333140] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1177.333301] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1177.333963] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1177.333967] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1177.334627] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1177.334631] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1177.334634] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1177.334636] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1177.334641] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1177.352550] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1177.354115] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1177.354123] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1177.354128] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1177.354132] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1177.354137] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1177.354141] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1177.354145] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1177.354147] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1177.354150] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1182.404868] [drm:drm_mode_addfb], [FB:188]
><7>[ 1182.404892] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1182.404898] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1182.404900] [drm:intel_crtc_set_config], [CRTC:3] [FB:188] #connectors=1 (x y) (0 0)
><7>[ 1182.404903] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1182.404905] [drm:drm_mode_debug_printmodeline], Modeline 188:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1182.404908] [drm:drm_mode_debug_printmodeline], Modeline 189:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1182.404911] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1182.404913] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1182.404915] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1182.404917] [drm:drm_mode_debug_printmodeline], Modeline 189:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1182.404920] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1182.404923] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1182.407709] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1182.442563] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1182.442570] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1182.442983] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1182.442986] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1182.443008] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1182.443011] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1182.443014] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1182.443017] [drm:drm_mode_debug_printmodeline], Modeline 189:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1182.443022] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1182.443024] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1182.443339] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1182.494502] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1182.498498] [drm:ironlake_update_plane], Writing base 0D2B6000 00000000 0 0 5120
><7>[ 1182.550437] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1182.550444] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1182.550448] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1182.550453] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:189:1280x960]
><7>[ 1182.550456] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1182.550460] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1182.550463] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1182.550467] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1182.550497] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1182.550500] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1182.602382] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1182.654325] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1182.654487] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1182.655148] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1182.655152] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1182.655810] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1182.655814] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1182.655817] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1182.655819] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1182.655824] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1182.673743] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1182.675311] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1182.675320] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1182.675325] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1182.675330] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1182.675334] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1182.675338] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1182.675342] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1182.675345] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1182.675347] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1187.722114] [drm:drm_mode_addfb], [FB:189]
><7>[ 1187.722138] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1187.722144] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1187.722146] [drm:intel_crtc_set_config], [CRTC:3] [FB:189] #connectors=1 (x y) (0 0)
><7>[ 1187.722149] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1187.722150] [drm:drm_mode_debug_printmodeline], Modeline 189:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1187.722153] [drm:drm_mode_debug_printmodeline], Modeline 190:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1187.722157] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1187.722159] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1187.722161] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1187.722162] [drm:drm_mode_debug_printmodeline], Modeline 190:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1187.722165] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1187.722168] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1187.734826] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1187.769710] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1187.769716] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1187.770129] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1187.770132] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1187.770168] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1187.770170] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1187.770173] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1187.770176] [drm:drm_mode_debug_printmodeline], Modeline 190:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1187.770180] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1187.770183] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1187.770497] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1187.821615] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1187.824429] [drm:ironlake_update_plane], Writing base 0D766000 00000000 0 0 5504
><7>[ 1187.875586] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1187.875593] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1187.875597] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1187.875601] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:190:1366x768]
><7>[ 1187.875605] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1187.875608] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1187.875612] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1187.875614] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1187.875644] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1187.875647] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1187.927532] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1187.979474] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1187.979636] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1187.980298] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1187.980301] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1187.980959] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1187.980964] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1187.980966] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1187.980969] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1187.980973] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1187.998956] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1188.000459] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1188.000469] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1188.000473] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1188.000478] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1188.000482] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1188.000486] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1188.000490] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1188.000493] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1188.000495] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1193.047138] [drm:drm_mode_addfb], [FB:190]
><7>[ 1193.047163] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1193.047169] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1193.047171] [drm:intel_crtc_set_config], [CRTC:3] [FB:190] #connectors=1 (x y) (0 0)
><7>[ 1193.047174] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1193.047175] [drm:drm_mode_debug_printmodeline], Modeline 190:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1193.047178] [drm:drm_mode_debug_printmodeline], Modeline 191:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1193.047182] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1193.047184] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1193.047186] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1193.047187] [drm:drm_mode_debug_printmodeline], Modeline 191:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1193.047190] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1193.047193] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1193.061113] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1193.094859] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1193.094865] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1193.095279] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1193.095282] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1193.095317] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1193.095320] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1193.095323] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1193.095325] [drm:drm_mode_debug_printmodeline], Modeline 191:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1193.095330] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1193.095333] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1193.095647] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1193.146768] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1193.150137] [drm:ironlake_update_plane], Writing base 0DB6E000 00000000 0 0 5440
><7>[ 1193.201734] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1193.201741] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1193.201745] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1193.201750] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:191:1360x768]
><7>[ 1193.201753] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1193.201757] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1193.201760] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1193.201764] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1193.201794] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1193.201797] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1193.253651] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1193.305590] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1193.305751] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1193.306413] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1193.306417] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1193.307076] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1193.307080] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1193.307082] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1193.307085] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1193.307089] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1193.325009] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1193.326575] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1193.326584] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1193.326588] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1193.326593] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1193.326597] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1193.326601] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1193.326605] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1193.326608] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1193.326610] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1198.376030] [drm:drm_mode_addfb], [FB:191]
><7>[ 1198.376054] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1198.376061] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1198.376063] [drm:intel_crtc_set_config], [CRTC:3] [FB:191] #connectors=1 (x y) (0 0)
><7>[ 1198.376066] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1198.376067] [drm:drm_mode_debug_printmodeline], Modeline 191:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1198.376070] [drm:drm_mode_debug_printmodeline], Modeline 192:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1198.376074] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1198.376076] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1198.376078] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1198.376079] [drm:drm_mode_debug_printmodeline], Modeline 192:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1198.376082] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1198.376085] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1198.384803] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1198.419980] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1198.419986] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1198.420399] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1198.420402] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1198.420424] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1198.420427] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1198.420430] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1198.420432] [drm:drm_mode_debug_printmodeline], Modeline 192:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1198.420438] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1198.420440] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1198.420755] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1198.471946] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1198.474643] [drm:ironlake_update_plane], Writing base 0DF6A000 00000000 0 0 5120
><7>[ 1198.525885] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1198.525892] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1198.525896] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1198.525900] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:192:1280x800]
><7>[ 1198.525904] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1198.525907] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1198.525910] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1198.525914] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1198.525944] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1198.525947] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1198.577830] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1198.629740] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1198.629901] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1198.630563] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1198.630567] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1198.631225] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1198.631229] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1198.631231] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1198.631234] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1198.631239] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1198.645828] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1198.646765] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1198.646775] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1198.646780] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1198.646784] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1198.646791] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1198.646796] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1198.646800] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1198.646802] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1198.646805] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1203.693792] [drm:drm_mode_addfb], [FB:192]
><7>[ 1203.693816] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1203.693822] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1203.693824] [drm:intel_crtc_set_config], [CRTC:3] [FB:192] #connectors=1 (x y) (0 0)
><7>[ 1203.693827] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1203.693829] [drm:drm_mode_debug_printmodeline], Modeline 192:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1203.693832] [drm:drm_mode_debug_printmodeline], Modeline 193:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1203.693836] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1203.693838] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1203.693839] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1203.693841] [drm:drm_mode_debug_printmodeline], Modeline 193:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1203.693844] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1203.693847] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1203.703428] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1203.731172] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1203.731178] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1203.731591] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1203.731594] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1203.731630] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1203.731633] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1203.731636] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1203.731638] [drm:drm_mode_debug_printmodeline], Modeline 193:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1203.731643] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1203.731646] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1203.731960] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1203.783110] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1203.785841] [drm:ironlake_update_plane], Writing base 0E352000 00000000 0 0 5120
><7>[ 1203.837048] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1203.837056] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1203.837060] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1203.837064] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:193:1280x800]
><7>[ 1203.837068] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1203.837071] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1203.837074] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1203.837078] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1203.837108] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1203.837111] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1203.888994] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1203.940937] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1203.941098] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1203.941760] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1203.941764] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1203.942422] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1203.942427] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1203.942429] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1203.942432] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1203.942436] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1203.960312] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1203.961922] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1203.961932] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1203.961937] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1203.961941] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1203.961945] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1203.961950] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1203.961954] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1203.961956] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1203.961959] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1209.008186] [drm:drm_mode_addfb], [FB:193]
><7>[ 1209.008211] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1209.008216] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1209.008218] [drm:intel_crtc_set_config], [CRTC:3] [FB:193] #connectors=1 (x y) (0 0)
><7>[ 1209.008221] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1209.008223] [drm:drm_mode_debug_printmodeline], Modeline 193:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1209.008226] [drm:drm_mode_debug_printmodeline], Modeline 194:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1209.008229] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1209.008231] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1209.008233] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1209.008234] [drm:drm_mode_debug_printmodeline], Modeline 194:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1209.008237] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1209.008240] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1209.011258] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1209.045333] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1209.045339] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1209.045752] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1209.045755] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1209.045778] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1209.045780] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1209.045783] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1209.045786] [drm:drm_mode_debug_printmodeline], Modeline 194:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1209.045791] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1209.045793] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1209.046108] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1209.097271] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1209.099892] [drm:ironlake_update_plane], Writing base 0E73A000 00000000 0 0 4608
><7>[ 1209.151209] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1209.151216] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1209.151220] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1209.151224] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:194:1152x864]
><7>[ 1209.151228] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1209.151231] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1209.151235] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1209.151238] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1209.151268] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1209.151271] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1209.203155] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1209.255097] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1209.255258] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1209.255919] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1209.255924] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1209.256582] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1209.256586] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1209.256589] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1209.256591] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1209.256596] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1209.271194] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1209.272086] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1209.272095] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1209.272100] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1209.272105] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1209.272109] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1209.272113] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1209.272117] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1209.272120] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1209.272123] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1214.319896] [drm:drm_mode_addfb], [FB:194]
><7>[ 1214.319919] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1214.319925] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1214.319927] [drm:intel_crtc_set_config], [CRTC:3] [FB:194] #connectors=1 (x y) (0 0)
><7>[ 1214.319929] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1214.319931] [drm:drm_mode_debug_printmodeline], Modeline 194:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1214.319934] [drm:drm_mode_debug_printmodeline], Modeline 195:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1214.319937] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1214.319939] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1214.319941] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1214.319942] [drm:drm_mode_debug_printmodeline], Modeline 195:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1214.319945] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1214.319948] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1214.332264] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1214.359494] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1214.359500] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1214.359913] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1214.359916] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1214.359952] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1214.359955] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1214.359958] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1214.359960] [drm:drm_mode_debug_printmodeline], Modeline 195:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1214.359965] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1214.359968] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1214.360282] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1214.411432] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1214.414020] [drm:ironlake_update_plane], Writing base 0EB06000 00000000 0 0 5120
><7>[ 1214.465370] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1214.465378] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1214.465381] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1214.465386] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:195:1280x768]
><7>[ 1214.465389] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1214.465393] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1214.465396] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1214.465400] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1214.465429] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1214.465432] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1214.517316] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1214.569259] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1214.569420] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1214.570082] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1214.570085] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1214.570743] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1214.570748] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1214.570750] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1214.570752] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1214.570757] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1214.585408] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1214.586248] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1214.586258] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1214.586264] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1214.586272] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1214.586276] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1214.586280] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1214.586284] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1214.586289] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1214.586294] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1219.641866] [drm:drm_mode_addfb], [FB:195]
><7>[ 1219.641898] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1219.641906] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1219.641909] [drm:intel_crtc_set_config], [CRTC:3] [FB:195] #connectors=1 (x y) (0 0)
><7>[ 1219.641913] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1219.641915] [drm:drm_mode_debug_printmodeline], Modeline 195:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1219.641918] [drm:drm_mode_debug_printmodeline], Modeline 196:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1219.641921] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1219.641924] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1219.641926] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1219.641927] [drm:drm_mode_debug_printmodeline], Modeline 196:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1219.641930] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1219.641934] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1219.652701] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1219.679607] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1219.679614] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1219.680028] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1219.680031] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1219.680056] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1219.680059] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1219.680062] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1219.680065] [drm:drm_mode_debug_printmodeline], Modeline 196:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1219.680070] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1219.680073] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1219.680388] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1219.731555] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1219.733487] [drm:ironlake_update_plane], Writing base 0EEC6000 00000000 0 0 5120
><7>[ 1219.784489] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1219.784501] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1219.784507] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1219.784513] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:196:1280x768]
><7>[ 1219.784516] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1219.784521] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1219.784524] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1219.784528] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1219.784559] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1219.784562] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1219.836434] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1219.888388] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1219.888551] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1219.889213] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1219.889217] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1219.889875] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1219.889879] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1219.889882] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1219.889885] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1219.889889] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1219.907840] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1219.909359] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1219.909369] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1219.909374] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1219.909379] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1219.909383] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1219.909387] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1219.909391] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1219.909394] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1219.909397] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1224.960962] [drm:drm_mode_addfb], [FB:196]
><7>[ 1224.960991] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1224.960998] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1224.961000] [drm:intel_crtc_set_config], [CRTC:3] [FB:196] #connectors=1 (x y) (0 0)
><7>[ 1224.961004] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1224.961005] [drm:drm_mode_debug_printmodeline], Modeline 196:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1224.961009] [drm:drm_mode_debug_printmodeline], Modeline 197:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1224.961012] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1224.961014] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1224.961016] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1224.961018] [drm:drm_mode_debug_printmodeline], Modeline 197:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1224.961021] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1224.961024] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1224.971289] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1225.004798] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1225.004804] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1225.005218] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1225.005221] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1225.005258] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1225.005261] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1225.005264] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1225.005267] [drm:drm_mode_debug_printmodeline], Modeline 197:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1225.005272] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1225.005274] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1225.005587] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1225.056736] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1225.059205] [drm:ironlake_update_plane], Writing base 0F286000 00000000 0 0 5120
><7>[ 1225.110643] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1225.110650] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1225.110654] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1225.110658] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:197:1280x720]
><7>[ 1225.110662] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1225.110665] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1225.110669] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1225.110672] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1225.110703] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1225.110705] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1225.162619] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1225.214569] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1225.214730] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1225.215391] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1225.215395] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1225.216054] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1225.216059] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1225.216061] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1225.216063] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1225.216068] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1225.237317] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1225.237514] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1225.237523] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1225.237528] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1225.237533] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1225.237537] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1225.237545] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1225.237551] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1225.237554] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1225.237557] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1230.283666] [drm:drm_mode_addfb], [FB:197]
><7>[ 1230.283689] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1230.283695] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1230.283697] [drm:intel_crtc_set_config], [CRTC:3] [FB:197] #connectors=1 (x y) (0 0)
><7>[ 1230.283700] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1230.283701] [drm:drm_mode_debug_printmodeline], Modeline 197:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1230.283704] [drm:drm_mode_debug_printmodeline], Modeline 198:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1230.283707] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1230.283709] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1230.283711] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1230.283713] [drm:drm_mode_debug_printmodeline], Modeline 198:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1230.283716] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1230.283718] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1230.291729] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1230.332944] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1230.332950] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1230.333362] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1230.333366] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1230.333401] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1230.333404] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1230.333407] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1230.333410] [drm:drm_mode_debug_printmodeline], Modeline 198:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1230.333415] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1230.333417] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1230.333732] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1230.384848] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1230.387702] [drm:ironlake_update_plane], Writing base 0F60A000 00000000 0 0 5120
><7>[ 1230.438820] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1230.438827] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1230.438831] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1230.438835] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:198:1280x720]
><7>[ 1230.438839] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1230.438842] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1230.438845] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1230.438849] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1230.438879] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1230.438882] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1230.490764] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1230.542708] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1230.542868] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1230.543530] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1230.543534] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1230.544192] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1230.544195] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1230.544197] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1230.544200] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1230.544204] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1230.562111] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1230.563692] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1230.563702] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1230.563707] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1230.563711] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1230.563716] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1230.563720] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1230.563724] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1230.563726] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1230.563729] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1235.608364] [drm:drm_mode_addfb], [FB:198]
><7>[ 1235.608388] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1235.608393] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1235.608396] [drm:intel_crtc_set_config], [CRTC:3] [FB:198] #connectors=1 (x y) (0 0)
><7>[ 1235.608398] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1235.608400] [drm:drm_mode_debug_printmodeline], Modeline 198:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1235.608403] [drm:drm_mode_debug_printmodeline], Modeline 199:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1235.608406] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1235.608408] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1235.608410] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1235.608412] [drm:drm_mode_debug_printmodeline], Modeline 199:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1235.608414] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1235.608417] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1235.623206] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1235.658092] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1235.658098] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1235.658511] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1235.658515] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1235.658537] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1235.658540] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1235.658543] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1235.658545] [drm:drm_mode_debug_printmodeline], Modeline 199:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1235.658550] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1235.658553] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1235.658866] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1235.710001] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1235.712074] [drm:ironlake_update_plane], Writing base 0F98E000 00000000 0 0 4096
><7>[ 1235.763968] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1235.763976] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1235.763979] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1235.763984] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:199:1024x768]
><7>[ 1235.763987] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1235.763991] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1235.763994] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1235.763998] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1235.764028] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1235.764030] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1235.815913] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1235.867857] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1235.868018] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1235.868679] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1235.868683] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1235.869341] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1235.869345] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1235.869348] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1235.869350] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1235.869355] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1235.883907] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1235.884844] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1235.884854] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1235.884859] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1235.884867] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1235.884871] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1235.884877] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1235.884881] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1235.884884] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1235.884886] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1240.930542] [drm:drm_mode_addfb], [FB:199]
><7>[ 1240.930566] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1240.930571] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1240.930573] [drm:intel_crtc_set_config], [CRTC:3] [FB:199] #connectors=1 (x y) (0 0)
><7>[ 1240.930576] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1240.930578] [drm:drm_mode_debug_printmodeline], Modeline 199:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1240.930581] [drm:drm_mode_debug_printmodeline], Modeline 200:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1240.930584] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1240.930587] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1240.930588] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1240.930590] [drm:drm_mode_debug_printmodeline], Modeline 200:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1240.930593] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1240.930596] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1240.940279] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1240.968258] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1240.968264] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1240.968677] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1240.968680] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1240.968716] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1240.968718] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1240.968721] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1240.968724] [drm:drm_mode_debug_printmodeline], Modeline 200:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1240.968729] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1240.968732] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1240.969046] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1241.020195] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1241.022613] [drm:ironlake_update_plane], Writing base 0FC8E000 00000000 0 0 4096
><7>[ 1241.074102] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1241.074109] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1241.074113] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1241.074117] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:200:1024x768]
><7>[ 1241.074121] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1241.074124] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1241.074127] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1241.074131] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1241.074161] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1241.074164] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1241.126078] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1241.178022] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1241.178183] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1241.178845] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1241.178849] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1241.179507] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1241.179512] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1241.179514] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1241.179517] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1241.179521] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1241.195003] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1241.195025] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1241.195033] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1241.195037] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1241.195042] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1241.195046] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1241.195050] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1241.195054] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1241.195057] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1241.195059] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1246.242998] [drm:drm_mode_addfb], [FB:200]
><7>[ 1246.243022] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1246.243028] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1246.243030] [drm:intel_crtc_set_config], [CRTC:3] [FB:200] #connectors=1 (x y) (0 0)
><7>[ 1246.243033] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1246.243034] [drm:drm_mode_debug_printmodeline], Modeline 200:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1246.243037] [drm:drm_mode_debug_printmodeline], Modeline 201:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1246.243041] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1246.243043] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1246.243045] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1246.243046] [drm:drm_mode_debug_printmodeline], Modeline 201:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1246.243049] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1246.243052] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1246.255868] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1246.284417] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1246.284423] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1246.284836] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1246.284839] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1246.284861] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1246.284864] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1246.284867] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1246.284869] [drm:drm_mode_debug_printmodeline], Modeline 201:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1246.284874] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1246.284877] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1246.285192] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1246.336354] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1246.338417] [drm:ironlake_update_plane], Writing base 0085C000 00000000 0 0 4096
><7>[ 1246.390292] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1246.390299] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1246.390303] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1246.390307] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:201:1024x768]
><7>[ 1246.390310] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1246.390314] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1246.390317] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1246.390321] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1246.390350] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1246.390353] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1246.442239] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1246.494180] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1246.494341] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1246.495003] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1246.495008] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1246.495665] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1246.495669] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1246.495672] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1246.495674] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1246.495679] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1246.513653] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1246.515165] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1246.515175] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1246.515180] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1246.515184] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1246.515189] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1246.515193] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1246.515197] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1246.515199] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1246.515202] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1251.555941] [drm:drm_mode_addfb], [FB:201]
><7>[ 1251.555964] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1251.555970] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1251.555972] [drm:intel_crtc_set_config], [CRTC:3] [FB:201] #connectors=1 (x y) (0 0)
><7>[ 1251.555975] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1251.555976] [drm:drm_mode_debug_printmodeline], Modeline 201:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1251.555979] [drm:drm_mode_debug_printmodeline], Modeline 202:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1251.555982] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1251.555984] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1251.555986] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1251.555988] [drm:drm_mode_debug_printmodeline], Modeline 202:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1251.555991] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1251.555994] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1251.556596] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1251.591557] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1251.591563] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1251.591976] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1251.591979] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1251.592002] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1251.592004] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1251.592007] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1251.592010] [drm:drm_mode_debug_printmodeline], Modeline 202:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1251.592015] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1251.592017] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1251.592330] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1251.643522] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1251.645058] [drm:ironlake_update_plane], Writing base 00B5C000 00000000 0 0 4096
><7>[ 1251.696462] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1251.696470] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1251.696474] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1251.696478] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:202:1024x576]
><7>[ 1251.696481] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1251.696485] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1251.696488] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1251.696492] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1251.696522] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1251.696525] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1251.748382] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1251.800350] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1251.800512] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1251.801173] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1251.801177] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1251.801835] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1251.801840] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1251.801842] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1251.801844] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1251.801849] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1251.819819] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1251.821302] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1251.821311] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1251.821316] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1251.821321] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1251.821325] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1251.821329] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1251.821333] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1251.821336] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1251.821338] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1256.860227] [drm:drm_mode_addfb], [FB:202]
><7>[ 1256.860251] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1256.860256] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1256.860258] [drm:intel_crtc_set_config], [CRTC:3] [FB:202] #connectors=1 (x y) (0 0)
><7>[ 1256.860261] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1256.860262] [drm:drm_mode_debug_printmodeline], Modeline 202:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1256.860265] [drm:drm_mode_debug_printmodeline], Modeline 203:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1256.860269] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1256.860271] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1256.860273] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1256.860274] [drm:drm_mode_debug_printmodeline], Modeline 203:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1256.860277] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1256.860280] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1256.862477] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1256.897755] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1256.897761] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1256.898174] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1256.898177] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1256.898199] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1256.898202] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1256.898205] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1256.898208] [drm:drm_mode_debug_printmodeline], Modeline 203:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1256.898213] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1256.898215] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1256.898530] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1256.949692] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1256.951063] [drm:ironlake_update_plane], Writing base 00D9C000 00000000 0 0 3328
><7>[ 1257.002632] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1257.002639] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1257.002643] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1257.002647] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:203:832x624]
><7>[ 1257.002651] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1257.002654] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1257.002657] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1257.002661] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1257.002691] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1257.002694] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1257.054577] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1257.106487] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1257.106648] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1257.107310] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1257.107314] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1257.107978] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1257.107982] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1257.107985] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1257.107987] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1257.107992] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1257.122656] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1257.123509] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1257.123519] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1257.123524] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1257.123531] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1257.123535] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1257.123541] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1257.123545] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1257.123548] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1257.123550] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1262.162815] [drm:drm_mode_addfb], [FB:203]
><7>[ 1262.162838] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1262.162843] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1262.162846] [drm:intel_crtc_set_config], [CRTC:3] [FB:203] #connectors=1 (x y) (0 0)
><7>[ 1262.162848] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1262.162850] [drm:drm_mode_debug_printmodeline], Modeline 203:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1262.162853] [drm:drm_mode_debug_printmodeline], Modeline 204:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1262.162856] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1262.162859] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1262.162860] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1262.162862] [drm:drm_mode_debug_printmodeline], Modeline 204:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1262.162865] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1262.162868] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1262.169645] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1262.197909] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1262.197915] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1262.198328] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1262.198331] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1262.198354] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1262.198356] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1262.198359] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1262.198362] [drm:drm_mode_debug_printmodeline], Modeline 204:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1262.198367] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1262.198370] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1262.198683] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1262.249840] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1262.251092] [drm:ironlake_update_plane], Writing base 00F97000 00000000 0 0 3200
><7>[ 1262.302808] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1262.302815] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1262.302819] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1262.302824] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:204:800x600]
><7>[ 1262.302827] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1262.302830] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1262.302834] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1262.302837] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1262.302866] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1262.302869] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1262.354753] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1262.406696] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1262.406857] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1262.407519] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1262.407523] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1262.408180] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1262.408185] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1262.408187] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1262.408190] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1262.408194] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1262.423388] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1262.423689] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1262.423700] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1262.423707] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1262.423713] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1262.423722] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1262.423731] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1262.423737] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1262.423741] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1262.423745] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1267.464468] [drm:drm_mode_addfb], [FB:204]
><7>[ 1267.464491] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1267.464496] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1267.464498] [drm:intel_crtc_set_config], [CRTC:3] [FB:204] #connectors=1 (x y) (0 0)
><7>[ 1267.464501] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1267.464503] [drm:drm_mode_debug_printmodeline], Modeline 204:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1267.464506] [drm:drm_mode_debug_printmodeline], Modeline 205:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1267.464509] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1267.464511] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1267.464513] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1267.464515] [drm:drm_mode_debug_printmodeline], Modeline 205:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1267.464517] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1267.464520] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1267.475268] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1267.504068] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1267.504075] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1267.504488] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1267.504491] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1267.504513] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1267.504516] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1267.504519] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1267.504521] [drm:drm_mode_debug_printmodeline], Modeline 205:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1267.504526] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1267.504529] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1267.504842] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1267.556038] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1267.557463] [drm:ironlake_update_plane], Writing base 0116C000 00000000 0 0 3200
><7>[ 1267.608977] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1267.608985] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1267.608989] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1267.608993] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:205:800x600]
><7>[ 1267.608996] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1267.609000] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1267.609003] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1267.609007] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1267.609037] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1267.609040] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1267.660923] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1267.712866] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1267.713027] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1267.713688] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1267.713692] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1267.714350] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1267.714354] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1267.714356] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1267.714359] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1267.714363] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1267.728901] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1267.729854] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1267.729864] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1267.729869] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1267.729874] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1267.729879] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1267.729884] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1267.729890] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1267.729893] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1267.729896] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1272.770512] [drm:drm_mode_addfb], [FB:205]
><7>[ 1272.770535] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1272.770540] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1272.770542] [drm:intel_crtc_set_config], [CRTC:3] [FB:205] #connectors=1 (x y) (0 0)
><7>[ 1272.770545] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1272.770547] [drm:drm_mode_debug_printmodeline], Modeline 205:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1272.770550] [drm:drm_mode_debug_printmodeline], Modeline 206:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1272.770553] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1272.770555] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1272.770557] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1272.770559] [drm:drm_mode_debug_printmodeline], Modeline 206:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1272.770561] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1272.770564] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1272.781415] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1272.808239] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1272.808246] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1272.808658] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1272.808661] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1272.808684] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1272.808687] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1272.808690] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1272.808692] [drm:drm_mode_debug_printmodeline], Modeline 206:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1272.808697] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1272.808700] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1272.809013] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1272.860210] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1272.861472] [drm:ironlake_update_plane], Writing base 01341000 00000000 0 0 3200
><7>[ 1272.913150] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1272.913157] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1272.913161] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1272.913166] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:206:800x600]
><7>[ 1272.913169] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1272.913173] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1272.913176] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1272.913180] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1272.913210] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1272.913213] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1272.965096] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1273.017039] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1273.017199] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1273.017860] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1273.017864] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1273.018524] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1273.018528] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1273.018531] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1273.018533] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1273.018537] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1273.036372] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1273.037982] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1273.037991] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1273.037995] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1273.037999] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1273.038004] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1273.038008] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1273.038012] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1273.038014] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1273.038017] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1278.087342] [drm:drm_mode_addfb], [FB:206]
><7>[ 1278.087374] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1278.087381] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1278.087384] [drm:intel_crtc_set_config], [CRTC:3] [FB:206] #connectors=1 (x y) (0 0)
><7>[ 1278.087388] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1278.087390] [drm:drm_mode_debug_printmodeline], Modeline 206:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1278.087393] [drm:drm_mode_debug_printmodeline], Modeline 207:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1278.087397] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1278.087399] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1278.087401] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1278.087403] [drm:drm_mode_debug_printmodeline], Modeline 207:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1278.087420] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1278.087427] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1278.103976] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1278.137389] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1278.137395] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1278.137809] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1278.137812] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1278.137850] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1278.137853] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1278.137856] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1278.137859] [drm:drm_mode_debug_printmodeline], Modeline 207:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1278.137864] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1278.137867] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1278.138182] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1278.189315] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1278.190268] [drm:ironlake_update_plane], Writing base 01516000 00000000 0 0 3200
><7>[ 1278.241256] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1278.241265] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1278.241270] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1278.241275] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:207:800x600]
><7>[ 1278.241279] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1278.241283] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1278.241287] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1278.241291] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1278.241320] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1278.241323] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1278.293200] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1278.345150] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1278.345312] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1278.345974] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1278.345978] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1278.346643] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1278.346648] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1278.346650] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1278.346653] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1278.346658] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1278.365639] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1278.366130] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1278.366140] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1278.366145] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1278.366150] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1278.366154] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1278.366158] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1278.366162] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1278.366167] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1278.366173] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1283.401151] [drm:drm_mode_addfb], [FB:207]
><7>[ 1283.401180] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1283.401186] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1283.401189] [drm:intel_crtc_set_config], [CRTC:3] [FB:207] #connectors=1 (x y) (0 0)
><7>[ 1283.401192] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1283.401194] [drm:drm_mode_debug_printmodeline], Modeline 207:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1283.401197] [drm:drm_mode_debug_printmodeline], Modeline 208:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1283.401200] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1283.401202] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1283.401204] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1283.401206] [drm:drm_mode_debug_printmodeline], Modeline 208:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1283.401209] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1283.401212] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1283.409006] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1283.445585] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1283.445591] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1283.446004] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1283.446008] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1283.446058] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1283.446060] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1283.446063] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1283.446066] [drm:drm_mode_debug_printmodeline], Modeline 208:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1283.446071] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1283.446074] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1283.446388] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1283.497490] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1283.498718] [drm:ironlake_update_plane], Writing base 016EB000 00000000 0 0 2880
><7>[ 1283.550463] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1283.550470] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1283.550474] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1283.550479] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:208:720x576]
><7>[ 1283.550482] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1283.550486] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1283.550489] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1283.550493] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1283.550523] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1283.550526] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1283.602407] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1283.654350] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1283.654511] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1283.655173] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1283.655177] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1283.655834] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1283.655839] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1283.655841] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1283.655843] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1283.655848] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1283.677100] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1283.677305] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1283.677314] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1283.677319] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1283.677324] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1283.677328] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1283.677332] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1283.677340] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1283.677346] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1283.677349] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1288.711398] [drm:drm_mode_addfb], [FB:208]
><7>[ 1288.711422] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1288.711428] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1288.711430] [drm:intel_crtc_set_config], [CRTC:3] [FB:208] #connectors=1 (x y) (0 0)
><7>[ 1288.711432] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1288.711434] [drm:drm_mode_debug_printmodeline], Modeline 208:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1288.711437] [drm:drm_mode_debug_printmodeline], Modeline 209:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1288.711440] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1288.711442] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1288.711444] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1288.711446] [drm:drm_mode_debug_printmodeline], Modeline 209:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1288.711449] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1288.711451] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1288.711477] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1288.752753] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1288.752759] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1288.753172] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1288.753175] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1288.753211] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1288.753214] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1288.753217] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1288.753219] [drm:drm_mode_debug_printmodeline], Modeline 209:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1288.753224] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1288.753227] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1288.753541] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1288.804692] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1288.805774] [drm:ironlake_update_plane], Writing base 01880000 00000000 0 0 3392
><7>[ 1288.857631] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1288.857638] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1288.857642] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1288.857646] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:209:848x480]
><7>[ 1288.857650] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1288.857653] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1288.857656] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1288.857660] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1288.857690] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1288.857693] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1288.909576] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1288.961487] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1288.961648] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1288.962309] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1288.962313] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1288.962977] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1288.962981] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1288.962983] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1288.962986] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1288.962990] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1288.980910] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1288.982503] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1288.982513] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1288.982517] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1288.982522] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1288.982526] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1288.982530] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1288.982534] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1288.982537] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1288.982539] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1294.013640] [drm:drm_mode_addfb], [FB:209]
><7>[ 1294.013663] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1294.013669] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1294.013671] [drm:intel_crtc_set_config], [CRTC:3] [FB:209] #connectors=1 (x y) (0 0)
><7>[ 1294.013674] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1294.013675] [drm:drm_mode_debug_printmodeline], Modeline 209:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1294.013678] [drm:drm_mode_debug_printmodeline], Modeline 210:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1294.013681] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1294.013684] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1294.013685] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1294.013687] [drm:drm_mode_debug_printmodeline], Modeline 210:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1294.013690] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1294.013693] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1294.025297] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1294.058923] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1294.058929] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1294.059343] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1294.059346] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1294.059395] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1294.059398] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1294.059401] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1294.059403] [drm:drm_mode_debug_printmodeline], Modeline 210:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1294.059408] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1294.059411] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1294.059726] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1294.110861] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1294.111731] [drm:ironlake_update_plane], Writing base 01A0E000 00000000 0 0 2880
><7>[ 1294.162775] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1294.162783] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1294.162787] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1294.162791] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:210:720x480]
><7>[ 1294.162795] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1294.162798] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1294.162802] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1294.162805] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1294.162835] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1294.162838] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1294.213748] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1294.265659] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1294.265819] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1294.266481] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1294.266485] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1294.267151] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1294.267155] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1294.267158] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1294.267160] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1294.267165] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1294.285102] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1294.286668] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1294.286678] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1294.286682] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1294.286687] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1294.286691] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1294.286696] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1294.286699] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1294.286702] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1294.286705] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1299.315546] [drm:drm_mode_addfb], [FB:210]
><7>[ 1299.315569] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1299.315574] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1299.315576] [drm:intel_crtc_set_config], [CRTC:3] [FB:210] #connectors=1 (x y) (0 0)
><7>[ 1299.315579] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1299.315580] [drm:drm_mode_debug_printmodeline], Modeline 210:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1299.315583] [drm:drm_mode_debug_printmodeline], Modeline 211:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1299.315586] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1299.315588] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1299.315590] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1299.315592] [drm:drm_mode_debug_printmodeline], Modeline 211:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1299.315595] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1299.315597] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1299.317906] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1299.353107] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1299.353113] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1299.353526] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1299.353529] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1299.353564] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1299.353567] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1299.353570] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1299.353572] [drm:drm_mode_debug_printmodeline], Modeline 211:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1299.353577] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1299.353580] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1299.353894] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1299.405044] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1299.405810] [drm:ironlake_update_plane], Writing base 01B60000 00000000 0 0 2560
><7>[ 1299.456984] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1299.456991] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1299.456995] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1299.457000] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:211:640x480]
><7>[ 1299.457003] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1299.457006] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1299.457009] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1299.457013] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1299.457042] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1299.457045] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1299.508897] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1299.560874] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1299.561036] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1299.561697] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1299.561702] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1299.562359] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1299.562364] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1299.562366] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1299.562369] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1299.562373] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1299.577367] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1299.577864] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1299.577874] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1299.577878] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1299.577883] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1299.577887] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1299.577891] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1299.577895] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1299.577898] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1299.577900] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1304.604254] [drm:drm_mode_addfb], [FB:211]
><7>[ 1304.604288] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1304.604294] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1304.604306] [drm:intel_crtc_set_config], [CRTC:3] [FB:211] #connectors=1 (x y) (0 0)
><7>[ 1304.604309] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1304.604311] [drm:drm_mode_debug_printmodeline], Modeline 211:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1304.604314] [drm:drm_mode_debug_printmodeline], Modeline 212:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1304.604318] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1304.604320] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1304.604324] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1304.604327] [drm:drm_mode_debug_printmodeline], Modeline 212:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1304.604333] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1304.604338] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1304.612365] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1304.640297] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1304.640303] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1304.640715] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1304.640719] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1304.640754] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1304.640757] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1304.640760] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1304.640762] [drm:drm_mode_debug_printmodeline], Modeline 212:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1304.640767] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1304.640770] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1304.641084] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1304.692230] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1304.693022] [drm:ironlake_update_plane], Writing base 01C8C000 00000000 0 0 2560
><7>[ 1304.744147] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1304.744154] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1304.744158] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1304.744163] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:212:640x480]
><7>[ 1304.744166] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1304.744169] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1304.744173] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1304.744176] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1304.744207] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1304.744210] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1304.796121] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1304.848065] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1304.848226] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1304.848888] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1304.848892] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1304.849549] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1304.849553] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1304.849556] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1304.849558] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1304.849563] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1304.864158] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1304.865075] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1304.865084] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1304.865089] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1304.865097] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1304.865102] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1304.865106] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1304.865110] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1304.865115] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1304.865120] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1309.893970] [drm:drm_mode_addfb], [FB:212]
><7>[ 1309.893993] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1309.893998] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1309.894000] [drm:intel_crtc_set_config], [CRTC:3] [FB:212] #connectors=1 (x y) (0 0)
><7>[ 1309.894003] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1309.894005] [drm:drm_mode_debug_printmodeline], Modeline 212:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1309.894008] [drm:drm_mode_debug_printmodeline], Modeline 213:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1309.894011] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1309.894013] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1309.894015] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1309.894016] [drm:drm_mode_debug_printmodeline], Modeline 213:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1309.894019] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1309.894022] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1309.898571] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1309.925489] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1309.925496] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1309.925909] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1309.925912] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1309.925948] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1309.925950] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1309.925953] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1309.925956] [drm:drm_mode_debug_printmodeline], Modeline 213:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1309.925961] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1309.925963] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1309.926278] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1309.977395] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1309.978161] [drm:ironlake_update_plane], Writing base 01DB8000 00000000 0 0 2560
><7>[ 1310.029368] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1310.029375] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1310.029379] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1310.029384] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:213:640x480]
><7>[ 1310.029387] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1310.029390] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1310.029394] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1310.029398] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1310.029428] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1310.029431] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1310.081314] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1310.133258] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1310.133419] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1310.134081] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1310.134084] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1310.134743] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1310.134747] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1310.134750] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1310.134752] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1310.134757] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1310.150921] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1310.152250] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1310.152260] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1310.152265] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1310.152269] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1310.152274] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1310.152278] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1310.152282] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1310.152284] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1310.152287] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1315.180631] [drm:drm_mode_addfb], [FB:213]
><7>[ 1315.180665] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1315.180671] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1315.180673] [drm:intel_crtc_set_config], [CRTC:3] [FB:213] #connectors=1 (x y) (0 0)
><7>[ 1315.180686] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1315.180688] [drm:drm_mode_debug_printmodeline], Modeline 213:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1315.180691] [drm:drm_mode_debug_printmodeline], Modeline 214:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1315.180694] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1315.180696] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1315.180699] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1315.180702] [drm:drm_mode_debug_printmodeline], Modeline 214:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1315.180708] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1315.180713] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1315.192805] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1315.222641] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1315.222648] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1315.223061] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1315.223064] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1315.223113] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1315.223116] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1315.223119] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1315.223121] [drm:drm_mode_debug_printmodeline], Modeline 214:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1315.223126] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1315.223129] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1315.223443] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1315.274607] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1315.275378] [drm:ironlake_update_plane], Writing base 01EE4000 00000000 0 0 2560
><7>[ 1315.326547] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1315.326555] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1315.326559] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1315.326563] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:214:640x480]
><7>[ 1315.326567] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1315.326570] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1315.326573] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1315.326577] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1315.326607] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1315.326610] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1315.378493] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1315.430438] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1315.430599] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1315.431261] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1315.431265] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1315.431923] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1315.431927] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1315.431930] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1315.431932] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1315.431937] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1315.449856] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1315.451390] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1315.451400] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1315.451405] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1315.451409] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1315.451414] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1315.451418] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1315.451422] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1315.451424] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1315.451427] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1320.477540] [drm:drm_mode_addfb], [FB:214]
><7>[ 1320.477563] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1320.477568] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1320.477570] [drm:intel_crtc_set_config], [CRTC:3] [FB:214] #connectors=1 (x y) (0 0)
><7>[ 1320.477573] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1320.477575] [drm:drm_mode_debug_printmodeline], Modeline 214:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1320.477577] [drm:drm_mode_debug_printmodeline], Modeline 215:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1320.477581] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1320.477583] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1320.477585] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1320.477586] [drm:drm_mode_debug_printmodeline], Modeline 215:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1320.477589] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1320.477592] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1320.494282] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1320.528839] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1320.528845] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1320.529259] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1320.529262] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1320.529311] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1320.529314] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1320.529317] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1320.529319] [drm:drm_mode_debug_printmodeline], Modeline 215:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1320.529324] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1320.529326] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1320.529641] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1320.580776] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1320.581546] [drm:ironlake_update_plane], Writing base 02010000 00000000 0 0 2560
><7>[ 1320.632685] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1320.632693] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1320.632697] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1320.632701] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:215:640x480]
><7>[ 1320.632704] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1320.632708] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1320.632711] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1320.632715] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1320.632745] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1320.632748] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1320.684630] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1320.736576] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1320.736737] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1320.737399] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1320.737403] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1320.738063] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1320.738068] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1320.738070] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1320.738072] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1320.738077] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1320.755997] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1320.757590] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1320.757599] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1320.757604] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1320.757609] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1320.757613] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1320.757617] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1320.757621] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1320.757624] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1320.757626] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1325.779448] [drm:drm_mode_addfb], [FB:215]
><7>[ 1325.779471] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1325.779476] [drm:drm_mode_setcrtc], [CONNECTOR:12:HDMI-A-1]
><7>[ 1325.779478] [drm:intel_crtc_set_config], [CRTC:3] [FB:215] #connectors=1 (x y) (0 0)
><7>[ 1325.779481] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1325.779483] [drm:drm_mode_debug_printmodeline], Modeline 215:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1325.779486] [drm:drm_mode_debug_printmodeline], Modeline 216:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1325.779489] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:3]
><7>[ 1325.779491] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1325.779493] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1325.779494] [drm:drm_mode_debug_printmodeline], Modeline 216:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1325.779497] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1325.779500] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1325.783762] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1325.817028] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1325.817035] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1325.817448] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1325.817451] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1325.817500] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1325.817503] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1325.817506] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1325.817508] [drm:drm_mode_debug_printmodeline], Modeline 216:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1325.817513] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6018
><7>[ 1325.817516] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1325.817830] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1325.868967] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1325.869698] [drm:ironlake_update_plane], Writing base 0213C000 00000000 0 0 2880
><7>[ 1325.920875] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1325.920883] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1325.920887] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1325.920891] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:216:720x400]
><7>[ 1325.920894] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1325.920898] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1325.920901] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1325.920905] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1325.920935] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1325.920938] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1325.972852] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1326.024795] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1326.024956] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1326.025618] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1326.025622] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1326.026280] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1326.026284] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1326.026286] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1326.026289] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 3
><7>[ 1326.026294] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1326.041867] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1326.043782] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1326.043792] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1326.043796] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1326.043801] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1326.043805] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1326.043809] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1326.043813] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1326.043816] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1326.043818] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1331.038423] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
><7>[ 1331.038431] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [NOCRTC]
><7>[ 1331.038434] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1331.038437] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1331.038440] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1331.038443] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
><7>[ 1331.051768] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1331.082244] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 3
><7>[ 1331.082250] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
><7>[ 1331.082663] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1331.082666] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1331.082679] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1331.082684] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1331.082688] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1331.082692] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1331.082696] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1331.082700] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1331.082703] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1331.082705] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1331.082718] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1331.082721] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set
><7>[ 1331.082729] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
><7>[ 1331.082734] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:HDMI-A-2]
><7>[ 1331.154134] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1331.226175] [drm:drm_edid_to_eld], ELD monitor VE228
><4>[ 1331.226181] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
><7>[ 1331.226184] [drm:drm_edid_to_eld], ELD size 7, SAD count 1
><7>[ 1331.226275] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:16:HDMI-A-2] probed modes :
><7>[ 1331.226278] [drm:drm_mode_debug_printmodeline], Modeline 135:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1331.226283] [drm:drm_mode_debug_printmodeline], Modeline 145:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1331.226287] [drm:drm_mode_debug_printmodeline], Modeline 57:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1331.226292] [drm:drm_mode_debug_printmodeline], Modeline 144:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1331.226296] [drm:drm_mode_debug_printmodeline], Modeline 136:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1331.226300] [drm:drm_mode_debug_printmodeline], Modeline 107:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1331.226304] [drm:drm_mode_debug_printmodeline], Modeline 108:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1331.226308] [drm:drm_mode_debug_printmodeline], Modeline 134:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1331.226313] [drm:drm_mode_debug_printmodeline], Modeline 130:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1331.226317] [drm:drm_mode_debug_printmodeline], Modeline 129:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1331.226321] [drm:drm_mode_debug_printmodeline], Modeline 133:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1331.226325] [drm:drm_mode_debug_printmodeline], Modeline 116:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1331.226329] [drm:drm_mode_debug_printmodeline], Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1331.226333] [drm:drm_mode_debug_printmodeline], Modeline 131:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1331.226338] [drm:drm_mode_debug_printmodeline], Modeline 106:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1331.226342] [drm:drm_mode_debug_printmodeline], Modeline 105:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1331.226346] [drm:drm_mode_debug_printmodeline], Modeline 58:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1331.226350] [drm:drm_mode_debug_printmodeline], Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1331.226354] [drm:drm_mode_debug_printmodeline], Modeline 127:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1331.226358] [drm:drm_mode_debug_printmodeline], Modeline 126:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1331.226362] [drm:drm_mode_debug_printmodeline], Modeline 103:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1331.226367] [drm:drm_mode_debug_printmodeline], Modeline 125:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1331.226371] [drm:drm_mode_debug_printmodeline], Modeline 124:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1331.226375] [drm:drm_mode_debug_printmodeline], Modeline 143:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1331.226379] [drm:drm_mode_debug_printmodeline], Modeline 137:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1331.226383] [drm:drm_mode_debug_printmodeline], Modeline 117:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1331.226387] [drm:drm_mode_debug_printmodeline], Modeline 118:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1331.226391] [drm:drm_mode_debug_printmodeline], Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1331.226395] [drm:drm_mode_debug_printmodeline], Modeline 132:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1331.226399] [drm:drm_mode_debug_printmodeline], Modeline 120:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1331.226404] [drm:drm_mode_debug_printmodeline], Modeline 122:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1331.226408] [drm:drm_mode_debug_printmodeline], Modeline 121:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1331.226412] [drm:drm_mode_debug_printmodeline], Modeline 109:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1331.226416] [drm:drm_mode_debug_printmodeline], Modeline 110:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1331.226420] [drm:drm_mode_debug_printmodeline], Modeline 142:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1331.226424] [drm:drm_mode_debug_printmodeline], Modeline 123:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1331.226428] [drm:drm_mode_debug_printmodeline], Modeline 139:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1331.226432] [drm:drm_mode_debug_printmodeline], Modeline 112:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1331.226436] [drm:drm_mode_debug_printmodeline], Modeline 111:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1331.226440] [drm:drm_mode_debug_printmodeline], Modeline 113:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1331.226444] [drm:drm_mode_debug_printmodeline], Modeline 114:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1331.226448] [drm:drm_mode_debug_printmodeline], Modeline 140:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1331.226452] [drm:drm_mode_debug_printmodeline], Modeline 115:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1331.226466] [drm:drm_mode_getconnector], [CONNECTOR:16:?]
><7>[ 1331.285981] [drm:drm_mode_addfb], [FB:215]
><7>[ 1331.286011] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1331.286017] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1331.286020] [drm:intel_crtc_set_config], [CRTC:3] [FB:215] #connectors=1 (x y) (0 0)
><7>[ 1331.286023] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
><7>[ 1331.286025] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1331.286026] [drm:drm_mode_debug_printmodeline], Modeline 216:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1331.286029] [drm:drm_mode_debug_printmodeline], Modeline 216:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1331.286033] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1331.286035] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1331.286036] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1331.286038] [drm:drm_mode_debug_printmodeline], Modeline 216:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1331.286041] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 4
><7>[ 1331.286046] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1331.286052] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1331.286074] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1331.286075] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1331.286077] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1331.286079] [drm:drm_mode_debug_printmodeline], Modeline 216:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1331.286082] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014
><7>[ 1331.286083] [drm:intel_get_pch_pll], using pll 0 for pipe 0
><7>[ 1331.286085] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1331.286398] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1331.337957] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1331.343247] [drm:ironlake_update_plane], Writing base 02256000 00000000 0 0 7680
><7>[ 1331.343255] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1331.343259] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1331.343262] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1331.343266] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
><7>[ 1331.343270] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:216:1920x1080]
><7>[ 1331.343274] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1331.343277] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1331.343281] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1331.343285] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1331.343315] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1331.343318] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1331.343321] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1331.343324] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
><7>[ 1331.394866] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1331.446838] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1331.446999] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1331.447660] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1331.447664] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1331.448322] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1331.448327] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1331.448329] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1331.448332] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1331.448336] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1331.466259] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1331.467824] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1331.467833] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1331.467838] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1331.467842] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1331.467846] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1331.467850] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1331.467854] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1331.467857] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1331.467860] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1336.521086] [drm:drm_mode_addfb], [FB:216]
><7>[ 1336.521114] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1336.521121] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1336.521123] [drm:intel_crtc_set_config], [CRTC:3] [FB:216] #connectors=1 (x y) (0 0)
><7>[ 1336.521126] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1336.521128] [drm:drm_mode_debug_printmodeline], Modeline 216:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1336.521131] [drm:drm_mode_debug_printmodeline], Modeline 217:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1336.521135] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1336.521137] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1336.521138] [drm:drm_mode_debug_printmodeline], Modeline 217:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1336.521141] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1336.521144] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1336.527306] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1336.562225] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1336.562231] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1336.562644] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1336.562647] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1336.562651] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1336.562654] [drm:ironlake_check_srwm], watermark 3: display plane 142, fbc lines 4, cursor 10
><7>[ 1336.562664] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1336.562697] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1336.562700] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1336.562703] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1336.562705] [drm:drm_mode_debug_printmodeline], Modeline 217:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1336.562710] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1336.562713] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1336.563025] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1336.614139] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1336.619136] [drm:ironlake_update_plane], Writing base 02A3F000 00000000 0 0 7680
><7>[ 1336.671059] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1336.671070] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1336.671077] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1336.671083] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1336.671088] [drm:ironlake_check_srwm], watermark 3: display plane 122, fbc lines 4, cursor 6
><7>[ 1336.671096] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:217:1920x1080]
><7>[ 1336.671102] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1336.671108] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1336.671114] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1336.671119] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1336.671152] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1336.671158] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1336.671163] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1336.671167] [drm:ironlake_check_srwm], watermark 3: display plane 122, fbc lines 4, cursor 6
><7>[ 1336.723005] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1336.773955] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1336.774118] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1336.774780] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1336.774784] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1336.775441] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1336.775445] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1336.775448] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1336.775451] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1336.775456] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1336.796659] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1336.797928] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1336.797938] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1336.797943] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1336.797947] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1336.797951] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1336.797956] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1336.797960] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1336.797963] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1336.797965] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1341.169143] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x2f40010, result 1
><7>[ 1341.169150] [drm:intel_crt_detect], CRT detected via hotplug
><7>[ 1341.169154] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 1 to 1
><7>[ 1341.241055] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1341.241062] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-1] status updated from 1 to 1
><7>[ 1341.312965] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1341.312972] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 1 to 1
><7>[ 1341.315541] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.319499] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.323507] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.324961] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1341.324977] [drm:output_poll_execute], [CONNECTOR:18:DP-1] status updated from 2 to 2
><7>[ 1341.327543] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.331503] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.335490] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1341.336939] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1341.336946] [drm:output_poll_execute], [CONNECTOR:20:DP-2] status updated from 2 to 2
><7>[ 1341.856447] [drm:drm_mode_addfb], [FB:217]
><7>[ 1341.856480] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1341.856487] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1341.856490] [drm:intel_crtc_set_config], [CRTC:3] [FB:217] #connectors=1 (x y) (0 0)
><7>[ 1341.856494] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1341.856495] [drm:drm_mode_debug_printmodeline], Modeline 217:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
><7>[ 1341.856498] [drm:drm_mode_debug_printmodeline], Modeline 218:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1341.856502] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1341.856504] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1341.856505] [drm:drm_mode_debug_printmodeline], Modeline 218:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1341.856509] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1341.856512] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1341.871069] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1341.912315] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1341.912321] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1341.912734] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1341.912738] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1341.912742] [drm:ironlake_check_srwm], watermark 2: display plane 67, fbc lines 3, cursor 6
><7>[ 1341.912745] [drm:ironlake_check_srwm], watermark 3: display plane 122, fbc lines 4, cursor 6
><7>[ 1341.912755] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1341.912789] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1341.912791] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1341.912794] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1341.912797] [drm:drm_mode_debug_printmodeline], Modeline 218:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1341.912802] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1341.912805] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1341.913119] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1341.964281] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1341.970469] [drm:ironlake_update_plane], Writing base 03228000 00000000 0 0 7680
><7>[ 1342.022184] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1342.022191] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1342.022195] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1342.022199] [drm:ironlake_check_srwm], watermark 2: display plane 63, fbc lines 3, cursor 6
><7>[ 1342.022202] [drm:ironlake_check_srwm], watermark 3: display plane 132, fbc lines 4, cursor 10
><7>[ 1342.022207] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:218:1920x1080]
><7>[ 1342.022210] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1342.022214] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1342.022217] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1342.022221] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1342.022251] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1342.022254] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1342.022257] [drm:ironlake_check_srwm], watermark 2: display plane 63, fbc lines 3, cursor 6
><7>[ 1342.022260] [drm:ironlake_check_srwm], watermark 3: display plane 132, fbc lines 4, cursor 10
><7>[ 1342.074181] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1342.126083] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1342.126244] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1342.126906] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1342.126910] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1342.127568] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1342.127573] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1342.127575] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1342.127577] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1342.127582] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1342.145551] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1342.147049] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1342.147057] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1342.147061] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1342.147066] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1342.147070] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1342.147074] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1342.147078] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1342.147081] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1342.147084] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1347.199862] [drm:drm_mode_addfb], [FB:218]
><7>[ 1347.199889] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1347.199896] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1347.199898] [drm:intel_crtc_set_config], [CRTC:3] [FB:218] #connectors=1 (x y) (0 0)
><7>[ 1347.199901] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1347.199902] [drm:drm_mode_debug_printmodeline], Modeline 218:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1110 0x40 0x9
><7>[ 1347.199905] [drm:drm_mode_debug_printmodeline], Modeline 219:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1347.199909] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1347.199911] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1347.199912] [drm:drm_mode_debug_printmodeline], Modeline 219:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1347.199915] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1347.199918] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1347.209300] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1347.243486] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1347.243493] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1347.243906] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1347.243909] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1347.243913] [drm:ironlake_check_srwm], watermark 2: display plane 63, fbc lines 3, cursor 6
><7>[ 1347.243916] [drm:ironlake_check_srwm], watermark 3: display plane 132, fbc lines 4, cursor 10
><7>[ 1347.243926] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1347.243959] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1347.243962] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1347.243965] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1347.243967] [drm:drm_mode_debug_printmodeline], Modeline 219:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1347.243972] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1347.243975] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1347.244289] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1347.295425] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1347.301790] [drm:ironlake_update_plane], Writing base 03A11000 00000000 0 0 7680
><7>[ 1347.353351] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1347.353359] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1347.353363] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1347.353367] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1347.353370] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1347.353375] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:219:1920x1080i]
><7>[ 1347.353378] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1347.353382] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1347.353385] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1347.353389] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1347.353419] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1347.353422] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1347.353426] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1347.353429] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1347.405302] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1347.457214] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1347.457375] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1347.458037] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1347.458041] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1347.458706] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1347.458711] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1347.458713] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1347.458716] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1347.458720] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1347.479993] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1347.480232] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1347.480241] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1347.480246] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1347.480250] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1347.480254] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1347.480259] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1347.480263] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1347.480265] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1347.480268] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1352.533386] [drm:drm_mode_addfb], [FB:219]
><7>[ 1352.533413] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1352.533419] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1352.533422] [drm:intel_crtc_set_config], [CRTC:3] [FB:219] #connectors=1 (x y) (0 0)
><7>[ 1352.533424] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1352.533426] [drm:drm_mode_debug_printmodeline], Modeline 219:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
><7>[ 1352.533429] [drm:drm_mode_debug_printmodeline], Modeline 220:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1352.533432] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1352.533434] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1352.533436] [drm:drm_mode_debug_printmodeline], Modeline 220:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1352.533439] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1352.533441] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1352.534382] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1352.574630] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1352.574636] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1352.575049] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1352.575052] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1352.575056] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1352.575059] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1352.575068] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1352.575101] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1352.575103] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1352.575106] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1352.575109] [drm:drm_mode_debug_printmodeline], Modeline 220:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1352.575114] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1352.575117] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1352.575431] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1352.626566] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1352.631846] [drm:ironlake_update_plane], Writing base 041FA000 00000000 0 0 7680
><7>[ 1352.683502] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1352.683509] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1352.683513] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1352.683517] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1352.683520] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1352.683525] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:220:1920x1080i]
><7>[ 1352.683528] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1352.683532] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1352.683535] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1352.683539] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1352.683569] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1352.683572] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1352.683575] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1352.683578] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1352.735446] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1352.787390] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1352.787551] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1352.788213] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1352.788217] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1352.788874] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1352.788879] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1352.788881] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1352.788883] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1352.788888] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1352.806829] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1352.808333] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1352.808341] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1352.808346] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1352.808350] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1352.808355] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1352.808359] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1352.808363] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1352.808366] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1352.808368] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1357.863097] [drm:drm_mode_addfb], [FB:220]
><7>[ 1357.863123] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1357.863130] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1357.863132] [drm:intel_crtc_set_config], [CRTC:3] [FB:220] #connectors=1 (x y) (0 0)
><7>[ 1357.863135] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1357.863136] [drm:drm_mode_debug_printmodeline], Modeline 220:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
><7>[ 1357.863140] [drm:drm_mode_debug_printmodeline], Modeline 221:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1357.863143] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1357.863145] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1357.863147] [drm:drm_mode_debug_printmodeline], Modeline 221:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1357.863150] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1357.863153] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1357.867875] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1357.902774] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1357.902780] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1357.903193] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1357.903196] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1357.903200] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1357.903203] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1357.903213] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1357.903233] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1357.903236] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1357.903239] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1357.903241] [drm:drm_mode_debug_printmodeline], Modeline 221:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1357.903246] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1357.903249] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1357.903563] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1357.954680] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1357.959610] [drm:ironlake_update_plane], Writing base 049E3000 00000000 0 0 6400
><7>[ 1358.010648] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1358.010655] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1358.010659] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
><7>[ 1358.010663] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
><7>[ 1358.010666] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
><7>[ 1358.010671] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:221:1600x1200]
><7>[ 1358.010674] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1358.010678] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1358.010681] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1358.010685] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1358.010715] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1358.010719] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
><7>[ 1358.010722] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
><7>[ 1358.010725] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
><7>[ 1358.062593] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1358.114510] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1358.114671] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1358.115333] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1358.115337] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1358.115994] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1358.115999] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1358.116001] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1358.116004] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1358.116008] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1358.133935] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1358.135492] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1358.135501] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1358.135506] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1358.135510] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1358.135514] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1358.135518] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1358.135521] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1358.135524] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1358.135526] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1363.188618] [drm:drm_mode_addfb], [FB:221]
><7>[ 1363.188643] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1363.188649] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1363.188652] [drm:intel_crtc_set_config], [CRTC:3] [FB:221] #connectors=1 (x y) (0 0)
><7>[ 1363.188654] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1363.188656] [drm:drm_mode_debug_printmodeline], Modeline 221:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
><7>[ 1363.188659] [drm:drm_mode_debug_printmodeline], Modeline 222:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1363.188662] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1363.188664] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1363.188666] [drm:drm_mode_debug_printmodeline], Modeline 222:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1363.188669] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1363.188672] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1363.194975] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1363.229888] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1363.229895] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1363.230308] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
><7>[ 1363.230311] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 6
><7>[ 1363.230315] [drm:ironlake_check_srwm], watermark 2: display plane 73, fbc lines 3, cursor 6
><7>[ 1363.230318] [drm:ironlake_check_srwm], watermark 3: display plane 154, fbc lines 4, cursor 10
><7>[ 1363.230328] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1363.230361] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1363.230364] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1363.230367] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1363.230369] [drm:drm_mode_debug_printmodeline], Modeline 222:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1363.230374] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1363.230377] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1363.230691] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1363.281858] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1363.286351] [drm:ironlake_update_plane], Writing base 05136000 00000000 0 0 6720
><7>[ 1363.337795] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1363.337802] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1363.337806] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1363.337810] [drm:ironlake_check_srwm], watermark 2: display plane 55, fbc lines 3, cursor 6
><7>[ 1363.337813] [drm:ironlake_check_srwm], watermark 3: display plane 114, fbc lines 4, cursor 10
><7>[ 1363.337818] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:222:1680x1050]
><7>[ 1363.337821] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1363.337825] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1363.337828] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1363.337832] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1363.337862] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1363.337866] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1363.337869] [drm:ironlake_check_srwm], watermark 2: display plane 55, fbc lines 3, cursor 6
><7>[ 1363.337872] [drm:ironlake_check_srwm], watermark 3: display plane 114, fbc lines 4, cursor 10
><7>[ 1363.389708] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1363.441683] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1363.441844] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1363.442506] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1363.442510] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1363.443167] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1363.443172] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1363.443174] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1363.443177] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1363.443181] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1363.461193] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1363.462669] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1363.462678] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1363.462683] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1363.462687] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1363.462691] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1363.462695] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1363.462699] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1363.462702] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1363.462705] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1368.514099] [drm:drm_mode_addfb], [FB:222]
><7>[ 1368.514124] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1368.514130] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1368.514132] [drm:intel_crtc_set_config], [CRTC:3] [FB:222] #connectors=1 (x y) (0 0)
><7>[ 1368.514135] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1368.514137] [drm:drm_mode_debug_printmodeline], Modeline 222:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
><7>[ 1368.514140] [drm:drm_mode_debug_printmodeline], Modeline 223:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1368.514144] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1368.514146] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1368.514147] [drm:drm_mode_debug_printmodeline], Modeline 223:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1368.514150] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1368.514153] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1368.520030] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1368.554038] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1368.554044] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1368.554457] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1368.554460] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1368.554464] [drm:ironlake_check_srwm], watermark 2: display plane 55, fbc lines 3, cursor 6
><7>[ 1368.554467] [drm:ironlake_check_srwm], watermark 3: display plane 114, fbc lines 4, cursor 10
><7>[ 1368.554477] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1368.554510] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1368.554512] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1368.554515] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1368.554518] [drm:drm_mode_debug_printmodeline], Modeline 223:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1368.554523] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1368.554525] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1368.554840] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1368.606008] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1368.610153] [drm:ironlake_update_plane], Writing base 057F1000 00000000 0 0 6720
><7>[ 1368.661946] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1368.661953] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1368.661957] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1368.661961] [drm:ironlake_check_srwm], watermark 2: display plane 60, fbc lines 3, cursor 6
><7>[ 1368.661964] [drm:ironlake_check_srwm], watermark 3: display plane 107, fbc lines 4, cursor 6
><7>[ 1368.661969] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:223:1680x945]
><7>[ 1368.661972] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1368.661976] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1368.661979] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1368.661983] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1368.662013] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1368.662016] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1368.662019] [drm:ironlake_check_srwm], watermark 2: display plane 60, fbc lines 3, cursor 6
><7>[ 1368.662022] [drm:ironlake_check_srwm], watermark 3: display plane 107, fbc lines 4, cursor 6
><7>[ 1368.713858] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1368.765833] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1368.765994] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1368.766656] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1368.766660] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1368.767318] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1368.767322] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1368.767325] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1368.767327] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1368.767332] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1368.785183] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1368.786819] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1368.786828] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1368.786833] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1368.786837] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1368.786841] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1368.786845] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1368.786849] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1368.786852] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1368.786854] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1373.837205] [drm:drm_mode_addfb], [FB:223]
><7>[ 1373.837231] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1373.837237] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1373.837239] [drm:intel_crtc_set_config], [CRTC:3] [FB:223] #connectors=1 (x y) (0 0)
><7>[ 1373.837242] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1373.837243] [drm:drm_mode_debug_printmodeline], Modeline 223:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
><7>[ 1373.837246] [drm:drm_mode_debug_printmodeline], Modeline 224:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1373.837250] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1373.837252] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1373.837253] [drm:drm_mode_debug_printmodeline], Modeline 224:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1373.837256] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1373.837259] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1373.841469] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1373.875224] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1373.875230] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1373.875643] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1373.875647] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1373.875650] [drm:ironlake_check_srwm], watermark 2: display plane 60, fbc lines 3, cursor 6
><7>[ 1373.875654] [drm:ironlake_check_srwm], watermark 3: display plane 107, fbc lines 4, cursor 6
><7>[ 1373.875663] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1373.875696] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1373.875699] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1373.875702] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1373.875704] [drm:drm_mode_debug_printmodeline], Modeline 224:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1373.875709] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1373.875712] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1373.876027] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1373.927133] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1373.931762] [drm:ironlake_update_plane], Writing base 05E00000 00000000 0 0 5632
><7>[ 1373.983098] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1373.983105] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1373.983110] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1373.983113] [drm:ironlake_check_srwm], watermark 2: display plane 71, fbc lines 3, cursor 6
><7>[ 1373.983117] [drm:ironlake_check_srwm], watermark 3: display plane 149, fbc lines 4, cursor 10
><7>[ 1373.983121] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:224:1400x1050]
><7>[ 1373.983125] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1373.983128] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1373.983132] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1373.983135] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1373.983166] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1373.983169] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1373.983172] [drm:ironlake_check_srwm], watermark 2: display plane 71, fbc lines 3, cursor 6
><7>[ 1373.983175] [drm:ironlake_check_srwm], watermark 3: display plane 149, fbc lines 4, cursor 10
><7>[ 1374.035044] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1374.086953] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1374.087114] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1374.087776] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1374.087780] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1374.088440] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1374.088444] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1374.088447] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1374.088449] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1374.088454] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1374.103054] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1374.103984] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1374.103993] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1374.103998] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1374.104003] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1374.104007] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1374.104011] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1374.104015] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1374.104017] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1374.104020] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1379.153584] [drm:drm_mode_addfb], [FB:224]
><7>[ 1379.153608] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1379.153614] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1379.153616] [drm:intel_crtc_set_config], [CRTC:3] [FB:224] #connectors=1 (x y) (0 0)
><7>[ 1379.153619] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1379.153620] [drm:drm_mode_debug_printmodeline], Modeline 224:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
><7>[ 1379.153623] [drm:drm_mode_debug_printmodeline], Modeline 225:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1379.153627] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1379.153629] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1379.153630] [drm:drm_mode_debug_printmodeline], Modeline 225:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1379.153633] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1379.153636] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1379.159815] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1379.187387] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1379.187394] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1379.187806] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1379.187810] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1379.187813] [drm:ironlake_check_srwm], watermark 2: display plane 71, fbc lines 3, cursor 6
><7>[ 1379.187816] [drm:ironlake_check_srwm], watermark 3: display plane 149, fbc lines 4, cursor 10
><7>[ 1379.187826] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1379.187859] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1379.187862] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1379.187864] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1379.187867] [drm:drm_mode_debug_printmodeline], Modeline 225:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1379.187872] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1379.187875] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1379.188189] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1379.239325] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1379.243124] [drm:ironlake_update_plane], Writing base 063A4000 00000000 0 0 5632
><7>[ 1379.294262] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1379.294270] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1379.294274] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1379.294278] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1379.294281] [drm:ironlake_check_srwm], watermark 3: display plane 97, fbc lines 4, cursor 10
><7>[ 1379.294285] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:225:1400x1050]
><7>[ 1379.294289] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1379.294293] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1379.294296] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1379.294300] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1379.294330] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1379.294333] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1379.294336] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1379.294340] [drm:ironlake_check_srwm], watermark 3: display plane 97, fbc lines 4, cursor 10
><7>[ 1379.346208] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1379.398150] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1379.398311] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1379.398973] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1379.398977] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1379.399634] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1379.399639] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1379.399641] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1379.399643] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1379.399648] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1379.417557] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1379.419137] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1379.419146] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1379.419151] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1379.419155] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1379.419159] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1379.419163] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1379.419167] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1379.419170] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1379.419173] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1384.468126] [drm:drm_mode_addfb], [FB:225]
><7>[ 1384.468150] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1384.468156] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1384.468158] [drm:intel_crtc_set_config], [CRTC:3] [FB:225] #connectors=1 (x y) (0 0)
><7>[ 1384.468161] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1384.468163] [drm:drm_mode_debug_printmodeline], Modeline 225:"1400x1050" 60 101000 1400 1448 1480 1560 1050 1053 1057 1080 0x40 0x9
><7>[ 1384.468166] [drm:drm_mode_debug_printmodeline], Modeline 226:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1384.468169] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1384.468171] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1384.468172] [drm:drm_mode_debug_printmodeline], Modeline 226:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1384.468175] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1384.468178] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1384.483074] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1384.517530] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1384.517537] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1384.517949] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1384.517953] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1384.517956] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1384.517960] [drm:ironlake_check_srwm], watermark 3: display plane 97, fbc lines 4, cursor 10
><7>[ 1384.517969] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1384.518002] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1384.518005] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1384.518008] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1384.518010] [drm:drm_mode_debug_printmodeline], Modeline 226:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1384.518015] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1384.518018] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1384.518332] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1384.569468] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1384.573201] [drm:ironlake_update_plane], Writing base 06948000 00000000 0 0 6400
><7>[ 1384.624407] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1384.624415] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1384.624419] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1384.624422] [drm:ironlake_check_srwm], watermark 2: display plane 54, fbc lines 3, cursor 6
><7>[ 1384.624426] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 6
><7>[ 1384.624430] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:226:1600x900]
><7>[ 1384.624434] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1384.624437] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1384.624441] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1384.624444] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1384.624475] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1384.624478] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1384.624481] [drm:ironlake_check_srwm], watermark 2: display plane 54, fbc lines 3, cursor 6
><7>[ 1384.624484] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 6
><7>[ 1384.676319] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1384.728294] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1384.728455] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1384.729116] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1384.729120] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1384.729778] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1384.729783] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1384.729785] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1384.729787] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1384.729792] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1384.747788] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1384.749280] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1384.749288] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1384.749293] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1384.749298] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1384.749302] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1384.749306] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1384.749310] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1384.749313] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1384.749315] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1389.798862] [drm:drm_mode_addfb], [FB:226]
><7>[ 1389.798886] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1389.798892] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1389.798894] [drm:intel_crtc_set_config], [CRTC:3] [FB:226] #connectors=1 (x y) (0 0)
><7>[ 1389.798897] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1389.798899] [drm:drm_mode_debug_printmodeline], Modeline 226:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
><7>[ 1389.798902] [drm:drm_mode_debug_printmodeline], Modeline 227:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1389.798905] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1389.798907] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1389.798909] [drm:drm_mode_debug_printmodeline], Modeline 227:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1389.798912] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1389.798915] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1389.813399] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1389.848674] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1389.848680] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1389.849092] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1389.849096] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 6
><7>[ 1389.849099] [drm:ironlake_check_srwm], watermark 2: display plane 54, fbc lines 3, cursor 6
><7>[ 1389.849103] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 6
><7>[ 1389.849113] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1389.849146] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1389.849148] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1389.849151] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1389.849153] [drm:drm_mode_debug_printmodeline], Modeline 227:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1389.849158] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1389.849161] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1389.849476] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1389.900578] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1389.903994] [drm:ironlake_update_plane], Writing base 06EC7000 00000000 0 0 5120
><7>[ 1389.955548] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1389.955555] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1389.955559] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1389.955563] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1389.955566] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
><7>[ 1389.955571] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:227:1280x1024]
><7>[ 1389.955574] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1389.955578] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1389.955581] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1389.955585] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1389.955616] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1389.955619] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1389.955622] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1389.955625] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
><7>[ 1390.007493] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1390.059404] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1390.059565] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1390.060226] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1390.060229] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1390.060891] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1390.060896] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1390.060898] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1390.060900] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1390.060905] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1390.075500] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1390.076426] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1390.076436] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1390.076440] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1390.076446] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1390.076451] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1390.076456] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1390.076460] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1390.076463] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1390.076465] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1395.125096] [drm:drm_mode_addfb], [FB:227]
><7>[ 1395.125120] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1395.125126] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1395.125128] [drm:intel_crtc_set_config], [CRTC:3] [FB:227] #connectors=1 (x y) (0 0)
><7>[ 1395.125131] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1395.125133] [drm:drm_mode_debug_printmodeline], Modeline 227:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1395.125136] [drm:drm_mode_debug_printmodeline], Modeline 228:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1395.125139] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1395.125141] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1395.125143] [drm:drm_mode_debug_printmodeline], Modeline 228:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1395.125146] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1395.125149] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1395.134882] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1395.162834] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1395.162840] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1395.163253] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1395.163256] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1395.163260] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1395.163263] [drm:ironlake_check_srwm], watermark 3: display plane 129, fbc lines 4, cursor 10
><7>[ 1395.163273] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1395.163292] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1395.163295] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1395.163298] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1395.163300] [drm:drm_mode_debug_printmodeline], Modeline 228:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1395.163305] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1395.163308] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1395.163622] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1395.214743] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1395.218930] [drm:ironlake_update_plane], Writing base 073C7000 00000000 0 0 5120
><7>[ 1395.270708] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1395.270715] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1395.270719] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1395.270723] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1395.270726] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1395.270731] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:228:1280x1024]
><7>[ 1395.270734] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1395.270738] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1395.270741] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1395.270745] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1395.270775] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1395.270778] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1395.270781] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1395.270785] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1395.322653] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1395.374564] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1395.374725] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1395.375385] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1395.375390] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1395.376054] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1395.376058] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1395.376060] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1395.376063] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1395.376068] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1395.393988] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1395.395582] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1395.395590] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1395.395595] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1395.395600] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1395.395604] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1395.395608] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1395.395612] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1395.395615] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1395.395617] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1400.450821] [drm:drm_mode_addfb], [FB:228]
><7>[ 1400.450862] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1400.450870] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1400.450872] [drm:intel_crtc_set_config], [CRTC:3] [FB:228] #connectors=1 (x y) (0 0)
><7>[ 1400.450876] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1400.450878] [drm:drm_mode_debug_printmodeline], Modeline 228:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
><7>[ 1400.450881] [drm:drm_mode_debug_printmodeline], Modeline 229:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1400.450885] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1400.450887] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1400.450889] [drm:drm_mode_debug_printmodeline], Modeline 229:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1400.450892] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1400.450896] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1400.453344] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1400.487950] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1400.487957] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1400.488370] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1400.488374] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1400.488378] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1400.488381] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1400.488391] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1400.488425] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1400.488428] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1400.488431] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1400.488433] [drm:drm_mode_debug_printmodeline], Modeline 229:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1400.488438] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1400.488441] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1400.488756] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1400.539921] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1400.542453] [drm:ironlake_update_plane], Writing base 078C7000 00000000 0 0 5760
><7>[ 1400.593845] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1400.593851] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1400.593855] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1400.593858] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1400.593861] [drm:ironlake_check_srwm], watermark 3: display plane 131, fbc lines 4, cursor 10
><7>[ 1400.593865] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:229:1440x900]
><7>[ 1400.593868] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1400.593871] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1400.593874] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1400.593877] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1400.593907] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1400.593910] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1400.593912] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1400.593915] [drm:ironlake_check_srwm], watermark 3: display plane 131, fbc lines 4, cursor 10
><7>[ 1400.645776] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1400.697714] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1400.697876] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1400.698538] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1400.698542] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1400.699200] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1400.699205] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1400.699207] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1400.699209] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1400.699214] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1400.713841] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1400.714747] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1400.714756] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1400.714773] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1400.714776] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1400.714778] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1400.714782] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1400.714785] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1400.714787] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1400.714788] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1405.762943] [drm:drm_mode_addfb], [FB:229]
><7>[ 1405.762973] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1405.762980] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1405.762982] [drm:intel_crtc_set_config], [CRTC:3] [FB:229] #connectors=1 (x y) (0 0)
><7>[ 1405.762986] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1405.762987] [drm:drm_mode_debug_printmodeline], Modeline 229:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
><7>[ 1405.762991] [drm:drm_mode_debug_printmodeline], Modeline 230:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1405.762994] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1405.762996] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1405.762998] [drm:drm_mode_debug_printmodeline], Modeline 230:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1405.763001] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1405.763004] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1405.771886] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1405.800147] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1405.800153] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1405.800566] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1405.800570] [drm:ironlake_check_srwm], watermark 1: display plane 11, fbc lines 3, cursor 6
><7>[ 1405.800573] [drm:ironlake_check_srwm], watermark 2: display plane 62, fbc lines 3, cursor 6
><7>[ 1405.800577] [drm:ironlake_check_srwm], watermark 3: display plane 131, fbc lines 4, cursor 10
><7>[ 1405.800587] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1405.800621] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1405.800623] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1405.800626] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1405.800629] [drm:drm_mode_debug_printmodeline], Modeline 230:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1405.800634] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1405.800637] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1405.800951] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1405.852052] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1405.855329] [drm:ironlake_update_plane], Writing base 07DB9000 00000000 0 0 5760
><7>[ 1405.906992] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1405.907000] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1405.907004] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1405.907008] [drm:ironlake_check_srwm], watermark 2: display plane 41, fbc lines 3, cursor 6
><7>[ 1405.907011] [drm:ironlake_check_srwm], watermark 3: display plane 86, fbc lines 3, cursor 6
><7>[ 1405.907016] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:230:1440x900]
><7>[ 1405.907019] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1405.907023] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1405.907027] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1405.907030] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1405.907060] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1405.907064] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1405.907067] [drm:ironlake_check_srwm], watermark 2: display plane 41, fbc lines 3, cursor 6
><7>[ 1405.907070] [drm:ironlake_check_srwm], watermark 3: display plane 86, fbc lines 3, cursor 6
><7>[ 1405.958967] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1406.010910] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1406.011071] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1406.011733] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1406.011737] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1406.012395] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1406.012399] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1406.012402] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1406.012404] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1406.012409] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1406.030319] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1406.031854] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1406.031861] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1406.031866] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1406.031871] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1406.031875] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1406.031879] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1406.031883] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1406.031886] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1406.031888] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1411.083076] [drm:drm_mode_addfb], [FB:230]
><7>[ 1411.083101] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1411.083106] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1411.083109] [drm:intel_crtc_set_config], [CRTC:3] [FB:230] #connectors=1 (x y) (0 0)
><7>[ 1411.083111] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1411.083113] [drm:drm_mode_debug_printmodeline], Modeline 230:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
><7>[ 1411.083116] [drm:drm_mode_debug_printmodeline], Modeline 231:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1411.083120] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1411.083122] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1411.083123] [drm:drm_mode_debug_printmodeline], Modeline 231:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1411.083126] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1411.083129] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1411.085475] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1411.120300] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1411.120306] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1411.120719] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1411.120722] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1411.120726] [drm:ironlake_check_srwm], watermark 2: display plane 41, fbc lines 3, cursor 6
><7>[ 1411.120729] [drm:ironlake_check_srwm], watermark 3: display plane 86, fbc lines 3, cursor 6
><7>[ 1411.120739] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1411.120759] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1411.120761] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1411.120764] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1411.120767] [drm:drm_mode_debug_printmodeline], Modeline 231:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1411.120772] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1411.120774] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1411.121089] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1411.172238] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1411.175319] [drm:ironlake_update_plane], Writing base 082AB000 00000000 0 0 5120
><7>[ 1411.227144] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1411.227151] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1411.227156] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1411.227159] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1411.227163] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1411.227167] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:231:1280x960]
><7>[ 1411.227170] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1411.227174] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1411.227177] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1411.227181] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1411.227210] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1411.227213] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1411.227217] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1411.227220] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1411.279121] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1411.331063] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1411.331224] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1411.331886] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1411.331890] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1411.332548] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1411.332553] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1411.332555] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1411.332557] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1411.332562] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1411.350488] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1411.352008] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1411.352017] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1411.352022] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1411.352026] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1411.352031] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1411.352035] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1411.352039] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1411.352041] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1411.352044] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1416.399920] [drm:drm_mode_addfb], [FB:231]
><7>[ 1416.399944] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1416.399950] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1416.399952] [drm:intel_crtc_set_config], [CRTC:3] [FB:231] #connectors=1 (x y) (0 0)
><7>[ 1416.399955] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1416.399956] [drm:drm_mode_debug_printmodeline], Modeline 231:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
><7>[ 1416.399960] [drm:drm_mode_debug_printmodeline], Modeline 232:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1416.399963] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1416.399965] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1416.399967] [drm:drm_mode_debug_printmodeline], Modeline 232:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1416.399970] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1416.399973] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1416.411536] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1416.445468] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1416.445475] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1416.445887] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1416.445891] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1416.445894] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1416.445898] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1416.445907] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1416.445940] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1416.445942] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1416.445945] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1416.445948] [drm:drm_mode_debug_printmodeline], Modeline 232:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1416.445953] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1416.445956] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1416.446270] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1416.497387] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1416.500043] [drm:ironlake_update_plane], Writing base 0875B000 00000000 0 0 5504
><7>[ 1416.551313] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1416.551321] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1416.551325] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1416.551328] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1416.551332] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1416.551336] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:232:1366x768]
><7>[ 1416.551340] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1416.551343] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1416.551346] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1416.551350] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1416.551380] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1416.551384] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1416.551387] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1416.551390] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1416.603271] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1416.655213] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1416.655374] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1416.656035] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1416.656039] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1416.656697] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1416.656701] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1416.656704] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1416.656706] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1416.656711] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1416.674694] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1416.676158] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1416.676167] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1416.676172] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1416.676176] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1416.676180] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1416.676184] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1416.676188] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1416.676191] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1416.676193] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1421.723889] [drm:drm_mode_addfb], [FB:232]
><7>[ 1421.723914] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1421.723920] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1421.723922] [drm:intel_crtc_set_config], [CRTC:3] [FB:232] #connectors=1 (x y) (0 0)
><7>[ 1421.723924] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1421.723926] [drm:drm_mode_debug_printmodeline], Modeline 232:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
><7>[ 1421.723929] [drm:drm_mode_debug_printmodeline], Modeline 233:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1421.723932] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1421.723935] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1421.723936] [drm:drm_mode_debug_printmodeline], Modeline 233:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1421.723939] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1421.723942] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1421.736875] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1421.771598] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1421.771605] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1421.772017] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1421.772021] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1421.772024] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1421.772028] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1421.772037] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1421.772070] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1421.772072] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1421.772075] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1421.772078] [drm:drm_mode_debug_printmodeline], Modeline 233:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1421.772083] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1421.772086] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1421.772400] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1421.823535] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1421.826192] [drm:ironlake_update_plane], Writing base 08B63000 00000000 0 0 5440
><7>[ 1421.877474] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1421.877481] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1421.877485] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1421.877489] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1421.877492] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1421.877497] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:233:1360x768]
><7>[ 1421.877500] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1421.877504] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1421.877507] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1421.877511] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1421.877541] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1421.877544] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1421.877547] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1421.877550] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1421.929418] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1421.981362] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1421.981522] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1421.982184] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1421.982188] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1421.982846] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1421.982850] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1421.982853] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1421.982855] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1421.982860] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1422.000782] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1422.002305] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1422.002314] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1422.002318] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1422.002323] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1422.002327] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1422.002331] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1422.002335] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1422.002338] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1422.002340] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1427.053146] [drm:drm_mode_addfb], [FB:233]
><7>[ 1427.053176] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1427.053183] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1427.053185] [drm:intel_crtc_set_config], [CRTC:3] [FB:233] #connectors=1 (x y) (0 0)
><7>[ 1427.053189] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1427.053191] [drm:drm_mode_debug_printmodeline], Modeline 233:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
><7>[ 1427.053194] [drm:drm_mode_debug_printmodeline], Modeline 234:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1427.053197] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1427.053199] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1427.053201] [drm:drm_mode_debug_printmodeline], Modeline 234:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1427.053204] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1427.053207] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1427.060574] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1427.094748] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1427.094755] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1427.095168] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1427.095172] [drm:ironlake_check_srwm], watermark 1: display plane 8, fbc lines 3, cursor 6
><7>[ 1427.095175] [drm:ironlake_check_srwm], watermark 2: display plane 40, fbc lines 3, cursor 6
><7>[ 1427.095178] [drm:ironlake_check_srwm], watermark 3: display plane 83, fbc lines 3, cursor 6
><7>[ 1427.095188] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1427.095208] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1427.095211] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1427.095214] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1427.095217] [drm:drm_mode_debug_printmodeline], Modeline 234:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1427.095222] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1427.095225] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1427.095539] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1427.146686] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1427.149382] [drm:ironlake_update_plane], Writing base 08F5F000 00000000 0 0 5120
><7>[ 1427.200625] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1427.200632] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1427.200637] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1427.200640] [drm:ironlake_check_srwm], watermark 2: display plane 49, fbc lines 3, cursor 6
><7>[ 1427.200644] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 10
><7>[ 1427.200648] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:234:1280x800]
><7>[ 1427.200652] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1427.200655] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1427.200659] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1427.200663] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1427.200693] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1427.200696] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1427.200699] [drm:ironlake_check_srwm], watermark 2: display plane 49, fbc lines 3, cursor 6
><7>[ 1427.200702] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 10
><7>[ 1427.252571] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1427.304513] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1427.304674] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1427.305336] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1427.305340] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1427.305997] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1427.306002] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1427.306004] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1427.306007] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1427.306011] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1427.320600] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1427.321505] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1427.321513] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1427.321520] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1427.321525] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1427.321529] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1427.321536] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1427.321540] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1427.321543] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1427.321546] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1432.370213] [drm:drm_mode_addfb], [FB:234]
><7>[ 1432.370242] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1432.370248] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1432.370250] [drm:intel_crtc_set_config], [CRTC:3] [FB:234] #connectors=1 (x y) (0 0)
><7>[ 1432.370254] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1432.370256] [drm:drm_mode_debug_printmodeline], Modeline 234:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
><7>[ 1432.370259] [drm:drm_mode_debug_printmodeline], Modeline 235:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1432.370262] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1432.370264] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1432.370266] [drm:drm_mode_debug_printmodeline], Modeline 235:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1432.370269] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1432.370272] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1432.378203] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1432.405913] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1432.405919] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1432.406332] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1432.406336] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1432.406339] [drm:ironlake_check_srwm], watermark 2: display plane 49, fbc lines 3, cursor 6
><7>[ 1432.406343] [drm:ironlake_check_srwm], watermark 3: display plane 102, fbc lines 4, cursor 10
><7>[ 1432.406352] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1432.406387] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1432.406389] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1432.406392] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1432.406395] [drm:drm_mode_debug_printmodeline], Modeline 235:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1432.406400] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1432.406402] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1432.406716] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1432.457851] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1432.460514] [drm:ironlake_update_plane], Writing base 09347000 00000000 0 0 5120
><7>[ 1432.511789] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1432.511796] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1432.511801] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1432.511804] [drm:ironlake_check_srwm], watermark 2: display plane 34, fbc lines 3, cursor 6
><7>[ 1432.511808] [drm:ironlake_check_srwm], watermark 3: display plane 69, fbc lines 3, cursor 6
><7>[ 1432.511812] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:235:1280x800]
><7>[ 1432.511815] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1432.511819] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1432.511823] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1432.511826] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1432.511856] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1432.511860] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1432.511863] [drm:ironlake_check_srwm], watermark 2: display plane 34, fbc lines 3, cursor 6
><7>[ 1432.511866] [drm:ironlake_check_srwm], watermark 3: display plane 69, fbc lines 3, cursor 6
><7>[ 1432.563706] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1432.615677] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1432.615838] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1432.616500] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1432.616504] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1432.617162] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1432.617166] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1432.617169] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1432.617171] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1432.617175] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1432.635069] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1432.636622] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1432.636631] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1432.636635] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1432.636640] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1432.636644] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1432.636648] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1432.636652] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1432.636655] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1432.636657] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1437.684501] [drm:drm_mode_addfb], [FB:235]
><7>[ 1437.684526] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1437.684532] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1437.684534] [drm:intel_crtc_set_config], [CRTC:3] [FB:235] #connectors=1 (x y) (0 0)
><7>[ 1437.684537] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1437.684539] [drm:drm_mode_debug_printmodeline], Modeline 235:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
><7>[ 1437.684542] [drm:drm_mode_debug_printmodeline], Modeline 236:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1437.684545] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1437.684547] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1437.684549] [drm:drm_mode_debug_printmodeline], Modeline 236:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1437.684552] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1437.684555] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1437.685986] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1437.720074] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1437.720080] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1437.720493] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1437.720497] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1437.720500] [drm:ironlake_check_srwm], watermark 2: display plane 34, fbc lines 3, cursor 6
><7>[ 1437.720503] [drm:ironlake_check_srwm], watermark 3: display plane 69, fbc lines 3, cursor 6
><7>[ 1437.720513] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1437.720533] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1437.720535] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1437.720538] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1437.720541] [drm:drm_mode_debug_printmodeline], Modeline 236:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1437.720546] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1437.720549] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1437.720863] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1437.772011] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1437.774659] [drm:ironlake_update_plane], Writing base 0972F000 00000000 0 0 4608
><7>[ 1437.825949] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1437.825957] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1437.825961] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1437.825965] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1437.825968] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1437.825973] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:236:1152x864]
><7>[ 1437.825976] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1437.825980] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1437.825983] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1437.825987] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1437.826017] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1437.826020] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1437.826024] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1437.826027] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1437.877863] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1437.929841] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1437.930002] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1437.930663] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1437.930667] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1437.931325] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1437.931330] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1437.931332] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1437.931335] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1437.931339] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1437.945936] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1437.946836] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1437.946845] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1437.946850] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1437.946855] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1437.946859] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1437.946863] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1437.946867] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1437.946870] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1437.946872] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1442.996102] [drm:drm_mode_addfb], [FB:236]
><7>[ 1442.996128] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1442.996133] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1442.996136] [drm:intel_crtc_set_config], [CRTC:3] [FB:236] #connectors=1 (x y) (0 0)
><7>[ 1442.996139] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1442.996140] [drm:drm_mode_debug_printmodeline], Modeline 236:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
><7>[ 1442.996143] [drm:drm_mode_debug_printmodeline], Modeline 237:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1442.996147] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1442.996149] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1442.996150] [drm:drm_mode_debug_printmodeline], Modeline 237:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1442.996153] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1442.996156] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1443.007007] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1443.035234] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1443.035240] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1443.035652] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
><7>[ 1443.035656] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1443.035659] [drm:ironlake_check_srwm], watermark 2: display plane 50, fbc lines 3, cursor 6
><7>[ 1443.035663] [drm:ironlake_check_srwm], watermark 3: display plane 104, fbc lines 4, cursor 10
><7>[ 1443.035673] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1443.035706] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1443.035708] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1443.035711] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1443.035713] [drm:drm_mode_debug_printmodeline], Modeline 237:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1443.035718] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1443.035721] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1443.036036] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1443.087172] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1443.089791] [drm:ironlake_update_plane], Writing base 09AFB000 00000000 0 0 5120
><7>[ 1443.141079] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1443.141086] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1443.141090] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1443.141094] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1443.141097] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1443.141101] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:237:1280x768]
><7>[ 1443.141105] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1443.141108] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1443.141112] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1443.141116] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1443.141146] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1443.141149] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1443.141152] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1443.141155] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1443.193055] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1443.244998] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1443.245159] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1443.245821] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1443.245825] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1443.246483] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1443.246487] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1443.246490] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1443.246492] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1443.246496] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1443.261146] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1443.261960] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1443.261969] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1443.261974] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1443.261978] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1443.261983] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1443.261987] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1443.261991] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1443.261993] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1443.262000] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1448.311216] [drm:drm_mode_addfb], [FB:237]
><7>[ 1448.311240] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1448.311246] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1448.311248] [drm:intel_crtc_set_config], [CRTC:3] [FB:237] #connectors=1 (x y) (0 0)
><7>[ 1448.311251] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1448.311253] [drm:drm_mode_debug_printmodeline], Modeline 237:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
><7>[ 1448.311256] [drm:drm_mode_debug_printmodeline], Modeline 238:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1448.311259] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1448.311261] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1448.311262] [drm:drm_mode_debug_printmodeline], Modeline 238:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1448.311265] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1448.311268] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1448.315126] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1448.342402] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1448.342409] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1448.342821] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
><7>[ 1448.342825] [drm:ironlake_check_srwm], watermark 1: display plane 9, fbc lines 3, cursor 6
><7>[ 1448.342828] [drm:ironlake_check_srwm], watermark 2: display plane 47, fbc lines 3, cursor 6
><7>[ 1448.342832] [drm:ironlake_check_srwm], watermark 3: display plane 82, fbc lines 4, cursor 6
><7>[ 1448.342841] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1448.342861] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1448.342864] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1448.342867] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1448.342869] [drm:drm_mode_debug_printmodeline], Modeline 238:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1448.342874] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1448.342877] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1448.343190] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1448.394340] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1448.396922] [drm:ironlake_update_plane], Writing base 09EBB000 00000000 0 0 5120
><7>[ 1448.448278] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1448.448285] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1448.448289] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1448.448293] [drm:ironlake_check_srwm], watermark 2: display plane 32, fbc lines 3, cursor 6
><7>[ 1448.448297] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 3, cursor 6
><7>[ 1448.448301] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:238:1280x768]
><7>[ 1448.448304] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1448.448308] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1448.448311] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1448.448315] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1448.448345] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1448.448348] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1448.448352] [drm:ironlake_check_srwm], watermark 2: display plane 32, fbc lines 3, cursor 6
><7>[ 1448.448355] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 3, cursor 6
><7>[ 1448.500225] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1448.552166] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1448.552327] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1448.552989] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1448.552993] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1448.553651] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1448.553655] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1448.553658] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1448.553660] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1448.553665] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1448.571648] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1448.573152] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1448.573161] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1448.573166] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1448.573170] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1448.573174] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1448.573178] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1448.573182] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1448.573185] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1448.573187] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1453.619071] [drm:drm_mode_addfb], [FB:238]
><7>[ 1453.619095] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1453.619101] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1453.619103] [drm:intel_crtc_set_config], [CRTC:3] [FB:238] #connectors=1 (x y) (0 0)
><7>[ 1453.619106] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1453.619108] [drm:drm_mode_debug_printmodeline], Modeline 238:"1280x768" 60 68250 1280 1328 1360 1440 768 771 778 790 0x40 0x9
><7>[ 1453.619111] [drm:drm_mode_debug_printmodeline], Modeline 239:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1453.619114] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1453.619116] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1453.619117] [drm:drm_mode_debug_printmodeline], Modeline 239:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1453.619120] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1453.619123] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1453.635051] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1453.668551] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1453.668557] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1453.668969] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1453.668973] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1453.668976] [drm:ironlake_check_srwm], watermark 2: display plane 32, fbc lines 3, cursor 6
><7>[ 1453.668980] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 3, cursor 6
><7>[ 1453.668989] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1453.669022] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1453.669024] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1453.669027] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1453.669030] [drm:drm_mode_debug_printmodeline], Modeline 239:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1453.669035] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1453.669037] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1453.669352] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1453.720455] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1453.722927] [drm:ironlake_update_plane], Writing base 0A27B000 00000000 0 0 5120
><7>[ 1453.774426] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1453.774433] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1453.774437] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1453.774441] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1453.774444] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1453.774449] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:239:1280x720]
><7>[ 1453.774452] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1453.774456] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1453.774459] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1453.774463] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1453.774493] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1453.774496] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1453.774499] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1453.774502] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1453.826372] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1453.878315] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1453.878476] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1453.879138] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1453.879142] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1453.879799] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1453.879803] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1453.879805] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1453.879808] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1453.879812] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1453.901063] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1453.901319] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1453.901328] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1453.901333] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1453.901337] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1453.901341] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1453.901346] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1453.901350] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1453.901352] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1453.901355] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1458.954072] [drm:drm_mode_addfb], [FB:239]
><7>[ 1458.954104] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1458.954112] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1458.954114] [drm:intel_crtc_set_config], [CRTC:3] [FB:239] #connectors=1 (x y) (0 0)
><7>[ 1458.954118] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1458.954120] [drm:drm_mode_debug_printmodeline], Modeline 239:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
><7>[ 1458.954123] [drm:drm_mode_debug_printmodeline], Modeline 240:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1458.954127] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1458.954129] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1458.954131] [drm:drm_mode_debug_printmodeline], Modeline 240:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1458.954134] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1458.954138] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1458.955435] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1458.995685] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1458.995692] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1458.996105] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1458.996109] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1458.996113] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1458.996116] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1458.996126] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1458.996160] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1458.996163] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1458.996166] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1458.996169] [drm:drm_mode_debug_printmodeline], Modeline 240:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1458.996174] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1458.996177] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1458.996492] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1459.047594] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1459.049410] [drm:ironlake_update_plane], Writing base 0A5FF000 00000000 0 0 5120
><7>[ 1459.100541] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1459.100553] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1459.100560] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1459.100565] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1459.100571] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1459.100578] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:240:1280x720]
><7>[ 1459.100582] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1459.100586] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1459.100590] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1459.100594] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1459.100624] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1459.100627] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1459.100630] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1459.100634] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1459.152479] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1459.204435] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1459.204597] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1459.205259] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1459.205263] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1459.205923] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1459.205928] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1459.205930] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1459.205933] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1459.205937] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1459.223822] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1459.225434] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1459.225443] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1459.225448] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1459.225453] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1459.225457] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1459.225461] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1459.225465] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1459.225468] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1459.225471] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1464.272672] [drm:drm_mode_addfb], [FB:240]
><7>[ 1464.272701] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1464.272707] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1464.272709] [drm:intel_crtc_set_config], [CRTC:3] [FB:240] #connectors=1 (x y) (0 0)
><7>[ 1464.272713] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1464.272715] [drm:drm_mode_debug_printmodeline], Modeline 240:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
><7>[ 1464.272718] [drm:drm_mode_debug_printmodeline], Modeline 241:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1464.272721] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1464.272723] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1464.272725] [drm:drm_mode_debug_printmodeline], Modeline 241:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1464.272728] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1464.272731] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1464.284937] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1464.319846] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1464.319853] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1464.320266] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1464.320269] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1464.320273] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1464.320276] [drm:ironlake_check_srwm], watermark 3: display plane 72, fbc lines 3, cursor 6
><7>[ 1464.320286] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1464.320307] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1464.320309] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1464.320312] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1464.320315] [drm:drm_mode_debug_printmodeline], Modeline 241:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1464.320320] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1464.320323] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1464.320637] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1464.371785] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1464.373882] [drm:ironlake_update_plane], Writing base 0A983000 00000000 0 0 4096
><7>[ 1464.425724] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1464.425731] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1464.425735] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1464.425739] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
><7>[ 1464.425742] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1464.425747] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:241:1024x768]
><7>[ 1464.425750] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1464.425754] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1464.425757] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1464.425761] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1464.425791] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1464.425794] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1464.425798] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
><7>[ 1464.425801] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1464.477636] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1464.529615] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1464.529776] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1464.530439] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1464.530443] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1464.531101] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1464.531105] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1464.531108] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1464.531110] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1464.531115] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1464.545667] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1464.546602] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1464.546611] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1464.546616] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1464.546620] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1464.546624] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1464.546629] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1464.546633] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1464.546636] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1464.546638] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1469.591237] [drm:drm_mode_addfb], [FB:241]
><7>[ 1469.591262] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1469.591268] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1469.591270] [drm:intel_crtc_set_config], [CRTC:3] [FB:241] #connectors=1 (x y) (0 0)
><7>[ 1469.591273] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1469.591275] [drm:drm_mode_debug_printmodeline], Modeline 241:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
><7>[ 1469.591278] [drm:drm_mode_debug_printmodeline], Modeline 242:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1469.591282] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1469.591284] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1469.591285] [drm:drm_mode_debug_printmodeline], Modeline 242:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1469.591288] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1469.591291] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1469.602027] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1469.629014] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1469.629020] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1469.629433] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1469.629436] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1469.629440] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
><7>[ 1469.629443] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1469.629453] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1469.629486] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1469.629489] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1469.629492] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1469.629494] [drm:drm_mode_debug_printmodeline], Modeline 242:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1469.629499] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1469.629502] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1469.629817] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1469.680952] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1469.683045] [drm:ironlake_update_plane], Writing base 0AC83000 00000000 0 0 4096
><7>[ 1469.734890] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1469.734897] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1469.734901] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1469.734905] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1469.734908] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1469.734913] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:242:1024x768]
><7>[ 1469.734916] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1469.734920] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1469.734923] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1469.734927] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1469.734957] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1469.734960] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1469.734963] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1469.734966] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1469.786834] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1469.838777] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1469.838938] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1469.839600] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1469.839604] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1469.840261] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1469.840266] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1469.840268] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1469.840271] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1469.840275] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1469.855755] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1469.855777] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1469.855785] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1469.855789] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1469.855794] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1469.855798] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1469.855802] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1469.855806] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1469.855809] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1469.855812] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1474.902620] [drm:drm_mode_addfb], [FB:242]
><7>[ 1474.902644] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1474.902650] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1474.902652] [drm:intel_crtc_set_config], [CRTC:3] [FB:242] #connectors=1 (x y) (0 0)
><7>[ 1474.902655] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1474.902656] [drm:drm_mode_debug_printmodeline], Modeline 242:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
><7>[ 1474.902659] [drm:drm_mode_debug_printmodeline], Modeline 243:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1474.902663] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1474.902665] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1474.902666] [drm:drm_mode_debug_printmodeline], Modeline 243:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1474.902669] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1474.902672] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1474.916608] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1474.946142] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1474.946148] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1474.946561] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1474.946565] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1474.946568] [drm:ironlake_check_srwm], watermark 2: display plane 35, fbc lines 3, cursor 6
><7>[ 1474.946572] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
><7>[ 1474.946581] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1474.946601] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1474.946604] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1474.946607] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1474.946609] [drm:drm_mode_debug_printmodeline], Modeline 243:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1474.946614] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1474.946617] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1474.946931] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1474.998109] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1475.000621] [drm:ironlake_update_plane], Writing base 0AF83000 00000000 0 0 4096
><7>[ 1475.052047] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1475.052054] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1475.052058] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1475.052062] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
><7>[ 1475.052065] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
><7>[ 1475.052069] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:243:1024x768]
><7>[ 1475.052073] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1475.052076] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1475.052079] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1475.052083] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1475.052113] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1475.052116] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1475.052119] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
><7>[ 1475.052122] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
><7>[ 1475.103993] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1475.155903] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1475.156064] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1475.156726] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1475.156730] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1475.157389] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1475.157394] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1475.157396] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1475.157398] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1475.157403] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1475.175364] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1475.176888] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1475.176897] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1475.176902] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1475.176906] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1475.176910] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1475.176915] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1475.176919] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1475.176921] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1475.176924] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1480.220125] [drm:drm_mode_addfb], [FB:243]
><7>[ 1480.220148] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1480.220154] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1480.220156] [drm:intel_crtc_set_config], [CRTC:3] [FB:243] #connectors=1 (x y) (0 0)
><7>[ 1480.220159] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1480.220160] [drm:drm_mode_debug_printmodeline], Modeline 243:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
><7>[ 1480.220163] [drm:drm_mode_debug_printmodeline], Modeline 244:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1480.220166] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1480.220168] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1480.220170] [drm:drm_mode_debug_printmodeline], Modeline 244:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1480.220173] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1480.220176] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1480.235048] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1480.269322] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1480.269328] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1480.269741] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
><7>[ 1480.269744] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
><7>[ 1480.269748] [drm:ironlake_check_srwm], watermark 2: display plane 31, fbc lines 3, cursor 6
><7>[ 1480.269751] [drm:ironlake_check_srwm], watermark 3: display plane 63, fbc lines 3, cursor 6
><7>[ 1480.269760] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1480.269780] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1480.269782] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1480.269785] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1480.269788] [drm:drm_mode_debug_printmodeline], Modeline 244:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1480.269793] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1480.269795] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1480.270110] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1480.321227] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1480.323005] [drm:ironlake_update_plane], Writing base 0B283000 00000000 0 0 4096
><7>[ 1480.374200] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1480.374207] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1480.374211] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1480.374215] [drm:ironlake_check_srwm], watermark 2: display plane 23, fbc lines 3, cursor 6
><7>[ 1480.374218] [drm:ironlake_check_srwm], watermark 3: display plane 46, fbc lines 3, cursor 6
><7>[ 1480.374222] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:244:1024x576]
><7>[ 1480.374226] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1480.374229] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1480.374232] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1480.374236] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1480.374266] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1480.374269] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1480.374273] [drm:ironlake_check_srwm], watermark 2: display plane 23, fbc lines 3, cursor 6
><7>[ 1480.374276] [drm:ironlake_check_srwm], watermark 3: display plane 46, fbc lines 3, cursor 6
><7>[ 1480.426144] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1480.478087] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1480.478249] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1480.478910] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1480.478915] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1480.479572] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1480.479576] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1480.479579] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1480.479581] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1480.479586] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1480.497558] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1480.499047] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1480.499055] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1480.499060] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1480.499064] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1480.499069] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1480.499073] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1480.499077] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1480.499080] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1480.499082] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1485.541906] [drm:drm_mode_addfb], [FB:244]
><7>[ 1485.541930] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1485.541936] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1485.541938] [drm:intel_crtc_set_config], [CRTC:3] [FB:244] #connectors=1 (x y) (0 0)
><7>[ 1485.541941] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1485.541942] [drm:drm_mode_debug_printmodeline], Modeline 244:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
><7>[ 1485.541945] [drm:drm_mode_debug_printmodeline], Modeline 245:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1485.541949] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1485.541951] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1485.541952] [drm:drm_mode_debug_printmodeline], Modeline 245:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1485.541955] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1485.541958] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1485.556889] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1485.591474] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1485.591480] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1485.591893] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
><7>[ 1485.591896] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1485.591900] [drm:ironlake_check_srwm], watermark 2: display plane 23, fbc lines 3, cursor 6
><7>[ 1485.591903] [drm:ironlake_check_srwm], watermark 3: display plane 46, fbc lines 3, cursor 6
><7>[ 1485.591913] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1485.591933] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1485.591935] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1485.591938] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1485.591941] [drm:drm_mode_debug_printmodeline], Modeline 245:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1485.591946] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1485.591949] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1485.592263] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1485.643412] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1485.644731] [drm:ironlake_update_plane], Writing base 0B4C3000 00000000 0 0 3328
><7>[ 1485.696352] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1485.696359] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1485.696363] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1485.696367] [drm:ironlake_check_srwm], watermark 2: display plane 28, fbc lines 3, cursor 6
><7>[ 1485.696370] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 4, cursor 6
><7>[ 1485.696375] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:245:832x624]
><7>[ 1485.696378] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1485.696382] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1485.696385] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1485.696389] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1485.696419] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1485.696422] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1485.696425] [drm:ironlake_check_srwm], watermark 2: display plane 28, fbc lines 3, cursor 6
><7>[ 1485.696429] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 4, cursor 6
><7>[ 1485.748296] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1485.800240] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1485.800401] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1485.801062] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1485.801066] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1485.801724] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1485.801729] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1485.801731] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1485.801733] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1485.801738] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1485.816401] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1485.817230] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1485.817239] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1485.817244] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1485.817251] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1485.817255] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1485.817259] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1485.817264] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1485.817270] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1485.817273] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1490.858432] [drm:drm_mode_addfb], [FB:245]
><7>[ 1490.858455] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1490.858461] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1490.858463] [drm:intel_crtc_set_config], [CRTC:3] [FB:245] #connectors=1 (x y) (0 0)
><7>[ 1490.858466] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1490.858467] [drm:drm_mode_debug_printmodeline], Modeline 245:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
><7>[ 1490.858470] [drm:drm_mode_debug_printmodeline], Modeline 246:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1490.858474] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1490.858476] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1490.858477] [drm:drm_mode_debug_printmodeline], Modeline 246:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1490.858480] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1490.858483] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1490.863358] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1490.891650] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1490.891656] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1490.892070] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 29, cursor: 6
><7>[ 1490.892073] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1490.892077] [drm:ironlake_check_srwm], watermark 2: display plane 28, fbc lines 3, cursor 6
><7>[ 1490.892080] [drm:ironlake_check_srwm], watermark 3: display plane 54, fbc lines 4, cursor 6
><7>[ 1490.892089] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1490.892109] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1490.892112] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1490.892115] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1490.892117] [drm:drm_mode_debug_printmodeline], Modeline 246:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1490.892122] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1490.892125] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1490.892439] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1490.943589] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1490.944821] [drm:ironlake_update_plane], Writing base 0B6BE000 00000000 0 0 3200
><7>[ 1490.996528] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1490.996535] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1490.996540] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1490.996543] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1490.996547] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1490.996551] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:246:800x600]
><7>[ 1490.996554] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1490.996558] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1490.996561] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1490.996565] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1490.996595] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1490.996598] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1490.996601] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1490.996605] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1491.048444] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1491.100417] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1491.100578] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1491.101240] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1491.101244] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1491.101902] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1491.101907] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1491.101909] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1491.101911] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1491.101916] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1491.117113] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1491.117428] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1491.117437] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1491.117442] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1491.117447] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1491.117451] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1491.117455] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1491.117459] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1491.117461] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1491.117464] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1496.156366] [drm:drm_mode_addfb], [FB:246]
><7>[ 1496.156390] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1496.156396] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1496.156398] [drm:intel_crtc_set_config], [CRTC:3] [FB:246] #connectors=1 (x y) (0 0)
><7>[ 1496.156400] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1496.156402] [drm:drm_mode_debug_printmodeline], Modeline 246:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
><7>[ 1496.156405] [drm:drm_mode_debug_printmodeline], Modeline 247:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1496.156408] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1496.156410] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1496.156412] [drm:drm_mode_debug_printmodeline], Modeline 247:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1496.156414] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1496.156417] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1496.168993] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1496.197821] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1496.197827] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1496.198240] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1496.198243] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1496.198247] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1496.198250] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1496.198259] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1496.198279] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1496.198282] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1496.198285] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1496.198287] [drm:drm_mode_debug_printmodeline], Modeline 247:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1496.198292] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1496.198295] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1496.198609] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1496.249759] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1496.251029] [drm:ironlake_update_plane], Writing base 0B893000 00000000 0 0 3200
><7>[ 1496.302667] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1496.302674] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1496.302678] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1496.302682] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1496.302685] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1496.302689] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:247:800x600]
><7>[ 1496.302692] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1496.302696] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1496.302699] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1496.302703] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1496.302733] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1496.302736] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1496.302739] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1496.302743] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1496.354643] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1496.406585] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1496.406746] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1496.407408] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1496.407412] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1496.408070] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1496.408074] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1496.408077] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1496.408079] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1496.408084] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1496.422621] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1496.423547] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1496.423556] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1496.423561] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1496.423566] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1496.423570] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1496.423574] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1496.423578] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1496.423581] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1496.423588] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1501.466008] [drm:drm_mode_addfb], [FB:247]
><7>[ 1501.466039] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1501.466047] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1501.466050] [drm:intel_crtc_set_config], [CRTC:3] [FB:247] #connectors=1 (x y) (0 0)
><7>[ 1501.466055] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1501.466058] [drm:drm_mode_debug_printmodeline], Modeline 247:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
><7>[ 1501.466063] [drm:drm_mode_debug_printmodeline], Modeline 248:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1501.466068] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1501.466071] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1501.466074] [drm:drm_mode_debug_printmodeline], Modeline 248:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1501.466078] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1501.466083] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1501.475123] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1501.501997] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1501.502003] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1501.502416] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1501.502420] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
><7>[ 1501.502423] [drm:ironlake_check_srwm], watermark 2: display plane 24, fbc lines 3, cursor 6
><7>[ 1501.502426] [drm:ironlake_check_srwm], watermark 3: display plane 49, fbc lines 3, cursor 6
><7>[ 1501.502436] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1501.502456] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1501.502458] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1501.502461] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1501.502463] [drm:drm_mode_debug_printmodeline], Modeline 248:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1501.502469] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1501.502471] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1501.502784] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1501.553931] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1501.555192] [drm:ironlake_update_plane], Writing base 0BA68000 00000000 0 0 3200
><7>[ 1501.606838] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1501.606846] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1501.606850] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1501.606854] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
><7>[ 1501.606857] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
><7>[ 1501.606861] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:248:800x600]
><7>[ 1501.606865] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1501.606868] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1501.606871] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1501.606875] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1501.606905] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1501.606909] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1501.606912] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
><7>[ 1501.606915] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
><7>[ 1501.658815] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1501.710757] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1501.710919] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1501.711581] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1501.711585] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1501.712242] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1501.712247] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1501.712249] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1501.712252] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1501.712256] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1501.730090] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1501.731701] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1501.731709] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1501.731714] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1501.731718] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1501.731723] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1501.731727] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1501.731731] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1501.731734] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1501.731736] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1506.772683] [drm:drm_mode_addfb], [FB:248]
><7>[ 1506.772707] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1506.772712] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1506.772714] [drm:intel_crtc_set_config], [CRTC:3] [FB:248] #connectors=1 (x y) (0 0)
><7>[ 1506.772717] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1506.772718] [drm:drm_mode_debug_printmodeline], Modeline 248:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
><7>[ 1506.772721] [drm:drm_mode_debug_printmodeline], Modeline 249:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1506.772725] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1506.772727] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1506.772728] [drm:drm_mode_debug_printmodeline], Modeline 249:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1506.772731] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1506.772734] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1506.781141] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1506.816154] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1506.816160] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1506.816573] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1506.816577] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1506.816580] [drm:ironlake_check_srwm], watermark 2: display plane 20, fbc lines 3, cursor 6
><7>[ 1506.816583] [drm:ironlake_check_srwm], watermark 3: display plane 40, fbc lines 3, cursor 6
><7>[ 1506.816593] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1506.816625] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1506.816628] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1506.816631] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1506.816633] [drm:drm_mode_debug_printmodeline], Modeline 249:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1506.816638] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1506.816641] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1506.816954] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1506.868091] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1506.869355] [drm:ironlake_update_plane], Writing base 0BC3D000 00000000 0 0 3200
><7>[ 1506.921000] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1506.921007] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1506.921011] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1506.921015] [drm:ironlake_check_srwm], watermark 2: display plane 18, fbc lines 3, cursor 6
><7>[ 1506.921018] [drm:ironlake_check_srwm], watermark 3: display plane 36, fbc lines 3, cursor 6
><7>[ 1506.921023] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:249:800x600]
><7>[ 1506.921026] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1506.921030] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1506.921033] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1506.921037] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1506.921066] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1506.921069] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1506.921073] [drm:ironlake_check_srwm], watermark 2: display plane 18, fbc lines 3, cursor 6
><7>[ 1506.921076] [drm:ironlake_check_srwm], watermark 3: display plane 36, fbc lines 3, cursor 6
><7>[ 1506.972976] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1507.024919] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1507.025080] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1507.025742] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1507.025747] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1507.026405] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1507.026409] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1507.026412] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1507.026414] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1507.026419] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1507.045450] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1507.045914] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1507.045925] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1507.045931] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1507.045935] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1507.045939] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1507.045944] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1507.045948] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1507.045950] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1507.045953] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1512.080412] [drm:drm_mode_addfb], [FB:249]
><7>[ 1512.080436] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1512.080441] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1512.080443] [drm:intel_crtc_set_config], [CRTC:3] [FB:249] #connectors=1 (x y) (0 0)
><7>[ 1512.080446] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1512.080447] [drm:drm_mode_debug_printmodeline], Modeline 249:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
><7>[ 1512.080450] [drm:drm_mode_debug_printmodeline], Modeline 250:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1512.080454] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1512.080456] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1512.080457] [drm:drm_mode_debug_printmodeline], Modeline 250:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1512.080460] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1512.080463] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1512.088763] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1512.124321] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1512.124328] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1512.124740] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 32, cursor: 6
><7>[ 1512.124743] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1512.124747] [drm:ironlake_check_srwm], watermark 2: display plane 18, fbc lines 3, cursor 6
><7>[ 1512.124750] [drm:ironlake_check_srwm], watermark 3: display plane 36, fbc lines 3, cursor 6
><7>[ 1512.124759] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1512.124806] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1512.124808] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1512.124811] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1512.124814] [drm:drm_mode_debug_printmodeline], Modeline 250:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1512.124818] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1512.124821] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1512.125136] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1512.176230] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1512.177303] [drm:ironlake_update_plane], Writing base 0BE12000 00000000 0 0 2880
><7>[ 1512.229198] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1512.229205] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1512.229210] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1512.229213] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1512.229217] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1512.229221] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:250:720x576]
><7>[ 1512.229224] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1512.229228] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1512.229231] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1512.229235] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1512.229265] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1512.229268] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1512.229271] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1512.229274] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1512.281144] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1512.333087] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1512.333248] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1512.333910] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1512.333914] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1512.334572] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1512.334576] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1512.334578] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1512.334581] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1512.334585] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1512.355837] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1512.356071] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1512.356080] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1512.356084] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1512.356089] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1512.356093] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1512.356097] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1512.356101] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1512.356104] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1512.356106] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1517.395977] [drm:drm_mode_addfb], [FB:250]
><7>[ 1517.396009] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1517.396017] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1517.396020] [drm:intel_crtc_set_config], [CRTC:3] [FB:250] #connectors=1 (x y) (0 0)
><7>[ 1517.396024] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1517.396026] [drm:drm_mode_debug_printmodeline], Modeline 250:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
><7>[ 1517.396029] [drm:drm_mode_debug_printmodeline], Modeline 251:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1517.396033] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1517.396035] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1517.396037] [drm:drm_mode_debug_printmodeline], Modeline 251:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1517.396040] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1517.396044] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1517.410193] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1517.451461] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1517.451468] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1517.451879] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1517.451883] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1517.451886] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1517.451890] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1517.451900] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1517.451935] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1517.451938] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1517.451941] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1517.451944] [drm:drm_mode_debug_printmodeline], Modeline 251:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1517.451949] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1517.451952] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1517.452267] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1517.503384] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1517.504200] [drm:ironlake_update_plane], Writing base 0BFA7000 00000000 0 0 3392
><7>[ 1517.555309] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1517.555321] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1517.555328] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1517.555334] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
><7>[ 1517.555341] [drm:ironlake_check_srwm], watermark 3: display plane 34, fbc lines 3, cursor 6
><7>[ 1517.555348] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:251:848x480]
><7>[ 1517.555354] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1517.555361] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1517.555367] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1517.555373] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1517.555405] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1517.555411] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1517.555416] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
><7>[ 1517.555422] [drm:ironlake_check_srwm], watermark 3: display plane 34, fbc lines 3, cursor 6
><7>[ 1517.607251] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1517.659192] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1517.659354] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1517.660016] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1517.660020] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1517.660687] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1517.660692] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1517.660694] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1517.660697] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1517.660702] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1517.678583] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1517.680181] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1517.680190] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1517.680195] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1517.680199] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1517.680204] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1517.680208] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1517.680212] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1517.680215] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1517.680217] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1522.711568] [drm:drm_mode_addfb], [FB:251]
><7>[ 1522.711596] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1522.711603] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1522.711606] [drm:intel_crtc_set_config], [CRTC:3] [FB:251] #connectors=1 (x y) (0 0)
><7>[ 1522.711609] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1522.711611] [drm:drm_mode_debug_printmodeline], Modeline 251:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
><7>[ 1522.711614] [drm:drm_mode_debug_printmodeline], Modeline 252:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1522.711617] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1522.711619] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1522.711621] [drm:drm_mode_debug_printmodeline], Modeline 252:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1522.711659] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1522.711663] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1522.723013] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1522.757638] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1522.757645] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1522.758058] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 26, cursor: 6
><7>[ 1522.758062] [drm:ironlake_check_srwm], watermark 1: display plane 5, fbc lines 3, cursor 6
><7>[ 1522.758065] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
><7>[ 1522.758069] [drm:ironlake_check_srwm], watermark 3: display plane 34, fbc lines 3, cursor 6
><7>[ 1522.758078] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1522.758125] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1522.758128] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1522.758131] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1522.758133] [drm:drm_mode_debug_printmodeline], Modeline 252:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1522.758138] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1522.758141] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1522.758456] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1522.809575] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1522.810455] [drm:ironlake_update_plane], Writing base 0C135000 00000000 0 0 2880
><7>[ 1522.861515] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1522.861523] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1522.861527] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1522.861531] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1522.861534] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1522.861539] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:252:720x480]
><7>[ 1522.861542] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1522.861546] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1522.861549] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1522.861553] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1522.861583] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1522.861587] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1522.861590] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1522.861593] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1522.913429] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1522.965404] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1522.965565] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1522.966227] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1522.966231] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1522.966889] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1522.966894] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1522.966896] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1522.966899] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1522.966903] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1522.984841] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1522.986389] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1522.986398] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1522.986403] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1522.986407] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1522.986411] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1522.986415] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1522.986419] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1522.986422] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1522.986424] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1528.015521] [drm:drm_mode_addfb], [FB:252]
><7>[ 1528.015544] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1528.015550] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1528.015552] [drm:intel_crtc_set_config], [CRTC:3] [FB:252] #connectors=1 (x y) (0 0)
><7>[ 1528.015555] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1528.015556] [drm:drm_mode_debug_printmodeline], Modeline 252:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
><7>[ 1528.015560] [drm:drm_mode_debug_printmodeline], Modeline 253:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1528.015563] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1528.015565] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1528.015566] [drm:drm_mode_debug_printmodeline], Modeline 253:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1528.015569] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1528.015572] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1528.017643] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1528.052819] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1528.052826] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1528.053238] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 41, cursor: 6
><7>[ 1528.053242] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1528.053245] [drm:ironlake_check_srwm], watermark 2: display plane 14, fbc lines 3, cursor 6
><7>[ 1528.053249] [drm:ironlake_check_srwm], watermark 3: display plane 28, fbc lines 3, cursor 6
><7>[ 1528.053258] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1528.053291] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1528.053293] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1528.053296] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1528.053299] [drm:drm_mode_debug_printmodeline], Modeline 253:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1528.053304] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1528.053306] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1528.053621] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1528.104757] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1528.105521] [drm:ironlake_update_plane], Writing base 0C287000 00000000 0 0 2560
><7>[ 1528.156698] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1528.156705] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1528.156710] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1528.156713] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1528.156717] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1528.156721] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:253:640x480]
><7>[ 1528.156724] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1528.156728] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1528.156731] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1528.156735] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1528.156764] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1528.156767] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1528.156770] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1528.156773] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1528.208611] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1528.260587] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1528.260748] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1528.261410] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1528.261414] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1528.262072] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1528.262077] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1528.262079] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1528.262081] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1528.262086] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1528.277079] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1528.277568] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1528.277578] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1528.277583] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1528.277587] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1528.277591] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1528.277595] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1528.277600] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1528.277602] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1528.277609] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1533.303499] [drm:drm_mode_addfb], [FB:253]
><7>[ 1533.303522] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1533.303528] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1533.303530] [drm:intel_crtc_set_config], [CRTC:3] [FB:253] #connectors=1 (x y) (0 0)
><7>[ 1533.303532] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1533.303534] [drm:drm_mode_debug_printmodeline], Modeline 253:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
><7>[ 1533.303537] [drm:drm_mode_debug_printmodeline], Modeline 254:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1533.303540] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1533.303542] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1533.303544] [drm:drm_mode_debug_printmodeline], Modeline 254:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1533.303546] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1533.303549] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1533.312093] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1533.341009] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1533.341015] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1533.341428] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1533.341432] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1533.341435] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1533.341438] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1533.341448] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1533.341481] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1533.341484] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1533.341487] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1533.341489] [drm:drm_mode_debug_printmodeline], Modeline 254:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1533.341494] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1533.341496] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1533.341811] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1533.392914] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1533.393802] [drm:ironlake_update_plane], Writing base 0C3B3000 00000000 0 0 2560
><7>[ 1533.444887] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1533.444894] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1533.444899] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1533.444902] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1533.444906] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1533.444910] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:254:640x480]
><7>[ 1533.444913] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1533.444917] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1533.444920] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1533.444924] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1533.444954] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1533.444957] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1533.444960] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1533.444963] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1533.496832] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1533.548776] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1533.548937] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1533.549599] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1533.549603] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1533.550261] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1533.550266] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1533.550269] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1533.550271] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1533.550276] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1533.564868] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1533.565765] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1533.565774] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1533.565779] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1533.565783] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1533.565788] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1533.565792] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1533.565796] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1533.565799] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1533.565801] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1538.593991] [drm:drm_mode_addfb], [FB:254]
><7>[ 1538.594014] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1538.594019] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1538.594021] [drm:intel_crtc_set_config], [CRTC:3] [FB:254] #connectors=1 (x y) (0 0)
><7>[ 1538.594024] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1538.594025] [drm:drm_mode_debug_printmodeline], Modeline 254:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
><7>[ 1538.594028] [drm:drm_mode_debug_printmodeline], Modeline 255:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1538.594031] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1538.594033] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1538.594035] [drm:drm_mode_debug_printmodeline], Modeline 255:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1538.594038] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1538.594041] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1538.599270] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1538.627168] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1538.627174] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1538.627588] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1538.627591] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1538.627595] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1538.627598] [drm:ironlake_check_srwm], watermark 3: display plane 32, fbc lines 3, cursor 6
><7>[ 1538.627607] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1538.627641] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1538.627643] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1538.627646] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1538.627648] [drm:drm_mode_debug_printmodeline], Modeline 255:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1538.627653] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1538.627656] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1538.627971] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1538.679138] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1538.679922] [drm:ironlake_update_plane], Writing base 0C4DF000 00000000 0 0 2560
><7>[ 1538.731079] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1538.731086] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1538.731090] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1538.731094] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1538.731097] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
><7>[ 1538.731102] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:255:640x480]
><7>[ 1538.731105] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1538.731109] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1538.731112] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1538.731116] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1538.731145] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1538.731149] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1538.731152] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1538.731155] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
><7>[ 1538.783024] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1538.834968] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1538.835128] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1538.835790] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1538.835794] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1538.836452] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1538.836456] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1538.836459] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1538.836461] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1538.836465] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1538.852654] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1538.853954] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1538.853963] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1538.853968] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1538.853972] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1538.853977] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1538.853981] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1538.853985] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1538.853987] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1538.853990] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1543.880933] [drm:drm_mode_addfb], [FB:255]
><7>[ 1543.880957] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1543.880963] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1543.880965] [drm:intel_crtc_set_config], [CRTC:3] [FB:255] #connectors=1 (x y) (0 0)
><7>[ 1543.880967] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1543.880969] [drm:drm_mode_debug_printmodeline], Modeline 255:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
><7>[ 1543.880972] [drm:drm_mode_debug_printmodeline], Modeline 256:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1543.880975] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1543.880977] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1543.880978] [drm:drm_mode_debug_printmodeline], Modeline 256:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1543.880981] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1543.880985] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1543.894527] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1543.924380] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1543.924387] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1543.924800] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 52, cursor: 6
><7>[ 1543.924803] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1543.924807] [drm:ironlake_check_srwm], watermark 2: display plane 16, fbc lines 3, cursor 6
><7>[ 1543.924810] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
><7>[ 1543.924820] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1543.924866] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1543.924869] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1543.924872] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1543.924874] [drm:drm_mode_debug_printmodeline], Modeline 256:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1543.924879] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1543.924882] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1543.925195] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1543.976289] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1543.977056] [drm:ironlake_update_plane], Writing base 0C60B000 00000000 0 0 2560
><7>[ 1544.027259] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1544.027266] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1544.027270] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1544.027274] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1544.027277] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1544.027282] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:256:640x480]
><7>[ 1544.027285] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1544.027289] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1544.027292] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1544.027296] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1544.027326] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1544.027329] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1544.027332] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1544.027335] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1544.079205] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1544.131119] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1544.131280] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1544.131942] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1544.131946] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1544.132605] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1544.132609] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1544.132612] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1544.132614] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1544.132619] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1544.150540] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1544.152134] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1544.152143] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1544.152148] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1544.152152] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1544.152156] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1544.152160] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1544.152164] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1544.152167] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1544.152169] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1549.181401] [drm:drm_mode_addfb], [FB:256]
><7>[ 1549.181424] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1549.181430] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1549.181432] [drm:intel_crtc_set_config], [CRTC:3] [FB:256] #connectors=1 (x y) (0 0)
><7>[ 1549.181435] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1549.181436] [drm:drm_mode_debug_printmodeline], Modeline 256:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1549.181439] [drm:drm_mode_debug_printmodeline], Modeline 257:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1549.181443] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1549.181445] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1549.181446] [drm:drm_mode_debug_printmodeline], Modeline 257:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1549.181449] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1549.181452] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1549.194964] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1549.228552] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1549.228558] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1549.228971] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1549.228975] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1549.228978] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1549.228981] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1549.228991] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1549.229037] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1549.229040] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1549.229043] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1549.229045] [drm:drm_mode_debug_printmodeline], Modeline 257:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1549.229050] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1549.229053] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1549.229367] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1549.280489] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1549.281264] [drm:ironlake_update_plane], Writing base 0C737000 00000000 0 0 2560
><7>[ 1549.332430] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1549.332437] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1549.332442] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1549.332445] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1549.332449] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1549.332453] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:257:640x480]
><7>[ 1549.332456] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1549.332460] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1549.332463] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1549.332467] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1549.332497] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1549.332500] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1549.332503] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1549.332507] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1549.384343] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1549.436319] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1549.436480] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1549.437140] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1549.437145] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1549.437802] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1549.437807] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1549.437809] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1549.437811] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1549.437816] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1549.455735] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1549.457305] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1549.457313] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1549.457318] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1549.457322] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1549.457327] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1549.457331] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1549.457335] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1549.457338] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1549.457340] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1554.479066] [drm:drm_mode_addfb], [FB:257]
><7>[ 1554.479089] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1554.479095] [drm:drm_mode_setcrtc], [CONNECTOR:16:HDMI-A-2]
><7>[ 1554.479097] [drm:intel_crtc_set_config], [CRTC:3] [FB:257] #connectors=1 (x y) (0 0)
><7>[ 1554.479099] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1554.479101] [drm:drm_mode_debug_printmodeline], Modeline 257:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
><7>[ 1554.479104] [drm:drm_mode_debug_printmodeline], Modeline 258:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1554.479107] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:3]
><7>[ 1554.479109] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1554.479111] [drm:drm_mode_debug_printmodeline], Modeline 258:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1554.479113] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1554.479116] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1554.483511] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1554.518710] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1554.518717] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1554.519128] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 51, cursor: 6
><7>[ 1554.519132] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1554.519135] [drm:ironlake_check_srwm], watermark 2: display plane 13, fbc lines 3, cursor 6
><7>[ 1554.519139] [drm:ironlake_check_srwm], watermark 3: display plane 26, fbc lines 3, cursor 6
><7>[ 1554.519148] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1554.519195] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1554.519198] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1554.519201] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1554.519203] [drm:drm_mode_debug_printmodeline], Modeline 258:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1554.519208] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
><7>[ 1554.519210] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1554.519524] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
><7>[ 1554.570678] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1554.571560] [drm:ironlake_update_plane], Writing base 0C863000 00000000 0 0 2880
><7>[ 1554.622618] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1554.622625] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1554.622629] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1554.622633] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
><7>[ 1554.622636] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
><7>[ 1554.622640] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:258:720x400]
><7>[ 1554.622644] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe A
><7>[ 1554.622647] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1554.622650] [drm:ironlake_write_eld], ELD on pipe A
><7>[ 1554.622654] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1554.622683] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1554.622686] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1554.622690] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
><7>[ 1554.622693] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
><7>[ 1554.674563] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1554.726506] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1554.726667] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1554.727329] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1554.727333] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1554.727991] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1554.727996] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1554.727998] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1554.728000] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1554.728005] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1554.743579] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1554.745495] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1554.745503] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1554.745508] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1554.745512] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1554.745516] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1554.745521] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1554.745525] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1554.745527] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1554.745530] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1559.740145] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
><7>[ 1559.740153] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [NOCRTC]
><7>[ 1559.740157] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1559.740160] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1559.740163] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
><7>[ 1559.753483] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1559.783925] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
><7>[ 1559.783931] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
><7>[ 1559.784344] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 42, cursor: 6
><7>[ 1559.784348] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 6
><7>[ 1559.784351] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
><7>[ 1559.784355] [drm:ironlake_check_srwm], watermark 3: display plane 29, fbc lines 3, cursor 6
><7>[ 1559.784366] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1559.784374] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1559.784379] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1559.784383] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1559.784387] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1559.784391] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1559.784395] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1559.784398] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1559.784400] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1559.784414] [drm:drm_mode_setcrtc], [CRTC:3]
><7>[ 1559.784417] [drm:drm_mode_setcrtc], Count connectors is 1 but no mode or fb set
><7>[ 1559.784427] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
><7>[ 1559.784432] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:DP-1]
><7>[ 1559.786993] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.791462] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.795457] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.796901] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1559.796910] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:DP-1] disconnected
><7>[ 1559.796922] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
><7>[ 1559.796928] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:DP-1]
><7>[ 1559.799483] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.803448] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.807483] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.808878] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1559.808883] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:DP-1] disconnected
><7>[ 1559.808900] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
><7>[ 1559.808906] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-2]
><7>[ 1559.811461] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.815435] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.819431] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.820874] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1559.820881] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-2] disconnected
><7>[ 1559.820892] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
><7>[ 1559.820897] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-2]
><7>[ 1559.823454] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.827461] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.831409] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1559.832861] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1559.832868] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-2] disconnected
><7>[ 1559.846918] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
><7>[ 1559.846924] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
><7>[ 1559.846926] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
><7>[ 1559.846928] [drm:drm_mode_debug_printmodeline], Modeline 258:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
><7>[ 1559.846931] [drm:drm_mode_debug_printmodeline], Modeline 56:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
><7>[ 1559.846934] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1559.846936] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1559.846938] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1559.846940] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1559.846941] [drm:drm_mode_debug_printmodeline], Modeline 56:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
><7>[ 1559.846944] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
><7>[ 1559.846951] [drm:intel_modeset_adjusted_mode], [CRTC:3]
><7>[ 1559.846957] [drm:ivb_modeset_global_resources], disabling fdi C rx
><7>[ 1559.846983] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1559.846985] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
><7>[ 1559.846987] [drm:drm_mode_debug_printmodeline], Modeline 56:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x48 0x6
><7>[ 1559.846990] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014
><7>[ 1559.846991] [drm:intel_get_pch_pll], using pll 0 for pipe 0
><7>[ 1559.846993] [drm:intel_get_pch_pll], switching PLL c6014 off
><7>[ 1559.847306] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
><7>[ 1559.898820] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1559.898829] [drm:ironlake_update_plane], Writing base 00073000 00000000 0 0 7680
><7>[ 1559.898836] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1559.898840] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1559.898844] [drm:ironlake_check_srwm], watermark 2: display plane 66, fbc lines 3, cursor 6
><7>[ 1559.898847] [drm:ironlake_check_srwm], watermark 3: display plane 140, fbc lines 4, cursor 10
><7>[ 1559.898852] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:56:1680x1050]
><7>[ 1559.898857] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1559.898861] [drm:ironlake_check_srwm], watermark 1: display plane 12, fbc lines 3, cursor 6
><7>[ 1559.898864] [drm:ironlake_check_srwm], watermark 2: display plane 66, fbc lines 3, cursor 6
><7>[ 1559.898867] [drm:ironlake_check_srwm], watermark 3: display plane 140, fbc lines 4, cursor 10
><7>[ 1559.950764] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.002679] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.002840] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1560.003502] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1560.003506] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1560.004163] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1560.004167] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1560.004170] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1560.004172] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
><7>[ 1560.004177] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
><7>[ 1560.022032] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1560.023678] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1560.023689] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1560.023694] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1560.023698] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1560.023702] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1560.023707] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1560.023711] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1560.023713] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1560.023716] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1560.023720] [drm:intel_crtc_set_config], [CRTC:5] [FB:102] #connectors=1 (x y) (0 0)
><7>[ 1560.023724] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
><7>[ 1560.023727] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1560.023730] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1560.023733] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1560.023737] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1560.023739] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1560.023742] [drm:drm_mode_debug_printmodeline], Modeline 94:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1560.023747] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
><7>[ 1560.023754] [drm:intel_modeset_adjusted_mode], [CRTC:5]
><7>[ 1560.023787] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1560.023789] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1560.023792] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
><7>[ 1560.023795] [drm:drm_mode_debug_printmodeline], Modeline 94:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1560.023801] [drm:intel_get_pch_pll], CRTC:5 allocated PCH PLL c6018
><7>[ 1560.023804] [drm:intel_get_pch_pll], using pll 1 for pipe 1
><7>[ 1560.023806] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1560.024120] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
><7>[ 1560.024126] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
><7>[ 1560.075627] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.075635] [drm:ironlake_update_plane], Writing base 00073000 00000000 0 0 7680
><7>[ 1560.075642] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.075645] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.075650] [drm:intel_crtc_mode_set], [ENCODER:11:TMDS-11] set [MODE:94:1920x1080]
><7>[ 1560.075653] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe B
><7>[ 1560.075657] [drm:intel_write_eld], ELD on [CONNECTOR:12:HDMI-A-1], [ENCODER:11:TMDS-11]
><7>[ 1560.075660] [drm:ironlake_write_eld], ELD on pipe B
><7>[ 1560.075664] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1560.075693] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.075696] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.127569] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.179512] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.179674] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1560.180334] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1560.180339] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1560.180996] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
><7>[ 1560.181001] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1560.181003] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1560.181006] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
><7>[ 1560.181011] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1560.198938] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1560.200456] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1560.200464] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1560.200472] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1560.200476] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1560.200481] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1560.200485] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1560.200489] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1560.200493] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1560.200496] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1560.200499] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1560.200502] [drm:intel_crtc_set_config], [CRTC:7] [FB:102] #connectors=1 (x y) (0 0)
><7>[ 1560.200507] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
><7>[ 1560.200510] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
><7>[ 1560.200513] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
><7>[ 1560.200516] [drm:intel_modeset_stage_output_state], [CONNECTOR:12:HDMI-A-1] to [CRTC:5]
><7>[ 1560.200520] [drm:intel_modeset_stage_output_state], [CONNECTOR:16:HDMI-A-2] to [CRTC:7]
><7>[ 1560.200523] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
><7>[ 1560.200525] [drm:intel_crtc_set_config], attempting to set mode from userspace
><7>[ 1560.200527] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1560.200533] [drm:intel_set_mode], set mode pipe masks: modeset: 4, prepare: 4, disable: 0
><7>[ 1560.200540] [drm:intel_modeset_adjusted_mode], [CRTC:7]
><7>[ 1560.200573] [drm:intel_choose_pipe_bpp_dither], forcing bpc to 8 for HDMI
><7>[ 1560.200576] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
><7>[ 1560.200579] [drm:ironlake_crtc_mode_set], Mode for pipe 2:
><7>[ 1560.200581] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
><7>[ 1560.200589] [drm:intel_get_pch_pll], CRTC:7 sharing existing PCH PLL c6018 (refcount 1, ative 1)
><7>[ 1560.200592] [drm:intel_get_pch_pll], using pll 1 for pipe 2
><7>[ 1560.200595] [drm:intel_get_pch_pll], switching PLL c6018 off
><7>[ 1560.200909] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 2, lanes 2
><7>[ 1560.252401] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.252409] [drm:ironlake_update_plane], Writing base 00073000 00000000 0 0 7680
><7>[ 1560.252415] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.252419] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.252422] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1560.252426] [drm:intel_crtc_mode_set], [ENCODER:15:TMDS-15] set [MODE:97:1920x1080]
><7>[ 1560.252429] [drm:intel_hdmi_mode_set], Enabling HDMI audio on pipe C
><7>[ 1560.252433] [drm:intel_write_eld], ELD on [CONNECTOR:16:HDMI-A-2], [ENCODER:15:TMDS-15]
><7>[ 1560.252436] [drm:ironlake_write_eld], ELD on pipe C
><7>[ 1560.252440] [drm:ironlake_write_eld], Audio directed to unknown port
><7>[ 1560.252469] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.252472] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.252475] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1560.304375] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.356318] [drm:ironlake_wait_for_vblank], vblank wait timed out
><7>[ 1560.356479] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
><7>[ 1560.357141] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
><7>[ 1560.357145] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
><7>[ 1560.357803] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x200
><7>[ 1560.357807] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
><7>[ 1560.357810] [drm:ivb_manual_fdi_link_train], FDI train done.
><7>[ 1560.357812] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 1, on? 0)for crtc 7
><7>[ 1560.357817] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
><7>[ 1560.375745] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
><7>[ 1560.377261] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
><7>[ 1560.377268] [drm:intel_connector_check_state], [CONNECTOR:12:HDMI-A-1]
><7>[ 1560.377274] [drm:intel_connector_check_state], [CONNECTOR:16:HDMI-A-2]
><7>[ 1560.377280] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
><7>[ 1560.377285] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
><7>[ 1560.377289] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
><7>[ 1560.377293] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
><7>[ 1560.377297] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
><7>[ 1560.377301] [drm:intel_modeset_check_state], [CRTC:3]
><7>[ 1560.377304] [drm:intel_modeset_check_state], [CRTC:5]
><7>[ 1560.377307] [drm:intel_modeset_check_state], [CRTC:7]
><7>[ 1560.377312] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.377315] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.377318] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1560.377322] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.377325] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.377328] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1560.377332] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
><7>[ 1560.377335] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 8, cursor: 6
><7>[ 1560.377338] [drm:sandybridge_update_wm], FIFO watermarks For pipe C - plane 8, cursor: 6
><7>[ 1569.813911] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x82f40010, result 1
><7>[ 1569.813918] [drm:intel_crt_detect], CRT detected via hotplug
><7>[ 1569.813921] [drm:output_poll_execute], [CONNECTOR:9:VGA-1] status updated from 1 to 1
><7>[ 1569.885822] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1569.885829] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-1] status updated from 1 to 1
><7>[ 1569.957745] [drm:drm_detect_monitor_audio], Monitor has basic audio support
><7>[ 1569.957752] [drm:output_poll_execute], [CONNECTOR:16:HDMI-A-2] status updated from 1 to 1
><7>[ 1569.960310] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.964279] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.968274] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.969722] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1569.969729] [drm:output_poll_execute], [CONNECTOR:18:DP-1] status updated from 2 to 2
><7>[ 1569.972286] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.976275] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.980264] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f
><7>[ 1569.981708] [drm:intel_dp_detect], DPCD: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
><7>[ 1569.981714] [drm:output_poll_execute], [CONNECTOR:20:DP-2] status updated from 2 to 2

Actions: View

Attachments on bug 57388: 70400

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.