Attachment 71479 Details for Bug 56568 – The reg dump after boot completes with this config and things work.

The reg dump after boot completes with this config and things work.

regdumper1.log (text/plain), 14.83 KB, created by Guang Yang on 2012-12-14 01:46:54 UTC

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Creator: Guang Yang

Created: 2012-12-14 01:46:54 UTC

Size: 14.83 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000000
>               GEN6_INSTDONE_1: 0xfffffffe
>               GEN6_INSTDONE_2: 0x00000000
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0x00000000
>                FDI_PLL_BIOS_1: 0x00000000
>                FDI_PLL_BIOS_2: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_0: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>              FDI_PLL_FREQ_CTL: 0x00000000
>                     PIPEACONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_A: 0x08bf068f (1680 active, 2240 total)
>                      HBLANK_A: 0x08bf068f (1680 start, 2240 end)
>                       HSYNC_A: 0x07a706f7 (1784 start, 1960 end)
>                      VTOTAL_A: 0x04400419 (1050 active, 1089 total)
>                      VBLANK_A: 0x04400419 (1050 start, 1089 end)
>                       VSYNC_A: 0x0422041c (1053 start, 1059 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x068f0419 (1680, 1050)
>                 PIPEA_DATA_M1: 0x7e358ef0 (TU 64, val 0x358ef0 3510000)
>                 PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x00023b4a (val 0x23b4a 146250)
>                 PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004000 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00001e00 (120)
>                      DSPASURF: 0x00073000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>                      HBLANK_B: 0x081f077f (1920 start, 2080 end)
>                       HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>                      VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>                      VBLANK_B: 0x04d204af (1200 start, 1235 end)
>                       VSYNC_B: 0x04b804b2 (1203 start, 1209 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      PIPEBSRC: 0x077f04af (1920, 1200)
>                 PIPEB_DATA_M1: 0x7e386580 (TU 64, val 0x386580 3696000)
>                 PIPEB_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x00025990 (val 0x25990 154000)
>                 PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPBCNTR: 0xd8004000 (enabled)
>                      DSPBBASE: 0x00000000
>                    DSPBSTRIDE: 0x00001e00 (120)
>                      DSPBSURF: 0x00073000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                     PIPECCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_C: 0x081f077f (1920 active, 2080 total)
>                      HBLANK_C: 0x081f077f (1920 start, 2080 end)
>                       HSYNC_C: 0x07cf07af (1968 start, 2000 end)
>                      VTOTAL_C: 0x04d204af (1200 active, 1235 total)
>                      VBLANK_C: 0x04d204af (1200 start, 1235 end)
>                       VSYNC_C: 0x04b804b2 (1203 start, 1209 end)
>                  VSYNCSHIFT_C: 0x00000000
>                      PIPECSRC: 0x077f04af (1920, 1200)
>                 PIPEC_DATA_M1: 0x7e386580 (TU 64, val 0x386580 3696000)
>                 PIPEC_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000)
>                 PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M1: 0x00025990 (val 0x25990 154000)
>                 PIPEC_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>                 PIPEC_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPCCNTR: 0xd8004000 (enabled)
>                      DSPCBASE: 0x00000000
>                    DSPCSTRIDE: 0x00001e00 (120)
>                      DSPCSURF: 0x00073000
>                   DSPCTILEOFF: 0x00000000 (0, 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007df3 (vscale 0.983978)
>                     PFA_CTL_3: 0x00003ef9 (vscale initial phase 0.491974)
>                     PFA_CTL_4: 0x00007cb8 (hscale 0.974365)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007df3 (vscale 0.983978)
>                     PFB_CTL_3: 0x00003ef9 (vscale initial phase 0.491974)
>                     PFB_CTL_4: 0x00007cb8 (hscale 0.974365)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>                     PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFC_CTL_2: 0x00007df3 (vscale 0.983978)
>                     PFC_CTL_3: 0x00003ef9 (vscale initial phase 0.491974)
>                     PFC_CTL_4: 0x00007cb8 (hscale 0.974365)
>                   PFC_WIN_POS: 0x00000000 (0, 0)
>                  PFC_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00000400 (cpu source disable, ssc_source disable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x01204860
>            PCH_SSC4_AUX_PARMS: 0x000029c5
>                  PCH_DPLL_SEL: 0x00000998 (TransA DPLL enable (DPLL A), TransB DPLL enable (DPLL B))
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x84020002 (enable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0xc4020002 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00021006 (n = 2, m1 = 16, m2 = 6)
>                      PCH_FPA1: 0x00021006 (n = 2, m1 = 16, m2 = 6)
>                      PCH_FPB0: 0x00021106 (n = 2, m1 = 17, m2 = 6)
>                      PCH_FPB1: 0x00021106 (n = 2, m1 = 17, m2 = 6)
>                TRANS_HTOTAL_A: 0x08bf068f (1680 active, 2240 total)
>                TRANS_HBLANK_A: 0x08bf068f (1680 start, 2240 end)
>                 TRANS_HSYNC_A: 0x07a706f7 (1784 start, 1960 end)
>                TRANS_VTOTAL_A: 0x04400419 (1050 active, 1089 total)
>                TRANS_VBLANK_A: 0x04400419 (1050 start, 1089 end)
>                 TRANS_VSYNC_A: 0x0422041c (1053 start, 1059 end)
>            TRANS_VSYNCSHIFT_A: 0x00000000
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x081f077f (1920 active, 2080 total)
>                TRANS_HBLANK_B: 0x081f077f (1920 start, 2080 end)
>                 TRANS_HSYNC_B: 0x07cf07af (1968 start, 2000 end)
>                TRANS_VTOTAL_B: 0x04d204af (1200 active, 1235 total)
>                TRANS_VBLANK_B: 0x04d204af (1200 start, 1235 end)
>                 TRANS_VSYNC_B: 0x04b804b2 (1203 start, 1209 end)
>            TRANS_VSYNCSHIFT_B: 0x00000000
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x081f077f (1920 active, 2080 total)
>                TRANS_HBLANK_C: 0x081f077f (1920 start, 2080 end)
>                 TRANS_HSYNC_C: 0x07cf07af (1968 start, 2000 end)
>                TRANS_VTOTAL_C: 0x04d204af (1200 active, 1235 total)
>                TRANS_VBLANK_C: 0x04d204af (1200 start, 1235 end)
>                 TRANS_VSYNC_C: 0x04b804b2 (1203 start, 1209 end)
>            TRANS_VSYNCSHIFT_C: 0x00000000
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                    TRANSACONF: 0xc0000000 (enable, active, progressive)
>                    TRANSBCONF: 0xc0000000 (enable, active, progressive)
>                    TRANSCCONF: 0xc0000000 (enable, active, progressive)
>                   FDI_TXA_CTL: 0x800c4b00 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0x800c4b00 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x800c4b00 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0x8c082b50 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0x8c082b50 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x8c082b50 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
>                  DPAFE_BMFUNC: 0x0001d233
>             DPAFE_DL_IREFCAL0: 0x00d22bdc
>             DPAFE_DL_IREFCAL1: 0x00d22bdc
>              DPAFE_DP_IREFCAL: 0x80d2218c
>             PCH_DSPCLK_GATE_D: 0x10000000
>              PCH_DSP_CHICKEN1: 0xa0000000
>              PCH_DSP_CHICKEN2: 0x00000000
>              PCH_DSP_CHICKEN3: 0x00000024
>                  FDI_RXA_MISC: 0x00200090 (FDI Delay 144)
>                  FDI_RXB_MISC: 0x00200090 (FDI Delay 144)
>                  FDI_RXC_MISC: 0x00200090 (FDI Delay 144)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x7e000000
>               FDI_RXC_TUSIZE2: 0x7e000000
>                 FDI_PLL_CTL_1: 0x7e000000
>                 FDI_PLL_CTL_2: 0x7e000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000008ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000008ff
>                      PCH_ADPA: 0x83f40010 (enabled, transcoder A, -hsync, +vsync)
>                         HDMIB: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                         HDMIC: 0xa000080c (enabled pipe B 8bpc TMDS DVI audio disabled -vsync +hsync detected)
>                         HDMID: 0xc000080c (enabled pipe C 8bpc TMDS DVI audio disabled -vsync +hsync detected)
>                      PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000000
>                      PCH_DP_C: 0x00000004
>                      PCH_DP_D: 0x00000004
>                TRANS_DP_CTL_A: 0x60000018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
>                TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
>              BLC_PWM_CPU_CTL2: 0x00000000
>               BLC_PWM_CPU_CTL: 0x00000000
>              BLC_PWM_PCH_CTL1: 0x00000000
>              BLC_PWM_PCH_CTL2: 0x00000000
>                 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0x00000008 (blacklight disabled, do not power down on reset, panel off)
>              PCH_PP_ON_DELAYS: 0x00000000
>             PCH_PP_OFF_DELAYS: 0x00000000
>                PCH_PP_DIVISOR: 0x00186904
>                      PORT_DBG: 0x00007777 (HW DRRS off)
>            RC6_RESIDENCY_TIME: 0x00000000
>           RC6p_RESIDENCY_TIME: 0x0fd1814e
>          RC6pp_RESIDENCY_TIME: 0x00000000
>               GEN6_RP_CONTROL: 0x00000d91 (enabled)
>                 GEN6_RPNSWREQ: 0x10000000
>          GEN6_RP_DOWN_TIMEOUT: 0x000f4240
>      GEN6_RP_INTERRUPT_LIMITS: 0x12080000
>          GEN6_RP_UP_THRESHOLD: 0x0000e808
>                 GEN6_RP_UP_EI: 0x000101d0
>               GEN6_RP_DOWN_EI: 0x00055730
>        GEN6_RP_IDLE_HYSTERSIS: 0x0000000a
>                 GEN6_RC_STATE: 0x00000000
>               GEN6_RC_CONTROL: 0x88060000
>      GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000
>      GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e
>   GEN6_RC_EVALUATION_INTERVAL: 0x0001e848
>        GEN6_RC_IDLE_HYSTERSIS: 0x00000019
>                 GEN6_RC_SLEEP: 0x00000000
>           GEN6_RC1e_THRESHOLD: 0x000003e8
>            GEN6_RC6_THRESHOLD: 0x0000c350
>            GEN6_RC_VIDEO_FREQ: 0x18000000
>                    GEN6_PMIER: 0x00000070
>                    GEN6_PMIMR: 0x00000000
>                GEN6_PMINTRMSK: 0x00000000

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Attachments on bug 56568: 69282 | 69289 | 70146 | 71419 | 71479 | 71480 | 71481

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