Attachment 72160 Details for Bug 58790 – 1920x1080i error showing dmesg

1920x1080i error showing dmesg

display5.dmesg (text/plain), 122.91 KB, created by shui yangwei on 2012-12-27 03:30:36 UTC

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Creator: shui yangwei

Created: 2012-12-27 03:30:36 UTC

Size: 122.91 KB

patch

obsolete

>[  191.655489] Pid: 3307, comm: testdisplay Tainted: G        W    3.7.0-rc4_next_queued_debug_20121226+ #3
>[  191.655490] Call Trace:
>[  191.655498]  [<c0226e54>] warn_slowpath_common+0x63/0x78
>[  191.655516]  [<f84a93ee>] ? intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  191.655519]  [<c0226ecd>] warn_slowpath_fmt+0x26/0x2a
>[  191.655538]  [<f84a93ee>] intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  191.655556]  [<f84a952a>] intel_disable_pipe+0x120/0x128 [i915]
>[  191.655574]  [<f84a9b11>] ironlake_crtc_disable+0xa5/0x715 [i915]
>[  191.655589]  [<f8187ecc>] ? drm_ut_debug_printk+0x32/0x36 [drm]
>[  191.655607]  [<f84abec4>] intel_crtc_disable+0x2d/0xdf [i915]
>[  191.655626]  [<f84af190>] intel_set_mode+0x1ef/0x6cd [i915]
>[  191.655644]  [<f84afbb2>] intel_crtc_set_config+0x544/0x65a [i915]
>[  191.655658]  [<f818c9c2>] drm_framebuffer_remove+0x4b/0xd9 [drm]
>[  191.655670]  [<f818f508>] drm_fb_release+0x3b/0x56 [drm]
>[  191.655681]  [<f81844a1>] drm_release+0x1de/0x40d [drm]
>[  191.655684]  [<c02d4204>] __fput+0xd3/0x1a0
>[  191.655687]  [<c02d42d9>] ____fput+0x8/0xa
>[  191.655690]  [<c023d0ab>] task_work_run+0x68/0x79
>[  191.655693]  [<c022b3b7>] do_exit+0x215/0x65e
>[  191.655697]  [<c056e052>] ? _raw_spin_unlock_irq+0x22/0x26
>[  191.655699]  [<c022baa5>] do_group_exit+0x5e/0x81
>[  191.655703]  [<c0235b0a>] get_signal_to_deliver+0x4c5/0x4dd
>[  191.655706]  [<c0201dea>] do_signal+0x20/0x6bd
>[  191.655709]  [<c02803e8>] ? __audit_syscall_exit+0x32e/0x349
>[  191.655713]  [<c0209fc1>] ? syscall_trace_leave+0x2d/0x118
>[  191.655716]  [<c0242f22>] ? up_read+0x16/0x29
>[  191.655719]  [<c0570ba3>] ? __do_page_fault+0x3ab/0x3e8
>[  191.655722]  [<c02d3510>] ? vfs_write+0xea/0x122
>[  191.655724]  [<c056e3d0>] ? work_notifysig+0x11/0x31
>[  191.655726]  [<c02025b4>] do_notify_resume+0x21/0x54
>[  191.655729]  [<c056e3e8>] work_notifysig+0x29/0x31
>[  191.655731] ---[ end trace a44f2f8f2ff6370d ]---
>[  191.661334] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  191.661341] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  191.661756] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  191.661759] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  191.661763] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  191.661766] [drm:intel_update_fbc], fbc set to per-chip default
>[  191.661768] [drm:intel_update_fbc], fbc disabled per module param
>[  191.661785] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  191.661789] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  191.661791] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  191.661794] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  191.661798] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  191.661801] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  191.661805] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  191.661808] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  191.661812] [drm:intel_modeset_check_state], [CRTC:3]
>[  191.661814] [drm:intel_modeset_check_state], [CRTC:5]
>[  191.670596] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  191.670600] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  191.670602] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  191.670605] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  191.670608] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  191.670611] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  191.670613] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  191.670615] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  191.670617] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  191.670619] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  191.670622] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  191.670628] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  191.670631] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  191.670633] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  191.670635] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  191.670642] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  191.670644] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  191.670646] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  191.670648] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  191.670655] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  191.722228] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  191.722241] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  191.722250] [drm:intel_update_fbc], fbc set to per-chip default
>[  191.722254] [drm:intel_update_fbc], fbc disabled per module param
>[  191.722260] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  191.722267] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  191.722273] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  191.722281] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  191.722287] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  191.722793] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  191.722796] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  191.722799] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  191.722804] [drm:ironlake_edp_pll_on], 
>[  191.774132] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  191.826047] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  191.826054] [drm:intel_update_fbc], fbc set to per-chip default
>[  191.826058] [drm:intel_update_fbc], fbc disabled per module param
>[  191.826064] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  191.826070] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  191.826076] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  191.826088] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  191.826094] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  192.126960] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  192.127561] [drm:intel_dp_start_link_train], clock recovery OK
>[  192.127565] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  192.127570] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  192.127575] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  192.127584] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  192.127589] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  192.467944] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  192.467957] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  192.518856] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  192.519814] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  192.519854] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  192.519972] [drm:ironlake_edp_backlight_on], 
>[  192.560797] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  192.570780] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  192.570797] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  192.570804] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  192.570810] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  192.570816] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  192.570823] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  192.570830] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  192.570836] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  192.570843] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  192.570849] [drm:intel_modeset_check_state], [CRTC:3]
>[  192.570854] [drm:intel_modeset_check_state], [CRTC:5]
>[  192.570860] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  192.570867] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  192.570872] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  192.570877] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  192.570883] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  192.570888] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  192.570892] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  192.570896] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  192.570905] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  192.570915] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  192.570921] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  192.570926] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  192.570931] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  192.570940] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  192.570945] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  192.570950] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  192.570954] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  192.570961] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  192.570966] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  192.570971] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  192.571287] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  192.622679] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  192.622690] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  192.622698] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  192.622706] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  192.622711] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  192.622718] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  192.622725] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  192.622731] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  192.622737] [drm:ironlake_write_eld], ELD on pipe B
>[  192.622743] [drm:ironlake_write_eld], Audio directed to unknown port
>[  192.622747] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  192.622765] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  192.622771] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  192.674607] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  192.725506] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  192.725823] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  192.725825] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  192.725982] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  192.725984] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  192.725986] [drm:ironlake_fdi_link_train], FDI train done
>[  192.725988] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  192.725991] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  192.727215] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  192.727706] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  192.728534] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  192.729336] [drm:intel_dp_start_link_train], clock recovery OK
>[  192.729340] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  192.730422] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  192.731492] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  192.732570] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  192.733670] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  192.734764] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  192.751541] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  192.752500] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  192.752513] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  192.752524] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  192.752535] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  192.752540] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  192.752545] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  192.752551] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  192.752556] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  192.752562] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  192.752567] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  192.752573] [drm:intel_modeset_check_state], [CRTC:3]
>[  192.752578] [drm:intel_modeset_check_state], [CRTC:5]
>[  192.752616] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  192.753079] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  192.753872] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  192.754203] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  192.754214] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  192.754386] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  192.754556] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  192.754560] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  192.754566] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  192.754573] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  192.754576] [drm:intel_crt_detect], CRT not detected via hotplug
>[  192.754732] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  192.754737] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  192.754740] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  192.754743] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  192.755095] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  192.755098] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  192.755101] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  192.755104] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  192.755269] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  192.755272] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  192.755275] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  192.755566] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  192.756423] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  192.780383] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  192.804249] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  192.804253] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  192.804256] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  192.804262] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  192.804267] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  192.804282] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  192.804291] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  195.752323] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  211.343525] [drm:i915_driver_open], 
>[  211.343582] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  211.343594] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.343601] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  211.343608] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  211.343615] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.343621] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  211.343654] [drm:i915_driver_open], 
>[  211.344006] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.344026] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.344047] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  211.344056] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  211.344422] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  211.345268] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.368828] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.392400] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.392405] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  211.393245] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.416870] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.440495] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.440592] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  211.440595] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  211.440656] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  211.440660] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  211.440664] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  211.440668] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  211.440675] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  211.440679] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  211.440683] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  211.440687] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  211.440692] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  211.440696] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  211.440700] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  211.440704] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  211.440708] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  211.440712] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  211.440717] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  211.440721] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  211.440725] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  211.440729] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  211.440733] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  211.440737] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  211.440741] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  211.440746] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  211.440750] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  211.440754] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  211.440758] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  211.440762] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  211.440766] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  211.440770] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  211.440775] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  211.440779] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  211.440783] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  211.440787] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  211.440791] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  211.440795] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  211.440800] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  211.440804] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  211.440808] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  211.440812] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  211.440816] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  211.440820] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  211.440824] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  211.440828] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  211.440832] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  211.440836] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  211.440840] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  211.440844] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  211.440858] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  211.689494] [drm:drm_mode_addfb], [FB:35]
>[  211.691069] [drm:drm_mode_setcrtc], [CRTC:3]
>[  211.691087] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  211.691094] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  211.691104] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  211.691110] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  211.691120] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  211.691130] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  211.691137] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  211.691143] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  211.691150] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  211.691155] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  211.691160] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  211.691165] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  211.691177] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  211.691380] [drm:intel_dp_link_down], 
>[  211.734618] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  211.767663] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  211.767670] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  211.768085] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  211.768089] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  211.768096] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  211.768108] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  211.768114] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  211.768119] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  211.768123] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  211.768126] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  211.768137] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  211.768143] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  211.768151] [drm:ironlake_edp_backlight_off], 
>[  211.968531] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  211.968537] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  211.968543] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  212.790002] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  212.806810] [drm:intel_dp_link_down], 
>[  212.858775] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.910321] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  212.910325] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  212.910329] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  212.910332] [drm:intel_update_fbc], fbc set to per-chip default
>[  212.910334] [drm:intel_update_fbc], fbc disabled per module param
>[  212.910341] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  212.910343] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  212.910345] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  212.910347] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  212.910350] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  212.910352] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  212.910354] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  212.910667] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  212.962601] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.962611] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 7680
>[  213.014518] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  213.014526] [drm:intel_update_fbc], fbc set to per-chip default
>[  213.014531] [drm:intel_update_fbc], fbc disabled per module param
>[  213.014540] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  213.014549] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  213.014555] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  213.014561] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1920x1080i]
>[  213.014567] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  213.014572] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  213.014576] [drm:ironlake_write_eld], ELD on pipe A
>[  213.014581] [drm:ironlake_write_eld], Audio directed to unknown port
>[  213.014585] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  213.014603] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  213.014608] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  213.014613] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  213.066426] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  213.118335] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  213.118651] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  213.118653] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  213.118810] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  213.118812] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  213.118814] [drm:ironlake_fdi_link_train], FDI train done
>[  213.118816] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  213.118819] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  213.120043] [drm:intel_update_fbc], fbc set to per-chip default
>[  213.120045] [drm:intel_update_fbc], fbc disabled per module param
>[  213.120529] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  213.121333] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  213.122108] [drm:intel_dp_start_link_train], clock recovery OK
>[  213.122111] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  213.123185] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  213.124255] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  213.125329] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  213.126423] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  213.127535] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  213.144221] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  213.145240] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  213.145255] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  213.145267] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  213.145274] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  213.145282] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  213.145290] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  213.145297] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  213.145305] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  213.145313] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  213.145320] [drm:intel_modeset_check_state], [CRTC:3]
>[  213.145331] [drm:intel_modeset_check_state], [CRTC:5]
>[  213.145359] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  213.145871] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  213.146218] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  213.146224] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  213.146230] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  213.146241] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  213.146245] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  213.447042] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  213.447219] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  213.447224] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  213.447230] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  213.447236] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  213.447239] [drm:intel_crt_detect], CRT not detected via hotplug
>[  213.447406] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  213.447411] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  213.447415] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  213.447417] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  213.447784] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  213.447787] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  213.447791] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  213.447796] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  213.448024] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  213.448028] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  213.448031] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  213.448324] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  213.449192] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.473013] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.496874] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.496877] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  213.496881] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  213.496886] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  213.496891] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  213.496896] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  213.496902] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  216.452603] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  263.138949] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  263.138960] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  263.138965] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  263.138969] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  263.138974] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  263.139164] [drm:intel_dp_link_down], 
>[  263.194006] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  263.295831] ------------[ cut here ]------------
>[  263.295885] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x114/0x130 [i915]()
>[  263.295888] Hardware name: Latitude E6510
>[  263.295891] pipe_off wait timed out
>[  263.295893] Modules linked in: lockd ip6t_REJECT ipt_REJECT xt_tcpudp nf_conntrack_ipv6 nf_conntrack_ipv4 nf_defrag_ipv6 nf_defrag_ipv4 xt_state iptable_filter nf_conntrack ip_tables ip6table_filter ip6_tables x_tables snd_hda_codec_hdmi snd_hda_codec_idt iTCO_wdt iTCO_vendor_support coretemp snd_hda_intel hwmon dcdbas snd_hda_codec kvm_intel snd_hwdep snd_seq snd_seq_device kvm microcode joydev snd_pcm snd_timer snd sg soundcore pcspkr lpc_ich i2c_i801 mfd_core e1000e snd_page_alloc wmi battery ppdev parport_pc parport ac uinput sunrpc ipv6 autofs4 ext3 jbd mbcache sr_mod cdrom firewire_ohci sd_mod firewire_core crc_itu_t ehci_hcd i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod
>[  263.295975] Pid: 3608, comm: testdisplay Tainted: G        W    3.7.0-rc4_next_queued_debug_20121226+ #3
>[  263.295977] Call Trace:
>[  263.295985]  [<c0226e54>] warn_slowpath_common+0x63/0x78
>[  263.296003]  [<f84a93ee>] ? intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  263.296006]  [<c0226ecd>] warn_slowpath_fmt+0x26/0x2a
>[  263.296024]  [<f84a93ee>] intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  263.296043]  [<f84a952a>] intel_disable_pipe+0x120/0x128 [i915]
>[  263.296060]  [<f84a9b11>] ironlake_crtc_disable+0xa5/0x715 [i915]
>[  263.296077]  [<f8187ecc>] ? drm_ut_debug_printk+0x32/0x36 [drm]
>[  263.296094]  [<f84abec4>] intel_crtc_disable+0x2d/0xdf [i915]
>[  263.296113]  [<f84af190>] intel_set_mode+0x1ef/0x6cd [i915]
>[  263.296131]  [<f84afbb2>] intel_crtc_set_config+0x544/0x65a [i915]
>[  263.296145]  [<f818c9c2>] drm_framebuffer_remove+0x4b/0xd9 [drm]
>[  263.296158]  [<f818f508>] drm_fb_release+0x3b/0x56 [drm]
>[  263.296168]  [<f81844a1>] drm_release+0x1de/0x40d [drm]
>[  263.296173]  [<c02d4204>] __fput+0xd3/0x1a0
>[  263.296175]  [<c02d42d9>] ____fput+0x8/0xa
>[  263.296178]  [<c023d0ab>] task_work_run+0x68/0x79
>[  263.296181]  [<c022b3b7>] do_exit+0x215/0x65e
>[  263.296185]  [<c056e052>] ? _raw_spin_unlock_irq+0x22/0x26
>[  263.296187]  [<c022baa5>] do_group_exit+0x5e/0x81
>[  263.296191]  [<c0235b0a>] get_signal_to_deliver+0x4c5/0x4dd
>[  263.296194]  [<c0201dea>] do_signal+0x20/0x6bd
>[  263.296197]  [<c02803e8>] ? __audit_syscall_exit+0x32e/0x349
>[  263.296201]  [<c0209fc1>] ? syscall_trace_leave+0x2d/0x118
>[  263.296205]  [<c0242f22>] ? up_read+0x16/0x29
>[  263.296208]  [<c0570ba3>] ? __do_page_fault+0x3ab/0x3e8
>[  263.296210]  [<c02d3510>] ? vfs_write+0xea/0x122
>[  263.296213]  [<c056e3d0>] ? work_notifysig+0x11/0x31
>[  263.296215]  [<c02025b4>] do_notify_resume+0x21/0x54
>[  263.296218]  [<c056e3e8>] work_notifysig+0x29/0x31
>[  263.296221]  [<c0560000>] ? detect_ht+0xd0/0x152
>[  263.296223] ---[ end trace a44f2f8f2ff6370e ]---
>[  263.301818] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  263.301825] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  263.302240] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  263.302245] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  263.302251] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  263.302258] [drm:intel_update_fbc], fbc set to per-chip default
>[  263.302261] [drm:intel_update_fbc], fbc disabled per module param
>[  263.302282] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  263.302288] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  263.302293] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  263.302298] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  263.302304] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  263.302309] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  263.302315] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  263.302320] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  263.302325] [drm:intel_modeset_check_state], [CRTC:3]
>[  263.302329] [drm:intel_modeset_check_state], [CRTC:5]
>[  263.308665] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  263.308673] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  263.308678] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  263.308683] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  263.308690] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  263.308697] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  263.308702] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  263.308708] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  263.308725] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  263.308730] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  263.308737] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  263.308755] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  263.308766] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  263.308777] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  263.308787] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  263.308799] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  263.308804] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  263.308809] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  263.308813] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  263.308826] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  263.360708] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  263.360719] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  263.360727] [drm:intel_update_fbc], fbc set to per-chip default
>[  263.360730] [drm:intel_update_fbc], fbc disabled per module param
>[  263.360735] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  263.360741] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  263.360747] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  263.360753] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  263.360759] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  263.361263] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  263.361269] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  263.361275] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  263.361282] [drm:ironlake_edp_pll_on], 
>[  263.412618] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  263.464532] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  263.464539] [drm:intel_update_fbc], fbc set to per-chip default
>[  263.464543] [drm:intel_update_fbc], fbc disabled per module param
>[  263.464549] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  263.464555] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  263.464561] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  263.464573] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  263.464578] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  263.765445] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  263.766050] [drm:intel_dp_start_link_train], clock recovery OK
>[  263.766054] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  263.766058] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  263.766064] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  263.766072] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  263.766078] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  264.106430] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  264.106442] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  264.157341] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  264.158304] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  264.158461] [drm:ironlake_edp_backlight_on], 
>[  264.174980] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  264.199215] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  264.209195] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  264.209213] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  264.209221] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  264.209228] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  264.209236] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  264.209244] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  264.209252] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  264.209260] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  264.209267] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  264.209275] [drm:intel_modeset_check_state], [CRTC:3]
>[  264.209281] [drm:intel_modeset_check_state], [CRTC:5]
>[  264.209290] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  264.209298] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  264.209305] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  264.209311] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  264.209320] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  264.209323] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  264.209326] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  264.209328] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  264.209333] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  264.209339] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  264.209342] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  264.209345] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  264.209348] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  264.209354] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  264.209357] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  264.209359] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  264.209362] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  264.209366] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  264.209369] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  264.209372] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  264.209686] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  264.261094] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  264.261105] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  264.261115] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  264.261123] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  264.261129] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  264.261138] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  264.261146] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  264.261154] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  264.261161] [drm:ironlake_write_eld], ELD on pipe B
>[  264.261168] [drm:ironlake_write_eld], Audio directed to unknown port
>[  264.261173] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  264.261193] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  264.261200] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  264.313082] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  264.364977] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  264.365297] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  264.365301] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  264.365460] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  264.365463] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  264.365467] [drm:ironlake_fdi_link_train], FDI train done
>[  264.365470] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  264.365477] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  264.366705] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  264.367159] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  264.367980] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  264.368785] [drm:intel_dp_start_link_train], clock recovery OK
>[  264.368788] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  264.369865] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  264.370946] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  264.372025] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  264.373131] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  264.374228] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  264.390945] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  264.391956] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  264.391974] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  264.391992] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  264.392002] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  264.392008] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  264.392015] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  264.392021] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  264.392028] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  264.392034] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  264.392040] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  264.392046] [drm:intel_modeset_check_state], [CRTC:3]
>[  264.392053] [drm:intel_modeset_check_state], [CRTC:5]
>[  264.392089] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  264.392554] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  264.393348] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  264.393680] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  264.393691] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  264.393862] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  264.394036] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  264.394040] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  264.394047] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  264.394053] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  264.394056] [drm:intel_crt_detect], CRT not detected via hotplug
>[  264.394225] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  264.394231] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  264.394234] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  264.394237] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  264.394594] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  264.394597] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  264.394599] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  264.394602] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  264.394761] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  264.394765] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  264.394767] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  264.395058] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  264.395909] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  264.419655] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  264.443607] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  264.443611] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  264.443615] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  264.443620] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  264.443626] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  264.443631] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  264.443636] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  267.396763] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  271.159797] [drm:i915_driver_open], 
>[  271.159855] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  271.159867] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  271.159874] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  271.159881] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  271.159888] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  271.159894] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  271.159926] [drm:i915_driver_open], 
>[  271.160354] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  271.160374] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  271.160397] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  271.160405] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  271.160716] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  271.161574] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.185513] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.209395] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.209399] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  271.210267] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.234243] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.258181] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  271.258278] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  271.258281] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  271.258341] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  271.258346] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  271.258349] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  271.258353] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  271.258361] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  271.258364] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  271.258368] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  271.258372] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  271.258376] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  271.258381] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  271.258385] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  271.258389] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  271.258393] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  271.258397] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  271.258401] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  271.258405] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  271.258409] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  271.258414] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  271.258418] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  271.258422] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  271.258426] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  271.258430] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  271.258434] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  271.258438] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  271.258442] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  271.258446] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  271.258451] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  271.258455] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  271.258459] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  271.258463] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  271.258467] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  271.258471] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  271.258475] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  271.258479] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  271.258484] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  271.258488] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  271.258492] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  271.258496] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  271.258501] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  271.258505] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  271.258509] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  271.258514] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  271.258518] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  271.258522] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  271.258526] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  271.258530] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  271.258544] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  271.467546] [drm:drm_mode_addfb], [FB:35]
>[  271.467764] [drm:drm_mode_setcrtc], [CRTC:3]
>[  271.467782] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  271.467790] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  271.467801] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  271.467808] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  271.467817] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  271.467834] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  271.467849] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  271.467856] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  271.467864] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  271.467871] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  271.467873] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  271.467876] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  271.467882] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  271.468066] [drm:intel_dp_link_down], 
>[  271.537615] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.553525] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  271.586469] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  271.586478] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  271.586894] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  271.586901] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  271.586910] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  271.586926] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  271.586934] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  271.586941] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  271.586947] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  271.586953] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  271.586966] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  271.586974] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  271.586983] [drm:ironlake_edp_backlight_off], 
>[  271.787342] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  271.787349] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  271.787354] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  272.622287] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  272.640651] [drm:intel_dp_link_down], 
>[  272.692557] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.744103] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  272.744113] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  272.744121] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  272.744130] [drm:intel_update_fbc], fbc set to per-chip default
>[  272.744135] [drm:intel_update_fbc], fbc disabled per module param
>[  272.744149] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  272.744156] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  272.744162] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  272.744167] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  272.744177] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  272.744183] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  272.744189] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  272.744508] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  272.796445] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.796455] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 7680
>[  272.848354] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.848360] [drm:intel_update_fbc], fbc set to per-chip default
>[  272.848363] [drm:intel_update_fbc], fbc disabled per module param
>[  272.848369] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  272.848375] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  272.848380] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  272.848387] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1920x1080i]
>[  272.848393] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  272.848398] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  272.848402] [drm:ironlake_write_eld], ELD on pipe A
>[  272.848407] [drm:ironlake_write_eld], Audio directed to unknown port
>[  272.848410] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  272.848428] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  272.848433] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  272.848439] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  272.900264] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.952106] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.952423] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  272.952428] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  272.952587] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  272.952591] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  272.952595] [drm:ironlake_fdi_link_train], FDI train done
>[  272.952599] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  272.952606] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  272.953835] [drm:intel_update_fbc], fbc set to per-chip default
>[  272.953839] [drm:intel_update_fbc], fbc disabled per module param
>[  272.954342] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  272.955153] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  272.955950] [drm:intel_dp_start_link_train], clock recovery OK
>[  272.955954] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  272.957030] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  272.958106] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  272.959184] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  272.960283] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  272.961378] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  272.978063] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  272.979079] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  272.979094] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  272.979103] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  272.979110] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  272.979122] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  272.979135] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  272.979144] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  272.979154] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  272.979162] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  272.979170] [drm:intel_modeset_check_state], [CRTC:3]
>[  272.979176] [drm:intel_modeset_check_state], [CRTC:5]
>[  272.979206] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  272.979716] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  272.980057] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  272.980063] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  272.980069] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  272.980081] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  272.980086] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  273.280834] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  273.281009] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  273.281013] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  273.281020] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  273.281025] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  273.281029] [drm:intel_crt_detect], CRT not detected via hotplug
>[  273.281198] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  273.281203] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  273.281207] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  273.281209] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  273.281580] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  273.281583] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  273.281587] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  273.281591] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  273.281751] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  273.281755] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  273.281758] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  273.282046] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  273.282900] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  273.306739] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  273.330611] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  273.330615] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  273.330618] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  273.330623] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  273.330629] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  273.330634] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  273.330639] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  276.285439] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  298.593662] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  298.593672] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  298.593676] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  298.593681] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  298.593685] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  298.593922] [drm:intel_dp_link_down], 
>[  298.654859] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  298.756683] ------------[ cut here ]------------
>[  298.756729] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x114/0x130 [i915]()
>[  298.756733] Hardware name: Latitude E6510
>[  298.756735] pipe_off wait timed out
>[  298.756737] Modules linked in: lockd ip6t_REJECT ipt_REJECT xt_tcpudp nf_conntrack_ipv6 nf_conntrack_ipv4 nf_defrag_ipv6 nf_defrag_ipv4 xt_state iptable_filter nf_conntrack ip_tables ip6table_filter ip6_tables x_tables snd_hda_codec_hdmi snd_hda_codec_idt iTCO_wdt iTCO_vendor_support coretemp snd_hda_intel hwmon dcdbas snd_hda_codec kvm_intel snd_hwdep snd_seq snd_seq_device kvm microcode joydev snd_pcm snd_timer snd sg soundcore pcspkr lpc_ich i2c_i801 mfd_core e1000e snd_page_alloc wmi battery ppdev parport_pc parport ac uinput sunrpc ipv6 autofs4 ext3 jbd mbcache sr_mod cdrom firewire_ohci sd_mod firewire_core crc_itu_t ehci_hcd i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod
>[  298.756827] Pid: 3769, comm: testdisplay Tainted: G        W    3.7.0-rc4_next_queued_debug_20121226+ #3
>[  298.756829] Call Trace:
>[  298.756841]  [<c0226e54>] warn_slowpath_common+0x63/0x78
>[  298.756873]  [<f84a93ee>] ? intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  298.756879]  [<c0226ecd>] warn_slowpath_fmt+0x26/0x2a
>[  298.756912]  [<f84a93ee>] intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  298.756946]  [<f84a952a>] intel_disable_pipe+0x120/0x128 [i915]
>[  298.756977]  [<f84a9b11>] ironlake_crtc_disable+0xa5/0x715 [i915]
>[  298.757002]  [<f8187ecc>] ? drm_ut_debug_printk+0x32/0x36 [drm]
>[  298.757034]  [<f84abec4>] intel_crtc_disable+0x2d/0xdf [i915]
>[  298.757067]  [<f84af190>] intel_set_mode+0x1ef/0x6cd [i915]
>[  298.757100]  [<f84afbb2>] intel_crtc_set_config+0x544/0x65a [i915]
>[  298.757124]  [<f818c9c2>] drm_framebuffer_remove+0x4b/0xd9 [drm]
>[  298.757146]  [<f818f508>] drm_fb_release+0x3b/0x56 [drm]
>[  298.757165]  [<f81844a1>] drm_release+0x1de/0x40d [drm]
>[  298.757171]  [<c02d4204>] __fput+0xd3/0x1a0
>[  298.757176]  [<c02d42d9>] ____fput+0x8/0xa
>[  298.757181]  [<c023d0ab>] task_work_run+0x68/0x79
>[  298.757185]  [<c022b3b7>] do_exit+0x215/0x65e
>[  298.757192]  [<c056e052>] ? _raw_spin_unlock_irq+0x22/0x26
>[  298.757196]  [<c022baa5>] do_group_exit+0x5e/0x81
>[  298.757202]  [<c0235b0a>] get_signal_to_deliver+0x4c5/0x4dd
>[  298.757207]  [<c0201dea>] do_signal+0x20/0x6bd
>[  298.757213]  [<c02803e8>] ? __audit_syscall_exit+0x32e/0x349
>[  298.757218]  [<c0209fc1>] ? syscall_trace_leave+0x2d/0x118
>[  298.757224]  [<c0242f22>] ? up_read+0x16/0x29
>[  298.757229]  [<c0570ba3>] ? __do_page_fault+0x3ab/0x3e8
>[  298.757234]  [<c02d3510>] ? vfs_write+0xea/0x122
>[  298.757238]  [<c056e3d0>] ? work_notifysig+0x11/0x31
>[  298.757242]  [<c02025b4>] do_notify_resume+0x21/0x54
>[  298.757247]  [<c056e3e8>] work_notifysig+0x29/0x31
>[  298.757250] ---[ end trace a44f2f8f2ff6370f ]---
>[  298.762678] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  298.762685] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  298.763100] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  298.763105] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  298.763111] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  298.763118] [drm:intel_update_fbc], fbc set to per-chip default
>[  298.763122] [drm:intel_update_fbc], fbc disabled per module param
>[  298.763144] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  298.763149] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  298.763154] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  298.763159] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  298.763165] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  298.763170] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  298.763176] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  298.763181] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  298.763186] [drm:intel_modeset_check_state], [CRTC:3]
>[  298.763190] [drm:intel_modeset_check_state], [CRTC:5]
>[  298.769845] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  298.769853] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  298.769858] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  298.769862] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  298.769869] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  298.769877] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  298.769882] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  298.769887] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  298.769891] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  298.769895] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  298.769902] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  298.769914] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  298.769921] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  298.769926] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  298.769931] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  298.769941] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  298.769946] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  298.769951] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  298.769955] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  298.769968] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  298.821569] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  298.821579] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  298.821587] [drm:intel_update_fbc], fbc set to per-chip default
>[  298.821591] [drm:intel_update_fbc], fbc disabled per module param
>[  298.821596] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  298.821601] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  298.821607] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  298.821613] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  298.821618] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  298.822123] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  298.822129] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  298.822134] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  298.822141] [drm:ironlake_edp_pll_on], 
>[  298.873479] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  298.925392] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  298.925399] [drm:intel_update_fbc], fbc set to per-chip default
>[  298.925403] [drm:intel_update_fbc], fbc disabled per module param
>[  298.925409] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  298.925415] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  298.925421] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  298.925433] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  298.925438] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  299.226309] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.226910] [drm:intel_dp_start_link_train], clock recovery OK
>[  299.226914] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  299.226918] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  299.226923] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  299.226932] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  299.226937] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  299.567227] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  299.567241] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  299.618198] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.619162] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  299.619201] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  299.619318] [drm:ironlake_edp_backlight_on], 
>[  299.660142] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  299.670118] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  299.670134] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  299.670140] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  299.670145] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  299.670150] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  299.670156] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  299.670161] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  299.670167] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  299.670173] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  299.670178] [drm:intel_modeset_check_state], [CRTC:3]
>[  299.670182] [drm:intel_modeset_check_state], [CRTC:5]
>[  299.670188] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  299.670194] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  299.670199] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  299.670202] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  299.670207] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  299.670211] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  299.670215] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  299.670218] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  299.670225] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  299.670233] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  299.670239] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  299.670243] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  299.670247] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  299.670255] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  299.670260] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  299.670264] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  299.670267] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  299.670273] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  299.670277] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  299.670281] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  299.670596] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  299.722019] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.722029] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  299.722036] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  299.722042] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  299.722047] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  299.722053] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  299.722059] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  299.722064] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  299.722068] [drm:ironlake_write_eld], ELD on pipe B
>[  299.722073] [drm:ironlake_write_eld], Audio directed to unknown port
>[  299.722077] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  299.722094] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  299.722099] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  299.772936] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.824848] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.825166] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  299.825170] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  299.825329] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  299.825332] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  299.825336] [drm:ironlake_fdi_link_train], FDI train done
>[  299.825340] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  299.825346] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  299.826572] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  299.827007] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.827832] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  299.828634] [drm:intel_dp_start_link_train], clock recovery OK
>[  299.828639] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  299.829709] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  299.830776] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  299.831849] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.832937] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  299.834029] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  299.850808] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  299.851798] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  299.851807] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  299.851816] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  299.851820] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  299.851824] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  299.851830] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  299.851834] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  299.851837] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  299.851841] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  299.851845] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  299.851850] [drm:intel_modeset_check_state], [CRTC:3]
>[  299.851856] [drm:intel_modeset_check_state], [CRTC:5]
>[  299.851878] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  299.852332] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  299.853129] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  299.853468] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  299.853479] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  299.853648] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  299.853814] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  299.853818] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  299.853825] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  299.853831] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  299.853834] [drm:intel_crt_detect], CRT not detected via hotplug
>[  299.854097] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  299.854101] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  299.854104] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  299.854106] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  299.854461] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  299.854464] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  299.854466] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  299.854470] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  299.854627] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  299.854631] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  299.854633] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  299.854925] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  299.855770] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.879377] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.903119] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.903123] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  299.903127] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  299.903132] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  299.903137] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  299.903142] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  299.903148] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  301.432438] [drm:i915_driver_open], 
>[  301.432495] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  301.432508] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  301.432514] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  301.432521] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  301.432530] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  301.432535] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  301.432569] [drm:i915_driver_open], 
>[  301.432915] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  301.432935] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  301.432956] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  301.432965] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  301.433382] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  301.434229] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.457914] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.481605] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.481610] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  301.482457] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.506123] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.529858] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  301.529958] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  301.529961] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  301.530021] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  301.530025] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  301.530029] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  301.530033] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  301.530040] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  301.530043] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  301.530047] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  301.530051] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  301.530055] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  301.530059] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  301.530063] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  301.530067] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  301.530071] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  301.530075] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  301.530079] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  301.530083] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  301.530087] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  301.530091] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  301.530095] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  301.530099] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  301.530103] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  301.530107] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  301.530111] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  301.530115] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  301.530119] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  301.530123] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  301.530127] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  301.530131] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  301.530135] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  301.530139] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  301.530143] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  301.530147] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  301.530151] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  301.530155] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  301.530159] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  301.530163] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  301.530167] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  301.530171] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  301.530175] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  301.530179] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  301.530183] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  301.530186] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  301.530190] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  301.530194] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.530198] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.530202] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  301.530216] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  301.754123] [drm:drm_mode_addfb], [FB:35]
>[  301.754272] [drm:drm_mode_setcrtc], [CRTC:3]
>[  301.754287] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  301.754293] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  301.754302] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  301.754306] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  301.754313] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  301.754322] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  301.754327] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  301.754333] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  301.754338] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  301.754342] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  301.754346] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  301.754350] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  301.754358] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  301.754555] [drm:intel_dp_link_down], 
>[  301.798281] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  301.831396] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  301.831404] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  301.831821] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  301.831826] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  301.831834] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  301.831848] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  301.831855] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  301.831860] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  301.831865] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  301.831870] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  301.831876] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  301.831880] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  301.831889] [drm:ironlake_edp_backlight_off], 
>[  302.032241] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  302.032248] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  302.032253] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  302.811948] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  302.829665] [drm:intel_dp_link_down], 
>[  302.881572] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  302.933116] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  302.933120] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  302.933124] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  302.933127] [drm:intel_update_fbc], fbc set to per-chip default
>[  302.933129] [drm:intel_update_fbc], fbc disabled per module param
>[  302.933136] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  302.933138] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  302.933141] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  302.933142] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  302.933145] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  302.933148] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  302.933149] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  302.933463] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  302.985393] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  302.985403] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 7680
>[  303.037304] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  303.037310] [drm:intel_update_fbc], fbc set to per-chip default
>[  303.037314] [drm:intel_update_fbc], fbc disabled per module param
>[  303.037319] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  303.037325] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  303.037331] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  303.037337] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1920x1080i]
>[  303.037343] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  303.037348] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  303.037352] [drm:ironlake_write_eld], ELD on pipe A
>[  303.037357] [drm:ironlake_write_eld], Audio directed to unknown port
>[  303.037361] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  303.037379] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  303.037384] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  303.037389] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  303.089213] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  303.141124] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  303.141440] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  303.141442] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  303.141599] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  303.141601] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  303.141603] [drm:ironlake_fdi_link_train], FDI train done
>[  303.141604] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  303.141608] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  303.142853] [drm:intel_update_fbc], fbc set to per-chip default
>[  303.142855] [drm:intel_update_fbc], fbc disabled per module param
>[  303.143343] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  303.144145] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  303.144939] [drm:intel_dp_start_link_train], clock recovery OK
>[  303.144942] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  303.146031] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  303.147107] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  303.148185] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  303.149284] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  303.150377] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  303.167091] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  303.168105] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  303.168121] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  303.168132] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  303.168145] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  303.168154] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  303.168163] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  303.168172] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  303.168181] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  303.168193] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  303.168199] [drm:intel_modeset_check_state], [CRTC:3]
>[  303.168202] [drm:intel_modeset_check_state], [CRTC:5]
>[  303.168214] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  303.168722] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  303.169171] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  303.169178] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  303.169185] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  303.169196] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  303.169200] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  303.469747] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  303.469920] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  303.469924] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  303.469930] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  303.469937] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  303.469940] [drm:intel_crt_detect], CRT not detected via hotplug
>[  303.470107] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  303.470112] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  303.470116] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  303.470118] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  303.470482] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  303.470489] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  303.470495] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  303.470502] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  303.470674] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  303.470683] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  303.470689] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  303.470989] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  303.471843] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  303.495590] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  303.519308] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  303.519312] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  303.519316] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  303.519321] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  303.519326] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  303.519331] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  303.519337] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  303.519352] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  316.670552] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  316.670563] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  316.670568] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  316.670572] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  316.670577] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  316.670762] [drm:intel_dp_link_down], 
>[  316.731694] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  316.832519] ------------[ cut here ]------------
>[  316.832563] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x114/0x130 [i915]()
>[  316.832566] Hardware name: Latitude E6510
>[  316.832568] pipe_off wait timed out
>[  316.832570] Modules linked in: lockd ip6t_REJECT ipt_REJECT xt_tcpudp nf_conntrack_ipv6 nf_conntrack_ipv4 nf_defrag_ipv6 nf_defrag_ipv4 xt_state iptable_filter nf_conntrack ip_tables ip6table_filter ip6_tables x_tables snd_hda_codec_hdmi snd_hda_codec_idt iTCO_wdt iTCO_vendor_support coretemp snd_hda_intel hwmon dcdbas snd_hda_codec kvm_intel snd_hwdep snd_seq snd_seq_device kvm microcode joydev snd_pcm snd_timer snd sg soundcore pcspkr lpc_ich i2c_i801 mfd_core e1000e snd_page_alloc wmi battery ppdev parport_pc parport ac uinput sunrpc ipv6 autofs4 ext3 jbd mbcache sr_mod cdrom firewire_ohci sd_mod firewire_core crc_itu_t ehci_hcd i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod
>[  316.832660] Pid: 3900, comm: testdisplay Tainted: G        W    3.7.0-rc4_next_queued_debug_20121226+ #3
>[  316.832662] Call Trace:
>[  316.832674]  [<c0226e54>] warn_slowpath_common+0x63/0x78
>[  316.832706]  [<f84a93ee>] ? intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  316.832712]  [<c0226ecd>] warn_slowpath_fmt+0x26/0x2a
>[  316.832745]  [<f84a93ee>] intel_wait_for_pipe_off+0x114/0x130 [i915]
>[  316.832778]  [<f84a952a>] intel_disable_pipe+0x120/0x128 [i915]
>[  316.832810]  [<f84a9b11>] ironlake_crtc_disable+0xa5/0x715 [i915]
>[  316.832835]  [<f8187ecc>] ? drm_ut_debug_printk+0x32/0x36 [drm]
>[  316.832867]  [<f84abec4>] intel_crtc_disable+0x2d/0xdf [i915]
>[  316.832900]  [<f84af190>] intel_set_mode+0x1ef/0x6cd [i915]
>[  316.832933]  [<f84afbb2>] intel_crtc_set_config+0x544/0x65a [i915]
>[  316.832956]  [<f818c9c2>] drm_framebuffer_remove+0x4b/0xd9 [drm]
>[  316.832979]  [<f818f508>] drm_fb_release+0x3b/0x56 [drm]
>[  316.832997]  [<f81844a1>] drm_release+0x1de/0x40d [drm]
>[  316.833003]  [<c02d4204>] __fput+0xd3/0x1a0
>[  316.833008]  [<c02d42d9>] ____fput+0x8/0xa
>[  316.833013]  [<c023d0ab>] task_work_run+0x68/0x79
>[  316.833018]  [<c022b3b7>] do_exit+0x215/0x65e
>[  316.833024]  [<c056e052>] ? _raw_spin_unlock_irq+0x22/0x26
>[  316.833028]  [<c022baa5>] do_group_exit+0x5e/0x81
>[  316.833034]  [<c0235b0a>] get_signal_to_deliver+0x4c5/0x4dd
>[  316.833039]  [<c0201dea>] do_signal+0x20/0x6bd
>[  316.833045]  [<c02803e8>] ? __audit_syscall_exit+0x32e/0x349
>[  316.833050]  [<c0209fc1>] ? syscall_trace_leave+0x2d/0x118
>[  316.833055]  [<c0242f22>] ? up_read+0x16/0x29
>[  316.833061]  [<c0570ba3>] ? __do_page_fault+0x3ab/0x3e8
>[  316.833065]  [<c02d3510>] ? vfs_write+0xea/0x122
>[  316.833070]  [<c056e3d0>] ? work_notifysig+0x11/0x31
>[  316.833074]  [<c02025b4>] do_notify_resume+0x21/0x54
>[  316.833079]  [<c056e3e8>] work_notifysig+0x29/0x31
>[  316.833082] ---[ end trace a44f2f8f2ff63710 ]---
>[  316.840509] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  316.840516] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  316.840930] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  316.840936] [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
>[  316.840942] [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
>[  316.840948] [drm:intel_update_fbc], fbc set to per-chip default
>[  316.840952] [drm:intel_update_fbc], fbc disabled per module param
>[  316.840972] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  316.840978] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  316.840982] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  316.840988] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  316.840993] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  316.840998] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  316.841004] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  316.841009] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  316.841014] [drm:intel_modeset_check_state], [CRTC:3]
>[  316.841018] [drm:intel_modeset_check_state], [CRTC:5]
>[  316.847668] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  316.847677] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  316.847681] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  316.847686] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  316.847693] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  316.847700] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  316.847705] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  316.847710] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  316.847715] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  316.847719] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  316.847726] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  316.847737] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  316.847743] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  316.847748] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  316.847754] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  316.847764] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  316.847769] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  316.847774] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  316.847778] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  316.847790] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  316.899400] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  316.899410] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  316.899418] [drm:intel_update_fbc], fbc set to per-chip default
>[  316.899421] [drm:intel_update_fbc], fbc disabled per module param
>[  316.899426] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  316.899432] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  316.899437] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  316.899443] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  316.899449] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  316.899954] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  316.899959] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  316.899964] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  316.899972] [drm:ironlake_edp_pll_on], 
>[  316.951310] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  317.003224] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  317.003231] [drm:intel_update_fbc], fbc set to per-chip default
>[  317.003235] [drm:intel_update_fbc], fbc disabled per module param
>[  317.003240] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  317.003247] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  317.003253] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  317.003264] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  317.003270] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  317.304145] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  317.304749] [drm:intel_dp_start_link_train], clock recovery OK
>[  317.304753] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  317.304757] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  317.304762] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  317.304771] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  317.304776] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  317.645059] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  317.645073] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  317.696030] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  317.696989] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  317.697028] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  317.697146] [drm:ironlake_edp_backlight_on], 
>[  317.737977] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  317.747949] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  317.747963] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  317.747969] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  317.747974] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  317.747979] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  317.747985] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  317.747991] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  317.747996] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  317.748002] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  317.748007] [drm:intel_modeset_check_state], [CRTC:3]
>[  317.748011] [drm:intel_modeset_check_state], [CRTC:5]
>[  317.748017] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  317.748023] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  317.748027] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  317.748031] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  317.748035] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  317.748040] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  317.748043] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  317.748046] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.748053] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  317.748063] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  317.748068] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  317.748072] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  317.748076] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  317.748084] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  317.748088] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  317.748093] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  317.748096] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.748102] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  317.748106] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  317.748110] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  317.748425] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  317.799851] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  317.799860] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  317.799867] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  317.799873] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  317.799878] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  317.799884] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  317.799890] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  317.799895] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  317.799900] [drm:ironlake_write_eld], ELD on pipe B
>[  317.799905] [drm:ironlake_write_eld], Audio directed to unknown port
>[  317.799908] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  317.799926] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  317.799932] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  317.851768] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  317.903665] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  317.903988] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  317.903993] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  317.904152] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  317.904156] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  317.904159] [drm:ironlake_fdi_link_train], FDI train done
>[  317.904163] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  317.904169] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  317.905397] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  317.905863] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  317.906690] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  317.907490] [drm:intel_dp_start_link_train], clock recovery OK
>[  317.907494] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  317.908567] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  317.909645] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  317.910721] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  317.911815] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  317.912914] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  317.929693] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  317.930634] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  317.930649] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  317.930661] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  317.930668] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  317.930679] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  317.930688] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  317.930694] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  317.930700] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  317.930705] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  317.930711] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  317.930716] [drm:intel_modeset_check_state], [CRTC:3]
>[  317.930720] [drm:intel_modeset_check_state], [CRTC:5]
>[  317.930752] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  317.931213] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  317.932005] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  317.932337] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  317.932348] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  317.932518] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  317.932692] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  317.932696] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  317.932703] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  317.932710] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  317.932714] [drm:intel_crt_detect], CRT not detected via hotplug
>[  317.932874] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  317.932879] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  317.932883] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  317.932886] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  317.933240] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  317.933243] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  317.933245] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  317.933248] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  317.933425] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  317.933433] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  317.933439] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  317.933737] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  317.934595] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  317.958282] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  317.982615] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  317.982619] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  317.982623] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  317.982628] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  317.982633] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  317.982638] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  317.982644] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  320.928468] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007

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