Attachment 72162 Details for Bug 58791 – Some modes can't light up dmesg

Some modes can't light up dmesg

modes_cant_lightup_dmesg (text/plain), 123.58 KB, created by shui yangwei on 2012-12-27 03:50:24 UTC

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Creator: shui yangwei

Created: 2012-12-27 03:50:24 UTC

Size: 123.58 KB

patch

obsolete

>[  100.673499] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  100.673502] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  100.673506] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  100.673512] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  100.673514] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  100.673517] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  100.673520] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  100.673522] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  100.673524] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  100.673527] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  100.673534] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  100.673721] [drm:intel_dp_link_down], 
>[  100.709332] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  100.742313] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  100.742321] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  100.742736] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  100.742742] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  100.742750] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  100.742764] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 135000KHz
>[  100.742771] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  100.742776] [drm:intel_dp_mode_fixup], DP link bw required 324000 available 518400
>[  100.742781] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  100.742786] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  100.742797] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  100.742804] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  100.742812] [drm:ironlake_edp_backlight_off], 
>[  100.943209] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  100.943215] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  100.943221] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  101.718564] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  101.735630] [drm:intel_dp_link_down], 
>[  101.787539] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  101.839080] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  101.839085] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  101.839088] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  101.839092] [drm:intel_update_fbc], fbc set to per-chip default
>[  101.839094] [drm:intel_update_fbc], fbc disabled per module param
>[  101.839100] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  101.839103] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  101.839105] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  101.839107] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  101.839110] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  101.839112] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  101.839114] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  101.839427] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  101.891360] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  101.891370] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 8192
>[  101.943271] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  101.943277] [drm:intel_update_fbc], fbc set to per-chip default
>[  101.943280] [drm:intel_update_fbc], fbc disabled per module param
>[  101.943286] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  101.943292] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  101.943297] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  101.943304] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1280x1024]
>[  101.943310] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  101.943315] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  101.943319] [drm:ironlake_write_eld], ELD on pipe A
>[  101.943324] [drm:ironlake_write_eld], Audio directed to unknown port
>[  101.943327] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  101.943345] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  101.943350] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  101.943356] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  101.995181] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  102.047091] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  102.047407] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  102.047409] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  102.047566] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  102.047568] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  102.047570] [drm:ironlake_fdi_link_train], FDI train done
>[  102.047572] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  102.047575] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  102.048797] [drm:intel_update_fbc], fbc set to per-chip default
>[  102.048799] [drm:intel_update_fbc], fbc disabled per module param
>[  102.049294] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  102.050112] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  102.050901] [drm:intel_dp_start_link_train], clock recovery OK
>[  102.050904] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  102.051976] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  102.053046] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  102.054121] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  102.055215] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  102.056321] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  102.069756] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  102.070001] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  102.070016] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  102.070024] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  102.070030] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  102.070042] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  102.070054] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  102.070062] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  102.070070] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  102.070078] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  102.070085] [drm:intel_modeset_check_state], [CRTC:3]
>[  102.070091] [drm:intel_modeset_check_state], [CRTC:5]
>[  102.070138] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  102.070641] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  102.070987] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  102.070993] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  102.070999] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  102.071009] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  102.071014] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  102.371723] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  102.371895] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  102.371899] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  102.371906] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  102.371912] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  102.371915] [drm:intel_crt_detect], CRT not detected via hotplug
>[  102.372084] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  102.372090] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  102.372093] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  102.372096] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  102.372455] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  102.372463] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  102.372469] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  102.372473] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  102.372704] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  102.372714] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  102.372721] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  102.374760] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  102.375620] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  102.399785] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  102.423432] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  102.423436] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  102.423440] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  102.423445] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  102.423451] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  102.423456] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  102.423461] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  105.371367] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  126.115596] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  126.115606] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  126.115611] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  126.115615] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  126.115619] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  126.115845] [drm:intel_dp_link_down], 
>[  126.138718] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  126.162515] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  126.162522] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  126.162936] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  126.162942] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  126.162947] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  126.162954] [drm:intel_update_fbc], fbc set to per-chip default
>[  126.162957] [drm:intel_update_fbc], fbc disabled per module param
>[  126.162978] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  126.162984] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  126.162988] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  126.162994] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  126.162999] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  126.163004] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  126.163010] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  126.163015] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  126.163020] [drm:intel_modeset_check_state], [CRTC:3]
>[  126.163024] [drm:intel_modeset_check_state], [CRTC:5]
>[  126.169801] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  126.169809] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  126.169814] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  126.169818] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  126.169826] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  126.169833] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  126.169838] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  126.169843] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  126.169848] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  126.169851] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  126.169859] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  126.169870] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  126.169876] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  126.169882] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  126.169887] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  126.169897] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  126.169902] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  126.169907] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  126.169911] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  126.169923] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  126.221408] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  126.221419] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  126.221426] [drm:intel_update_fbc], fbc set to per-chip default
>[  126.221430] [drm:intel_update_fbc], fbc disabled per module param
>[  126.221435] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  126.221440] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  126.221446] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  126.221452] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  126.221457] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  126.221962] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  126.221968] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  126.221973] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  126.221980] [drm:ironlake_edp_pll_on], 
>[  126.273319] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  126.325232] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  126.325239] [drm:intel_update_fbc], fbc set to per-chip default
>[  126.325243] [drm:intel_update_fbc], fbc disabled per module param
>[  126.325249] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  126.325255] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  126.325262] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  126.325273] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  126.325279] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  126.626144] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  126.626749] [drm:intel_dp_start_link_train], clock recovery OK
>[  126.626753] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  126.626757] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  126.626762] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  126.626771] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  126.626776] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  126.967130] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  126.967142] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  127.018038] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  127.018998] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  127.019170] [drm:ironlake_edp_backlight_on], 
>[  127.035734] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  127.059981] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  127.069964] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  127.069981] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  127.069988] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  127.069994] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  127.070001] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  127.070007] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  127.070014] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  127.070020] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  127.070027] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  127.070033] [drm:intel_modeset_check_state], [CRTC:3]
>[  127.070038] [drm:intel_modeset_check_state], [CRTC:5]
>[  127.070045] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  127.070052] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  127.070057] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  127.070062] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  127.070070] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  127.070073] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  127.070075] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  127.070077] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  127.070080] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  127.070086] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  127.070088] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  127.070091] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  127.070093] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  127.070098] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  127.070100] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  127.070102] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  127.070104] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  127.070107] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  127.070110] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  127.070111] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  127.070425] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  127.121869] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  127.121879] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  127.121886] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  127.121892] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  127.121896] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  127.121902] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  127.121908] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  127.121913] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  127.121917] [drm:ironlake_write_eld], ELD on pipe B
>[  127.121922] [drm:ironlake_write_eld], Audio directed to unknown port
>[  127.121925] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  127.121943] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  127.121947] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  127.173769] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  127.225679] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  127.225995] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  127.225997] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  127.226154] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  127.226157] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  127.226158] [drm:ironlake_fdi_link_train], FDI train done
>[  127.226160] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  127.226164] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  127.227386] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  127.227881] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  127.228704] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  127.229506] [drm:intel_dp_start_link_train], clock recovery OK
>[  127.229509] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  127.230596] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  127.231669] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  127.232748] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  127.233845] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  127.234949] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  127.251727] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  127.252578] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  127.252591] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  127.252604] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  127.252612] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  127.252619] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  127.252627] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  127.252635] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  127.252645] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  127.252660] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  127.252672] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  127.252679] [drm:intel_modeset_check_state], [CRTC:3]
>[  127.252685] [drm:intel_modeset_check_state], [CRTC:5]
>[  131.014232] [drm:i915_driver_open], 
>[  131.014291] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  131.014302] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  131.014308] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  131.014316] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  131.014323] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  131.014330] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  131.014370] [drm:i915_driver_open], 
>[  131.014733] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  131.014753] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  131.014773] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  131.014782] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  131.015101] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  131.015947] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.040138] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.063856] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.063860] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  131.064715] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.088493] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.112729] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  131.112825] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  131.112828] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  131.112899] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  131.112907] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  131.112911] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  131.112915] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  131.112923] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  131.112926] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  131.112930] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  131.112935] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  131.112939] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  131.112943] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  131.112948] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  131.112953] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  131.112957] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  131.112962] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  131.112966] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  131.112970] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  131.112974] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  131.112979] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  131.112986] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  131.112994] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  131.113002] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  131.113011] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  131.113019] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  131.113024] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  131.113028] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  131.113032] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  131.113037] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  131.113041] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  131.113045] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  131.113049] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  131.113053] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  131.113058] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  131.113062] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  131.113066] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  131.113070] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  131.113075] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  131.113079] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  131.113083] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  131.113088] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  131.113092] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  131.113096] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  131.113101] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  131.113105] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  131.113110] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  131.113114] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  131.113118] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  131.113132] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  131.209752] [drm:drm_mode_addfb], [FB:35]
>[  131.209845] [drm:drm_mode_setcrtc], [CRTC:3]
>[  131.209853] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  131.209856] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  131.209860] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  131.209863] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  131.209866] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  131.209870] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  131.209872] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  131.209875] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  131.209877] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  131.209879] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  131.209881] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  131.209883] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  131.209887] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  131.210075] [drm:intel_dp_link_down], 
>[  131.247607] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  131.280692] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  131.280699] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  131.281114] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  131.281118] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  131.281125] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  131.281137] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 135000KHz
>[  131.281143] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  131.281147] [drm:intel_dp_mode_fixup], DP link bw required 324000 available 518400
>[  131.281151] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  131.281155] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  131.281166] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  131.281172] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  131.281180] [drm:ironlake_edp_backlight_off], 
>[  131.481521] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  131.481527] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  131.481533] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  132.306945] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  132.323893] [drm:intel_dp_link_down], 
>[  132.375801] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  132.427346] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  132.427354] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  132.427360] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  132.427366] [drm:intel_update_fbc], fbc set to per-chip default
>[  132.427370] [drm:intel_update_fbc], fbc disabled per module param
>[  132.427380] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  132.427384] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  132.427388] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  132.427392] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  132.427398] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  132.427402] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  132.427405] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  132.427720] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  132.479626] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  132.479637] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 5120
>[  132.531533] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  132.531539] [drm:intel_update_fbc], fbc set to per-chip default
>[  132.531542] [drm:intel_update_fbc], fbc disabled per module param
>[  132.531548] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  132.531554] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  132.531559] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  132.531566] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1280x1024]
>[  132.531572] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  132.531577] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  132.531581] [drm:ironlake_write_eld], ELD on pipe A
>[  132.531586] [drm:ironlake_write_eld], Audio directed to unknown port
>[  132.531589] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  132.531607] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  132.531612] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  132.531618] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  132.583495] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  132.635350] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  132.635667] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  132.635671] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  132.635830] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  132.635833] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  132.635837] [drm:ironlake_fdi_link_train], FDI train done
>[  132.635840] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  132.635846] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  132.637071] [drm:intel_update_fbc], fbc set to per-chip default
>[  132.637076] [drm:intel_update_fbc], fbc disabled per module param
>[  132.637534] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  132.638352] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  132.639153] [drm:intel_dp_start_link_train], clock recovery OK
>[  132.639156] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  132.640231] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  132.641309] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  132.642387] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  132.643481] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  132.644584] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  132.658017] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  132.658242] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  132.658253] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  132.658257] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  132.658261] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  132.658268] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  132.658273] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  132.658277] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  132.658281] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  132.658286] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  132.658290] [drm:intel_modeset_check_state], [CRTC:3]
>[  132.658293] [drm:intel_modeset_check_state], [CRTC:5]
>[  132.658306] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  132.658805] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  132.659145] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  132.659151] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  132.659156] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  132.659166] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  132.659170] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  132.958985] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  132.959157] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  132.959162] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  132.959169] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  132.959174] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  132.959178] [drm:intel_crt_detect], CRT not detected via hotplug
>[  132.959359] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  132.959370] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  132.959377] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  132.959383] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  132.959771] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  132.959779] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  132.959786] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  132.959793] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  132.959973] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  132.959978] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  132.959982] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  132.960281] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  132.961137] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  132.985936] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  133.010167] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  133.010172] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  133.010175] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  133.010181] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  133.010186] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  133.010191] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  133.010196] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  135.958633] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  199.441703] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  199.441714] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  199.441719] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  199.441723] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  199.441727] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  199.441918] [drm:intel_dp_link_down], 
>[  199.466335] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  199.490090] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  199.490097] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  199.490512] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  199.490517] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  199.490523] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  199.490530] [drm:intel_update_fbc], fbc set to per-chip default
>[  199.490534] [drm:intel_update_fbc], fbc disabled per module param
>[  199.490554] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  199.490560] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  199.490564] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  199.490570] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  199.490575] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  199.490581] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  199.490586] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  199.490591] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  199.490596] [drm:intel_modeset_check_state], [CRTC:3]
>[  199.490600] [drm:intel_modeset_check_state], [CRTC:5]
>[  199.494707] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  199.494715] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  199.494720] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  199.494725] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  199.494732] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  199.494739] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  199.494744] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  199.494749] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  199.494754] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  199.494758] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  199.494765] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  199.494777] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  199.494783] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  199.494788] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  199.494793] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  199.494804] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  199.494809] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  199.494814] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  199.494818] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  199.494830] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  199.545987] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  199.545997] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  199.546005] [drm:intel_update_fbc], fbc set to per-chip default
>[  199.546009] [drm:intel_update_fbc], fbc disabled per module param
>[  199.546014] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  199.546020] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  199.546025] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  199.546032] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  199.546037] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  199.546542] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  199.546547] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  199.546552] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  199.546560] [drm:ironlake_edp_pll_on], 
>[  199.597897] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  199.649808] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  199.649815] [drm:intel_update_fbc], fbc set to per-chip default
>[  199.649819] [drm:intel_update_fbc], fbc disabled per module param
>[  199.649825] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  199.649831] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  199.649837] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  199.649849] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  199.649855] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  199.950732] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  199.951335] [drm:intel_dp_start_link_train], clock recovery OK
>[  199.951339] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  199.951343] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  199.951349] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  199.951358] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  199.951363] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  200.291708] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  200.291720] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  200.342621] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.343579] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  200.343732] [drm:ironlake_edp_backlight_on], 
>[  200.360252] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  200.384548] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  200.394535] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  200.394551] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  200.394557] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  200.394561] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  200.394567] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  200.394573] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  200.394578] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  200.394583] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  200.394589] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  200.394594] [drm:intel_modeset_check_state], [CRTC:3]
>[  200.394598] [drm:intel_modeset_check_state], [CRTC:5]
>[  200.394604] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  200.394609] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  200.394614] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  200.394618] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  200.394622] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  200.394626] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  200.394630] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  200.394634] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  200.394640] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  200.394649] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  200.394654] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  200.394658] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  200.394662] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  200.394670] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  200.394675] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  200.394679] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  200.394682] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  200.394688] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  200.394692] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  200.394695] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  200.395011] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  200.446410] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.446421] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  200.446430] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  200.446438] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  200.446443] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  200.446450] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  200.446457] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  200.446463] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  200.446469] [drm:ironlake_write_eld], ELD on pipe B
>[  200.446475] [drm:ironlake_write_eld], Audio directed to unknown port
>[  200.446479] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  200.446497] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  200.446503] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  200.498348] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.550259] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.550575] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  200.550577] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  200.550734] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  200.550736] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  200.550738] [drm:ironlake_fdi_link_train], FDI train done
>[  200.550740] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  200.550744] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  200.551965] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  200.552450] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.553271] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  200.554075] [drm:intel_dp_start_link_train], clock recovery OK
>[  200.554079] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  200.555159] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  200.556236] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  200.557315] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.558410] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  200.559515] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  200.576230] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  200.577173] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  200.577185] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  200.577199] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  200.577206] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  200.577212] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  200.577219] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  200.577225] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  200.577231] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  200.577238] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  200.577244] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  200.577250] [drm:intel_modeset_check_state], [CRTC:3]
>[  200.577260] [drm:intel_modeset_check_state], [CRTC:5]
>[  210.973575] [drm:i915_driver_open], 
>[  210.973608] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  210.973617] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  210.973620] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  210.973624] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  210.973627] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  210.973630] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  210.973648] [drm:i915_driver_open], 
>[  210.973845] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  210.973855] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  210.973865] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  210.973871] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  210.974171] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  210.975021] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  210.999185] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.023406] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.023412] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  211.024254] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.048553] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.072784] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  211.072913] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  211.072915] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  211.072977] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  211.072982] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  211.072985] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  211.072990] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  211.072998] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  211.073001] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  211.073005] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  211.073009] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  211.073014] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  211.073018] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  211.073022] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  211.073042] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  211.073049] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  211.073058] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  211.073066] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  211.073083] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  211.073092] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  211.073102] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  211.073111] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  211.073121] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  211.073131] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  211.073141] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  211.073150] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  211.073161] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  211.073171] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  211.073181] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  211.073192] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  211.073203] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  211.073214] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  211.073224] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  211.073234] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  211.073245] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  211.073256] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  211.073267] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  211.073278] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  211.073289] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  211.073299] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  211.073310] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  211.073320] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  211.073330] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  211.073341] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  211.073352] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  211.073363] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  211.073373] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  211.073383] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  211.073394] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  211.073437] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  211.272139] [drm:drm_mode_addfb], [FB:35]
>[  211.272333] [drm:drm_mode_setcrtc], [CRTC:3]
>[  211.272351] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  211.272359] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  211.272372] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  211.272377] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  211.272386] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  211.272397] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  211.272404] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  211.272410] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  211.272417] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  211.272422] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  211.272428] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  211.272434] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  211.272446] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  211.272719] [drm:intel_dp_link_down], 
>[  211.316500] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  211.349641] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  211.349648] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  211.350062] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  211.350067] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  211.350073] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  211.350086] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 131481KHz
>[  211.350092] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  211.350096] [drm:intel_dp_mode_fixup], DP link bw required 315555 available 518400
>[  211.350100] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  211.350104] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  211.350115] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  211.350122] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  211.350129] [drm:ironlake_edp_backlight_off], 
>[  211.550504] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  211.550510] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  211.550516] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  212.399310] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  212.417799] [drm:intel_dp_link_down], 
>[  212.469708] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.521246] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  212.521251] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  212.521254] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  212.521258] [drm:intel_update_fbc], fbc set to per-chip default
>[  212.521259] [drm:intel_update_fbc], fbc disabled per module param
>[  212.521266] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  212.521268] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  212.521271] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  212.521273] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  212.521276] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  212.521278] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  212.521280] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  212.521593] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  212.573529] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.573539] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 6720
>[  212.625439] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.625446] [drm:intel_update_fbc], fbc set to per-chip default
>[  212.625449] [drm:intel_update_fbc], fbc disabled per module param
>[  212.625455] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  212.625461] [drm:ironlake_check_srwm], watermark 1: display plane 44, fbc lines 3, cursor 6
>[  212.625466] [drm:ironlake_check_srwm], watermark 2: display plane 142, fbc lines 4, cursor 10
>[  212.625473] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1680x945]
>[  212.625479] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  212.625484] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  212.625488] [drm:ironlake_write_eld], ELD on pipe A
>[  212.625493] [drm:ironlake_write_eld], Audio directed to unknown port
>[  212.625497] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  212.625514] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  212.625520] [drm:ironlake_check_srwm], watermark 1: display plane 44, fbc lines 3, cursor 6
>[  212.625525] [drm:ironlake_check_srwm], watermark 2: display plane 142, fbc lines 4, cursor 10
>[  212.677350] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.729260] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.729576] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  212.729578] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  212.729735] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  212.729737] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  212.729738] [drm:ironlake_fdi_link_train], FDI train done
>[  212.729740] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  212.729744] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  212.730967] [drm:intel_update_fbc], fbc set to per-chip default
>[  212.730968] [drm:intel_update_fbc], fbc disabled per module param
>[  212.731454] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  212.732269] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  212.733058] [drm:intel_dp_start_link_train], clock recovery OK
>[  212.733061] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  212.734144] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  212.735219] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  212.736301] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  212.737398] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  212.738504] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  212.755220] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  212.756242] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  212.756259] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  212.756269] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  212.756277] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  212.756286] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  212.756301] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  212.756310] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  212.756319] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  212.756327] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  212.756337] [drm:intel_modeset_check_state], [CRTC:3]
>[  212.756343] [drm:intel_modeset_check_state], [CRTC:5]
>[  212.756373] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  212.756896] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  212.757239] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  212.757245] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  212.757250] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  212.757260] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  212.757265] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  213.057881] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  213.058052] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  213.058056] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  213.058062] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  213.058068] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  213.058072] [drm:intel_crt_detect], CRT not detected via hotplug
>[  213.058236] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  213.058241] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  213.058244] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  213.058247] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  213.058601] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  213.058622] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  213.058629] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  213.058634] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  213.058806] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  213.058810] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  213.058813] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  213.059107] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  213.059980] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.084829] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.109152] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  213.109156] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  213.109160] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  213.109165] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  213.109171] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  213.109176] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  213.109181] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  216.060527] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  532.215770] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  532.215781] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  532.215785] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  532.215789] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  532.215794] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  532.216031] [drm:intel_dp_link_down], 
>[  532.238981] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  532.267268] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  532.267277] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  532.267691] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  532.267695] [drm:ironlake_check_srwm], watermark 1: display plane 44, fbc lines 3, cursor 6
>[  532.267699] [drm:ironlake_check_srwm], watermark 2: display plane 142, fbc lines 4, cursor 10
>[  532.267703] [drm:intel_update_fbc], fbc set to per-chip default
>[  532.267704] [drm:intel_update_fbc], fbc disabled per module param
>[  532.267721] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  532.267725] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  532.267727] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  532.267730] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  532.267734] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  532.267737] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  532.267740] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  532.267744] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  532.267747] [drm:intel_modeset_check_state], [CRTC:3]
>[  532.267750] [drm:intel_modeset_check_state], [CRTC:5]
>[  532.271168] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  532.271172] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  532.271174] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  532.271177] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  532.271180] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  532.271183] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  532.271185] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  532.271187] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  532.271189] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  532.271191] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  532.271194] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  532.271200] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  532.271203] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  532.271205] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  532.271207] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  532.271213] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  532.271215] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  532.271217] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  532.271219] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  532.271226] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  532.322235] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  532.322246] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  532.322253] [drm:intel_update_fbc], fbc set to per-chip default
>[  532.322257] [drm:intel_update_fbc], fbc disabled per module param
>[  532.322262] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  532.322268] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  532.322273] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  532.322279] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  532.322285] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  532.322789] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  532.322792] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  532.322795] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  532.322801] [drm:ironlake_edp_pll_on], 
>[  532.374145] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  532.426058] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  532.426066] [drm:intel_update_fbc], fbc set to per-chip default
>[  532.426070] [drm:intel_update_fbc], fbc disabled per module param
>[  532.426075] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  532.426081] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  532.426087] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  532.426098] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  532.426104] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  532.726958] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  532.727565] [drm:intel_dp_start_link_train], clock recovery OK
>[  532.727569] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  532.727573] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  532.727578] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  532.727587] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  532.727592] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  533.067945] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  533.067957] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  533.118859] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  533.119810] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  533.119967] [drm:ironlake_edp_backlight_on], 
>[  533.136481] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  533.160724] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  533.170790] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  533.170806] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  533.170812] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  533.170816] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  533.170822] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  533.170828] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  533.170833] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  533.170839] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  533.170845] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  533.170850] [drm:intel_modeset_check_state], [CRTC:3]
>[  533.170855] [drm:intel_modeset_check_state], [CRTC:5]
>[  533.170860] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  533.170866] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  533.170870] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  533.170874] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  533.170879] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  533.170883] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  533.170887] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  533.170890] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  533.170897] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  533.170906] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  533.170911] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  533.170915] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  533.170919] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  533.170926] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  533.170931] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  533.170935] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  533.170938] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  533.170944] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  533.170948] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  533.170952] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  533.171267] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  533.222686] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  533.222695] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  533.222703] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  533.222709] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  533.222713] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  533.222719] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  533.222725] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  533.222730] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  533.222735] [drm:ironlake_write_eld], ELD on pipe B
>[  533.222740] [drm:ironlake_write_eld], Audio directed to unknown port
>[  533.222744] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  533.222761] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  533.222766] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  533.274597] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  533.326507] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  533.326823] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  533.326827] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  533.326986] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  533.326990] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  533.326993] [drm:ironlake_fdi_link_train], FDI train done
>[  533.326997] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  533.327003] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  533.328229] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  533.328694] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  533.329523] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  533.330326] [drm:intel_dp_start_link_train], clock recovery OK
>[  533.330330] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  533.331708] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  533.332858] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  533.333960] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  533.335130] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  533.336231] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  533.352945] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  533.354469] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  533.354479] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  533.354490] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  533.354496] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  533.354500] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  533.354506] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  533.354512] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  533.354518] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  533.354523] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  533.354529] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  533.354534] [drm:intel_modeset_check_state], [CRTC:3]
>[  533.354538] [drm:intel_modeset_check_state], [CRTC:5]
>[  533.354624] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  533.355095] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  533.355889] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  533.356223] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  533.356234] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  533.356406] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  533.356573] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  533.356577] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  533.356583] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  533.356590] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  533.356594] [drm:intel_crt_detect], CRT not detected via hotplug
>[  533.356818] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  533.356823] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  533.356827] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  533.356829] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  533.357185] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  533.357188] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  533.357191] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  533.357194] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  533.357352] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  533.357357] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  533.357361] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  533.357664] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  533.358513] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  533.382181] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  533.405889] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  533.405893] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  533.405897] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  533.405903] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  533.405908] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  533.405913] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  533.405918] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  536.356295] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  537.631709] [drm:i915_driver_open], 
>[  537.631741] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  537.631748] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  537.631751] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  537.631754] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  537.631758] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  537.631760] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  537.631778] [drm:i915_driver_open], 
>[  537.631976] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  537.631986] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  537.632018] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  537.632025] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  537.632325] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  537.633174] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.657293] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.680948] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.680952] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  537.681795] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.705512] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.729153] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  537.729249] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  537.729252] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  537.729312] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  537.729316] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  537.729320] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  537.729324] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  537.729332] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  537.729335] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  537.729339] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  537.729343] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  537.729348] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  537.729352] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  537.729356] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  537.729361] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  537.729365] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  537.729369] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  537.729374] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  537.729378] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  537.729382] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  537.729386] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  537.729390] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  537.729394] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  537.729398] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  537.729402] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  537.729406] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  537.729409] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  537.729413] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  537.729417] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  537.729422] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  537.729425] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  537.729429] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  537.729433] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  537.729437] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  537.729441] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  537.729445] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  537.729450] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  537.729454] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  537.729458] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  537.729462] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  537.729466] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  537.729470] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  537.729474] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  537.729478] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  537.729482] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  537.729486] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  537.729490] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  537.729494] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  537.729498] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  537.729513] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  537.925025] [drm:drm_mode_addfb], [FB:35]
>[  537.925117] [drm:drm_mode_setcrtc], [CRTC:3]
>[  537.925126] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  537.925130] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  537.925135] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  537.925138] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  537.925141] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  537.925145] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  537.925147] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  537.925150] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  537.925152] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  537.925154] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  537.925156] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  537.925157] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  537.925161] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  537.925344] [drm:intel_dp_link_down], 
>[  537.966416] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  537.999453] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  537.999460] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  537.999875] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  537.999879] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  537.999886] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  537.999898] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  537.999904] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  537.999908] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  537.999912] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  537.999916] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  537.999927] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  537.999934] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  537.999941] [drm:ironlake_edp_backlight_off], 
>[  538.200361] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  538.200368] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  538.200373] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  539.023001] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  539.040657] [drm:intel_dp_link_down], 
>[  539.092566] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  539.144110] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  539.144118] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  539.144124] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  539.144131] [drm:intel_update_fbc], fbc set to per-chip default
>[  539.144134] [drm:intel_update_fbc], fbc disabled per module param
>[  539.144144] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  539.144149] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  539.144153] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  539.144156] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  539.144162] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  539.144166] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  539.144170] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  539.144485] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  539.196388] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  539.196399] [drm:ironlake_update_plane], Writing base 00913000 00000000 0 0 7680
>[  539.248297] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  539.248303] [drm:intel_update_fbc], fbc set to per-chip default
>[  539.248307] [drm:intel_update_fbc], fbc disabled per module param
>[  539.248312] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  539.248319] [drm:ironlake_check_srwm], watermark 1: display plane 51, fbc lines 3, cursor 6
>[  539.248324] [drm:ironlake_check_srwm], watermark 2: display plane 166, fbc lines 4, cursor 10
>[  539.248331] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1920x1200]
>[  539.248337] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  539.248341] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  539.248346] [drm:ironlake_write_eld], ELD on pipe A
>[  539.248351] [drm:ironlake_write_eld], Audio directed to unknown port
>[  539.248355] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  539.248372] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  539.248378] [drm:ironlake_check_srwm], watermark 1: display plane 51, fbc lines 3, cursor 6
>[  539.248383] [drm:ironlake_check_srwm], watermark 2: display plane 166, fbc lines 4, cursor 10
>[  539.300208] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  539.352118] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  539.352435] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  539.352439] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  539.352598] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  539.352602] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  539.352605] [drm:ironlake_fdi_link_train], FDI train done
>[  539.352608] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  539.352614] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  539.353840] [drm:intel_update_fbc], fbc set to per-chip default
>[  539.353844] [drm:intel_update_fbc], fbc disabled per module param
>[  539.354306] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  539.355129] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  539.355933] [drm:intel_dp_start_link_train], clock recovery OK
>[  539.355936] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  539.357009] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  539.358096] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  539.359171] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  539.360268] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  539.361371] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  539.378140] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  539.379086] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  539.379104] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  539.379114] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  539.379126] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  539.379138] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  539.379147] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  539.379155] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  539.379164] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  539.379172] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  539.379185] [drm:intel_modeset_check_state], [CRTC:3]
>[  539.379188] [drm:intel_modeset_check_state], [CRTC:5]
>[  539.379207] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  539.379722] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  539.380064] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  539.380070] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  539.380075] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  539.380085] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  539.380090] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  539.680773] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  539.680949] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  539.680953] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  539.680960] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  539.680966] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  539.680969] [drm:intel_crt_detect], CRT not detected via hotplug
>[  539.681137] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  539.681143] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  539.681146] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  539.681149] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  539.681512] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  539.681515] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  539.681518] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  539.681523] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  539.681741] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  539.681749] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  539.681754] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  539.682055] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  539.682930] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  539.706581] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  539.730218] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  539.730222] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  539.730225] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  539.730231] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  539.730236] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  539.730241] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  539.730246] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  542.681385] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  543.501555] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  543.501564] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  543.501568] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  543.501572] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  543.501577] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  543.501805] [drm:intel_dp_link_down], 
>[  543.524801] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  543.557869] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  543.557876] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  543.558291] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  543.558297] [drm:ironlake_check_srwm], watermark 1: display plane 51, fbc lines 3, cursor 6
>[  543.558303] [drm:ironlake_check_srwm], watermark 2: display plane 166, fbc lines 4, cursor 10
>[  543.558309] [drm:intel_update_fbc], fbc set to per-chip default
>[  543.558313] [drm:intel_update_fbc], fbc disabled per module param
>[  543.558331] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  543.558337] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  543.558342] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  543.558347] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  543.558353] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  543.558358] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  543.558364] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  543.558369] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  543.558374] [drm:intel_modeset_check_state], [CRTC:3]
>[  543.558378] [drm:intel_modeset_check_state], [CRTC:5]
>[  543.565835] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  543.565844] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  543.565848] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  543.565853] [drm:drm_mode_debug_printmodeline], Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  543.565860] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  543.565867] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  543.565872] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  543.565877] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  543.565882] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  543.565886] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  543.565893] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  543.565904] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  543.565910] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  543.565915] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  543.565920] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  543.565929] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  543.565935] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  543.565940] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  543.565944] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  543.565956] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  543.617764] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  543.617773] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  543.617781] [drm:intel_update_fbc], fbc set to per-chip default
>[  543.617784] [drm:intel_update_fbc], fbc disabled per module param
>[  543.617790] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  543.617795] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  543.617801] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  543.617807] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  543.617812] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  543.618316] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  543.618320] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  543.618323] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  543.618328] [drm:ironlake_edp_pll_on], 
>[  543.669674] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  543.721584] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  543.721592] [drm:intel_update_fbc], fbc set to per-chip default
>[  543.721595] [drm:intel_update_fbc], fbc disabled per module param
>[  543.721601] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  543.721607] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  543.721614] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  543.721625] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  543.721631] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  544.022500] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  544.023101] [drm:intel_dp_start_link_train], clock recovery OK
>[  544.023105] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  544.023109] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  544.023114] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  544.023123] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  544.023128] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  544.363482] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  544.363494] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  544.414427] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  544.415378] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  544.415535] [drm:ironlake_edp_backlight_on], 
>[  544.432051] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  544.456344] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  544.466283] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  544.466300] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  544.466307] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  544.466313] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  544.466319] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  544.466326] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  544.466332] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  544.466338] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  544.466345] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  544.466351] [drm:intel_modeset_check_state], [CRTC:3]
>[  544.466356] [drm:intel_modeset_check_state], [CRTC:5]
>[  544.466363] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  544.466370] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  544.466375] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  544.466380] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  544.466385] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  544.466390] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  544.466395] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  544.466399] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  544.466408] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  544.466418] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  544.466424] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  544.466429] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  544.466434] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  544.466443] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  544.466448] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  544.466453] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  544.466457] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  544.466464] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  544.466469] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  544.466473] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  544.466790] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  544.518183] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  544.518192] [drm:ironlake_update_plane], Writing base 00049000 00000000 0 0 7680
>[  544.518201] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  544.518207] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  544.518212] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  544.518220] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  544.518226] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  544.518232] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  544.518237] [drm:ironlake_write_eld], ELD on pipe B
>[  544.518243] [drm:ironlake_write_eld], Audio directed to unknown port
>[  544.518247] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  544.518265] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  544.518270] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  544.570127] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  544.622004] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  544.622323] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  544.622328] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  544.622487] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  544.622492] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  544.622496] [drm:ironlake_fdi_link_train], FDI train done
>[  544.622500] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  544.622507] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  544.623737] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  544.624214] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  544.625032] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  544.625832] [drm:intel_dp_start_link_train], clock recovery OK
>[  544.625835] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  544.626905] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  544.627983] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  544.629060] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  544.630153] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  544.631258] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  544.648037] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  544.648932] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  544.648945] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  544.648960] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  544.648968] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  544.648975] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  544.648982] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  544.648990] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  544.649005] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  544.649018] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  544.649027] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  544.649034] [drm:intel_modeset_check_state], [CRTC:3]
>[  544.649040] [drm:intel_modeset_check_state], [CRTC:5]
>[  544.649081] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  544.649542] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  544.650334] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  544.650665] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  544.650675] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  544.650846] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  544.651018] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  544.651021] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  544.651028] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  544.651033] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  544.651036] [drm:intel_crt_detect], CRT not detected via hotplug
>[  544.651195] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  544.651200] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  544.651204] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  544.651207] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  544.651557] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  544.651561] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  544.651564] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  544.651567] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  544.651730] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  544.651734] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  544.651736] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  544.652048] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  544.652904] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  544.676573] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  544.700355] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  544.700360] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  544.700363] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  544.700368] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  544.700374] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  544.700379] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  544.700384] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  547.656810] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  608.304703] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  608.304715] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  608.304720] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  608.304725] [drm:ironlake_edp_backlight_off], 
>[  608.505142] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  608.505146] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  608.505152] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  609.332965] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  609.350369] [drm:intel_dp_link_down], 
>[  609.402277] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  609.453827] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  609.453832] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  609.453839] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  609.453854] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  609.453867] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  609.453873] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  609.453878] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  609.453884] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  609.453890] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  609.453896] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  609.453902] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  609.453907] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  609.453913] [drm:intel_modeset_check_state], [CRTC:3]
>[  609.453917] [drm:intel_modeset_check_state], [CRTC:5]
>[  609.454157] [drm:intel_dp_link_down], 
>[  609.509096] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  609.524996] [drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[  609.558076] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  609.558079] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  609.558491] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  609.558494] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  609.558499] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  609.558515] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  609.558519] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  609.558522] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  609.558527] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  609.558531] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  609.558535] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  609.558539] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  609.558543] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  609.558547] [drm:intel_modeset_check_state], [CRTC:3]
>[  609.558549] [drm:intel_modeset_check_state], [CRTC:5]
>[  609.625159] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  609.625169] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  609.625177] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  609.625184] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  609.625196] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  609.625203] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  609.925662] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  609.925839] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  609.925843] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  609.925851] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  609.925856] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  609.925859] [drm:intel_crt_detect], CRT not detected via hotplug
>[  609.926026] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  609.926031] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  609.926034] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  609.926037] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  609.926401] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  609.926407] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  609.926414] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  609.926420] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  609.926587] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  609.926591] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  609.926599] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  609.926899] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  609.927758] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  609.951709] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  609.975622] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  609.975626] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  609.975630] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  609.975635] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  609.975640] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  609.975645] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  609.975650] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  612.928275] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0000

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Attachments on bug 58791: 72162 | 73356 | 78912

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