Attachment 72932 Details for Bug 59069 – better logging v2

[patch] better logging v2

loggingv2.patch (text/plain), 56.15 KB, created by Marcin Slusarz on 2013-01-12 23:20:34 UTC

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Creator: Marcin Slusarz

Created: 2013-01-12 23:20:34 UTC

Size: 56.15 KB

patch

obsolete

>commit 8f0c91ab4e230915fc210108ea6ddc59a6e822d2
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sat Jan 12 23:56:28 2013 +0100
>
>    ttm/nouveau: dump more data when validation fails
>    
>    Conflicts:
>    	include/drm/ttm/ttm_bo_api.h
>
>commit 41e1d5fccc335a1fbda039c520176897c3d22a6b
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Fri Jan 4 17:07:14 2013 +0100
>
>    drm/nouveau: report how much memory userspace tried to "validate"
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>
>commit 57c0b63d71a747bc02a6e560d67af0a387df83fd
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Fri Jan 4 16:40:59 2013 +0100
>
>    drm/nouveau: report channel owner in pushbuf ioctl error paths
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>
>commit d35d6c4beca8a6f30a6d649ce01bf6e47ece403f
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sun Dec 9 23:00:34 2012 +0100
>
>    drm/nouveau: report channel owner in error messages
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>    Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
>    
>    Conflicts:
>    	drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
>    	drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
>    	drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
>
>commit e9452bf5f77e51de6c134caba1384525f38c473a
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sun Dec 9 15:45:21 2012 +0100
>
>    drm/nouveau: prepare for reporting channel owner
>    
>    - record channel owner process name
>    - add some helpers for accessing this information
>    - let nouveau_enum hold additional value (will be needed in the next patch)
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>    Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
>
>commit 9ebfc83a2ab1e0c80f368db99e6ee0027781232d
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sun Dec 9 15:45:20 2012 +0100
>
>    drm/nouveau: use pr_cont
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>    Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
>
>commit 2c2d2d8c7c2ff2a5921178069154cf6ae7643453
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sun Dec 9 15:45:19 2012 +0100
>
>    drm/nouveau: split fifo interrupt handler
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>    Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
>
>commit 715926dbff22877d4a54ad94a96b4439dec8dc48
>Author: Marcin Slusarz <marcin.slusarz@gmail.com>
>Date:   Sun Nov 25 23:00:57 2012 +0100
>
>    drm/nouveau: raise reporting levels of some messages
>    
>    Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
>    Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
>diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c
>index c617f04..762e4fc 100644
>--- a/drivers/gpu/drm/nouveau/core/core/client.c
>+++ b/drivers/gpu/drm/nouveau/core/core/client.c
>@@ -101,3 +101,13 @@ nouveau_client_fini(struct nouveau_client *client, bool suspend)
> 	nv_debug(client, "%s completed with %d\n", name[suspend], ret);
> 	return ret;
> }
>+
>+const char *
>+nouveau_client_name(void *obj)
>+{
>+	const char *client_name = "unknown";
>+	struct nouveau_client *client = nouveau_client(obj);
>+	if (client)
>+		client_name = client->name;
>+	return client_name;
>+}
>diff --git a/drivers/gpu/drm/nouveau/core/core/enum.c b/drivers/gpu/drm/nouveau/core/core/enum.c
>index 7cc7133..dd43479 100644
>--- a/drivers/gpu/drm/nouveau/core/core/enum.c
>+++ b/drivers/gpu/drm/nouveau/core/core/enum.c
>@@ -40,14 +40,15 @@ nouveau_enum_find(const struct nouveau_enum *en, u32 value)
> 	return NULL;
> }
> 
>-void
>+const struct nouveau_enum *
> nouveau_enum_print(const struct nouveau_enum *en, u32 value)
> {
> 	en = nouveau_enum_find(en, value);
> 	if (en)
>-		printk("%s", en->name);
>+		pr_cont("%s", en->name);
> 	else
>-		printk("(unknown enum 0x%08x)", value);
>+		pr_cont("(unknown enum 0x%08x)", value);
>+	return en;
> }
> 
> void
>@@ -55,7 +56,7 @@ nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
> {
> 	while (bf->name) {
> 		if (value & bf->mask) {
>-			printk(" %s", bf->name);
>+			pr_cont(" %s", bf->name);
> 			value &= ~bf->mask;
> 		}
> 
>@@ -63,5 +64,5 @@ nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
> 	}
> 
> 	if (value)
>-		printk(" (unknown bits 0x%08x)", value);
>+		pr_cont(" (unknown bits 0x%08x)", value);
> }
>diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
>index 4df6da0..87b79d0 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/enum.h>
> #include <core/class.h>
>@@ -123,8 +124,9 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00000040) {
> 		nv_error(priv, "DISPATCH_ERROR [");
> 		nouveau_enum_print(nva3_copy_isr_error_name, ssta);
>-		printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
>-		       chid, inst << 12, subc, mthd, data);
>+		pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
>+		       chid, inst << 12, nouveau_client_name(engctx), subc,
>+		       mthd, data);
> 		nv_wr32(priv, 0x104004, 0x00000040);
> 		stat &= ~0x00000040;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
>index 1d85e5b..cf87288 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/enum.h>
> #include <core/class.h>
>@@ -150,8 +151,9 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
> 	if (stat) {
> 		nv_error(priv, "");
> 		nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
>-		printk(" ch %d [0x%010llx] mthd 0x%04x data 0x%08x\n",
>-		       chid, (u64)inst << 12, mthd, data);
>+		pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
>+		       chid, (u64)inst << 12, nouveau_client_name(engctx),
>+		       mthd, data);
> 	}
> 
> 	nv_wr32(priv, 0x102130, stat);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
>index 9e3876c..6e21b35 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/enum.h>
> #include <core/class.h>
>@@ -123,8 +124,9 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00000040) {
> 		nv_error(priv, "DISPATCH_ERROR [");
> 		nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
>-		printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
>-		       chid, (u64)inst << 12, subc, mthd, data);
>+		pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
>+		       chid, (u64)inst << 12, nouveau_client_name(engctx),
>+		       subc, mthd, data);
> 		nv_wr32(priv, 0x087004, 0x00000040);
> 		stat &= ~0x00000040;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
>index bbb43c6..0bf45d1 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/object.h>
> #include <core/handle.h>
> 
>@@ -147,6 +148,20 @@ nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
> 	return -1;
> }
> 
>+const char *
>+nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
>+{
>+	struct nouveau_fifo_chan *chan = NULL;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&fifo->lock, flags);
>+	if (chid >= fifo->min && chid <= fifo->max)
>+		chan = (void *)fifo->channel[chid];
>+	spin_unlock_irqrestore(&fifo->lock, flags);
>+
>+	return nouveau_client_name(chan);
>+}
>+
> void
> nouveau_fifo_destroy(struct nouveau_fifo *priv)
> {
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
>index ea76e3e..ba3a9df 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
>@@ -398,6 +398,98 @@ out:
> 	return handled;
> }
> 
>+static void
>+nv04_fifo_cache_error(struct nouveau_device *device,
>+		struct nv04_fifo_priv *priv, u32 chid, u32 get)
>+{
>+	u32 mthd, data;
>+	int ptr;
>+
>+	/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my
>+	 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests
>+	 * show that it wraps around to the start at GET=0x800.. No clue as to
>+	 * why..
>+	 */
>+	ptr = (get & 0x7ff) >> 2;
>+
>+	if (device->card_type < NV_40) {
>+		mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr));
>+		data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr));
>+	} else {
>+		mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr));
>+		data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr));
>+	}
>+
>+	if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
>+		const char *client_name =
>+			nouveau_client_name_for_fifo_chid(&priv->base, chid);
>+		nv_error(priv,
>+			 "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
>+			 chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc,
>+			 data);
>+	}
>+
>+	nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
>+	nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
>+
>+	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
>+		nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1);
>+	nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
>+	nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
>+		nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1);
>+	nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0);
>+
>+	nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH,
>+		nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
>+	nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
>+}
>+
>+static void
>+nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
>+		u32 chid)
>+{
>+	const char *client_name;
>+	u32 dma_get = nv_rd32(priv, 0x003244);
>+	u32 dma_put = nv_rd32(priv, 0x003240);
>+	u32 push = nv_rd32(priv, 0x003220);
>+	u32 state = nv_rd32(priv, 0x003228);
>+
>+	client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid);
>+
>+	if (device->card_type == NV_50) {
>+		u32 ho_get = nv_rd32(priv, 0x003328);
>+		u32 ho_put = nv_rd32(priv, 0x003320);
>+		u32 ib_get = nv_rd32(priv, 0x003334);
>+		u32 ib_put = nv_rd32(priv, 0x003330);
>+
>+		nv_error(priv,
>+			 "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
>+			 chid, client_name, ho_get, dma_get, ho_put, dma_put,
>+			 ib_get, ib_put, state, nv_dma_state_err(state), push);
>+
>+		/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
>+		nv_wr32(priv, 0x003364, 0x00000000);
>+		if (dma_get != dma_put || ho_get != ho_put) {
>+			nv_wr32(priv, 0x003244, dma_put);
>+			nv_wr32(priv, 0x003328, ho_put);
>+		} else
>+		if (ib_get != ib_put)
>+			nv_wr32(priv, 0x003334, ib_put);
>+	} else {
>+		nv_error(priv,
>+			 "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
>+			 chid, client_name, dma_get, dma_put, state,
>+			 nv_dma_state_err(state), push);
>+
>+		if (dma_get != dma_put)
>+			nv_wr32(priv, 0x003244, dma_put);
>+	}
>+
>+	nv_wr32(priv, 0x003228, 0x00000000);
>+	nv_wr32(priv, 0x003220, 0x00000001);
>+	nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
>+}
>+
> void
> nv04_fifo_intr(struct nouveau_subdev *subdev)
> {
>@@ -416,96 +508,12 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
> 		get  = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);
> 
> 		if (status & NV_PFIFO_INTR_CACHE_ERROR) {
>-			uint32_t mthd, data;
>-			int ptr;
>-
>-			/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
>-			 * wrapping on my G80 chips, but CACHE1 isn't big
>-			 * enough for this much data.. Tests show that it
>-			 * wraps around to the start at GET=0x800.. No clue
>-			 * as to why..
>-			 */
>-			ptr = (get & 0x7ff) >> 2;
>-
>-			if (device->card_type < NV_40) {
>-				mthd = nv_rd32(priv,
>-					NV04_PFIFO_CACHE1_METHOD(ptr));
>-				data = nv_rd32(priv,
>-					NV04_PFIFO_CACHE1_DATA(ptr));
>-			} else {
>-				mthd = nv_rd32(priv,
>-					NV40_PFIFO_CACHE1_METHOD(ptr));
>-				data = nv_rd32(priv,
>-					NV40_PFIFO_CACHE1_DATA(ptr));
>-			}
>-
>-			if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
>-				nv_info(priv, "CACHE_ERROR - Ch %d/%d "
>-					      "Mthd 0x%04x Data 0x%08x\n",
>-					chid, (mthd >> 13) & 7, mthd & 0x1ffc,
>-					data);
>-			}
>-
>-			nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
>-			nv_wr32(priv, NV03_PFIFO_INTR_0,
>-						NV_PFIFO_INTR_CACHE_ERROR);
>-
>-			nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
>-				nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1);
>-			nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
>-			nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
>-				nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1);
>-			nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0);
>-
>-			nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH,
>-				nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
>-			nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
>-
>+			nv04_fifo_cache_error(device, priv, chid, get);
> 			status &= ~NV_PFIFO_INTR_CACHE_ERROR;
> 		}
> 
> 		if (status & NV_PFIFO_INTR_DMA_PUSHER) {
>-			u32 dma_get = nv_rd32(priv, 0x003244);
>-			u32 dma_put = nv_rd32(priv, 0x003240);
>-			u32 push = nv_rd32(priv, 0x003220);
>-			u32 state = nv_rd32(priv, 0x003228);
>-
>-			if (device->card_type == NV_50) {
>-				u32 ho_get = nv_rd32(priv, 0x003328);
>-				u32 ho_put = nv_rd32(priv, 0x003320);
>-				u32 ib_get = nv_rd32(priv, 0x003334);
>-				u32 ib_put = nv_rd32(priv, 0x003330);
>-
>-				nv_info(priv, "DMA_PUSHER - Ch %d Get 0x%02x%08x "
>-				     "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
>-				     "State 0x%08x (err: %s) Push 0x%08x\n",
>-					chid, ho_get, dma_get, ho_put,
>-					dma_put, ib_get, ib_put, state,
>-					nv_dma_state_err(state),
>-					push);
>-
>-				/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
>-				nv_wr32(priv, 0x003364, 0x00000000);
>-				if (dma_get != dma_put || ho_get != ho_put) {
>-					nv_wr32(priv, 0x003244, dma_put);
>-					nv_wr32(priv, 0x003328, ho_put);
>-				} else
>-				if (ib_get != ib_put) {
>-					nv_wr32(priv, 0x003334, ib_put);
>-				}
>-			} else {
>-				nv_info(priv, "DMA_PUSHER - Ch %d Get 0x%08x "
>-					     "Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n",
>-					chid, dma_get, dma_put, state,
>-					nv_dma_state_err(state), push);
>-
>-				if (dma_get != dma_put)
>-					nv_wr32(priv, 0x003244, dma_put);
>-			}
>-
>-			nv_wr32(priv, 0x003228, 0x00000000);
>-			nv_wr32(priv, 0x003220, 0x00000001);
>-			nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
>+			nv04_fifo_dma_pusher(device, priv, chid);
> 			status &= ~NV_PFIFO_INTR_DMA_PUSHER;
> 		}
> 
>@@ -532,7 +540,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
> 		}
> 
> 		if (status) {
>-			nv_info(priv, "unknown intr 0x%08x, ch %d\n",
>+			nv_warn(priv, "unknown intr 0x%08x, ch %d\n",
> 				status, chid);
> 			nv_wr32(priv, NV03_PFIFO_INTR_0, status);
> 			status = 0;
>@@ -542,7 +550,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev)
> 	}
> 
> 	if (status) {
>-		nv_info(priv, "still angry after %d spins, halt\n", cnt);
>+		nv_error(priv, "still angry after %d spins, halt\n", cnt);
> 		nv_wr32(priv, 0x002140, 0);
> 		nv_wr32(priv, 0x000140, 0);
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
>index 536e763..6473566 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
>@@ -137,7 +137,8 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
> 	/* do the kickoff... */
> 	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
> 	if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
>-		nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
>+		nv_error(priv, "channel %d [%s] unload timeout\n",
>+			 chan->base.chid, nouveau_client_name(chan));
> 		if (suspend)
> 			ret = -EBUSY;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
>index b4fd26d..8d60e9d 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
>@@ -108,7 +108,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
> 	done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
> 	nv_wr32(priv, 0x002520, save);
> 	if (!done) {
>-		nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
>+		nv_error(priv, "channel %d [%s] unload timeout\n",
>+			 chan->base.chid, nouveau_client_name(chan));
> 		if (suspend)
> 			return -EBUSY;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
>index 6f21be6..b243937 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
>@@ -147,7 +147,8 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
> 
> 	nv_wr32(priv, 0x002634, chan->base.chid);
> 	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
>-		nv_error(priv, "channel %d kick timeout\n", chan->base.chid);
>+		nv_error(priv, "channel %d [%s] kick timeout\n",
>+			 chan->base.chid, nouveau_client_name(chan));
> 		if (suspend)
> 			return -EBUSY;
> 	}
>@@ -325,17 +326,17 @@ nvc0_fifo_cclass = {
>  ******************************************************************************/
> 
> static const struct nouveau_enum nvc0_fifo_fault_unit[] = {
>-	{ 0x00, "PGRAPH" },
>+	{ 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
> 	{ 0x03, "PEEPHOLE" },
> 	{ 0x04, "BAR1" },
> 	{ 0x05, "BAR3" },
>-	{ 0x07, "PFIFO" },
>-	{ 0x10, "PBSP" },
>-	{ 0x11, "PPPP" },
>+	{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
>+	{ 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
>+	{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
> 	{ 0x13, "PCOUNTER" },
>-	{ 0x14, "PVP" },
>-	{ 0x15, "PCOPY0" },
>-	{ 0x16, "PCOPY1" },
>+	{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
>+	{ 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
>+	{ 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
> 	{ 0x17, "PDAEMON" },
> 	{}
> };
>@@ -394,6 +395,9 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
> 	u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
> 	u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
> 	u32 client = (stat & 0x00001f00) >> 8;
>+	const struct nouveau_enum *en;
>+	struct nouveau_engine *engine;
>+	struct nouveau_object *engctx = NULL;
> 
> 	switch (unit) {
> 	case 3: /* PEEPHOLE */
>@@ -412,16 +416,26 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
> 	nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
> 		 "write" : "read", (u64)vahi << 32 | valo);
> 	nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
>-	printk("] from ");
>-	nouveau_enum_print(nvc0_fifo_fault_unit, unit);
>+	pr_cont("] from ");
>+	en = nouveau_enum_print(nvc0_fifo_fault_unit, unit);
> 	if (stat & 0x00000040) {
>-		printk("/");
>+		pr_cont("/");
> 		nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
> 	} else {
>-		printk("/GPC%d/", (stat & 0x1f000000) >> 24);
>+		pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
> 		nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
> 	}
>-	printk(" on channel 0x%010llx\n", (u64)inst << 12);
>+
>+	if (en && en->data2) {
>+		engine = nouveau_engine(priv, en->data2);
>+		if (engine)
>+			engctx = nouveau_engctx_get(engine, inst);
>+
>+	}
>+	pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
>+			nouveau_client_name(engctx));
>+
>+	nouveau_engctx_put(engctx);
> }
> 
> static int
>@@ -476,10 +490,12 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
> 	if (show) {
> 		nv_error(priv, "SUBFIFO%d:", unit);
> 		nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
>-		printk("\n");
>-		nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
>-			       "data 0x%08x\n",
>-			 unit, chid, subc, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
>+			 unit, chid,
>+			 nouveau_client_name_for_fifo_chid(&priv->base, chid),
>+			 subc, mthd, data);
> 	}
> 
> 	nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
>@@ -494,7 +510,7 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev)
> 	u32 stat = nv_rd32(priv, 0x002100) & mask;
> 
> 	if (stat & 0x00000100) {
>-		nv_info(priv, "unknown status 0x00000100\n");
>+		nv_warn(priv, "unknown status 0x00000100\n");
> 		nv_wr32(priv, 0x002100, 0x00000100);
> 		stat &= ~0x00000100;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
>index 36e81b6..e0c757e 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
>@@ -182,7 +182,8 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
> 
> 	nv_wr32(priv, 0x002634, chan->base.chid);
> 	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
>-		nv_error(priv, "channel %d kick timeout\n", chan->base.chid);
>+		nv_error(priv, "channel %d [%s] kick timeout\n",
>+			 chan->base.chid, nouveau_client_name(chan));
> 		if (suspend)
> 			return -EBUSY;
> 	}
>@@ -407,20 +408,34 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
> 	u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
> 	u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
> 	u32 client = (stat & 0x00001f00) >> 8;
>+	const struct nouveau_enum *en;
>+	struct nouveau_engine *engine;
>+	struct nouveau_object *engctx = NULL;
> 
> 	nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
> 		       "write" : "read", (u64)vahi << 32 | valo);
> 	nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
>-	printk("] from ");
>-	nouveau_enum_print(nve0_fifo_fault_unit, unit);
>+	pr_cont("] from ");
>+	en = nouveau_enum_print(nve0_fifo_fault_unit, unit);
> 	if (stat & 0x00000040) {
>-		printk("/");
>+		pr_cont("/");
> 		nouveau_enum_print(nve0_fifo_fault_hubclient, client);
> 	} else {
>-		printk("/GPC%d/", (stat & 0x1f000000) >> 24);
>+		pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
> 		nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
> 	}
>-	printk(" on channel 0x%010llx\n", (u64)inst << 12);
>+
>+	if (en && en->data2) {
>+		engine = nouveau_engine(priv, en->data2);
>+		if (engine)
>+			engctx = nouveau_engctx_get(engine, inst);
>+
>+	}
>+
>+	pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
>+			nouveau_client_name(engctx));
>+
>+	nouveau_engctx_put(engctx);
> }
> 
> static int
>@@ -475,10 +490,12 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
> 	if (show) {
> 		nv_error(priv, "SUBFIFO%d:", unit);
> 		nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
>-		printk("\n");
>-		nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
>-			       "data 0x%08x\n",
>-			 unit, chid, subc, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
>+			 unit, chid,
>+			 nouveau_client_name_for_fifo_chid(&priv->base, chid),
>+			 subc, mthd, data);
> 	}
> 
> 	nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
>index 6185282..9a37453 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
>@@ -22,6 +22,7 @@
>  * DEALINGS IN THE SOFTWARE.
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/class.h>
> #include <core/handle.h>
>@@ -1299,14 +1300,15 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
> 	if (show) {
> 		nv_error(priv, "");
> 		nouveau_bitfield_print(nv04_graph_intr_name, show);
>-		printk(" nsource:");
>+		pr_cont(" nsource:");
> 		nouveau_bitfield_print(nv04_graph_nsource, nsource);
>-		printk(" nstatus:");
>+		pr_cont(" nstatus:");
> 		nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
>-		printk("\n");
>-		nv_error(priv, "ch %d/%d class 0x%04x "
>-			       "mthd 0x%04x data 0x%08x\n",
>-			 chid, subc, class, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, nouveau_client_name(chan), subc, class, mthd,
>+			 data);
> 	}
> 
> 	nouveau_namedb_put(handle);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
>index 92521c8..be252ec 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
>@@ -22,6 +22,7 @@
>  * DEALINGS IN THE SOFTWARE.
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/class.h>
> #include <core/handle.h>
>@@ -1195,14 +1196,15 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
> 	if (show) {
> 		nv_error(priv, "");
> 		nouveau_bitfield_print(nv10_graph_intr_name, show);
>-		printk(" nsource:");
>+		pr_cont(" nsource:");
> 		nouveau_bitfield_print(nv04_graph_nsource, nsource);
>-		printk(" nstatus:");
>+		pr_cont(" nstatus:");
> 		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
>-		printk("\n");
>-		nv_error(priv, "ch %d/%d class 0x%04x "
>-			       "mthd 0x%04x data 0x%08x\n",
>-			 chid, subc, class, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, nouveau_client_name(chan), subc, class, mthd,
>+			 data);
> 	}
> 
> 	nouveau_namedb_put(handle);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
>index 8f3f619..7238849 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
>@@ -1,3 +1,4 @@
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/class.h>
> #include <core/engctx.h>
>@@ -224,15 +225,17 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
> 	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
> 
> 	if (show) {
>-		nv_info(priv, "");
>+		nv_error(priv, "");
> 		nouveau_bitfield_print(nv10_graph_intr_name, show);
>-		printk(" nsource:");
>+		pr_cont(" nsource:");
> 		nouveau_bitfield_print(nv04_graph_nsource, nsource);
>-		printk(" nstatus:");
>+		pr_cont(" nstatus:");
> 		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
>-		printk("\n");
>-		nv_info(priv, "ch %d/%d class 0x%04x mthd 0x%04x data 0x%08x\n",
>-			chid, subc, class, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, nouveau_client_name(engctx), subc, class, mthd,
>+			 data);
> 	}
> 
> 	nouveau_engctx_put(engctx);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
>index cc6574e..a96bc26 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/class.h>
> #include <core/handle.h>
>@@ -293,16 +294,17 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
> 	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
> 
> 	if (show) {
>-		nv_info(priv, "");
>+		nv_error(priv, "");
> 		nouveau_bitfield_print(nv10_graph_intr_name, show);
>-		printk(" nsource:");
>+		pr_cont(" nsource:");
> 		nouveau_bitfield_print(nv04_graph_nsource, nsource);
>-		printk(" nstatus:");
>+		pr_cont(" nstatus:");
> 		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
>-		printk("\n");
>-		nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x "
>-			       "mthd 0x%04x data 0x%08x\n",
>-			 chid, inst << 4, subc, class, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, inst << 4, nouveau_client_name(engctx), subc,
>+			 class, mthd, data);
> 	}
> 
> 	nouveau_engctx_put(engctx);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
>index ab3b9dc..5fbebb4 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
>@@ -24,6 +24,7 @@
> 
> #include <core/os.h>
> #include <core/class.h>
>+#include <core/client.h>
> #include <core/handle.h>
> #include <core/engctx.h>
> #include <core/enum.h>
>@@ -350,7 +351,7 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
> 			nv_error(priv, "TRAP_MP_EXEC - "
> 					"TP %d MP %d: ", tpid, i);
> 			nouveau_enum_print(nv50_mp_exec_error_names, status);
>-			printk(" at %06x warp %d, opcode %08x %08x\n",
>+			pr_cont(" at %06x warp %d, opcode %08x %08x\n",
> 					pc&0xffffff, pc >> 24,
> 					oplow, ophigh);
> 		}
>@@ -453,18 +454,18 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
> 		}
> 		if (ustatus) {
> 			if (display)
>-				nv_info(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
>+				nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
> 		}
> 		nv_wr32(priv, ustatus_addr, 0xc0000000);
> 	}
> 
> 	if (!tps && display)
>-		nv_info(priv, "%s - No TPs claiming errors?\n", name);
>+		nv_warn(priv, "%s - No TPs claiming errors?\n", name);
> }
> 
> static int
> nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
>-			int chid, u64 inst)
>+			int chid, u64 inst, struct nouveau_object *engctx)
> {
> 	u32 status = nv_rd32(priv, 0x400108);
> 	u32 ustatus;
>@@ -497,12 +498,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 
> 			nv_error(priv, "TRAP DISPATCH_FAULT\n");
> 			if (display && (addr & 0x80000000)) {
>-				nv_error(priv, "ch %d [0x%010llx] "
>-					     "subc %d class 0x%04x mthd 0x%04x "
>-					     "data 0x%08x%08x "
>-					     "400808 0x%08x 400848 0x%08x\n",
>-					chid, inst, subc, class, mthd, datah,
>-					datal, addr, r848);
>+				nv_error(priv,
>+					 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
>+					 chid, inst,
>+					 nouveau_client_name(engctx), subc,
>+					 class, mthd, datah, datal, addr, r848);
> 			} else
> 			if (display) {
> 				nv_error(priv, "no stuck command?\n");
>@@ -523,11 +523,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 
> 			nv_error(priv, "TRAP DISPATCH_QUERY\n");
> 			if (display && (addr & 0x80000000)) {
>-				nv_error(priv, "ch %d [0x%010llx] "
>-					     "subc %d class 0x%04x mthd 0x%04x "
>-					     "data 0x%08x 40084c 0x%08x\n",
>-					chid, inst, subc, class, mthd,
>-					data, addr);
>+				nv_error(priv,
>+					 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
>+					 chid, inst,
>+					 nouveau_client_name(engctx), subc,
>+					 class, mthd, data, addr);
> 			} else
> 			if (display) {
> 				nv_error(priv, "no stuck command?\n");
>@@ -555,7 +555,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 		if (display) {
> 			nv_error(priv, "TRAP_M2MF");
> 			nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
>-			printk("\n");
>+			pr_cont("\n");
> 			nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
> 				nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
> 				nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
>@@ -576,7 +576,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 		if (display) {
> 			nv_error(priv, "TRAP_VFETCH");
> 			nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
>-			printk("\n");
>+			pr_cont("\n");
> 			nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
> 				nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
> 				nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
>@@ -593,7 +593,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 		if (display) {
> 			nv_error(priv, "TRAP_STRMOUT");
> 			nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
>-			printk("\n");
>+			pr_cont("\n");
> 			nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
> 				nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
> 				nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
>@@ -614,7 +614,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
> 		if (display) {
> 			nv_error(priv, "TRAP_CCACHE");
> 			nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
>-			printk("\n");
>+			pr_cont("\n");
> 			nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
> 				     " %08x %08x %08x\n",
> 				nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
>@@ -706,11 +706,12 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
> 		u32 ecode = nv_rd32(priv, 0x400110);
> 		nv_error(priv, "DATA_ERROR ");
> 		nouveau_enum_print(nv50_data_error_names, ecode);
>-		printk("\n");
>+		pr_cont("\n");
> 	}
> 
> 	if (stat & 0x00200000) {
>-		if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12))
>+		if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
>+				engctx))
> 			show &= ~0x00200000;
> 	}
> 
>@@ -718,12 +719,13 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
> 	nv_wr32(priv, 0x400500, 0x00010001);
> 
> 	if (show) {
>-		nv_info(priv, "");
>+		nv_error(priv, "");
> 		nouveau_bitfield_print(nv50_graph_intr_name, show);
>-		printk("\n");
>-		nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x "
>-			       "mthd 0x%04x data 0x%08x\n",
>-			 chid, (u64)inst << 12, subc, class, mthd, data);
>+		pr_cont("\n");
>+		nv_error(priv,
>+			 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, (u64)inst << 12, nouveau_client_name(engctx),
>+			 subc, class, mthd, data);
> 		nv50_fb_trap(nouveau_fb(priv), 1);
> 	}
> 
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
>index c62f2d0..4c5b085 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
>@@ -433,10 +433,10 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00000010) {
> 		handle = nouveau_handle_get_class(engctx, class);
> 		if (!handle || nv_call(handle->object, mthd, data)) {
>-			nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx] "
>-				     "subc %d class 0x%04x mthd 0x%04x "
>-				     "data 0x%08x\n",
>-				 chid, inst << 12, subc, class, mthd, data);
>+			nv_error(priv,
>+				 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+				 chid, inst << 12, nouveau_client_name(engctx),
>+				 subc, class, mthd, data);
> 		}
> 		nouveau_handle_put(handle);
> 		nv_wr32(priv, 0x400100, 0x00000010);
>@@ -444,9 +444,10 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
> 	}
> 
> 	if (stat & 0x00000020) {
>-		nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
>-			     "class 0x%04x mthd 0x%04x data 0x%08x\n",
>-			chid, inst << 12, subc, class, mthd, data);
>+		nv_error(priv,
>+			 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, inst << 12, nouveau_client_name(engctx), subc,
>+			 class, mthd, data);
> 		nv_wr32(priv, 0x400100, 0x00000020);
> 		stat &= ~0x00000020;
> 	}
>@@ -454,15 +455,16 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00100000) {
> 		nv_error(priv, "DATA_ERROR [");
> 		nouveau_enum_print(nv50_data_error_names, code);
>-		printk("] ch %d [0x%010llx] subc %d class 0x%04x "
>-		       "mthd 0x%04x data 0x%08x\n",
>-		       chid, inst << 12, subc, class, mthd, data);
>+		pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			chid, inst << 12, nouveau_client_name(engctx), subc,
>+			class, mthd, data);
> 		nv_wr32(priv, 0x400100, 0x00100000);
> 		stat &= ~0x00100000;
> 	}
> 
> 	if (stat & 0x00200000) {
>-		nv_error(priv, "TRAP ch %d [0x%010llx]\n", chid, inst << 12);
>+		nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
>+			 nouveau_client_name(engctx));
> 		nvc0_graph_trap_intr(priv);
> 		nv_wr32(priv, 0x400100, 0x00200000);
> 		stat &= ~0x00200000;
>@@ -814,7 +816,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
> 		nv_wr32(priv, 0x41a100, 0x00000002);
> 		nv_wr32(priv, 0x409100, 0x00000002);
> 		if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
>-			nv_info(priv, "0x409800 wait failed\n");
>+			nv_warn(priv, "0x409800 wait failed\n");
> 
> 		nv_wr32(priv, 0x409840, 0xffffffff);
> 		nv_wr32(priv, 0x409500, 0x7fffffff);
>diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
>index 539d4c7..9265b70 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
>@@ -78,15 +78,16 @@ nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
> }
> 
> static void
>-nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
>+nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst,
>+		struct nouveau_object *engctx)
> {
> 	u32 trap = nv_rd32(priv, 0x400108);
> 	int rop;
> 
> 	if (trap & 0x00000001) {
> 		u32 stat = nv_rd32(priv, 0x404000);
>-		nv_error(priv, "DISPATCH ch %d [0x%010llx] 0x%08x\n",
>-			 chid, inst, stat);
>+		nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
>+			 chid, inst, nouveau_client_name(engctx), stat);
> 		nv_wr32(priv, 0x404000, 0xc0000000);
> 		nv_wr32(priv, 0x400108, 0x00000001);
> 		trap &= ~0x00000001;
>@@ -94,8 +95,8 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
> 
> 	if (trap & 0x00000010) {
> 		u32 stat = nv_rd32(priv, 0x405840);
>-		nv_error(priv, "SHADER ch %d [0x%010llx] 0x%08x\n",
>-			 chid, inst, stat);
>+		nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
>+			 chid, inst, nouveau_client_name(engctx), stat);
> 		nv_wr32(priv, 0x405840, 0xc0000000);
> 		nv_wr32(priv, 0x400108, 0x00000010);
> 		trap &= ~0x00000010;
>@@ -105,8 +106,10 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
> 		for (rop = 0; rop < priv->rop_nr; rop++) {
> 			u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
> 			u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
>-			nv_error(priv, "ROP%d ch %d [0x%010llx] 0x%08x 0x%08x\n",
>-				 rop, chid, inst, statz, statc);
>+			nv_error(priv,
>+				 "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
>+				 rop, chid, inst, nouveau_client_name(engctx),
>+				 statz, statc);
> 			nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
> 			nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
> 		}
>@@ -115,8 +118,8 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
> 	}
> 
> 	if (trap) {
>-		nv_error(priv, "TRAP ch %d [0x%010llx] 0x%08x\n",
>-			 chid, inst, trap);
>+		nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
>+			 chid, inst, nouveau_client_name(engctx), trap);
> 		nv_wr32(priv, 0x400108, trap);
> 	}
> }
>@@ -145,10 +148,10 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00000010) {
> 		handle = nouveau_handle_get_class(engctx, class);
> 		if (!handle || nv_call(handle->object, mthd, data)) {
>-			nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx] "
>-				     "subc %d class 0x%04x mthd 0x%04x "
>-				     "data 0x%08x\n",
>-				 chid, inst, subc, class, mthd, data);
>+			nv_error(priv,
>+				 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+				 chid, inst, nouveau_client_name(engctx), subc,
>+				 class, mthd, data);
> 		}
> 		nouveau_handle_put(handle);
> 		nv_wr32(priv, 0x400100, 0x00000010);
>@@ -156,9 +159,10 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
> 	}
> 
> 	if (stat & 0x00000020) {
>-		nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
>-			     "class 0x%04x mthd 0x%04x data 0x%08x\n",
>-			 chid, inst, subc, class, mthd, data);
>+		nv_error(priv,
>+			 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			 chid, inst, nouveau_client_name(engctx), subc, class,
>+			 mthd, data);
> 		nv_wr32(priv, 0x400100, 0x00000020);
> 		stat &= ~0x00000020;
> 	}
>@@ -166,15 +170,15 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
> 	if (stat & 0x00100000) {
> 		nv_error(priv, "DATA_ERROR [");
> 		nouveau_enum_print(nv50_data_error_names, code);
>-		printk("] ch %d [0x%010llx] subc %d class 0x%04x "
>-		       "mthd 0x%04x data 0x%08x\n",
>-		       chid, inst, subc, class, mthd, data);
>+		pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
>+			chid, inst, nouveau_client_name(engctx), subc, class,
>+			mthd, data);
> 		nv_wr32(priv, 0x400100, 0x00100000);
> 		stat &= ~0x00100000;
> 	}
> 
> 	if (stat & 0x00200000) {
>-		nve0_graph_trap_isr(priv, chid, inst);
>+		nve0_graph_trap_isr(priv, chid, inst, engctx);
> 		nv_wr32(priv, 0x400100, 0x00200000);
> 		stat &= ~0x00200000;
> 	}
>diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
>index 1f394a2..1274c77 100644
>--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
>+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
>@@ -22,6 +22,7 @@
>  * Authors: Ben Skeggs
>  */
> 
>+#include <core/client.h>
> #include <core/os.h>
> #include <core/class.h>
> #include <core/engctx.h>
>@@ -231,8 +232,10 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
> 	nv_wr32(priv, 0x00b230, 0x00000001);
> 
> 	if (show) {
>-		nv_error(priv, "ch %d [0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
>-			 chid, inst << 4, stat, type, mthd, data);
>+		nv_error(priv,
>+			 "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
>+			 chid, inst << 4, nouveau_client_name(engctx), stat,
>+			 type, mthd, data);
> 	}
> 
> 	nouveau_engctx_put(engctx);
>diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h
>index 0193532..b8d0457 100644
>--- a/drivers/gpu/drm/nouveau/core/include/core/client.h
>+++ b/drivers/gpu/drm/nouveau/core/include/core/client.h
>@@ -7,7 +7,7 @@ struct nouveau_client {
> 	struct nouveau_namedb base;
> 	struct nouveau_handle *root;
> 	struct nouveau_object *device;
>-	char name[16];
>+	char name[32];
> 	u32 debug;
> 	struct nouveau_vm *vm;
> };
>@@ -38,5 +38,6 @@ int  nouveau_client_create_(const char *name, u64 device, const char *cfg,
> 			    const char *dbg, int, void **);
> int  nouveau_client_init(struct nouveau_client *);
> int  nouveau_client_fini(struct nouveau_client *, bool suspend);
>+const char *nouveau_client_name(void *obj);
> 
> #endif
>diff --git a/drivers/gpu/drm/nouveau/core/include/core/enum.h b/drivers/gpu/drm/nouveau/core/include/core/enum.h
>index e7b1e18..4fc62bb 100644
>--- a/drivers/gpu/drm/nouveau/core/include/core/enum.h
>+++ b/drivers/gpu/drm/nouveau/core/include/core/enum.h
>@@ -5,12 +5,13 @@ struct nouveau_enum {
> 	u32 value;
> 	const char *name;
> 	const void *data;
>+	u32 data2;
> };
> 
> const struct nouveau_enum *
> nouveau_enum_find(const struct nouveau_enum *, u32 value);
> 
>-void
>+const struct nouveau_enum *
> nouveau_enum_print(const struct nouveau_enum *en, u32 value);
> 
> struct nouveau_bitfield {
>diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
>index d67fed1..a64726a 100644
>--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
>+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
>@@ -92,6 +92,8 @@ int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *,
> 			 struct nouveau_oclass *, int min, int max,
> 			 int size, void **);
> void nouveau_fifo_destroy(struct nouveau_fifo *);
>+const char *
>+nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
> 
> #define _nouveau_fifo_init _nouveau_engine_init
> #define _nouveau_fifo_fini _nouveau_engine_fini
>diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
>index 5f570806..c155862 100644
>--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
>+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
>@@ -22,8 +22,10 @@
>  * Authors: Ben Skeggs
>  */
> 
>-#include <core/object.h>
>+#include <core/client.h>
> #include <core/enum.h>
>+#include <core/engctx.h>
>+#include <core/object.h>
> 
> #include <subdev/fb.h>
> #include <subdev/bios.h>
>@@ -396,17 +398,18 @@ static const struct nouveau_enum vm_client[] = {
> };
> 
> static const struct nouveau_enum vm_engine[] = {
>-	{ 0x00000000, "PGRAPH", NULL },
>-	{ 0x00000001, "PVP", NULL },
>+	{ 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
>+	{ 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
> 	{ 0x00000004, "PEEPHOLE", NULL },
>-	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
>+	{ 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
> 	{ 0x00000006, "BAR", vm_bar_subclients },
>-	{ 0x00000008, "PPPP", NULL },
>-	{ 0x00000009, "PBSP", NULL },
>-	{ 0x0000000a, "PCRYPT", NULL },
>+	{ 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
>+	{ 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
>+	{ 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
>+	{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
> 	{ 0x0000000b, "PCOUNTER", NULL },
> 	{ 0x0000000c, "SEMAPHORE_BG", NULL },
>-	{ 0x0000000d, "PCOPY", NULL },
>+	{ 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
> 	{ 0x0000000e, "PDAEMON", NULL },
> 	{}
> };
>@@ -428,8 +431,10 @@ void
> nv50_fb_trap(struct nouveau_fb *pfb, int display)
> {
> 	struct nouveau_device *device = nv_device(pfb);
>+	struct nouveau_engine *engine;
> 	struct nv50_fb_priv *priv = (void *)pfb;
> 	const struct nouveau_enum *en, *cl;
>+	struct nouveau_object *engctx = NULL;
> 	u32 trap[6], idx, chan;
> 	u8 st0, st1, st2, st3;
> 	int i;
>@@ -463,34 +468,53 @@ nv50_fb_trap(struct nouveau_fb *pfb, int display)
> 	}
> 	chan = (trap[2] << 16) | trap[1];
> 
>-	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x ",
>+	en = nouveau_enum_find(vm_engine, st0);
>+
>+	if (en && en->data2) {
>+		const struct nouveau_enum *orig_en = en;
>+		while (en->name && en->value == st0 && en->data2) {
>+			engine = nouveau_engine(&pfb->base, en->data2);
>+			if (engine) {
>+				engctx = nouveau_engctx_get(engine, chan);
>+				if (engctx)
>+					break;
>+			}
>+			en++;
>+		}
>+		if (!engctx)
>+			en = orig_en;
>+	}
>+
>+	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
> 		 (trap[5] & 0x00000100) ? "read" : "write",
>-		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan);
>+		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
>+		 nouveau_client_name(engctx));
>+
>+	nouveau_engctx_put(engctx);
> 
>-	en = nouveau_enum_find(vm_engine, st0);
> 	if (en)
>-		printk("%s/", en->name);
>+		pr_cont("%s/", en->name);
> 	else
>-		printk("%02x/", st0);
>+		pr_cont("%02x/", st0);
> 
> 	cl = nouveau_enum_find(vm_client, st2);
> 	if (cl)
>-		printk("%s/", cl->name);
>+		pr_cont("%s/", cl->name);
> 	else
>-		printk("%02x/", st2);
>+		pr_cont("%02x/", st2);
> 
> 	if      (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
> 	else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
> 	else                     cl = NULL;
> 	if (cl)
>-		printk("%s", cl->name);
>+		pr_cont("%s", cl->name);
> 	else
>-		printk("%02x", st3);
>+		pr_cont("%02x", st3);
> 
>-	printk(" reason: ");
>+	pr_cont(" reason: ");
> 	en = nouveau_enum_find(vm_fault, st1);
> 	if (en)
>-		printk("%s\n", en->name);
>+		pr_cont("%s\n", en->name);
> 	else
>-		printk("0x%08x\n", st1);
>+		pr_cont("0x%08x\n", st1);
> }
>diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
>index 839ca1e..4bde7f7 100644
>--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
>+++ b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
>@@ -156,15 +156,15 @@ mxms_foreach(struct nouveau_mxm *mxm, u8 types,
> 
> 			nv_debug(mxm, "%4s: ", mxms_desc_name[type]);
> 			for (j = headerlen - 1; j >= 0; j--)
>-				printk("%02x", dump[j]);
>-			printk("\n");
>+				pr_cont("%02x", dump[j]);
>+			pr_cont("\n");
> 			dump += headerlen;
> 
> 			for (i = 0; i < entries; i++, dump += recordlen) {
> 				nv_debug(mxm, "      ");
> 				for (j = recordlen - 1; j >= 0; j--)
>-					printk("%02x", dump[j]);
>-				printk("\n");
>+					pr_cont("%02x", dump[j]);
>+				pr_cont("\n");
> 			}
> 		}
> 
>diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
>index 09fdef2..0c2e069 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
>@@ -2163,9 +2163,9 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
> 		if (conn[0] != 0xff) {
> 			NV_INFO(drm, "DCB conn %02d: ", idx);
> 			if (olddcb_conntab(dev)[3] < 4)
>-				printk("%04x\n", ROM16(conn[0]));
>+				pr_cont("%04x\n", ROM16(conn[0]));
> 			else
>-				printk("%08x\n", ROM32(conn[0]));
>+				pr_cont("%08x\n", ROM32(conn[0]));
> 		}
> 	}
> 	dcb_fake_connectors(bios);
>diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
>index c1d7301..c3a42f9 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
>@@ -58,7 +58,8 @@ nouveau_channel_idle(struct nouveau_channel *chan)
> 	}
> 
> 	if (ret)
>-		NV_ERROR(cli, "failed to idle channel 0x%08x\n", chan->handle);
>+		NV_ERROR(cli, "failed to idle channel 0x%08x [%s]\n",
>+			 chan->handle, cli->base.name);
> 	return ret;
> }
> 
>diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
>index 8503b2e..19f5cf6 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
>@@ -506,10 +506,11 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
> 	struct pci_dev *pdev = dev->pdev;
> 	struct nouveau_drm *drm = nouveau_drm(dev);
> 	struct nouveau_cli *cli;
>-	char name[16];
>+	char name[32], tmpname[TASK_COMM_LEN];
> 	int ret;
> 
>-	snprintf(name, sizeof(name), "%d", pid_nr(fpriv->pid));
>+	get_task_comm(tmpname, current);
>+	snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
> 
> 	ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli);
> 	if (ret)
>diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
>index 5e2f521..86d9329 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
>@@ -277,6 +277,9 @@ struct validate_op {
> 	struct list_head vram_list;
> 	struct list_head gart_list;
> 	struct list_head both_list;
>+	unsigned long vram_list_size;
>+	unsigned long gart_list_size;
>+	unsigned long both_list_size;
> };
> 
> static void
>@@ -323,6 +326,10 @@ validate_init(struct nouveau_channel *chan, struct drm_file *file_priv,
> 
> 	sequence = atomic_add_return(1, &drm->ttm.validate_sequence);
> retry:
>+	op->vram_list_size = 0;
>+	op->gart_list_size = 0;
>+	op->both_list_size = 0;
>+
> 	if (++trycnt > 100000) {
> 		NV_ERROR(drm, "%s failed and gave up.\n", __func__);
> 		return -EINVAL;
>@@ -367,15 +374,16 @@ retry:
> 		nvbo->reserved_by = file_priv;
> 		nvbo->pbbo_index = i;
> 		if ((b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
>-		    (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART))
>+		    (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART)) {
> 			list_add_tail(&nvbo->entry, &op->both_list);
>-		else
>-		if (b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM)
>+			op->both_list_size += nvbo->bo.mem.size;
>+		} else if (b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) {
> 			list_add_tail(&nvbo->entry, &op->vram_list);
>-		else
>-		if (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART)
>+			op->vram_list_size += nvbo->bo.mem.size;
>+		} else if (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART) {
> 			list_add_tail(&nvbo->entry, &op->gart_list);
>-		else {
>+			op->gart_list_size += nvbo->bo.mem.size;
>+		} else {
> 			NV_ERROR(drm, "invalid valid domains: 0x%08x\n",
> 				 b->valid_domains);
> 			list_add_tail(&nvbo->entry, &op->both_list);
>@@ -480,6 +488,7 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan,
> {
> 	struct nouveau_drm *drm = chan->drm;
> 	int ret, relocs = 0;
>+	const char *err;
> 
> 	INIT_LIST_HEAD(&op->vram_list);
> 	INIT_LIST_HEAD(&op->gart_list);
>@@ -497,33 +506,48 @@ nouveau_gem_pushbuf_validate(struct nouveau_channel *chan,
> 
> 	ret = validate_list(chan, &op->vram_list, pbbo, user_buffers);
> 	if (unlikely(ret < 0)) {
>-		if (ret != -ERESTARTSYS)
>-			NV_ERROR(drm, "validate vram_list\n");
>-		validate_fini(op, NULL);
>-		return ret;
>+		err = "vram";
>+		goto fail;
> 	}
> 	relocs += ret;
> 
> 	ret = validate_list(chan, &op->gart_list, pbbo, user_buffers);
> 	if (unlikely(ret < 0)) {
>-		if (ret != -ERESTARTSYS)
>-			NV_ERROR(drm, "validate gart_list\n");
>-		validate_fini(op, NULL);
>-		return ret;
>+		err = "gart";
>+		goto fail;
> 	}
> 	relocs += ret;
> 
> 	ret = validate_list(chan, &op->both_list, pbbo, user_buffers);
> 	if (unlikely(ret < 0)) {
>-		if (ret != -ERESTARTSYS)
>-			NV_ERROR(drm, "validate both_list\n");
>-		validate_fini(op, NULL);
>-		return ret;
>+		err = "both";
>+		goto fail;
> 	}
> 	relocs += ret;
> 
> 	*apply_relocs = relocs;
> 	return 0;
>+
>+fail:
>+	if (ret != -ERESTARTSYS) {
>+		if (ret == -ENOMEM) {
>+			NV_ERROR(drm,
>+				 "validate %s_list, vram_list_size: %lu, gart_list_size: %lu, both_list_size: %lu\n",
>+				 err, op->vram_list_size, op->gart_list_size,
>+				 op->both_list_size);
>+		} else
>+			NV_ERROR(drm, "validate %s_list\n", err);
>+	}
>+	validate_fini(op, NULL);
>+	if (ret == -ENOMEM) {
>+		NV_ERROR(drm, "vram_available: %llu, gart_available: %llu\n",
>+			 drm->gem.vram_available, drm->gem.gart_available);
>+		NV_ERROR(drm, "TT:\n");
>+		ttm_mem_type_debug(&chan->drm->ttm.bdev, TTM_PL_TT);
>+		NV_ERROR(drm, "VRAM:\n");
>+		ttm_mem_type_debug(&chan->drm->ttm.bdev, TTM_PL_VRAM);
>+	}
>+	return ret;
> }
> 
> static inline void *
>@@ -642,6 +666,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	struct validate_op op;
> 	struct nouveau_fence *fence = NULL;
> 	int i, j, ret = 0, do_reloc = 0;
>+	const char *client_name;
> 
> 	if (unlikely(!abi16))
> 		return -ENOMEM;
>@@ -655,6 +680,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 
> 	if (!chan)
> 		return nouveau_abi16_put(abi16, -ENOENT);
>+	client_name = chan->cli->base.name;
> 
> 	req->vram_available = drm->gem.vram_available;
> 	req->gart_available = drm->gem.gart_available;
>@@ -662,20 +688,23 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 		goto out_next;
> 
> 	if (unlikely(req->nr_push > NOUVEAU_GEM_MAX_PUSH)) {
>-		NV_ERROR(drm, "pushbuf push count exceeds limit: %d max %d\n",
>-			 req->nr_push, NOUVEAU_GEM_MAX_PUSH);
>+		NV_ERROR(drm,
>+			 "pushbuf push count exceeds limit: %d max %d [%s]\n",
>+			 req->nr_push, NOUVEAU_GEM_MAX_PUSH, client_name);
> 		return nouveau_abi16_put(abi16, -EINVAL);
> 	}
> 
> 	if (unlikely(req->nr_buffers > NOUVEAU_GEM_MAX_BUFFERS)) {
>-		NV_ERROR(drm, "pushbuf bo count exceeds limit: %d max %d\n",
>-			 req->nr_buffers, NOUVEAU_GEM_MAX_BUFFERS);
>+		NV_ERROR(drm,
>+			 "pushbuf bo count exceeds limit: %d max %d [%s]\n",
>+			 req->nr_buffers, NOUVEAU_GEM_MAX_BUFFERS, client_name);
> 		return nouveau_abi16_put(abi16, -EINVAL);
> 	}
> 
> 	if (unlikely(req->nr_relocs > NOUVEAU_GEM_MAX_RELOCS)) {
>-		NV_ERROR(drm, "pushbuf reloc count exceeds limit: %d max %d\n",
>-			 req->nr_relocs, NOUVEAU_GEM_MAX_RELOCS);
>+		NV_ERROR(drm,
>+			 "pushbuf reloc count exceeds limit: %d max %d [%s]\n",
>+			 req->nr_relocs, NOUVEAU_GEM_MAX_RELOCS, client_name);
> 		return nouveau_abi16_put(abi16, -EINVAL);
> 	}
> 
>@@ -692,7 +721,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	/* Ensure all push buffers are on validate list */
> 	for (i = 0; i < req->nr_push; i++) {
> 		if (push[i].bo_index >= req->nr_buffers) {
>-			NV_ERROR(drm, "push %d buffer not in list\n", i);
>+			NV_ERROR(drm, "push %d buffer not in list [%s]\n", i,
>+				 client_name);
> 			ret = -EINVAL;
> 			goto out_prevalid;
> 		}
>@@ -703,7 +733,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 					   req->nr_buffers, &op, &do_reloc);
> 	if (ret) {
> 		if (ret != -ERESTARTSYS)
>-			NV_ERROR(drm, "validate: %d\n", ret);
>+			NV_ERROR(drm, "validate: %d [%s]\n", ret, client_name);
> 		goto out_prevalid;
> 	}
> 
>@@ -711,7 +741,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	if (do_reloc) {
> 		ret = nouveau_gem_pushbuf_reloc_apply(dev, req, bo);
> 		if (ret) {
>-			NV_ERROR(drm, "reloc apply: %d\n", ret);
>+			NV_ERROR(drm, "reloc apply: %d [%s]\n", ret,
>+				 client_name);
> 			goto out;
> 		}
> 	}
>@@ -719,7 +750,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	if (chan->dma.ib_max) {
> 		ret = nouveau_dma_wait(chan, req->nr_push + 1, 16);
> 		if (ret) {
>-			NV_ERROR(drm, "nv50cal_space: %d\n", ret);
>+			NV_ERROR(drm, "nv50cal_space: %d [%s]\n", ret,
>+				 client_name);
> 			goto out;
> 		}
> 
>@@ -734,7 +766,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	if (nv_device(drm->device)->chipset >= 0x25) {
> 		ret = RING_SPACE(chan, req->nr_push * 2);
> 		if (ret) {
>-			NV_ERROR(drm, "cal_space: %d\n", ret);
>+			NV_ERROR(drm, "cal_space: %d [%s]\n", ret, client_name);
> 			goto out;
> 		}
> 
>@@ -748,7 +780,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 	} else {
> 		ret = RING_SPACE(chan, req->nr_push * (2 + NOUVEAU_DMA_SKIPS));
> 		if (ret) {
>-			NV_ERROR(drm, "jmp_space: %d\n", ret);
>+			NV_ERROR(drm, "jmp_space: %d [%s]\n", ret, client_name);
> 			goto out;
> 		}
> 
>@@ -786,7 +818,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
> 
> 	ret = nouveau_fence_new(chan, &fence);
> 	if (ret) {
>-		NV_ERROR(drm, "error fencing pushbuf: %d\n", ret);
>+		NV_ERROR(drm, "error fencing pushbuf: %d [%s]\n", ret,
>+			 client_name);
> 		WIND_RING(chan);
> 		goto out;
> 	}
>diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
>index bf6e4b5..e396301 100644
>--- a/drivers/gpu/drm/ttm/ttm_bo.c
>+++ b/drivers/gpu/drm/ttm/ttm_bo.c
>@@ -66,7 +66,7 @@ static inline int ttm_mem_type_from_flags(uint32_t flags, uint32_t *mem_type)
> 	return -EINVAL;
> }
> 
>-static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type)
>+void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type)
> {
> 	struct ttm_mem_type_manager *man = &bdev->man[mem_type];
> 
>@@ -80,6 +80,7 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type)
> 	if (mem_type != TTM_PL_SYSTEM)
> 		(*man->func->debug)(man, TTM_PFX);
> }
>+EXPORT_SYMBOL(ttm_mem_type_debug);
> 
> static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo,
> 					struct ttm_placement *placement)
>diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
>index e8028ad..0eb6242 100644
>--- a/include/drm/ttm/ttm_bo_api.h
>+++ b/include/drm/ttm/ttm_bo_api.h
>@@ -736,4 +736,5 @@ extern ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
> 
> extern void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
> 
>+void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type);
> #endif

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Attachments on bug 59069: 72569 | 72570 | 72571 | 72588 | 72616 | 72680 | 72932 | 73073 | 73074 | 73165 | 73179 | 75140 | 75214 | 117543 | 117544 | 120530 | 123753 | 123756 | 123757

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