Attachment 73356 Details for Bug 58791 – modes-cannot-lightup.dmesg

modes-cannot-lightup.dmesg

modes-cannot-lightup.dmesg (text/plain), 123.58 KB, created by yanbing on 2013-01-21 06:21:40 UTC

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Creator: yanbing

Created: 2013-01-21 06:21:40 UTC

Size: 123.58 KB

patch

obsolete

>[  266.493634] [drm:intel_crt_detect], CRT not detected via hotplug
>[  266.493788] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  266.493792] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  266.493794] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  266.493796] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  266.494148] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  266.494151] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  266.494153] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  266.494155] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  266.494307] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  266.494310] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  266.494315] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  266.494599] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  266.495411] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  266.518166] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  266.541440] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  266.541443] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  266.541446] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  266.541451] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  266.541456] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  266.541460] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  266.541464] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  269.495993] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  269.989569] [drm:i915_driver_open], 
>[  269.989593] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  269.989602] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  269.989607] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  269.989613] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  269.989618] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  269.989623] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  269.989640] [drm:i915_driver_open], 
>[  269.989904] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  269.989915] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  269.989931] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  269.989937] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  269.990287] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  269.991101] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.013915] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.037238] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.037241] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  270.038051] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.060872] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.083653] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  270.083712] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  270.083715] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  270.083743] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  270.083746] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  270.083749] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  270.083752] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  270.083758] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  270.083760] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  270.083764] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  270.083767] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  270.083771] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  270.083774] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  270.083777] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  270.083781] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  270.083785] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  270.083788] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  270.083792] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  270.083795] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  270.083799] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  270.083803] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  270.083806] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  270.083810] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  270.083813] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  270.083817] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  270.083820] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  270.083824] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  270.083827] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  270.083831] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  270.083834] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  270.083838] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  270.083841] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  270.083844] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  270.083848] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  270.083851] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  270.083855] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  270.083858] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  270.083861] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  270.083865] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  270.083868] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  270.083872] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  270.083875] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  270.083878] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  270.083882] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  270.083885] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  270.083889] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  270.083892] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  270.083904] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  270.083917] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  270.083933] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  270.305039] [drm:drm_mode_addfb], [FB:35]
>[  270.305139] [drm:drm_mode_setcrtc], [CRTC:3]
>[  270.305149] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  270.305154] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  270.305164] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  270.305168] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  270.305176] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  270.305185] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  270.305190] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  270.305196] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  270.305201] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  270.305204] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  270.305208] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  270.305212] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  270.305221] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  270.305403] [drm:intel_dp_link_down], 
>[  270.389450] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  270.389456] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  270.389869] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  270.389872] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  270.389875] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  270.389877] [drm:intel_update_fbc], fbc set to per-chip default
>[  270.389879] [drm:intel_update_fbc], fbc disabled per module param
>[  270.389886] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 131481KHz
>[  270.389890] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  270.389892] [drm:intel_dp_mode_fixup], DP link bw required 315555 available 518400
>[  270.389894] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  270.389895] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  270.389903] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  270.389906] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  270.389911] [drm:ironlake_edp_backlight_off], 
>[  270.590291] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  270.590297] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  270.590302] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  271.464598] [drm:intel_dp_link_down], 
>[  271.516505] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.568051] [drm:intel_update_fbc], no output, disabling
>[  271.568058] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  271.568060] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  271.568062] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  271.568063] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  271.568066] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  271.568067] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  271.568069] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  271.568381] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  271.620329] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.620337] [drm:ironlake_update_plane], Writing base 00911000 00000000 0 0 6720
>[  271.672240] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.672244] [drm:intel_update_fbc], no output, disabling
>[  271.672251] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1680x945]
>[  271.672256] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  271.672260] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  271.672264] [drm:ironlake_write_eld], ELD on pipe A
>[  271.672268] [drm:ironlake_write_eld], Audio directed to unknown port
>[  271.672270] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  271.672287] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  271.672292] [drm:ironlake_check_srwm], watermark 1: display plane 44, fbc lines 3, cursor 6
>[  271.672297] [drm:ironlake_check_srwm], watermark 2: display plane 142, fbc lines 4, cursor 10
>[  271.724150] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.776060] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.776375] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  271.776377] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  271.776533] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  271.776535] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  271.776536] [drm:ironlake_fdi_link_train], FDI train done
>[  271.776537] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  271.776540] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  271.777762] [drm:intel_update_fbc], fbc set to per-chip default
>[  271.777763] [drm:intel_update_fbc], fbc disabled per module param
>[  271.778230] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  271.779033] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  271.779822] [drm:intel_dp_start_link_train], clock recovery OK
>[  271.779825] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  271.780883] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  271.781935] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  271.782998] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  271.784071] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  271.785144] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  271.802959] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  271.802971] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  271.802978] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  271.802983] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  271.802989] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  271.802995] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  271.803002] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  271.803008] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  271.803014] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  271.803019] [drm:intel_modeset_check_state], [CRTC:3]
>[  271.803024] [drm:intel_modeset_check_state], [CRTC:5]
>[  271.803038] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  271.803524] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  271.803842] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  271.803847] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  271.803851] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  271.803860] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  271.803864] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  272.103705] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  272.103869] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  272.103872] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  272.103877] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  272.103881] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  272.103884] [drm:intel_crt_detect], CRT not detected via hotplug
>[  272.104038] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  272.104043] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  272.104045] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  272.104047] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  272.104399] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  272.104401] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  272.104403] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  272.104405] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  272.104571] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  272.104579] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  272.104585] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  272.104873] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  272.105681] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  272.128875] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  272.151541] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  272.151544] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  272.151546] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  272.151551] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  272.151555] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  272.151559] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  272.151563] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  275.102339] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  279.200503] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  279.200510] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  279.200513] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  279.200516] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  279.200519] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  279.200733] [drm:intel_dp_link_down], 
>[  279.245201] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  279.245208] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  279.245622] [drm:intel_update_fbc], no output, disabling
>[  279.245636] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  279.245639] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  279.245641] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  279.245644] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  279.245648] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  279.245651] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  279.245654] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  279.245657] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  279.245660] [drm:intel_modeset_check_state], [CRTC:3]
>[  279.245662] [drm:intel_modeset_check_state], [CRTC:5]
>[  279.248987] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  279.248989] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  279.248991] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  279.248992] [drm:drm_mode_debug_printmodeline], Modeline 69:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  279.248995] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  279.248998] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  279.249000] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  279.249001] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  279.249003] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  279.249004] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  279.249006] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  279.249010] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  279.249013] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  279.249015] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  279.249017] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  279.249020] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  279.249021] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  279.249023] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  279.249025] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  279.249032] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  279.300100] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  279.300108] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  279.300115] [drm:intel_update_fbc], no output, disabling
>[  279.300122] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  279.300127] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  279.300630] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  279.300633] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  279.300636] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  279.300641] [drm:ironlake_edp_pll_on], 
>[  279.352002] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  279.403921] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  279.403926] [drm:intel_update_fbc], fbc set to per-chip default
>[  279.403928] [drm:intel_update_fbc], fbc disabled per module param
>[  279.403933] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  279.403938] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  279.403943] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  279.403953] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  279.403957] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  279.704807] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  279.705386] [drm:intel_dp_start_link_train], clock recovery OK
>[  279.705389] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  279.705392] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  279.705397] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  279.705404] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  279.705409] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  280.045753] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  280.045764] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  280.096666] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  280.097597] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  280.097745] [drm:ironlake_edp_backlight_on], 
>[  280.138603] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  280.148578] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  280.148593] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  280.148601] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  280.148606] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  280.148613] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  280.148619] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  280.148625] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  280.148632] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  280.148638] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  280.148644] [drm:intel_modeset_check_state], [CRTC:3]
>[  280.148648] [drm:intel_modeset_check_state], [CRTC:5]
>[  280.148654] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  280.148660] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  280.148665] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  280.148669] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  280.148675] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  280.148680] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  280.148684] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  280.148688] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  280.148697] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  280.148705] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  280.148713] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  280.148718] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  280.148723] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  280.148731] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  280.148736] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  280.148741] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  280.148744] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  280.148752] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  280.148757] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  280.148762] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  280.149079] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  280.200553] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  280.200561] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  280.200568] [drm:intel_update_fbc], fbc set to per-chip default
>[  280.200572] [drm:intel_update_fbc], fbc disabled per module param
>[  280.200576] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  280.200582] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  280.200587] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  280.200593] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  280.200599] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  280.200603] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  280.200607] [drm:ironlake_write_eld], ELD on pipe B
>[  280.200611] [drm:ironlake_write_eld], Audio directed to unknown port
>[  280.200614] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  280.200631] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  280.200635] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  280.252464] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  280.304375] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  280.304692] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  280.304695] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  280.304853] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  280.304857] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  280.304860] [drm:ironlake_fdi_link_train], FDI train done
>[  280.304862] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  280.304868] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  280.306094] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  280.306560] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  280.307363] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  280.308145] [drm:intel_dp_start_link_train], clock recovery OK
>[  280.308147] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  280.309200] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  280.310246] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  280.311303] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  280.312372] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  280.313441] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  280.331333] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  280.331343] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  280.331355] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  280.331360] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  280.331364] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  280.331370] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  280.331375] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  280.331380] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  280.331385] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  280.331390] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  280.331395] [drm:intel_modeset_check_state], [CRTC:3]
>[  280.331398] [drm:intel_modeset_check_state], [CRTC:5]
>[  283.076857] [drm:i915_driver_open], 
>[  283.076881] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  283.076891] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  283.076896] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  283.076901] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  283.076906] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  283.076911] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  283.076928] [drm:i915_driver_open], 
>[  283.077199] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  283.077210] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  283.077227] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  283.077232] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  283.077582] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  283.078398] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.102292] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.126653] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.126657] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  283.127479] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.151051] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.174534] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  283.174586] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  283.174589] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  283.174615] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  283.174618] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  283.174620] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  283.174624] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  283.174629] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  283.174632] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  283.174635] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  283.174639] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  283.174643] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  283.174646] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  283.174650] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  283.174654] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  283.174657] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  283.174661] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  283.174664] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  283.174668] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  283.174671] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  283.174674] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  283.174678] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  283.174681] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  283.174685] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  283.174688] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  283.174692] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  283.174695] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  283.174699] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  283.174702] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  283.174706] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  283.174709] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  283.174713] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  283.174716] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  283.174720] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  283.174723] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  283.174727] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  283.174730] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  283.174733] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  283.174737] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  283.174740] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  283.174744] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  283.174747] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  283.174751] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  283.174754] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  283.174758] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  283.174762] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  283.174765] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  283.174769] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  283.174772] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  283.174784] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  283.361267] [drm:drm_mode_addfb], [FB:35]
>[  283.361363] [drm:drm_mode_setcrtc], [CRTC:3]
>[  283.361374] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  283.361379] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  283.361388] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  283.361392] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  283.361399] [drm:drm_mode_debug_printmodeline], Modeline 69:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  283.361409] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  283.361414] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  283.361420] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  283.361424] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  283.361429] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  283.361433] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  283.361437] [drm:drm_mode_debug_printmodeline], Modeline 69:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  283.361445] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  283.361711] [drm:intel_dp_link_down], 
>[  283.430920] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  283.479903] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  283.479909] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  283.480322] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  283.480325] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  283.480328] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  283.480330] [drm:intel_update_fbc], fbc set to per-chip default
>[  283.480332] [drm:intel_update_fbc], fbc disabled per module param
>[  283.480338] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 121750KHz
>[  283.480342] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  283.480344] [drm:intel_dp_mode_fixup], DP link bw required 292200 available 518400
>[  283.480346] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  283.480347] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  283.480356] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  283.480360] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  283.480365] [drm:ironlake_edp_backlight_off], 
>[  283.680695] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  283.680701] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  283.680705] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  284.555050] [drm:intel_dp_link_down], 
>[  284.606960] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  284.658500] [drm:intel_update_fbc], no output, disabling
>[  284.658507] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  284.658509] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  284.658511] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  284.658512] [drm:drm_mode_debug_printmodeline], Modeline 69:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  284.658515] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  284.658516] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  284.658517] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  284.658830] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  284.710782] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  284.710791] [drm:ironlake_update_plane], Writing base 00911000 00000000 0 0 5632
>[  284.762692] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  284.762697] [drm:intel_update_fbc], no output, disabling
>[  284.762703] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1400x1050]
>[  284.762708] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  284.762712] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  284.762716] [drm:ironlake_write_eld], ELD on pipe A
>[  284.762720] [drm:ironlake_write_eld], Audio directed to unknown port
>[  284.762722] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  284.762739] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  284.762744] [drm:ironlake_check_srwm], watermark 1: display plane 41, fbc lines 3, cursor 6
>[  284.762748] [drm:ironlake_check_srwm], watermark 2: display plane 132, fbc lines 4, cursor 10
>[  284.814602] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  284.866513] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  284.866828] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  284.866829] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  284.866986] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  284.866987] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  284.866988] [drm:ironlake_fdi_link_train], FDI train done
>[  284.866989] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  284.866993] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  284.868213] [drm:intel_update_fbc], fbc set to per-chip default
>[  284.868215] [drm:intel_update_fbc], fbc disabled per module param
>[  284.868682] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  284.869486] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  284.870276] [drm:intel_dp_start_link_train], clock recovery OK
>[  284.870279] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  284.872634] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  284.873695] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  284.874759] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  284.875833] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  284.876919] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  284.894407] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  284.894419] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  284.894426] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  284.894431] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  284.894438] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  284.894444] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  284.894450] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  284.894457] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  284.894463] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  284.894469] [drm:intel_modeset_check_state], [CRTC:3]
>[  284.894473] [drm:intel_modeset_check_state], [CRTC:5]
>[  284.894489] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  284.894972] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  284.895288] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  284.895293] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  284.895298] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  284.895307] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  284.895310] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  285.195159] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  285.195322] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  285.195326] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  285.195330] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  285.195335] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  285.195337] [drm:intel_crt_detect], CRT not detected via hotplug
>[  285.195492] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  285.195496] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  285.195498] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  285.195500] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  285.195856] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  285.195858] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  285.195860] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  285.195862] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  285.196069] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  285.196075] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  285.196079] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  285.196408] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  285.197230] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  285.220550] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  285.243860] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  285.243863] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  285.243866] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  285.243870] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  285.243875] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  285.243879] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  285.243883] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  288.199777] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  293.545901] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  293.545907] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  293.545911] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  293.545914] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  293.545917] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  293.546088] [drm:intel_dp_link_down], 
>[  293.602400] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  293.704296] ------------[ cut here ]------------
>[  293.704333] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x108/0x122 [i915]()
>[  293.704337] Hardware name: Latitude E6510
>[  293.704339] pipe_off wait timed out
>[  293.704341] Modules linked in: bnep bluetooth rfkill snd_hda_codec_hdmi snd_hda_codec_idt iTCO_wdt iTCO_vendor_support snd_hda_intel coretemp hwmon snd_hda_codec kvm_intel snd_hwdep snd_pcm kvm snd_page_alloc snd_timer snd lpc_ich microcode i2c_i801 dcdbas joydev pcspkr uinput mfd_core e1000e soundcore wmi battery ppdev parport_pc parport ac ipv6 autofs4 ext4 crc16 jbd2 mbcache sr_mod cdrom sd_mod firewire_ohci firewire_core crc_itu_t i915 video button i2c_algo_bit drm_kms_helper drm i2c_core dm_mirror dm_region_hash dm_log dm_mod
>[  293.704398] Pid: 3595, comm: testdisplay Tainted: G        W    3.8.0-rc3_next_queued_20130120+ #1
>[  293.704401] Call Trace:
>[  293.704413]  [<c1023dde>] ? warn_slowpath_common+0x68/0x79
>[  293.704432]  [<f861a0a4>] ? intel_wait_for_pipe_off+0x108/0x122 [i915]
>[  293.704438]  [<c1023e57>] ? warn_slowpath_fmt+0x29/0x2d
>[  293.704459]  [<f861a0a4>] ? intel_wait_for_pipe_off+0x108/0x122 [i915]
>[  293.704479]  [<f861a7ae>] ? ironlake_crtc_disable+0xa4/0x6cf [i915]
>[  293.704495]  [<f8517ba5>] ? drm_ut_debug_printk+0x34/0x37 [drm]
>[  293.704515]  [<f861cb0a>] ? intel_crtc_disable+0x2a/0xd9 [i915]
>[  293.704535]  [<f8620258>] ? intel_set_mode+0x1e5/0x6c3 [i915]
>[  293.704548]  [<f8517ba5>] ? drm_ut_debug_printk+0x34/0x37 [drm]
>[  293.704568]  [<f8620c4c>] ? intel_crtc_set_config+0x516/0x623 [i915]
>[  293.704583]  [<f851c0f5>] ? drm_framebuffer_remove+0x49/0xe5 [drm]
>[  293.704597]  [<f851ebf8>] ? drm_fb_release+0x30/0x49 [drm]
>[  293.704608]  [<f8514314>] ? drm_release+0x1cd/0x404 [drm]
>[  293.704617]  [<c10aa2ef>] ? __fput+0xc6/0x193
>[  293.704624]  [<c10357cd>] ? task_work_run+0x65/0x74
>[  293.704629]  [<c1027bde>] ? do_exit+0x2e0/0x75f
>[  293.704634]  [<c102d5be>] ? __dequeue_signal+0xd/0xce
>[  293.704638]  [<c1028182>] ? do_group_exit+0x59/0x7c
>[  293.704643]  [<c102f168>] ? get_signal_to_deliver+0x425/0x43c
>[  293.704648]  [<c1001d5a>] ? do_signal+0x20/0x624
>[  293.704655]  [<c1009040>] ? syscall_trace_leave+0x29/0xd5
>[  293.704662]  [<c10d4a7b>] ? eventfd_ctx_read+0x3a/0x138
>[  293.704667]  [<c10a9672>] ? vfs_read+0xe2/0x117
>[  293.704672]  [<c1002485>] ? do_notify_resume+0x1e/0x52
>[  293.704678]  [<c13a4e8b>] ? work_notifysig+0x24/0x29
>[  293.704682] ---[ end trace d10e5d6802a2f149 ]---
>[  293.712279] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  293.712284] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  293.712698] [drm:intel_update_fbc], no output, disabling
>[  293.712715] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  293.712720] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  293.712723] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  293.712728] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  293.712732] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  293.712736] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  293.712741] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  293.712745] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  293.712749] [drm:intel_modeset_check_state], [CRTC:3]
>[  293.712752] [drm:intel_modeset_check_state], [CRTC:5]
>[  293.717441] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  293.717447] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  293.717450] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  293.717453] [drm:drm_mode_debug_printmodeline], Modeline 69:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  293.717459] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  293.717465] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  293.717469] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  293.717473] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  293.717476] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  293.717478] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  293.717485] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  293.717492] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  293.717498] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  293.717502] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  293.717506] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  293.717513] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  293.717517] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  293.717520] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  293.717523] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  293.717535] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  293.769175] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  293.769182] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  293.769189] [drm:intel_update_fbc], no output, disabling
>[  293.769195] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  293.769199] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  293.769703] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  293.769707] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  293.769712] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  293.769719] [drm:ironlake_edp_pll_on], 
>[  293.821085] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  293.873001] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  293.873005] [drm:intel_update_fbc], fbc set to per-chip default
>[  293.873008] [drm:intel_update_fbc], fbc disabled per module param
>[  293.873012] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  293.873017] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  293.873022] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  293.873032] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  293.873037] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  294.173896] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  294.174473] [drm:intel_dp_start_link_train], clock recovery OK
>[  294.174476] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  294.174479] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  294.174484] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  294.174492] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  294.174496] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  294.514897] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  294.514908] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  294.565808] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  294.566735] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  294.566881] [drm:ironlake_edp_backlight_on], 
>[  294.607680] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  294.617655] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  294.617671] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  294.617678] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  294.617683] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  294.617690] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  294.617696] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  294.617702] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  294.617708] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  294.617714] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  294.617720] [drm:intel_modeset_check_state], [CRTC:3]
>[  294.617724] [drm:intel_modeset_check_state], [CRTC:5]
>[  294.617730] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  294.617737] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  294.617741] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  294.617746] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  294.617751] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  294.617757] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  294.617761] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  294.617764] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  294.617773] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  294.617781] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  294.617789] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  294.617794] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  294.617799] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  294.617807] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  294.617812] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  294.617817] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  294.617820] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  294.617828] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  294.617833] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  294.617837] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  294.618154] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  294.669633] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  294.669641] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  294.669648] [drm:intel_update_fbc], fbc set to per-chip default
>[  294.669651] [drm:intel_update_fbc], fbc disabled per module param
>[  294.669656] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  294.669661] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  294.669667] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  294.669672] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  294.669678] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  294.669682] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  294.669686] [drm:ironlake_write_eld], ELD on pipe B
>[  294.669691] [drm:ironlake_write_eld], Audio directed to unknown port
>[  294.669694] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  294.669711] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  294.669715] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  294.721538] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  294.773448] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  294.773764] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  294.773767] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  294.773924] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  294.773927] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  294.773929] [drm:ironlake_fdi_link_train], FDI train done
>[  294.773931] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  294.773936] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  294.775160] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  294.775602] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  294.776403] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  294.777181] [drm:intel_dp_start_link_train], clock recovery OK
>[  294.777183] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  294.778237] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  294.779296] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  294.780352] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  294.781428] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  294.782496] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  294.800407] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  294.800418] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  294.800428] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  294.800434] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  294.800438] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  294.800443] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  294.800449] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  294.800453] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  294.800458] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  294.800463] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  294.800468] [drm:intel_modeset_check_state], [CRTC:3]
>[  294.800471] [drm:intel_modeset_check_state], [CRTC:5]
>[  294.800492] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  294.800931] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  294.801694] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  294.802015] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  294.802025] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  294.802185] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  294.802344] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  294.802347] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  294.802352] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  294.802356] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  294.802358] [drm:intel_crt_detect], CRT not detected via hotplug
>[  294.802510] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  294.802514] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  294.802515] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  294.802517] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  294.802868] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  294.802870] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  294.802871] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  294.802873] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  294.803029] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  294.803032] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  294.803034] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  294.803315] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  294.804125] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  294.826764] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  294.850953] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  294.850956] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  294.850958] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  294.850963] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  294.850967] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  294.850971] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  294.850975] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  297.799247] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  297.841799] [drm:i915_driver_open], 
>[  297.850217] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  297.850228] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  297.850233] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  297.850237] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  297.850241] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  297.850245] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  297.850267] [drm:i915_driver_open], 
>[  297.850510] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  297.850518] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  297.850532] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  297.850537] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  297.850886] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  297.851703] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.874893] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.898077] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.898081] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  297.898887] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.922611] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.946285] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  297.946343] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  297.946345] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  297.946371] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  297.946375] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  297.946377] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  297.946380] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  297.946386] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  297.946389] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  297.946392] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  297.946396] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  297.946400] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  297.946403] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  297.946406] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  297.946410] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  297.946413] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  297.946417] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  297.946421] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  297.946424] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  297.946427] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  297.946431] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  297.946434] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  297.946439] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  297.946442] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  297.946446] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  297.946449] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  297.946453] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  297.946456] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  297.946460] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  297.946463] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  297.946467] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  297.946470] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  297.946473] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  297.946477] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  297.946480] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  297.946484] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  297.946487] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  297.946491] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  297.946494] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  297.946497] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  297.946501] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  297.946504] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  297.946508] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  297.946511] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  297.946514] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  297.946518] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  297.946521] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  297.946524] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  297.946528] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  297.946537] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  298.130037] [drm:drm_mode_addfb], [FB:35]
>[  298.130129] [drm:drm_mode_setcrtc], [CRTC:3]
>[  298.130137] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  298.130141] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  298.130148] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  298.130152] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  298.130158] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  298.130165] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  298.130169] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  298.130172] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  298.130176] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  298.130179] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  298.130182] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  298.130185] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  298.130192] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  298.130375] [drm:intel_dp_link_down], 
>[  298.212528] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  298.212533] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  298.212946] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  298.212949] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  298.212952] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  298.212954] [drm:intel_update_fbc], fbc set to per-chip default
>[  298.212956] [drm:intel_update_fbc], fbc disabled per module param
>[  298.212962] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 135000KHz
>[  298.212966] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  298.212968] [drm:intel_dp_mode_fixup], DP link bw required 324000 available 518400
>[  298.212970] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  298.212971] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  298.212980] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  298.212984] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  298.212988] [drm:ironlake_edp_backlight_off], 
>[  298.413426] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  298.413432] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  298.413437] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  299.257727] [drm:intel_dp_link_down], 
>[  299.309637] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.361178] [drm:intel_update_fbc], no output, disabling
>[  299.361185] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  299.361186] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  299.361188] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  299.361190] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  299.361192] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  299.361194] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  299.361195] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  299.361508] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  299.413458] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.413466] [drm:ironlake_update_plane], Writing base 00911000 00000000 0 0 5120
>[  299.465368] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.465373] [drm:intel_update_fbc], no output, disabling
>[  299.465379] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1280x1024]
>[  299.465384] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  299.465388] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  299.465392] [drm:ironlake_write_eld], ELD on pipe A
>[  299.465396] [drm:ironlake_write_eld], Audio directed to unknown port
>[  299.465398] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  299.465415] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  299.465420] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  299.465425] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  299.517275] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.569189] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  299.569505] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  299.569506] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  299.569662] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  299.569664] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  299.569665] [drm:ironlake_fdi_link_train], FDI train done
>[  299.569666] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  299.569670] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  299.570891] [drm:intel_update_fbc], fbc set to per-chip default
>[  299.570893] [drm:intel_update_fbc], fbc disabled per module param
>[  299.571360] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.572158] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  299.572948] [drm:intel_dp_start_link_train], clock recovery OK
>[  299.572951] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  299.574006] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  299.575055] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  299.576112] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  299.577181] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  299.578250] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  299.592100] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  299.592109] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  299.592113] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  299.592115] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  299.592118] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  299.592122] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  299.592125] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  299.592128] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  299.592131] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  299.592134] [drm:intel_modeset_check_state], [CRTC:3]
>[  299.592136] [drm:intel_modeset_check_state], [CRTC:5]
>[  299.592145] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  299.592627] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  299.592946] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  299.592951] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  299.592955] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  299.592964] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  299.592968] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  299.892843] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  299.893007] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  299.893010] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  299.893014] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  299.893019] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  299.893021] [drm:intel_crt_detect], CRT not detected via hotplug
>[  299.893181] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  299.893188] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  299.893192] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  299.893195] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  299.893573] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  299.893589] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  299.893595] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  299.893600] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  299.893767] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  299.893771] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  299.893773] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  299.894057] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  299.894886] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.918079] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.941249] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  299.941252] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  299.941254] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  299.941259] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  299.941263] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  299.941268] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  299.941272] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  302.894471] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  307.511912] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  307.511918] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  307.511920] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  307.511922] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  307.511924] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  307.512173] [drm:intel_dp_link_down], 
>[  307.558434] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  307.558441] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  307.558857] [drm:intel_update_fbc], no output, disabling
>[  307.558878] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  307.558883] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  307.558887] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  307.558892] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  307.558897] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  307.558902] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  307.558907] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  307.558912] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  307.558917] [drm:intel_modeset_check_state], [CRTC:3]
>[  307.558920] [drm:intel_modeset_check_state], [CRTC:5]
>[  307.563253] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  307.563258] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  307.563262] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  307.563265] [drm:drm_mode_debug_printmodeline], Modeline 69:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.563271] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  307.563277] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  307.563281] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  307.563285] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  307.563288] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  307.563291] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  307.563297] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  307.563304] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  307.563312] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  307.563316] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  307.563320] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  307.563328] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  307.563332] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  307.563336] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  307.563347] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  307.563360] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  307.615326] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  307.615334] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  307.615340] [drm:intel_update_fbc], no output, disabling
>[  307.615346] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  307.615350] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  307.615854] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  307.615857] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  307.615860] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  307.615863] [drm:ironlake_edp_pll_on], 
>[  307.667236] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  307.719151] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  307.719156] [drm:intel_update_fbc], fbc set to per-chip default
>[  307.719158] [drm:intel_update_fbc], fbc disabled per module param
>[  307.719162] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  307.719167] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  307.719172] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  307.719183] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  307.719188] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  308.020040] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  308.020618] [drm:intel_dp_start_link_train], clock recovery OK
>[  308.020621] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  308.020625] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  308.020630] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  308.020637] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  308.020642] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  308.361048] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  308.361059] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  308.411958] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  308.412886] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  308.413032] [drm:ironlake_edp_backlight_on], 
>[  308.453819] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  308.463873] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  308.463888] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  308.463894] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  308.463899] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  308.463904] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  308.463909] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  308.463914] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  308.463919] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  308.463924] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  308.463928] [drm:intel_modeset_check_state], [CRTC:3]
>[  308.463932] [drm:intel_modeset_check_state], [CRTC:5]
>[  308.463936] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  308.463942] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  308.463945] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  308.463949] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  308.463953] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  308.463957] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  308.463960] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  308.463963] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  308.463970] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  308.463976] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  308.463982] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  308.463987] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  308.463991] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  308.463997] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  308.464001] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  308.464005] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  308.464008] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  308.464014] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  308.464018] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  308.464021] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  308.464335] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  308.515777] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  308.515785] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  308.515793] [drm:intel_update_fbc], fbc set to per-chip default
>[  308.515796] [drm:intel_update_fbc], fbc disabled per module param
>[  308.515800] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  308.515805] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  308.515811] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  308.515816] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  308.515822] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  308.515826] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  308.515831] [drm:ironlake_write_eld], ELD on pipe B
>[  308.515836] [drm:ironlake_write_eld], Audio directed to unknown port
>[  308.515838] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  308.515856] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  308.515860] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  308.567694] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  308.619600] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  308.619915] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  308.619918] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  308.620076] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  308.620078] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  308.620080] [drm:ironlake_fdi_link_train], FDI train done
>[  308.620083] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  308.620088] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  308.621312] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  308.621752] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  308.622557] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  308.623337] [drm:intel_dp_start_link_train], clock recovery OK
>[  308.623339] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  308.624391] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  308.626726] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  308.627785] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  308.628861] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  308.629935] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  308.647487] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  308.647498] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  308.647510] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  308.647516] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  308.647522] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  308.647528] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  308.647535] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  308.647541] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  308.647547] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  308.647553] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  308.647559] [drm:intel_modeset_check_state], [CRTC:3]
>[  308.647563] [drm:intel_modeset_check_state], [CRTC:5]
>[  311.133025] [drm:i915_driver_open], 
>[  311.133048] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  311.133059] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  311.133064] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  311.133068] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  311.133074] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  311.133078] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  311.133096] [drm:i915_driver_open], 
>[  311.133382] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  311.133393] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  311.133411] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  311.133416] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  311.133711] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  311.134533] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.157460] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.180448] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.180451] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  311.181265] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.205321] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.228834] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  311.228890] [drm:drm_edid_to_eld], ELD monitor DELL U2410
>[  311.228892] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  311.228918] [drm:drm_mode_debug_printmodeline], Modeline 125:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  311.228922] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  311.228924] [drm:drm_mode_debug_printmodeline], Modeline 123:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  311.228928] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  311.228934] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] probed modes :
>[  311.228936] [drm:drm_mode_debug_printmodeline], Modeline 12:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  311.228940] [drm:drm_mode_debug_printmodeline], Modeline 74:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  311.228944] [drm:drm_mode_debug_printmodeline], Modeline 66:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  311.228948] [drm:drm_mode_debug_printmodeline], Modeline 78:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  311.228951] [drm:drm_mode_debug_printmodeline], Modeline 77:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  311.228955] [drm:drm_mode_debug_printmodeline], Modeline 67:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  311.228959] [drm:drm_mode_debug_printmodeline], Modeline 37:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  311.228962] [drm:drm_mode_debug_printmodeline], Modeline 61:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  311.228966] [drm:drm_mode_debug_printmodeline], Modeline 65:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  311.228970] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  311.228974] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  311.228977] [drm:drm_mode_debug_printmodeline], Modeline 43:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  311.228981] [drm:drm_mode_debug_printmodeline], Modeline 36:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  311.228985] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  311.228988] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  311.228992] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  311.228995] [drm:drm_mode_debug_printmodeline], Modeline 63:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  311.228999] [drm:drm_mode_debug_printmodeline], Modeline 57:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  311.229003] [drm:drm_mode_debug_printmodeline], Modeline 55:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  311.229006] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  311.229010] [drm:drm_mode_debug_printmodeline], Modeline 38:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  311.229013] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  311.229017] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  311.229021] [drm:drm_mode_debug_printmodeline], Modeline 76:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  311.229024] [drm:drm_mode_debug_printmodeline], Modeline 68:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  311.229040] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  311.229051] [drm:drm_mode_debug_printmodeline], Modeline 51:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  311.229061] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  311.229072] [drm:drm_mode_debug_printmodeline], Modeline 62:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  311.229080] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  311.229083] [drm:drm_mode_debug_printmodeline], Modeline 46:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  311.229087] [drm:drm_mode_debug_printmodeline], Modeline 39:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  311.229090] [drm:drm_mode_debug_printmodeline], Modeline 48:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  311.229094] [drm:drm_mode_debug_printmodeline], Modeline 80:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  311.229097] [drm:drm_mode_debug_printmodeline], Modeline 50:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  311.229101] [drm:drm_mode_debug_printmodeline], Modeline 70:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  311.229104] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  311.229108] [drm:drm_mode_debug_printmodeline], Modeline 40:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  311.229112] [drm:drm_mode_debug_printmodeline], Modeline 41:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  311.229115] [drm:drm_mode_debug_printmodeline], Modeline 73:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  311.229119] [drm:drm_mode_debug_printmodeline], Modeline 42:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  311.229129] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  311.338253] [drm:drm_mode_addfb], [FB:35]
>[  311.338318] [drm:drm_mode_setcrtc], [CRTC:3]
>[  311.338324] [drm:drm_mode_setcrtc], [CONNECTOR:21:DP-1]
>[  311.338327] [drm:intel_crtc_set_config], [CRTC:3] [FB:35] #connectors=1 (x y) (0 0)
>[  311.338332] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  311.338334] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  311.338337] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  311.338342] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  311.338344] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  311.338346] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:3]
>[  311.338348] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  311.338350] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  311.338352] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  311.338353] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  311.338358] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  311.338534] [drm:intel_dp_link_down], 
>[  311.397822] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  311.446667] [drm:intel_disable_pch_pll], disable PCH PLL c6018 (active 1, on? 1) for crtc 5
>[  311.446674] [drm:intel_disable_pch_pll], disabling PCH PLL c6018
>[  311.447088] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  311.447092] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  311.447095] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  311.447098] [drm:intel_update_fbc], fbc set to per-chip default
>[  311.447100] [drm:intel_update_fbc], fbc disabled per module param
>[  311.447106] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 136750KHz
>[  311.447111] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  311.447113] [drm:intel_dp_mode_fixup], DP link bw required 328200 available 518400
>[  311.447115] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  311.447117] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  311.447126] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  311.447130] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  311.447136] [drm:ironlake_edp_backlight_off], 
>[  311.647521] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  311.647527] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  311.647531] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  312.437027] [drm:intel_dp_link_down], 
>[  312.488937] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  312.540479] [drm:intel_update_fbc], no output, disabling
>[  312.540489] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  312.540493] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  312.540496] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  312.540498] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  312.540504] [drm:intel_get_pch_pll], CRTC:3 using pre-allocated PCH PLL c6014
>[  312.540507] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  312.540509] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  312.540824] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  312.592757] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  312.592765] [drm:ironlake_update_plane], Writing base 00911000 00000000 0 0 5760
>[  312.644668] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  312.644672] [drm:intel_update_fbc], no output, disabling
>[  312.644679] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:69:1440x900]
>[  312.644684] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  312.644688] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  312.644692] [drm:ironlake_write_eld], ELD on pipe A
>[  312.644695] [drm:ironlake_write_eld], Audio directed to unknown port
>[  312.644697] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  312.644715] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  312.644719] [drm:ironlake_check_srwm], watermark 1: display plane 45, fbc lines 3, cursor 6
>[  312.644724] [drm:ironlake_check_srwm], watermark 2: display plane 148, fbc lines 4, cursor 10
>[  312.696578] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  312.748488] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  312.748804] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  312.748807] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  312.748964] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  312.748967] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  312.748969] [drm:ironlake_fdi_link_train], FDI train done
>[  312.748972] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  312.748977] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  312.750201] [drm:intel_update_fbc], fbc set to per-chip default
>[  312.750204] [drm:intel_update_fbc], fbc disabled per module param
>[  312.750644] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  312.751446] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  312.752231] [drm:intel_dp_start_link_train], clock recovery OK
>[  312.752234] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  312.753304] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  312.754360] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  312.755418] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  312.756490] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  312.757560] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  312.771393] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  312.771406] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  312.771413] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  312.771418] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  312.771425] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  312.771431] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  312.771437] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  312.771444] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  312.771450] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  312.771456] [drm:intel_modeset_check_state], [CRTC:3]
>[  312.771460] [drm:intel_modeset_check_state], [CRTC:5]
>[  312.771475] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  312.771960] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  312.772277] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  312.772282] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  312.772286] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 40000000 control abcd0000
>[  312.772295] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0008
>[  312.772299] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  313.072133] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  313.072300] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  313.072303] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  313.072307] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  313.072312] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  313.072315] [drm:intel_crt_detect], CRT not detected via hotplug
>[  313.072473] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  313.072477] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  313.072480] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  313.072482] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  313.072834] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  313.072836] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  313.072838] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  313.072841] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  313.073004] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  313.073010] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  313.073015] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  313.073303] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  313.074117] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  313.097141] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  313.120927] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  313.120930] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  313.120932] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  313.120938] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  313.120942] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  313.120947] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  313.120951] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  316.071772] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x40000000 PCH_PP_CONTROL: 0xabcd0000
>[  318.994577] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  318.994584] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [NOCRTC]
>[  318.994587] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  318.994590] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  318.994593] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  318.994770] [drm:intel_dp_link_down], 
>[  319.037656] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  319.037661] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  319.038075] [drm:intel_update_fbc], no output, disabling
>[  319.038092] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  319.038096] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  319.038100] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  319.038104] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  319.038109] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  319.038113] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  319.038118] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  319.038122] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  319.038126] [drm:intel_modeset_check_state], [CRTC:3]
>[  319.038129] [drm:intel_modeset_check_state], [CRTC:5]
>[  319.042238] [drm:intel_crtc_set_config], [CRTC:3] [FB:34] #connectors=1 (x y) (0 0)
>[  319.042245] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  319.042248] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  319.042251] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  319.042257] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  319.042264] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  319.042268] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  319.042272] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  319.042275] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  319.042278] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  319.042285] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  319.042291] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  319.042297] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  319.042301] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  319.042305] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  319.042311] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  319.042315] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  319.042318] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  319.042321] [drm:drm_mode_debug_printmodeline], Modeline 32:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  319.042334] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  319.093556] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  319.093563] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  319.093569] [drm:intel_update_fbc], no output, disabling
>[  319.093575] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:32:1366x768]
>[  319.093579] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  319.094083] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  319.094088] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  319.094092] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  319.094098] [drm:ironlake_edp_pll_on], 
>[  319.145467] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  319.197381] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  319.197386] [drm:intel_update_fbc], fbc set to per-chip default
>[  319.197388] [drm:intel_update_fbc], fbc disabled per module param
>[  319.197393] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  319.197398] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  319.197402] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  319.197415] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  319.197419] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  319.498274] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  319.498854] [drm:intel_dp_start_link_train], clock recovery OK
>[  319.498857] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  319.498860] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  319.498865] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  319.498873] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  319.498877] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  319.839284] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  319.839296] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  319.890195] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  319.891082] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  319.891229] [drm:ironlake_edp_backlight_on], 
>[  319.932061] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  319.942036] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  319.942051] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  319.942058] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  319.942063] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  319.942069] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  319.942076] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  319.942082] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  319.942088] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  319.942094] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  319.942100] [drm:intel_modeset_check_state], [CRTC:3]
>[  319.942104] [drm:intel_modeset_check_state], [CRTC:5]
>[  319.942109] [drm:intel_crtc_set_config], [CRTC:5] [FB:34] #connectors=1 (x y) (0 0)
>[  319.942116] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  319.942120] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  319.942125] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  319.942130] [drm:intel_modeset_stage_output_state], [CONNECTOR:21:DP-1] to [CRTC:5]
>[  319.942135] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  319.942139] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  319.942144] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.942153] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  319.942160] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 154000KHz
>[  319.942167] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  319.942173] [drm:intel_dp_mode_fixup], DP link bw required 369600 available 518400
>[  319.942177] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  319.942185] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  319.942190] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  319.942194] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  319.942198] [drm:drm_mode_debug_printmodeline], Modeline 33:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.942206] [drm:intel_get_pch_pll], CRTC:5 using pre-allocated PCH PLL c6018
>[  319.942211] [drm:intel_get_pch_pll], using pll 1 for pipe 1
>[  319.942215] [drm:intel_get_pch_pll], switching PLL c6018 off
>[  319.942531] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 2
>[  319.994013] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  319.994022] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 7680
>[  319.994029] [drm:intel_update_fbc], fbc set to per-chip default
>[  319.994032] [drm:intel_update_fbc], fbc disabled per module param
>[  319.994037] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  319.994042] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  319.994047] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  319.994053] [drm:intel_crtc_mode_set], [ENCODER:20:TMDS-20] set [MODE:33:1920x1200]
>[  319.994059] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[  319.994063] [drm:intel_write_eld], ELD on [CONNECTOR:21:DP-1], [ENCODER:20:TMDS-20]
>[  319.994067] [drm:ironlake_write_eld], ELD on pipe B
>[  319.994071] [drm:ironlake_write_eld], Audio directed to unknown port
>[  319.994074] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  319.994092] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  319.994096] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 9, cursor: 6
>[  320.045925] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  320.097834] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  320.098152] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  320.098155] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  320.098313] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x200
>[  320.098317] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  320.098319] [drm:ironlake_fdi_link_train], FDI train done
>[  320.098322] [drm:ironlake_enable_pch_pll], enable PCH PLL c6018 (active 0, on? 0)for crtc 5
>[  320.098328] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6018
>[  320.099553] [drm:intel_update_fbc], more than one pipe active, disabling compression
>[  320.100008] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  320.100815] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  320.101596] [drm:intel_dp_start_link_train], clock recovery OK
>[  320.101598] [drm:intel_dp_set_signal_levels], Using signal levels 02800000
>[  320.102654] [drm:intel_dp_set_signal_levels], Using signal levels 00800000
>[  320.103703] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  320.104761] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  320.105829] [drm:intel_dp_set_signal_levels], Using signal levels 00400000
>[  320.106898] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  320.124722] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  320.124733] [drm:intel_connector_check_state], [CONNECTOR:21:DP-1]
>[  320.124745] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  320.124751] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  320.124757] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  320.124763] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  320.124769] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  320.124776] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  320.124782] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  320.124789] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  320.124794] [drm:intel_modeset_check_state], [CRTC:3]
>[  320.124799] [drm:intel_modeset_check_state], [CRTC:5]
>[  320.124818] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[  320.125257] [drm:intel_dp_get_dpcd], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  320.126021] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  320.126341] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  320.126351] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  320.126508] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  320.126666] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  320.126669] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  320.126673] [drm:drm_helper_hpd_irq_event], [CONNECTOR:10:eDP-1] status updated from 1 to 1
>[  320.126677] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  320.126680] [drm:intel_crt_detect], CRT not detected via hotplug
>[  320.126837] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  320.126840] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  320.126843] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  320.126845] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  320.127198] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  320.127200] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  320.127202] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  320.127204] [drm:drm_helper_hpd_irq_event], [CONNECTOR:7:VGA-1] status updated from 2 to 2
>[  320.127361] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  320.127365] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  320.127367] [drm:drm_helper_hpd_irq_event], [CONNECTOR:19:HDMI-A-1] status updated from 2 to 2
>[  320.127648] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 00 00 00 00 00 00 00 00 00
>[  320.128454] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  320.152082] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  320.175222] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  320.175225] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  320.175228] [drm:drm_helper_hpd_irq_event], [CONNECTOR:21:DP-1] status updated from 1 to 1
>[  320.175232] [drm:drm_helper_hpd_irq_event], [CONNECTOR:23:HDMI-A-2] status updated from 2 to 2
>[  320.175236] [drm:drm_helper_hpd_irq_event], [CONNECTOR:25:HDMI-A-3] status updated from 2 to 2
>[  320.175241] [drm:drm_helper_hpd_irq_event], [CONNECTOR:27:DP-2] status updated from 2 to 2
>[  320.175245] [drm:drm_helper_hpd_irq_event], [CONNECTOR:29:DP-3] status updated from 2 to 2
>[  323.131609] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007

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