Attachment 73358 Details for Bug 59651 – dmesg of jittering mode 1920x1200

dmesg of jittering mode 1920x1200

dmesg.dp.1920x1200 (text/plain), 123.83 KB, created by cancan,feng on 2013-01-21 08:06:43 UTC

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Creator: cancan,feng

Created: 2013-01-21 08:06:43 UTC

Size: 123.83 KB

patch

obsolete

>[    6.046613] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    6.046621] i915 0000:00:02.0: registered panic notifier
>[    6.047713] i915 0000:00:02.0: More than 8 outputs detected
>[    6.061071] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.061086] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.061094] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.061557] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.061568] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.061575] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.062941] acpi device:65: registered as cooling_device9
>[    6.064299] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.064317] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.064327] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.064686] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.064700] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.064706] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.065565] acpi device:66: registered as cooling_device10
>[    6.066824] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.066838] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.066844] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.067182] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.067196] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.067202] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.068079] acpi device:67: registered as cooling_device11
>[    6.069298] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.069317] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.069323] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.069720] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.069735] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.069741] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.070613] acpi device:68: registered as cooling_device12
>[    6.071871] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.071885] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.071891] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.072229] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.072244] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.072249] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.073101] acpi device:69: registered as cooling_device13
>[    6.074353] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.074368] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.074374] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.074717] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.074726] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.074731] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.075615] acpi device:6a: registered as cooling_device14
>[    6.076841] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.076853] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.076858] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.077196] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.077205] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.077209] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.077954] acpi device:6b: registered as cooling_device15
>[    6.079229] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.079241] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.079246] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.079627] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.079636] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.079640] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.080318] acpi device:6d: registered as cooling_device16
>[    6.081443] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.081455] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.081459] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.081797] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.081806] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.081810] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.082485] acpi device:6e: registered as cooling_device17
>[    6.083643] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.083654] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.083659] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.083994] [drm:asle_set_backlight], bclp = 0x800000ff
>[    6.084003] [drm:intel_panel_get_max_backlight], max backlight PWM = 937
>[    6.084007] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[    6.084659] acpi device:6f: registered as cooling_device18
>[    6.084808] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    6.085365] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input6
>[    6.086636] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
>[    6.120945] dracut: Starting plymouth daemon
>[    6.138945] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[    6.138955] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[    6.138959] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[    6.138967] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[    6.138972] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[    6.138975] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[    6.357612] dracut: rd.dm=0: removing DM RAID activation
>[    6.370418] dracut: rd.md=0: removing MD RAID activation
>[    6.608680] pata_acpi 0000:00:16.2: enabling device (0000 -> 0001)
>[    6.608841] pata_acpi 0000:00:16.2: setting latency timer to 64
>[    6.625801] sd 1:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB)
>[    6.626191] sd 1:0:0:0: [sda] Write Protect is off
>[    6.626205] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    6.626316] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    6.631165]  sda: sda1 sda2
>[    6.639221] sd 1:0:0:0: [sda] Attached SCSI disk
>[    6.864146] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
>[    6.904207] dracut: Checking ext4: /dev/disk/by-uuid/7de86781-daac-4fdf-b2a5-4a78c03d8a55
>[    6.904333] dracut: issuing e2fsck -a  /dev/disk/by-uuid/7de86781-daac-4fdf-b2a5-4a78c03d8a55
>[    6.914347] dracut: /dev/disk/by-uuid/7de86781-daac-4fdf-b2a5-4a78c03d8a55: clean, 1990120/7077888 files, 23322265/28280832 blocks
>[    6.914973] dracut: Remounting /dev/disk/by-uuid/7de86781-daac-4fdf-b2a5-4a78c03d8a55 with -o ro
>[    6.926125] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
>[    6.932194] dracut: Mounted root filesystem /dev/sda2
>[    7.009459] dracut: Switching root
>[    7.076440] systemd[1]: systemd 36 running in system mode. (+PAM +LIBWRAP +AUDIT +SELINUX +SYSVINIT +LIBCRYPTSETUP; fedora)
>[    7.102515] NET: Registered protocol family 10
>[    7.106169] systemd[1]: Set hostname to <x-hswu21>.
>[    7.260739] systemd-readahead-replay[1879]: Bumped block_nr parameter of 8:0 to 16384. This is a temporary hack and should be removed one day.
>[    7.277850] systemd-readahead-collect[1880]: Failed to create fanotify object: Function not implemented
>[    7.392570] udevd[1894]: starting version 173
>[    7.457050] systemd[1]: systemd-readahead-collect.service: main process exited, code=exited, status=1
>[    7.591823] EXT4-fs (sda2): re-mounted. Opts: (null)
>[    7.738244] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    7.742286] ACPI: AC Adapter [ADP1] (on-line)
>[    7.855862] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    7.855906] ACPI: Battery Slot [BAT0] (battery present)
>[    7.856158] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    7.856184] ACPI: Battery Slot [BAT1] (battery absent)
>[    7.857626] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    7.857689] ACPI: Battery Slot [BAT2] (battery absent)
>[    8.060986] e1000e: Intel(R) PRO/1000 Network Driver - 2.1.4-k
>[    8.060997] e1000e: Copyright(c) 1999 - 2012 Intel Corporation.
>[    8.061487] e1000e 0000:00:19.0: setting latency timer to 64
>[    8.064657] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
>[    8.068256] e1000e 0000:00:19.0: irq 59 for MSI/MSI-X
>[    8.145373] input: PC Speaker as /devices/platform/pcspkr/input/input7
>[    8.199458] microcode: CPU0 sig=0x40650, pf=0x40, revision=0xffff0007
>[    8.247760] sd 1:0:0:0: Attached scsi generic sg0 type 0
>[    8.252486] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:13:20:fc:d2:d9
>[    8.252498] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection
>[    8.252780] e1000e 0000:00:19.0 eth0: MAC: 11, PHY: 12, PBA No: FFFFFF-0FF
>[    8.252906] ACPI Warning: 0x000000000000efa0-0x000000000000efbf SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20121018/utaddress-251)
>[    8.252931] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    8.261879] ACPI Warning: 0x0000000000001828-0x000000000000182f SystemIO conflicts with Region \PMIO 1 (20121018/utaddress-251)
>[    8.261909] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    8.261925] ACPI Warning: 0x0000000000000830-0x000000000000083f SystemIO conflicts with Region \GPR_ 1 (20121018/utaddress-251)
>[    8.261946] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    8.261954] ACPI Warning: 0x0000000000000800-0x000000000000082f SystemIO conflicts with Region \GPR_ 1 (20121018/utaddress-251)
>[    8.261972] ACPI Warning: 0x0000000000000800-0x000000000000082f SystemIO conflicts with Region \IO_D 2 (20121018/utaddress-251)
>[    8.261991] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    8.261999] lpc_ich: Resource conflict(s) found affecting gpio_ich
>[    8.268726] mtp-probe[2698]: checking bus 2, device 2: "/sys/devices/pci0000:00/0000:00:14.0/usb2/2-1"
>[    8.269438] snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X
>[    8.310440] udev-configure-printer[2735]: add /module/lpc_ich
>[    8.319159] udev-configure-printer[2735]: Failed to get parent
>[    8.340161] mtp-probe[2698]: bus: 2, device: 2 was not an MTP device
>[    8.393262] microcode: CPU1 sig=0x40650, pf=0x40, revision=0xffff0007
>[    8.433502] udev-configure-printer[2796]: add /bus/pci/drivers/lpc_ich
>[    8.434703] udev-configure-printer[2796]: Failed to get parent
>[    8.444356] iTCO_vendor_support: vendor-support=0
>[    8.445965] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.10
>[    8.446119] iTCO_wdt: Found a Lynx Point_LP TCO device (Version=2, TCOBASE=0x1860)
>[    8.453702] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>[    8.503877] microcode: CPU2 sig=0x40650, pf=0x40, revision=0xffff0007
>[    8.515866] microcode: CPU3 sig=0x40650, pf=0x40, revision=0xffff0007
>[    8.527081] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[    8.533641] Adding 4095996k swap on /dev/sda1.  Priority:0 extents:1 across:4095996k SS
>[   11.285552] ALSA sound/pci/hda/hda_intel.c:911 0000:00:03.0: azx_get_response timeout, switching to polling mode: last cmd=0x000f0000
>[   12.287191] ALSA sound/pci/hda/hda_intel.c:919 0000:00:03.0: No response from codec, disabling MSI: last cmd=0x000f0000
>[   13.288830] ALSA sound/pci/hda/hda_intel.c:1678 0000:00:03.0: Codec #0 probe error; disabling it...
>[   14.292463] ALSA sound/pci/hda/hda_intel.c:950 hda_intel: azx_get_response timeout, switching to single_cmd mode: last cmd=0x000f0001
>[   14.390446] rmmod[2874]: ERROR: Module scsi_wait_scan does not exist in /proc/modules
>[   14.411119] modprobe[2876]: FATAL: Module scsi_wait_scan not found.
>[   14.429402] rmmod[2878]: ERROR: Module scsi_wait_scan does not exist in /proc/modules
>[   14.524880] fedora-storage-init[2880]: Setting up Logical Volume Management:   No volume groups found
>[   14.526058] fedora-storage-init[2880]: [  OK  ]
>[   14.611637] fedora-storage-init[2886]: Setting up Logical Volume Management:   No volume groups found
>[   14.613021] fedora-storage-init[2886]: [  OK  ]
>[   14.660108] lvm[2892]: No volume groups found
>[   14.811213] alsactl[2900]: /sbin/alsactl: set_control:1403: Cannot write control '3:3:0:Playback Channel Map:0' : File descriptor in bad state
>[   14.811253] alsactl[2900]: /sbin/alsactl: set_control:1403: Cannot write control '3:7:0:Playback Channel Map:0' : File descriptor in bad state
>[   14.811283] alsactl[2900]: /sbin/alsactl: set_control:1403: Cannot write control '3:8:0:Playback Channel Map:0' : File descriptor in bad state
>[   14.866274] watchdog[2910]: starting daemon (5.9):
>[   14.866313] watchdog[2910]: int=1s realtime=yes sync=no soft=no mla=0 mem=0
>[   14.866343] watchdog[2910]: ping: no machine to check
>[   14.866370] watchdog[2910]: file: no file to check
>[   14.866396] watchdog[2910]: pidfile: no server process to check
>[   14.866422] watchdog[2910]: interface: no interface to check
>[   14.866451] watchdog[2910]: test=none(0) repair=none(0) alive=/dev/watchdog heartbeat=none temp=none to=root no_act=no
>[   14.866630] watchdog[2910]: hardware wartchdog identity: iTCO_wdt
>[   14.870958] watchdog[2910]: cannot set scheduler (errno = 1 = 'Operation not permitted')
>[   14.871039] watchdog (2910): /proc/2910/oom_adj is deprecated, please use /proc/2910/oom_score_adj instead.
>[   14.907078] /usr/sbin/gpm[2926]: *** info [daemon/startup.c(136)]:
>[   14.907146] /usr/sbin/gpm[2926]: Started gpm successfully. Entered daemon mode.
>[   14.947503] auditd[2927]: Started dispatcher: /sbin/audispd pid: 2930
>[   14.949823] audispd[2930]: priority_boost_parser called with: 4
>[   14.949859] audispd[2930]: max_restarts_parser called with: 10
>[   14.950619] audispd[2930]: audispd initialized with q_depth=120 and 1 active plugins
>[   14.966461] auditctl[2928]: No rules
>[   14.966499] auditctl[2928]: AUDIT_STATUS: enabled=0 flag=1 pid=2927 rate_limit=0 backlog_limit=320 lost=0 backlog=0
>[   15.039706] NetworkManager[2946]: <info> NetworkManager (version 0.9.1.90-5.git20110927.fc16) is starting...
>[   15.039745] NetworkManager[2946]: <info> Read config file /etc/NetworkManager/NetworkManager.conf
>[   15.039775] NetworkManager[2946]: NetworkManager[2946]: <info> NetworkManager (version 0.9.1.90-5.git20110927.fc16) is starting...
>[   15.039802] NetworkManager[2946]: NetworkManager[2946]: <info> Read config file /etc/NetworkManager/NetworkManager.conf
>[   15.050991] auditd[2927]: Init complete, auditd 2.1.3 listening for events (startup state enable)
>[   15.052481] acpid[2951]: starting up with proc fs
>[   15.052906] acpid[2951]: skipping incomplete file /etc/acpi/events/videoconf
>[   15.053086] acpid[2951]: 1 rule loaded
>[   15.053322] acpid[2951]: waiting for events: event logging is off
>[   15.183275] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183287] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183291] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183301] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183306] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183310] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183314] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[   15.183319] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183323] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183330] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183335] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183339] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183344] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183348] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183352] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183374] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183379] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183383] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.183387] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   15.183392] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   15.183395] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   15.217187] avahi-daemon[2962]: Found user 'avahi' (UID 70) and group 'avahi' (GID 70).
>[   15.217441] avahi-daemon[2962]: Successfully dropped root privileges.
>[   15.218113] avahi-daemon[2962]: avahi-daemon 0.6.30 starting up.
>[   15.219817] avahi-daemon[2962]: WARNING: No NSS support for mDNS detected, consider installing nss-mdns!
>[   15.309414] mcelog[2968]: mcelog: Unsupported new Family 6 Model 45 CPU: only decoding architectural errors
>[   15.377086] /usr/sbin/crond[2970]: (CRON) INFO (running with inotify support)
>[   15.409405] dbus[2972]: [system] Activating systemd to hand-off: service name='org.freedesktop.NetworkManager' unit='dbus-org.freedesktop.NetworkManager.service'
>[   15.409448] dbus-daemon[2972]: dbus[2972]: [system] Activating systemd to hand-off: service name='org.freedesktop.NetworkManager' unit='dbus-org.freedesktop.NetworkManager.service'
>[   15.410455] abrtd[2949]: Init complete, entering main loop
>[   15.412338] avahi-daemon[2962]: Successfully called chroot().
>[   15.412377] NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.openvpn
>[   15.412406] avahi-daemon[2962]: Successfully dropped remaining capabilities.
>[   15.412437] NetworkManager[2946]: NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.openvpn
>[   15.412465] NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.pptp
>[   15.412492] NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.vpnc
>[   15.417089] NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.openconnect
>[   15.418669] avahi-daemon[2962]: Loading service file /services/ssh.service.
>[   15.418707] avahi-daemon[2962]: Loading service file /services/udisks.service.
>[   15.418737] NetworkManager[2946]: NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.pptp
>[   15.418765] NetworkManager[2946]: NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.vpnc
>[   15.418794] NetworkManager[2946]: NetworkManager[2946]: <info> VPN: loaded org.freedesktop.NetworkManager.openconnect
>[   15.418817] avahi-daemon[2962]: Network interface enumeration completed.
>[   15.418845] avahi-daemon[2962]: Registering HINFO record with values 'X86_64'/'LINUX'.
>[   15.418873] avahi-daemon[2962]: Server startup complete. Host name is x-hswu21.local. Local service cookie is 4263724550.
>[   15.418901] avahi-daemon[2962]: Service "x-hswu21" (/services/udisks.service) successfully established.
>[   15.418983] avahi-daemon[2962]: Service "x-hswu21" (/services/ssh.service) successfully established.
>[   15.419014] dbus-daemon[2972]: dbus[2972]: [system] Successfully activated service 'org.freedesktop.systemd1'
>[   15.419042] dbus[2972]: [system] Successfully activated service 'org.freedesktop.systemd1'
>[   15.419070] systemd-logind[2961]: New seat seat0.
>[   15.426574] dbus[2972]: [system] Activating service name='org.freedesktop.PolicyKit1' (using servicehelper)
>[   15.426783] dbus-daemon[2972]: dbus[2972]: [system] Activating service name='org.freedesktop.PolicyKit1' (using servicehelper)
>[   15.642909] e1000e 0000:00:19.0: irq 59 for MSI/MSI-X
>[   15.744178] e1000e 0000:00:19.0: irq 59 for MSI/MSI-X
>[   15.744651] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
>[   17.247492] e1000e: eth1 NIC Link is Up 100 Mbps Full Duplex, Flow Control: Rx/Tx
>[   17.247507] e1000e 0000:00:19.0 eth1: 10/100 speed: disabling TSO
>[   17.247663] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
>[   82.547080] [drm:i915_driver_open], 
>[   82.547490] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[   82.547505] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   82.547512] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   82.547520] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   82.547528] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   82.547534] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   82.547540] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[   82.547546] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   82.547552] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[   82.547566] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[   82.547573] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[   82.547584] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[   82.547590] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[   82.547600] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[   82.547606] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[   82.547674] [drm:i915_driver_open], 
>[   82.548114] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[   82.548181] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[   82.548209] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[   82.548223] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1]
>[   82.548722] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[   82.549726] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.576997] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.604263] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.604275] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[   82.605325] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.632580] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.659898] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[   82.660302] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[   82.660310] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[   82.660796] [drm:drm_mode_debug_printmodeline], Modeline 173:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[   82.660811] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[   82.660821] [drm:drm_mode_debug_printmodeline], Modeline 170:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[   82.660834] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[   82.660860] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1] probed modes :
>[   82.660868] [drm:drm_mode_debug_printmodeline], Modeline 12:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[   82.660882] [drm:drm_mode_debug_printmodeline], Modeline 88:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[   82.660894] [drm:drm_mode_debug_printmodeline], Modeline 35:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[   82.660907] [drm:drm_mode_debug_printmodeline], Modeline 80:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[   82.660919] [drm:drm_mode_debug_printmodeline], Modeline 79:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[   82.660931] [drm:drm_mode_debug_printmodeline], Modeline 78:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[   82.660943] [drm:drm_mode_debug_printmodeline], Modeline 87:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[   82.660956] [drm:drm_mode_debug_printmodeline], Modeline 82:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[   82.660968] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[   82.660980] [drm:drm_mode_debug_printmodeline], Modeline 34:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[   82.660992] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   82.661004] [drm:drm_mode_debug_printmodeline], Modeline 89:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   82.661017] [drm:drm_mode_debug_printmodeline], Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   82.661029] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   82.661042] [drm:drm_mode_debug_printmodeline], Modeline 90:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   82.661054] [drm:drm_mode_debug_printmodeline], Modeline 74:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   82.661066] [drm:drm_mode_debug_printmodeline], Modeline 73:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   82.661079] [drm:drm_mode_debug_printmodeline], Modeline 72:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   82.661091] [drm:drm_mode_debug_printmodeline], Modeline 71:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   82.661103] [drm:drm_mode_debug_printmodeline], Modeline 33:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   82.661115] [drm:drm_mode_debug_printmodeline], Modeline 77:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[   82.661127] [drm:drm_mode_debug_printmodeline], Modeline 76:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[   82.661139] [drm:drm_mode_debug_printmodeline], Modeline 75:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   82.661152] [drm:drm_mode_debug_printmodeline], Modeline 86:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[   82.661164] [drm:drm_mode_debug_printmodeline], Modeline 67:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[   82.661177] [drm:drm_mode_debug_printmodeline], Modeline 66:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[   82.661189] [drm:drm_mode_debug_printmodeline], Modeline 65:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[   82.661201] [drm:drm_mode_debug_printmodeline], Modeline 85:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[   82.661214] [drm:drm_mode_debug_printmodeline], Modeline 63:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[   82.661226] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   82.661239] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   82.661251] [drm:drm_mode_debug_printmodeline], Modeline 70:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[   82.661263] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   82.661276] [drm:drm_mode_debug_printmodeline], Modeline 68:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   82.661288] [drm:drm_mode_debug_printmodeline], Modeline 62:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[   82.661300] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   82.661313] [drm:drm_mode_debug_printmodeline], Modeline 84:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[   82.661325] [drm:drm_mode_debug_printmodeline], Modeline 64:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[   82.661337] [drm:drm_mode_debug_printmodeline], Modeline 60:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[   82.661349] [drm:drm_mode_debug_printmodeline], Modeline 59:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[   82.661361] [drm:drm_mode_debug_printmodeline], Modeline 31:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[   82.661374] [drm:drm_mode_debug_printmodeline], Modeline 30:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   82.661386] [drm:drm_mode_debug_printmodeline], Modeline 58:"1280x768" 85 117500 1280 1360 1496 1712 768 771 778 809 0x40 0x6
>[   82.661398] [drm:drm_mode_debug_printmodeline], Modeline 57:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[   82.661410] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[   82.661423] [drm:drm_mode_debug_printmodeline], Modeline 101:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   82.661435] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   82.661447] [drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40 0x5
>[   82.661460] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   82.661472] [drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   82.661484] [drm:drm_mode_debug_printmodeline], Modeline 42:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   82.661497] [drm:drm_mode_debug_printmodeline], Modeline 53:"1024x768i" 86 44900 1024 1032 1208 1264 768 768 772 817 0x40 0x15
>[   82.661509] [drm:drm_mode_debug_printmodeline], Modeline 83:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[   82.661521] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
>[   82.661533] [drm:drm_mode_debug_printmodeline], Modeline 50:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   82.661546] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   82.661558] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   82.661570] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   82.661582] [drm:drm_mode_debug_printmodeline], Modeline 99:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   82.661594] [drm:drm_mode_debug_printmodeline], Modeline 52:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[   82.661639] [drm:drm_mode_debug_printmodeline], Modeline 93:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   82.661652] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
>[   82.661664] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   82.661686] [drm:drm_mode_debug_printmodeline], Modeline 37:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   82.661712] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   82.661734] [drm:drm_mode_debug_printmodeline], Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   82.661755] [drm:drm_mode_debug_printmodeline], Modeline 46:"720x400" 85 35500 720 756 828 936 400 401 404 446 0x40 0x6
>[   82.661778] [drm:drm_mode_debug_printmodeline], Modeline 39:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   82.661798] [drm:drm_mode_debug_printmodeline], Modeline 45:"640x400" 85 31500 640 672 736 832 400 401 404 445 0x40 0x6
>[   82.661820] [drm:drm_mode_debug_printmodeline], Modeline 44:"640x350" 85 31500 640 672 736 832 350 382 385 445 0x40 0x9
>[   82.661869] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[   82.953463] [drm:drm_mode_addfb], [FB:29]
>[   82.953740] [drm:drm_mode_setcrtc], [CRTC:3]
>[   82.953760] [drm:drm_mode_setcrtc], [CONNECTOR:20:DP-1]
>[   82.953767] [drm:intel_crtc_set_config], [CRTC:3] [FB:29] #connectors=1 (x y) (0 0)
>[   82.953776] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[   82.953781] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   82.953790] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[   82.953799] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   82.953804] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   82.953810] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:3]
>[   82.953815] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   82.953820] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   82.953824] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[   82.953828] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[   82.953837] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   82.985640] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[   82.985675] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 281250KHz
>[   82.985690] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[   82.985697] [drm:intel_dp_mode_fixup], DP link bw required 675000 available 864000
>[   82.985703] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[   82.985710] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   82.985725] [drm:ironlake_edp_backlight_off], 
>[   83.204562] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   83.204602] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000b
>[   83.204614] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   83.204631] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   83.204644] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   84.040271] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[   84.040283] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[   84.040289] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[   84.040295] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[   84.049871] [drm:ironlake_update_plane], Writing base 01014000 00000000 0 0 7680
>[   84.101207] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   84.101230] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:92:1920x1200]
>[   84.101239] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe A
>[   84.101245] [drm:intel_ddi_mode_set], DP audio on pipe A on DDI
>[   84.101250] [drm:intel_ddi_mode_set], DP audio: write eld information
>[   84.101257] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[   84.101264] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[   84.101269] [drm:haswell_write_eld], HDMI audio: enable codec
>[   84.153215] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   84.153227] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      54
>[   84.153235] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[   84.153240] [drm:haswell_write_eld], HDMI audio: audio conf: 0x  70fa60
>[   84.153246] [drm:haswell_write_eld], ELD on pipe A
>[   84.153252] [drm:haswell_write_eld], ELD: DisplayPort detected
>[   84.153261] [drm:haswell_write_eld], port num:0
>[   84.153266] [drm:haswell_write_eld], ELD size 9
>[   84.153282] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 15, cursor: 6
>[   84.154516] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   84.155358] [drm:intel_dp_start_link_train], clock recovery OK
>[   84.155368] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   84.156478] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[   84.182098] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[   84.182111] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[   84.182121] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[   84.182130] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[   84.182138] [drm:intel_modeset_check_state], [CRTC:3]
>[   84.182146] [drm:intel_modeset_check_state], [CRTC:5]
>[   84.182154] [drm:intel_modeset_check_state], [CRTC:7]
>[  142.463504] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  142.463520] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [NOCRTC]
>[  142.463526] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  142.463532] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  142.463538] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  142.479147] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  142.479159] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  142.479166] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  142.479171] [drm:intel_modeset_check_state], [CRTC:3]
>[  142.479176] [drm:intel_modeset_check_state], [CRTC:5]
>[  142.479181] [drm:intel_modeset_check_state], [CRTC:7]
>[  142.480087] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  142.480105] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  142.480112] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  142.480117] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  142.480127] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  142.480135] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  142.480141] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  142.480147] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  142.480152] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  142.480156] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  142.480165] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  142.480184] [drm:intel_dp_mode_fixup], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  142.480197] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  142.480203] [drm:intel_dp_mode_fixup], DP link bw required 333072 available 432000
>[  142.480209] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  142.480222] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 8
>[  142.480228] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was 8) to eDP (6)
>[  142.480233] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  142.480238] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  142.480253] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  142.480282] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  142.480307] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:26:1920x1080]
>[  142.480323] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port A, pipe A
>[  142.480337] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  142.480351] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  142.480371] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  142.480384] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  142.480415] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  142.480425] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  142.681087] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  142.681104] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  142.681118] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  142.681143] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  142.681156] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b
>[  142.889974] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  142.890011] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  142.942115] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  142.942848] [drm:intel_dp_start_link_train], clock recovery OK
>[  142.942869] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  142.943882] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  142.945839] [drm:intel_dp_set_link_train] *ERROR* Timed out waiting for DP idle patterns
>[  142.946017] [drm:i915_write32] *ERROR* Unknown unclaimed register before writing to 64040
>[  142.981826] [drm:ironlake_edp_backlight_on], 
>[  142.983843] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[  142.997864] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  142.997878] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  142.997888] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  142.997897] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  142.997905] [drm:intel_modeset_check_state], [CRTC:3]
>[  142.997914] [drm:intel_modeset_check_state], [CRTC:5]
>[  142.997921] [drm:intel_modeset_check_state], [CRTC:7]
>[  142.997934] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  142.997946] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  142.997955] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  142.997964] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  142.997973] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  142.997982] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  142.997989] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  142.997997] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  142.998012] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  142.998029] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[  142.998047] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  142.998056] [drm:intel_dp_mode_fixup], DP link bw required 644400 available 864000
>[  142.998065] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  142.998083] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  142.998092] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  142.998100] [drm:haswell_crtc_mode_set], Mode for pipe 1:
>[  142.998107] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  142.998137] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  142.998153] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  142.998167] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:27:2560x1600]
>[  142.998176] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe B
>[  142.998184] [drm:intel_ddi_mode_set], DP audio on pipe B on DDI
>[  142.998191] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  142.998200] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  142.998210] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  142.998217] [drm:haswell_write_eld], HDMI audio: enable codec
>[  143.049795] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  143.049804] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  143.049813] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  143.049821] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  143.049830] [drm:haswell_write_eld], ELD on pipe B
>[  143.049837] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  143.049851] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  143.049860] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  143.050984] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  143.051811] [drm:intel_dp_start_link_train], clock recovery OK
>[  143.051820] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  143.052924] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  143.106783] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  143.106797] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  143.106808] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  143.106817] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  143.106826] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  143.106835] [drm:intel_modeset_check_state], [CRTC:3]
>[  143.106843] [drm:intel_modeset_check_state], [CRTC:5]
>[  143.106850] [drm:intel_modeset_check_state], [CRTC:7]
>[  143.106862] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  143.106872] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  143.106881] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  143.106897] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  143.106906] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  143.106920] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  143.106929] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  143.106943] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  143.106952] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  154.199663] [drm:i915_driver_open], 
>[  154.199738] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  154.199797] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  154.199814] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  154.199830] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  154.199838] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  154.199844] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  154.199851] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  154.199857] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  154.199863] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  154.199877] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  154.199884] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  154.199894] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  154.199901] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  154.199911] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  154.199918] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  154.199953] [drm:i915_driver_open], 
>[  154.200389] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  154.200417] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  154.200443] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  154.200453] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1]
>[  154.201001] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[  154.202250] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.229528] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.256798] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.256809] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  154.257801] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.285055] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.312297] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  154.312629] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[  154.312638] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  154.313059] [drm:drm_mode_debug_printmodeline], Modeline 173:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  154.313070] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  154.313077] [drm:drm_mode_debug_printmodeline], Modeline 170:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  154.313085] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  154.313106] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1] probed modes :
>[  154.313112] [drm:drm_mode_debug_printmodeline], Modeline 12:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  154.313121] [drm:drm_mode_debug_printmodeline], Modeline 88:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  154.313128] [drm:drm_mode_debug_printmodeline], Modeline 35:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  154.313136] [drm:drm_mode_debug_printmodeline], Modeline 80:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  154.313143] [drm:drm_mode_debug_printmodeline], Modeline 79:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  154.313150] [drm:drm_mode_debug_printmodeline], Modeline 78:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  154.313158] [drm:drm_mode_debug_printmodeline], Modeline 87:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  154.313165] [drm:drm_mode_debug_printmodeline], Modeline 82:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  154.313173] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  154.313180] [drm:drm_mode_debug_printmodeline], Modeline 34:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  154.313188] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  154.313195] [drm:drm_mode_debug_printmodeline], Modeline 89:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  154.313202] [drm:drm_mode_debug_printmodeline], Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  154.313209] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  154.313217] [drm:drm_mode_debug_printmodeline], Modeline 90:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  154.313224] [drm:drm_mode_debug_printmodeline], Modeline 74:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  154.313232] [drm:drm_mode_debug_printmodeline], Modeline 73:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  154.313239] [drm:drm_mode_debug_printmodeline], Modeline 72:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  154.313246] [drm:drm_mode_debug_printmodeline], Modeline 71:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  154.313253] [drm:drm_mode_debug_printmodeline], Modeline 33:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  154.313260] [drm:drm_mode_debug_printmodeline], Modeline 77:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  154.313267] [drm:drm_mode_debug_printmodeline], Modeline 76:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  154.313274] [drm:drm_mode_debug_printmodeline], Modeline 75:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  154.313282] [drm:drm_mode_debug_printmodeline], Modeline 86:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  154.313289] [drm:drm_mode_debug_printmodeline], Modeline 67:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  154.313296] [drm:drm_mode_debug_printmodeline], Modeline 66:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  154.313303] [drm:drm_mode_debug_printmodeline], Modeline 65:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  154.313310] [drm:drm_mode_debug_printmodeline], Modeline 85:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  154.313317] [drm:drm_mode_debug_printmodeline], Modeline 63:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  154.313324] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  154.313332] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  154.313339] [drm:drm_mode_debug_printmodeline], Modeline 70:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  154.313346] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  154.313353] [drm:drm_mode_debug_printmodeline], Modeline 68:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  154.313360] [drm:drm_mode_debug_printmodeline], Modeline 62:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  154.313368] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  154.313375] [drm:drm_mode_debug_printmodeline], Modeline 84:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  154.313382] [drm:drm_mode_debug_printmodeline], Modeline 64:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  154.313389] [drm:drm_mode_debug_printmodeline], Modeline 60:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  154.313396] [drm:drm_mode_debug_printmodeline], Modeline 59:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  154.313403] [drm:drm_mode_debug_printmodeline], Modeline 31:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  154.313411] [drm:drm_mode_debug_printmodeline], Modeline 30:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  154.313418] [drm:drm_mode_debug_printmodeline], Modeline 58:"1280x768" 85 117500 1280 1360 1496 1712 768 771 778 809 0x40 0x6
>[  154.313425] [drm:drm_mode_debug_printmodeline], Modeline 57:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  154.313432] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  154.313439] [drm:drm_mode_debug_printmodeline], Modeline 101:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  154.313447] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  154.313454] [drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40 0x5
>[  154.313461] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  154.313469] [drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  154.313476] [drm:drm_mode_debug_printmodeline], Modeline 42:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  154.313483] [drm:drm_mode_debug_printmodeline], Modeline 53:"1024x768i" 86 44900 1024 1032 1208 1264 768 768 772 817 0x40 0x15
>[  154.313490] [drm:drm_mode_debug_printmodeline], Modeline 83:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  154.313497] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
>[  154.313505] [drm:drm_mode_debug_printmodeline], Modeline 50:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  154.313512] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  154.313519] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  154.313527] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  154.313534] [drm:drm_mode_debug_printmodeline], Modeline 99:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  154.313541] [drm:drm_mode_debug_printmodeline], Modeline 52:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  154.313548] [drm:drm_mode_debug_printmodeline], Modeline 93:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  154.313555] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
>[  154.313562] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  154.313570] [drm:drm_mode_debug_printmodeline], Modeline 37:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  154.313576] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  154.313584] [drm:drm_mode_debug_printmodeline], Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  154.313591] [drm:drm_mode_debug_printmodeline], Modeline 46:"720x400" 85 35500 720 756 828 936 400 401 404 446 0x40 0x6
>[  154.313598] [drm:drm_mode_debug_printmodeline], Modeline 39:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  154.313605] [drm:drm_mode_debug_printmodeline], Modeline 45:"640x400" 85 31500 640 672 736 832 400 401 404 445 0x40 0x6
>[  154.313612] [drm:drm_mode_debug_printmodeline], Modeline 44:"640x350" 85 31500 640 672 736 832 350 382 385 445 0x40 0x9
>[  154.313643] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  154.587855] [drm:drm_mode_addfb], [FB:29]
>[  154.588056] [drm:drm_mode_setcrtc], [CRTC:3]
>[  154.588074] [drm:drm_mode_setcrtc], [CONNECTOR:20:DP-1]
>[  154.588081] [drm:intel_crtc_set_config], [CRTC:3] [FB:29] #connectors=1 (x y) (0 0)
>[  154.588091] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  154.588096] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  154.588105] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  154.588114] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  154.588120] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  154.588126] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:3]
>[  154.588131] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  154.588136] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  154.588141] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  154.588145] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  154.588154] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  154.607754] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  154.607787] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 281250KHz
>[  154.607804] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  154.607810] [drm:intel_dp_mode_fixup], DP link bw required 675000 available 864000
>[  154.607816] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  154.607823] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  154.607837] [drm:ironlake_edp_backlight_off], 
>[  154.826671] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  154.826710] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000b
>[  154.826722] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  154.826738] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  154.826751] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  155.607405] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  155.607418] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  155.607424] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  155.607429] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  155.616831] [drm:ironlake_update_plane], Writing base 01014000 00000000 0 0 7680
>[  155.668376] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  155.668424] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:92:1920x1200]
>[  155.668435] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe A
>[  155.668440] [drm:intel_ddi_mode_set], DP audio on pipe A on DDI
>[  155.668445] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  155.668452] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  155.668459] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  155.668463] [drm:haswell_write_eld], HDMI audio: enable codec
>[  155.720332] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  155.720343] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  155.720352] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  155.720357] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  155.720363] [drm:haswell_write_eld], ELD on pipe A
>[  155.720369] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  155.720384] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 15, cursor: 6
>[  155.721612] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  155.722459] [drm:intel_dp_start_link_train], clock recovery OK
>[  155.722468] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  155.723585] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  155.761218] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  155.761230] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  155.761240] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  155.761249] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  155.761257] [drm:intel_modeset_check_state], [CRTC:3]
>[  155.761265] [drm:intel_modeset_check_state], [CRTC:5]
>[  155.761273] [drm:intel_modeset_check_state], [CRTC:7]
>[  159.374815] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  159.374832] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [NOCRTC]
>[  159.374839] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  159.374846] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  159.374853] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  159.399018] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  159.399030] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  159.399037] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  159.399042] [drm:intel_modeset_check_state], [CRTC:3]
>[  159.399047] [drm:intel_modeset_check_state], [CRTC:5]
>[  159.399052] [drm:intel_modeset_check_state], [CRTC:7]
>[  159.399633] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  159.399644] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  159.399650] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  159.399655] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  159.399664] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  159.399673] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  159.399679] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  159.399685] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  159.399690] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  159.399695] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  159.399704] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  159.399718] [drm:intel_dp_mode_fixup], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  159.399733] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  159.399739] [drm:intel_dp_mode_fixup], DP link bw required 333072 available 432000
>[  159.399745] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  159.399759] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 8
>[  159.399765] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was 8) to eDP (6)
>[  159.399770] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  159.399775] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  159.399780] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  159.399803] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  159.399819] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:26:1920x1080]
>[  159.399826] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port A, pipe A
>[  159.399834] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  159.399842] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  159.399855] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  159.399920] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  159.399955] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  159.399973] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  159.600929] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  159.600945] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  159.600959] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  159.600983] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  159.600996] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b
>[  159.809854] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  159.809891] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  159.861990] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.862689] [drm:intel_dp_start_link_train], clock recovery OK
>[  159.862731] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.863767] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  159.865723] [drm:intel_dp_set_link_train] *ERROR* Timed out waiting for DP idle patterns
>[  159.865901] [drm:i915_write32] *ERROR* Unknown unclaimed register before writing to 64040
>[  159.901708] [drm:ironlake_edp_backlight_on], 
>[  159.903726] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[  159.917711] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  159.917725] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  159.917735] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  159.917744] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  159.917753] [drm:intel_modeset_check_state], [CRTC:3]
>[  159.917761] [drm:intel_modeset_check_state], [CRTC:5]
>[  159.917769] [drm:intel_modeset_check_state], [CRTC:7]
>[  159.917782] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  159.917794] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  159.917803] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  159.917811] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  159.917821] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  159.917829] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  159.917837] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  159.917845] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  159.917860] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  159.917877] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[  159.917895] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  159.917905] [drm:intel_dp_mode_fixup], DP link bw required 644400 available 864000
>[  159.917913] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  159.917931] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  159.917940] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  159.917948] [drm:haswell_crtc_mode_set], Mode for pipe 1:
>[  159.917956] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  159.917986] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  159.918002] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  159.918017] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:27:2560x1600]
>[  159.918026] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe B
>[  159.918035] [drm:intel_ddi_mode_set], DP audio on pipe B on DDI
>[  159.918042] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  159.918051] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  159.918061] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  159.918068] [drm:haswell_write_eld], HDMI audio: enable codec
>[  159.969797] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  159.969809] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  159.969817] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  159.969822] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  159.969828] [drm:haswell_write_eld], ELD on pipe B
>[  159.969834] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  159.969848] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  159.969855] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  159.971064] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.971878] [drm:intel_dp_start_link_train], clock recovery OK
>[  159.971888] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.973002] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  160.026671] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  160.026686] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  160.026697] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  160.026707] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  160.026717] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  160.026725] [drm:intel_modeset_check_state], [CRTC:3]
>[  160.026733] [drm:intel_modeset_check_state], [CRTC:5]
>[  160.026741] [drm:intel_modeset_check_state], [CRTC:7]
>[  160.026754] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  160.026766] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  160.026775] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  160.026791] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  160.026801] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  160.026814] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  160.026824] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  160.026838] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  160.026847] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  179.756723] [drm:i915_driver_open], 
>[  179.756796] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  179.756809] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  179.756817] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  179.756825] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  179.756833] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  179.756839] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  179.756845] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  179.756852] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  179.756857] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  179.756871] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  179.756878] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  179.756889] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  179.756895] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  179.756906] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  179.756912] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  179.756943] [drm:i915_driver_open], 
>[  179.757365] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  179.757392] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  179.757418] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  179.757428] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1]
>[  179.757898] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[  179.758937] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.786237] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.813513] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.813524] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  179.814524] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.841794] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.869063] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  179.869401] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[  179.869409] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  179.869893] [drm:drm_mode_debug_printmodeline], Modeline 173:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  179.869908] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  179.869918] [drm:drm_mode_debug_printmodeline], Modeline 170:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  179.869931] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  179.869957] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1] probed modes :
>[  179.869966] [drm:drm_mode_debug_printmodeline], Modeline 12:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  179.869979] [drm:drm_mode_debug_printmodeline], Modeline 88:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  179.869992] [drm:drm_mode_debug_printmodeline], Modeline 35:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  179.870005] [drm:drm_mode_debug_printmodeline], Modeline 80:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  179.870017] [drm:drm_mode_debug_printmodeline], Modeline 79:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  179.870030] [drm:drm_mode_debug_printmodeline], Modeline 78:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  179.870042] [drm:drm_mode_debug_printmodeline], Modeline 87:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  179.870054] [drm:drm_mode_debug_printmodeline], Modeline 82:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  179.870067] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  179.870079] [drm:drm_mode_debug_printmodeline], Modeline 34:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  179.870092] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  179.870104] [drm:drm_mode_debug_printmodeline], Modeline 89:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  179.870117] [drm:drm_mode_debug_printmodeline], Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  179.870129] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  179.870142] [drm:drm_mode_debug_printmodeline], Modeline 90:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  179.870155] [drm:drm_mode_debug_printmodeline], Modeline 74:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  179.870167] [drm:drm_mode_debug_printmodeline], Modeline 73:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  179.870179] [drm:drm_mode_debug_printmodeline], Modeline 72:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  179.870192] [drm:drm_mode_debug_printmodeline], Modeline 71:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  179.870204] [drm:drm_mode_debug_printmodeline], Modeline 33:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  179.870217] [drm:drm_mode_debug_printmodeline], Modeline 77:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  179.870229] [drm:drm_mode_debug_printmodeline], Modeline 76:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  179.870242] [drm:drm_mode_debug_printmodeline], Modeline 75:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  179.870254] [drm:drm_mode_debug_printmodeline], Modeline 86:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  179.870266] [drm:drm_mode_debug_printmodeline], Modeline 67:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  179.870278] [drm:drm_mode_debug_printmodeline], Modeline 66:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  179.870291] [drm:drm_mode_debug_printmodeline], Modeline 65:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  179.870303] [drm:drm_mode_debug_printmodeline], Modeline 85:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  179.870315] [drm:drm_mode_debug_printmodeline], Modeline 63:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  179.870328] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  179.870340] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  179.870353] [drm:drm_mode_debug_printmodeline], Modeline 70:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  179.870365] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  179.870377] [drm:drm_mode_debug_printmodeline], Modeline 68:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  179.870390] [drm:drm_mode_debug_printmodeline], Modeline 62:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  179.870402] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  179.870414] [drm:drm_mode_debug_printmodeline], Modeline 84:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  179.870426] [drm:drm_mode_debug_printmodeline], Modeline 64:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  179.870439] [drm:drm_mode_debug_printmodeline], Modeline 60:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  179.870451] [drm:drm_mode_debug_printmodeline], Modeline 59:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  179.870495] [drm:drm_mode_debug_printmodeline], Modeline 31:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  179.870508] [drm:drm_mode_debug_printmodeline], Modeline 30:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  179.870521] [drm:drm_mode_debug_printmodeline], Modeline 58:"1280x768" 85 117500 1280 1360 1496 1712 768 771 778 809 0x40 0x6
>[  179.870543] [drm:drm_mode_debug_printmodeline], Modeline 57:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  179.870566] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  179.870590] [drm:drm_mode_debug_printmodeline], Modeline 101:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  179.870615] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  179.870636] [drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40 0x5
>[  179.870659] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  179.870681] [drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  179.870702] [drm:drm_mode_debug_printmodeline], Modeline 42:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  179.870722] [drm:drm_mode_debug_printmodeline], Modeline 53:"1024x768i" 86 44900 1024 1032 1208 1264 768 768 772 817 0x40 0x15
>[  179.870743] [drm:drm_mode_debug_printmodeline], Modeline 83:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  179.870756] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
>[  179.870769] [drm:drm_mode_debug_printmodeline], Modeline 50:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  179.870781] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  179.870794] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  179.870806] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  179.870819] [drm:drm_mode_debug_printmodeline], Modeline 99:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  179.870831] [drm:drm_mode_debug_printmodeline], Modeline 52:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  179.870843] [drm:drm_mode_debug_printmodeline], Modeline 93:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  179.870856] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
>[  179.870868] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  179.870880] [drm:drm_mode_debug_printmodeline], Modeline 37:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  179.870893] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  179.870906] [drm:drm_mode_debug_printmodeline], Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  179.870918] [drm:drm_mode_debug_printmodeline], Modeline 46:"720x400" 85 35500 720 756 828 936 400 401 404 446 0x40 0x6
>[  179.870930] [drm:drm_mode_debug_printmodeline], Modeline 39:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  179.870942] [drm:drm_mode_debug_printmodeline], Modeline 45:"640x400" 85 31500 640 672 736 832 400 401 404 445 0x40 0x6
>[  179.870955] [drm:drm_mode_debug_printmodeline], Modeline 44:"640x350" 85 31500 640 672 736 832 350 382 385 445 0x40 0x9
>[  179.870996] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  180.163800] [drm:drm_mode_addfb], [FB:29]
>[  180.165526] [drm:drm_mode_setcrtc], [CRTC:3]
>[  180.165545] [drm:drm_mode_setcrtc], [CONNECTOR:20:DP-1]
>[  180.165552] [drm:intel_crtc_set_config], [CRTC:3] [FB:29] #connectors=1 (x y) (0 0)
>[  180.165561] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  180.165567] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  180.165576] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  180.165585] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  180.165590] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  180.165597] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:3]
>[  180.165602] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  180.165607] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  180.165611] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  180.165616] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  180.165624] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  180.195496] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  180.195529] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 281250KHz
>[  180.195544] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  180.195550] [drm:intel_dp_mode_fixup], DP link bw required 675000 available 864000
>[  180.195557] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  180.195563] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  180.195578] [drm:ironlake_edp_backlight_off], 
>[  180.426415] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  180.426455] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000b
>[  180.426467] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  180.426484] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  180.426497] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
>[  181.196156] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  181.196168] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  181.196174] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  181.196179] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  181.205596] [drm:ironlake_update_plane], Writing base 01014000 00000000 0 0 7680
>[  181.257088] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  181.257111] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:92:1920x1200]
>[  181.257120] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe A
>[  181.257125] [drm:intel_ddi_mode_set], DP audio on pipe A on DDI
>[  181.257130] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  181.257137] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  181.257144] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  181.257148] [drm:haswell_write_eld], HDMI audio: enable codec
>[  181.309082] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  181.309094] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  181.309102] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  181.309107] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  181.309113] [drm:haswell_write_eld], ELD on pipe A
>[  181.309118] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  181.309132] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 15, cursor: 6
>[  181.310332] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  181.311168] [drm:intel_dp_start_link_train], clock recovery OK
>[  181.311177] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  181.312291] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  181.349970] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  181.349983] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  181.349992] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  181.350001] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  181.350009] [drm:intel_modeset_check_state], [CRTC:3]
>[  181.350017] [drm:intel_modeset_check_state], [CRTC:5]
>[  181.350025] [drm:intel_modeset_check_state], [CRTC:7]
>[  185.145430] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  185.145446] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [NOCRTC]
>[  185.145453] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  185.145458] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  185.145465] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  185.164706] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  185.164718] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  185.164725] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  185.164730] [drm:intel_modeset_check_state], [CRTC:3]
>[  185.164736] [drm:intel_modeset_check_state], [CRTC:5]
>[  185.164741] [drm:intel_modeset_check_state], [CRTC:7]
>[  185.165334] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  185.165346] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  185.165352] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  185.165357] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  185.165366] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  185.165375] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  185.165381] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  185.165387] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  185.165392] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  185.165397] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  185.165406] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  185.165420] [drm:intel_dp_mode_fixup], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  185.165434] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  185.165440] [drm:intel_dp_mode_fixup], DP link bw required 333072 available 432000
>[  185.165445] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  185.165460] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 8
>[  185.165466] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was 8) to eDP (6)
>[  185.165471] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  185.165476] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  185.165481] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  185.165504] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  185.165519] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:26:1920x1080]
>[  185.165526] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port A, pipe A
>[  185.165534] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.165543] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  185.165606] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  185.165619] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  185.165652] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  185.165669] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  185.366618] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  185.366635] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  185.366649] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  185.366674] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  185.366688] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b
>[  185.575543] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  185.575578] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  185.627676] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  185.628375] [drm:intel_dp_start_link_train], clock recovery OK
>[  185.628418] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  185.629444] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  185.631409] [drm:intel_dp_set_link_train] *ERROR* Timed out waiting for DP idle patterns
>[  185.631586] [drm:i915_write32] *ERROR* Unknown unclaimed register before writing to 64040
>[  185.667400] [drm:ironlake_edp_backlight_on], 
>[  185.669417] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[  185.683402] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  185.683418] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  185.683429] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  185.683438] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  185.683446] [drm:intel_modeset_check_state], [CRTC:3]
>[  185.683455] [drm:intel_modeset_check_state], [CRTC:5]
>[  185.683462] [drm:intel_modeset_check_state], [CRTC:7]
>[  185.683475] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  185.683487] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  185.683496] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  185.683505] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  185.683514] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  185.683523] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  185.683531] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  185.683538] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  185.683554] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  185.683572] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[  185.683590] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  185.683599] [drm:intel_dp_mode_fixup], DP link bw required 644400 available 864000
>[  185.683608] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  185.683627] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  185.683636] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  185.683644] [drm:haswell_crtc_mode_set], Mode for pipe 1:
>[  185.683652] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  185.683682] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  185.683698] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.683712] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:27:2560x1600]
>[  185.683722] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe B
>[  185.683730] [drm:intel_ddi_mode_set], DP audio on pipe B on DDI
>[  185.683737] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  185.683747] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  185.683757] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  185.683764] [drm:haswell_write_eld], HDMI audio: enable codec
>[  185.735368] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  185.735377] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  185.735386] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  185.735394] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  185.735402] [drm:haswell_write_eld], ELD on pipe B
>[  185.735410] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  185.735424] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.735434] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  185.736580] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  185.737442] [drm:intel_dp_start_link_train], clock recovery OK
>[  185.737453] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  185.738598] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  185.792354] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  185.792369] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  185.792380] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  185.792390] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  185.792400] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  185.792408] [drm:intel_modeset_check_state], [CRTC:3]
>[  185.792417] [drm:intel_modeset_check_state], [CRTC:5]
>[  185.792425] [drm:intel_modeset_check_state], [CRTC:7]
>[  185.792437] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  185.792448] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  185.792458] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  185.792474] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.792484] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  185.792498] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.792507] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  185.792521] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  185.792530] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  195.460683] [drm:i915_driver_open], 
>[  195.460758] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  195.460771] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  195.460778] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  195.460786] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  195.460794] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  195.460800] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  195.460807] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  195.460813] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  195.460819] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  195.460881] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  195.460902] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  195.460930] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  195.460942] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  195.460956] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  195.460965] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  195.461015] [drm:i915_driver_open], 
>[  195.461527] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  195.461555] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[3]
>[  195.461582] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  195.461592] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1]
>[  195.462006] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[  195.463062] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.490373] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.517622] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.517634] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  195.518647] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.545877] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.573137] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  195.573469] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[  195.573477] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  195.573962] [drm:drm_mode_debug_printmodeline], Modeline 173:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  195.573977] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  195.573987] [drm:drm_mode_debug_printmodeline], Modeline 170:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  195.574000] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  195.574026] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DP-1] probed modes :
>[  195.574035] [drm:drm_mode_debug_printmodeline], Modeline 12:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  195.574049] [drm:drm_mode_debug_printmodeline], Modeline 88:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  195.574062] [drm:drm_mode_debug_printmodeline], Modeline 35:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  195.574075] [drm:drm_mode_debug_printmodeline], Modeline 80:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  195.574087] [drm:drm_mode_debug_printmodeline], Modeline 79:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  195.574100] [drm:drm_mode_debug_printmodeline], Modeline 78:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  195.574112] [drm:drm_mode_debug_printmodeline], Modeline 87:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  195.574125] [drm:drm_mode_debug_printmodeline], Modeline 82:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  195.574137] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  195.574149] [drm:drm_mode_debug_printmodeline], Modeline 34:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  195.574162] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  195.574174] [drm:drm_mode_debug_printmodeline], Modeline 89:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  195.574186] [drm:drm_mode_debug_printmodeline], Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  195.574199] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  195.574212] [drm:drm_mode_debug_printmodeline], Modeline 90:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  195.574224] [drm:drm_mode_debug_printmodeline], Modeline 74:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  195.574237] [drm:drm_mode_debug_printmodeline], Modeline 73:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  195.574249] [drm:drm_mode_debug_printmodeline], Modeline 72:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  195.574261] [drm:drm_mode_debug_printmodeline], Modeline 71:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  195.574274] [drm:drm_mode_debug_printmodeline], Modeline 33:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  195.574286] [drm:drm_mode_debug_printmodeline], Modeline 77:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  195.574298] [drm:drm_mode_debug_printmodeline], Modeline 76:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  195.574310] [drm:drm_mode_debug_printmodeline], Modeline 75:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  195.574323] [drm:drm_mode_debug_printmodeline], Modeline 86:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  195.574335] [drm:drm_mode_debug_printmodeline], Modeline 67:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  195.574348] [drm:drm_mode_debug_printmodeline], Modeline 66:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  195.574360] [drm:drm_mode_debug_printmodeline], Modeline 65:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  195.574372] [drm:drm_mode_debug_printmodeline], Modeline 85:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  195.574384] [drm:drm_mode_debug_printmodeline], Modeline 63:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  195.574397] [drm:drm_mode_debug_printmodeline], Modeline 40:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  195.574409] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  195.574421] [drm:drm_mode_debug_printmodeline], Modeline 70:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  195.574434] [drm:drm_mode_debug_printmodeline], Modeline 69:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  195.574446] [drm:drm_mode_debug_printmodeline], Modeline 68:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  195.574459] [drm:drm_mode_debug_printmodeline], Modeline 62:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  195.574471] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  195.574484] [drm:drm_mode_debug_printmodeline], Modeline 84:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  195.574496] [drm:drm_mode_debug_printmodeline], Modeline 64:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  195.574508] [drm:drm_mode_debug_printmodeline], Modeline 60:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  195.574521] [drm:drm_mode_debug_printmodeline], Modeline 59:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  195.574533] [drm:drm_mode_debug_printmodeline], Modeline 31:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  195.574545] [drm:drm_mode_debug_printmodeline], Modeline 30:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  195.574557] [drm:drm_mode_debug_printmodeline], Modeline 58:"1280x768" 85 117500 1280 1360 1496 1712 768 771 778 809 0x40 0x6
>[  195.574570] [drm:drm_mode_debug_printmodeline], Modeline 57:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  195.574582] [drm:drm_mode_debug_printmodeline], Modeline 56:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  195.574594] [drm:drm_mode_debug_printmodeline], Modeline 101:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  195.574606] [drm:drm_mode_debug_printmodeline], Modeline 91:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  195.574619] [drm:drm_mode_debug_printmodeline], Modeline 55:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40 0x5
>[  195.574631] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  195.574644] [drm:drm_mode_debug_printmodeline], Modeline 54:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  195.574656] [drm:drm_mode_debug_printmodeline], Modeline 42:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  195.574668] [drm:drm_mode_debug_printmodeline], Modeline 53:"1024x768i" 86 44900 1024 1032 1208 1264 768 768 772 817 0x40 0x15
>[  195.574680] [drm:drm_mode_debug_printmodeline], Modeline 83:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  195.574693] [drm:drm_mode_debug_printmodeline], Modeline 51:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
>[  195.574705] [drm:drm_mode_debug_printmodeline], Modeline 50:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  195.574717] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  195.574730] [drm:drm_mode_debug_printmodeline], Modeline 36:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  195.574742] [drm:drm_mode_debug_printmodeline], Modeline 49:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  195.574755] [drm:drm_mode_debug_printmodeline], Modeline 99:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  195.574767] [drm:drm_mode_debug_printmodeline], Modeline 52:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  195.574779] [drm:drm_mode_debug_printmodeline], Modeline 93:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  195.574823] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
>[  195.574837] [drm:drm_mode_debug_printmodeline], Modeline 47:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  195.574858] [drm:drm_mode_debug_printmodeline], Modeline 37:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  195.574874] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  195.574888] [drm:drm_mode_debug_printmodeline], Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  195.574904] [drm:drm_mode_debug_printmodeline], Modeline 46:"720x400" 85 35500 720 756 828 936 400 401 404 446 0x40 0x6
>[  195.574919] [drm:drm_mode_debug_printmodeline], Modeline 39:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  195.574933] [drm:drm_mode_debug_printmodeline], Modeline 45:"640x400" 85 31500 640 672 736 832 400 401 404 445 0x40 0x6
>[  195.574948] [drm:drm_mode_debug_printmodeline], Modeline 44:"640x350" 85 31500 640 672 736 832 350 382 385 445 0x40 0x9
>[  195.574994] [drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[  195.857165] [drm:drm_mode_addfb], [FB:29]
>[  195.857392] [drm:drm_mode_setcrtc], [CRTC:3]
>[  195.857411] [drm:drm_mode_setcrtc], [CONNECTOR:20:DP-1]
>[  195.857418] [drm:intel_crtc_set_config], [CRTC:3] [FB:29] #connectors=1 (x y) (0 0)
>[  195.857427] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  195.857432] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  195.857442] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  195.857451] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  195.857456] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  195.857462] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:3]
>[  195.857467] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  195.857472] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  195.857476] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  195.857481] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  195.857490] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  195.876828] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  195.876861] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 281250KHz
>[  195.876876] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  195.876883] [drm:intel_dp_mode_fixup], DP link bw required 675000 available 864000
>[  195.876889] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  195.876896] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  195.876910] [drm:ironlake_edp_backlight_off], 
>[  196.095756] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  196.095795] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000b
>[  196.095807] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  196.095824] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  196.095837] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
>[  196.898481] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  196.898493] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  196.898500] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  196.898506] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  196.915529] [drm:ironlake_update_plane], Writing base 01014000 00000000 0 0 8192
>[  196.967416] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  196.967440] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:92:1920x1200]
>[  196.967449] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe A
>[  196.967455] [drm:intel_ddi_mode_set], DP audio on pipe A on DDI
>[  196.967460] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  196.967468] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  196.967474] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  196.967479] [drm:haswell_write_eld], HDMI audio: enable codec
>[  197.019411] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  197.019422] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  197.019430] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  197.019436] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  197.019442] [drm:haswell_write_eld], ELD on pipe A
>[  197.019448] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  197.019462] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 15, cursor: 6
>[  197.020695] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  197.021547] [drm:intel_dp_start_link_train], clock recovery OK
>[  197.021556] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  197.022666] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  197.060289] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  197.060305] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  197.060315] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  197.060324] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  197.060332] [drm:intel_modeset_check_state], [CRTC:3]
>[  197.060341] [drm:intel_modeset_check_state], [CRTC:5]
>[  197.060348] [drm:intel_modeset_check_state], [CRTC:7]
>[  199.930246] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  199.930263] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [NOCRTC]
>[  199.930270] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  199.930275] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  199.930282] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  199.944370] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  199.944382] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  199.944388] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  199.944394] [drm:intel_modeset_check_state], [CRTC:3]
>[  199.944399] [drm:intel_modeset_check_state], [CRTC:5]
>[  199.944404] [drm:intel_modeset_check_state], [CRTC:7]
>[  199.945447] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[  199.945459] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  199.945464] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  199.945469] [drm:drm_mode_debug_printmodeline], Modeline 92:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  199.945479] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  199.945493] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  199.945512] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  199.945528] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  199.945541] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  199.945547] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  199.945556] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  199.945570] [drm:intel_dp_mode_fixup], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  199.945584] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 2 clock 270000 bpp 24
>[  199.945590] [drm:intel_dp_mode_fixup], DP link bw required 333072 available 432000
>[  199.945596] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  199.945610] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 8
>[  199.945616] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was 8) to eDP (6)
>[  199.945622] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  199.945627] [drm:haswell_crtc_mode_set], Mode for pipe 0:
>[  199.945632] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  199.945662] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  199.945685] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:26:1920x1080]
>[  199.945698] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port A, pipe A
>[  199.945709] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  199.945717] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  199.945730] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  199.945743] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  199.945774] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  199.945784] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  200.146261] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  200.146277] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  200.146291] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  200.146315] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  200.146328] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd000b
>[  200.355197] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  200.355233] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  200.407299] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.407998] [drm:intel_dp_start_link_train], clock recovery OK
>[  200.408007] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.409061] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  200.411065] [drm:intel_dp_set_link_train] *ERROR* Timed out waiting for DP idle patterns
>[  200.411244] [drm:i915_write32] *ERROR* Unknown unclaimed register before writing to 64040
>[  200.447051] [drm:ironlake_edp_backlight_on], 
>[  200.449068] [drm:intel_panel_actually_set_backlight], set backlight PWM = 937
>[  200.463105] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  200.463119] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  200.463127] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  200.463133] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  200.463138] [drm:intel_modeset_check_state], [CRTC:3]
>[  200.463143] [drm:intel_modeset_check_state], [CRTC:5]
>[  200.463148] [drm:intel_modeset_check_state], [CRTC:7]
>[  200.463158] [drm:intel_crtc_set_config], [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  200.463166] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  200.463172] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  200.463178] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  200.463184] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  200.463190] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  200.463195] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  200.463200] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  200.463210] [drm:intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  200.463223] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[  200.463237] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  200.463243] [drm:intel_dp_mode_fixup], DP link bw required 644400 available 864000
>[  200.463248] [drm:intel_modeset_adjusted_mode], [CRTC:5]
>[  200.463262] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  200.463269] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  200.463274] [drm:haswell_crtc_mode_set], Mode for pipe 1:
>[  200.463279] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  200.463303] [drm:ironlake_update_plane], Writing base 00074000 00000000 0 0 10240
>[  200.463315] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  200.463326] [drm:intel_crtc_mode_set], [ENCODER:18:TMDS-18] set [MODE:27:2560x1600]
>[  200.463332] [drm:intel_ddi_mode_set], Preparing DDI mode for Haswell on port B, pipe B
>[  200.463337] [drm:intel_ddi_mode_set], DP audio on pipe B on DDI
>[  200.463342] [drm:intel_ddi_mode_set], DP audio: write eld information
>[  200.463348] [drm:intel_write_eld], ELD on [CONNECTOR:20:DP-1], [ENCODER:18:TMDS-18]
>[  200.463354] [drm:haswell_write_eld], HDMI: Haswell Audio initialize....
>[  200.463358] [drm:haswell_write_eld], HDMI audio: enable codec
>[  200.515035] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.515045] [drm:haswell_write_eld], HDMI audio: pin eld vld status=0x      55
>[  200.515052] [drm:haswell_write_eld], HDMI audio: eld vld status=0x      55
>[  200.515058] [drm:haswell_write_eld], HDMI audio: audio conf: 0x20800000
>[  200.515063] [drm:haswell_write_eld], ELD on pipe B
>[  200.515069] [drm:haswell_write_eld], ELD: DisplayPort detected
>[  200.515080] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  200.515087] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  200.516297] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.517125] [drm:intel_dp_start_link_train], clock recovery OK
>[  200.517137] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  200.518272] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  200.572017] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  200.572032] [drm:intel_connector_check_state], [CONNECTOR:20:DP-1]
>[  200.572043] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  200.572053] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  200.572063] [drm:intel_modeset_check_state], [ENCODER:21:TMDS-21]
>[  200.572071] [drm:intel_modeset_check_state], [CRTC:3]
>[  200.572079] [drm:intel_modeset_check_state], [CRTC:5]
>[  200.572087] [drm:intel_modeset_check_state], [CRTC:7]
>[  200.572100] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  200.572111] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  200.572121] [drm:intel_modeset_stage_output_state], [CONNECTOR:20:DP-1] to [CRTC:5]
>[  200.572137] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  200.572147] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  200.572161] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  200.572170] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6
>[  200.572184] [drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  200.572193] [drm:sandybridge_update_wm], FIFO watermarks For pipe B - plane 14, cursor: 6

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Attachments on bug 59651: 73358 | 73366 | 73369 | 73370

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