Attachment 73801 Details for Bug 59999 – inter-flip-ILK.dmesg

inter-flip-ILK.dmesg

inter-flip-ILK.dmesg (text/plain), 122.60 KB, created by yanbing on 2013-01-29 03:10:05 UTC

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Description:

Filename:

MIME Type:

Creator: yanbing

Created: 2013-01-29 03:10:05 UTC

Size: 122.60 KB

patch

obsolete

>[  112.663969] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  112.663973] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  112.663975] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  112.663977] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  112.663978] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  112.663988] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  112.663989] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  112.715598] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  112.715605] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  112.715613] [drm:intel_update_fbc], no output, disabling
>[  112.715618] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:11:1366x768]
>[  112.715624] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  112.715629] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  112.715635] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  112.715642] [drm:ironlake_edp_pll_on], 
>[  112.767508] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  112.819464] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  112.819469] [drm:intel_update_fbc], fbc set to per-chip default
>[  112.819473] [drm:intel_update_fbc], fbc disabled per module param
>[  112.819477] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  112.819483] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  112.819488] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  112.819499] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  112.819504] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  113.120348] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  113.121077] [drm:intel_dp_start_link_train], clock recovery OK
>[  113.121078] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  113.121081] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  113.121085] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  113.121092] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  113.121096] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  113.461341] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  113.461352] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  113.513275] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  113.513484] [drm:ironlake_edp_backlight_on], 
>[  113.554164] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  113.564115] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  113.564131] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  113.564137] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  113.564141] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  113.564146] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  113.564151] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  113.564156] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  113.564160] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  113.564165] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  113.564170] [drm:intel_modeset_check_state], [CRTC:3]
>[  113.564173] [drm:intel_modeset_check_state], [CRTC:5]
>[  113.564177] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  113.564182] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  125.935037] [drm:i915_driver_open], 
>[  125.935065] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  125.935075] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  125.935080] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  125.935084] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  125.935101] [drm:i915_driver_open], 
>[  125.935261] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  125.935271] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  125.935288] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  125.935293] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  125.935298] [drm:intel_dp_detect], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  125.935301] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  125.935312] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  125.935523] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  125.935785] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  125.935787] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  125.935801] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  125.935805] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  125.935807] [drm:drm_mode_debug_printmodeline], Modeline 30:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  125.935811] [drm:drm_mode_debug_printmodeline], Modeline 31:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  125.935817] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  125.984758] [drm:drm_mode_addfb], [FB:32]
>[  126.021910] [drm:drm_mode_addfb], [FB:33]
>[  126.021971] [drm:drm_mode_setcrtc], [CRTC:3]
>[  126.021979] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  126.021983] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  126.021992] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  126.022001] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  126.035658] [drm:intel_update_fbc], fbc set to per-chip default
>[  126.035662] [drm:intel_update_fbc], fbc disabled per module param
>[  127.048954] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.048959] [drm:intel_update_fbc], fbc disabled per module param
>[  127.065607] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.065611] [drm:intel_update_fbc], fbc disabled per module param
>[  127.082257] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.082262] [drm:intel_update_fbc], fbc disabled per module param
>[  127.098882] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.098887] [drm:intel_update_fbc], fbc disabled per module param
>[  127.115456] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.115461] [drm:intel_update_fbc], fbc disabled per module param
>[  127.132121] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.132125] [drm:intel_update_fbc], fbc disabled per module param
>[  127.148771] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.148776] [drm:intel_update_fbc], fbc disabled per module param
>[  127.165405] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.165409] [drm:intel_update_fbc], fbc disabled per module param
>[  127.181977] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.181982] [drm:intel_update_fbc], fbc disabled per module param
>[  127.198670] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.198674] [drm:intel_update_fbc], fbc disabled per module param
>[  127.215288] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.215293] [drm:intel_update_fbc], fbc disabled per module param
>[  127.231888] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.231893] [drm:intel_update_fbc], fbc disabled per module param
>[  127.248556] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.248561] [drm:intel_update_fbc], fbc disabled per module param
>[  127.265186] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.265191] [drm:intel_update_fbc], fbc disabled per module param
>[  127.281749] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.281754] [drm:intel_update_fbc], fbc disabled per module param
>[  127.298430] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.298434] [drm:intel_update_fbc], fbc disabled per module param
>[  127.315088] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.315093] [drm:intel_update_fbc], fbc disabled per module param
>[  127.331658] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.331662] [drm:intel_update_fbc], fbc disabled per module param
>[  127.348262] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.348266] [drm:intel_update_fbc], fbc disabled per module param
>[  127.364899] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.364903] [drm:intel_update_fbc], fbc disabled per module param
>[  127.381577] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.381581] [drm:intel_update_fbc], fbc disabled per module param
>[  127.398171] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.398175] [drm:intel_update_fbc], fbc disabled per module param
>[  127.414803] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.414807] [drm:intel_update_fbc], fbc disabled per module param
>[  127.431427] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.431431] [drm:intel_update_fbc], fbc disabled per module param
>[  127.448094] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.448099] [drm:intel_update_fbc], fbc disabled per module param
>[  127.464661] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.464666] [drm:intel_update_fbc], fbc disabled per module param
>[  127.481300] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.481305] [drm:intel_update_fbc], fbc disabled per module param
>[  127.497942] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.497946] [drm:intel_update_fbc], fbc disabled per module param
>[  127.514571] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.514576] [drm:intel_update_fbc], fbc disabled per module param
>[  127.531199] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.531204] [drm:intel_update_fbc], fbc disabled per module param
>[  127.547867] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.547871] [drm:intel_update_fbc], fbc disabled per module param
>[  127.564457] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.564462] [drm:intel_update_fbc], fbc disabled per module param
>[  127.581069] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.581073] [drm:intel_update_fbc], fbc disabled per module param
>[  127.597723] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.597728] [drm:intel_update_fbc], fbc disabled per module param
>[  127.614327] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.614331] [drm:intel_update_fbc], fbc disabled per module param
>[  127.630943] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.630948] [drm:intel_update_fbc], fbc disabled per module param
>[  127.647614] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.647619] [drm:intel_update_fbc], fbc disabled per module param
>[  127.664133] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.664137] [drm:intel_update_fbc], fbc disabled per module param
>[  127.680894] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.680898] [drm:intel_update_fbc], fbc disabled per module param
>[  127.697503] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.697508] [drm:intel_update_fbc], fbc disabled per module param
>[  127.714112] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.714116] [drm:intel_update_fbc], fbc disabled per module param
>[  127.730716] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.730721] [drm:intel_update_fbc], fbc disabled per module param
>[  127.747347] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.747352] [drm:intel_update_fbc], fbc disabled per module param
>[  127.764022] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.764026] [drm:intel_update_fbc], fbc disabled per module param
>[  127.780670] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.780675] [drm:intel_update_fbc], fbc disabled per module param
>[  127.797296] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.797300] [drm:intel_update_fbc], fbc disabled per module param
>[  127.813858] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.813863] [drm:intel_update_fbc], fbc disabled per module param
>[  127.830521] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.830526] [drm:intel_update_fbc], fbc disabled per module param
>[  127.847140] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.847145] [drm:intel_update_fbc], fbc disabled per module param
>[  127.863796] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.863800] [drm:intel_update_fbc], fbc disabled per module param
>[  127.880371] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.880376] [drm:intel_update_fbc], fbc disabled per module param
>[  127.897085] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.897089] [drm:intel_update_fbc], fbc disabled per module param
>[  127.913653] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.913658] [drm:intel_update_fbc], fbc disabled per module param
>[  127.930281] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.930286] [drm:intel_update_fbc], fbc disabled per module param
>[  127.946886] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.946891] [drm:intel_update_fbc], fbc disabled per module param
>[  127.963541] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.963546] [drm:intel_update_fbc], fbc disabled per module param
>[  127.980152] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.980156] [drm:intel_update_fbc], fbc disabled per module param
>[  127.996763] [drm:intel_update_fbc], fbc set to per-chip default
>[  127.996768] [drm:intel_update_fbc], fbc disabled per module param
>[  128.013423] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.013427] [drm:intel_update_fbc], fbc disabled per module param
>[  128.030080] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.030085] [drm:intel_update_fbc], fbc disabled per module param
>[  128.046682] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.046687] [drm:intel_update_fbc], fbc disabled per module param
>[  128.063262] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.063265] [drm:intel_update_fbc], fbc disabled per module param
>[  128.080005] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.080009] [drm:intel_update_fbc], fbc disabled per module param
>[  128.096562] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.096566] [drm:intel_update_fbc], fbc disabled per module param
>[  128.113231] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.113236] [drm:intel_update_fbc], fbc disabled per module param
>[  128.129796] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.129801] [drm:intel_update_fbc], fbc disabled per module param
>[  128.146460] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.146465] [drm:intel_update_fbc], fbc disabled per module param
>[  128.163106] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.163111] [drm:intel_update_fbc], fbc disabled per module param
>[  128.179747] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.179751] [drm:intel_update_fbc], fbc disabled per module param
>[  128.196312] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.196317] [drm:intel_update_fbc], fbc disabled per module param
>[  128.212993] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.212997] [drm:intel_update_fbc], fbc disabled per module param
>[  128.229594] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.229599] [drm:intel_update_fbc], fbc disabled per module param
>[  128.246221] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.246226] [drm:intel_update_fbc], fbc disabled per module param
>[  128.262878] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.262882] [drm:intel_update_fbc], fbc disabled per module param
>[  128.279454] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.279459] [drm:intel_update_fbc], fbc disabled per module param
>[  128.296106] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.296110] [drm:intel_update_fbc], fbc disabled per module param
>[  128.312769] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.312774] [drm:intel_update_fbc], fbc disabled per module param
>[  128.329395] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.329399] [drm:intel_update_fbc], fbc disabled per module param
>[  128.345968] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.345973] [drm:intel_update_fbc], fbc disabled per module param
>[  128.362597] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.362602] [drm:intel_update_fbc], fbc disabled per module param
>[  128.379271] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.379276] [drm:intel_update_fbc], fbc disabled per module param
>[  128.395877] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.395881] [drm:intel_update_fbc], fbc disabled per module param
>[  128.412499] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.412503] [drm:intel_update_fbc], fbc disabled per module param
>[  128.429110] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.429115] [drm:intel_update_fbc], fbc disabled per module param
>[  128.445791] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.445795] [drm:intel_update_fbc], fbc disabled per module param
>[  128.462330] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.462336] [drm:intel_update_fbc], fbc disabled per module param
>[  128.478967] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.478972] [drm:intel_update_fbc], fbc disabled per module param
>[  128.495650] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.495655] [drm:intel_update_fbc], fbc disabled per module param
>[  128.512305] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.512309] [drm:intel_update_fbc], fbc disabled per module param
>[  128.528855] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.528860] [drm:intel_update_fbc], fbc disabled per module param
>[  128.545534] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.545539] [drm:intel_update_fbc], fbc disabled per module param
>[  128.562201] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.562205] [drm:intel_update_fbc], fbc disabled per module param
>[  128.578766] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.578771] [drm:intel_update_fbc], fbc disabled per module param
>[  128.595372] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.595377] [drm:intel_update_fbc], fbc disabled per module param
>[  128.612087] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.612091] [drm:intel_update_fbc], fbc disabled per module param
>[  128.628717] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.628722] [drm:intel_update_fbc], fbc disabled per module param
>[  128.645289] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.645293] [drm:intel_update_fbc], fbc disabled per module param
>[  128.661838] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.661844] [drm:intel_update_fbc], fbc disabled per module param
>[  128.678571] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.678575] [drm:intel_update_fbc], fbc disabled per module param
>[  128.695215] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.695220] [drm:intel_update_fbc], fbc disabled per module param
>[  128.711846] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.711851] [drm:intel_update_fbc], fbc disabled per module param
>[  128.728421] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.728426] [drm:intel_update_fbc], fbc disabled per module param
>[  128.745049] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.745054] [drm:intel_update_fbc], fbc disabled per module param
>[  128.761677] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.761682] [drm:intel_update_fbc], fbc disabled per module param
>[  128.778336] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.778341] [drm:intel_update_fbc], fbc disabled per module param
>[  128.794987] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.794991] [drm:intel_update_fbc], fbc disabled per module param
>[  128.811607] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.811611] [drm:intel_update_fbc], fbc disabled per module param
>[  128.828191] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.828196] [drm:intel_update_fbc], fbc disabled per module param
>[  128.844829] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.844834] [drm:intel_update_fbc], fbc disabled per module param
>[  128.861440] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.861445] [drm:intel_update_fbc], fbc disabled per module param
>[  128.878142] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.878146] [drm:intel_update_fbc], fbc disabled per module param
>[  128.894706] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.894711] [drm:intel_update_fbc], fbc disabled per module param
>[  128.911390] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.911394] [drm:intel_update_fbc], fbc disabled per module param
>[  128.927987] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.927992] [drm:intel_update_fbc], fbc disabled per module param
>[  128.937702] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  128.944681] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.944685] [drm:intel_update_fbc], fbc disabled per module param
>[  128.994502] [drm:intel_update_fbc], fbc set to per-chip default
>[  128.994506] [drm:intel_update_fbc], fbc disabled per module param
>[  128.994953] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  128.994960] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  128.994964] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  128.994966] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  128.994970] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  128.994974] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  128.994984] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  128.994990] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  128.994996] [drm:ironlake_edp_backlight_off], 
>[  129.195424] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  129.195431] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  129.195436] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  130.042754] [drm:intel_dp_link_down], 
>[  130.112270] [drm:intel_update_fbc], no output, disabling
>[  130.112288] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  130.112293] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  130.112297] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  130.112301] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  130.112306] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  130.112310] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  130.112315] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  130.112319] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  130.112323] [drm:intel_modeset_check_state], [CRTC:3]
>[  130.112326] [drm:intel_modeset_check_state], [CRTC:5]
>[  130.119107] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  130.119113] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  130.119117] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  130.119120] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  130.119124] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  130.119127] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  130.119131] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  130.119137] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  130.119144] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  130.119149] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  130.119153] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  130.119157] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  130.119164] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  130.119168] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  130.119173] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  130.119176] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  130.119189] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  130.119193] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  130.171531] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  130.171538] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  130.171545] [drm:intel_update_fbc], no output, disabling
>[  130.171550] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:11:1366x768]
>[  130.171555] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  130.171560] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  130.171564] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  130.171571] [drm:ironlake_edp_pll_on], 
>[  130.223441] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  130.275352] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  130.275357] [drm:intel_update_fbc], fbc set to per-chip default
>[  130.275360] [drm:intel_update_fbc], fbc disabled per module param
>[  130.275364] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  130.275369] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  130.275374] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  130.275384] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  130.275388] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  130.576250] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  130.576980] [drm:intel_dp_start_link_train], clock recovery OK
>[  130.576981] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  130.576984] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  130.576988] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  130.576995] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  130.576999] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  130.917248] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  130.917259] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  130.969178] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  130.969387] [drm:ironlake_edp_backlight_on], 
>[  131.010066] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  131.020069] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  131.020083] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  131.020088] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  131.020092] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  131.020096] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  131.020101] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  131.020105] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  131.020110] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  131.020114] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  131.020118] [drm:intel_modeset_check_state], [CRTC:3]
>[  131.020121] [drm:intel_modeset_check_state], [CRTC:5]
>[  131.020124] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  131.020128] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  138.917451] [drm:i915_driver_open], 
>[  138.917477] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  138.917488] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  138.917493] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  138.917497] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  138.917514] [drm:i915_driver_open], 
>[  138.917679] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  138.917689] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  138.917706] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  138.917711] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  138.917715] [drm:intel_dp_detect], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  138.917719] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  138.917730] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  138.917942] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  138.918191] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  138.918194] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  138.918212] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  138.918219] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  138.918223] [drm:drm_mode_debug_printmodeline], Modeline 30:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  138.918229] [drm:drm_mode_debug_printmodeline], Modeline 31:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  138.918238] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  138.965949] [drm:drm_mode_addfb], [FB:32]
>[  139.001927] [drm:drm_mode_addfb], [FB:33]
>[  139.001992] [drm:drm_mode_setcrtc], [CRTC:3]
>[  139.002000] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  139.002005] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  139.002013] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  139.002023] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  139.019276] [drm:intel_update_fbc], fbc set to per-chip default
>[  139.019280] [drm:intel_update_fbc], fbc disabled per module param
>[  140.031857] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.031862] [drm:intel_update_fbc], fbc disabled per module param
>[  140.048487] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.048491] [drm:intel_update_fbc], fbc disabled per module param
>[  140.065113] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.065118] [drm:intel_update_fbc], fbc disabled per module param
>[  140.081666] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.081671] [drm:intel_update_fbc], fbc disabled per module param
>[  140.098351] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.098356] [drm:intel_update_fbc], fbc disabled per module param
>[  140.114930] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.114935] [drm:intel_update_fbc], fbc disabled per module param
>[  140.131601] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.131606] [drm:intel_update_fbc], fbc disabled per module param
>[  140.148289] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.148293] [drm:intel_update_fbc], fbc disabled per module param
>[  140.164833] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.164838] [drm:intel_update_fbc], fbc disabled per module param
>[  140.181510] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.181514] [drm:intel_update_fbc], fbc disabled per module param
>[  140.198180] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.198185] [drm:intel_update_fbc], fbc disabled per module param
>[  140.214769] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.214774] [drm:intel_update_fbc], fbc disabled per module param
>[  140.231356] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.231360] [drm:intel_update_fbc], fbc disabled per module param
>[  140.248007] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.248012] [drm:intel_update_fbc], fbc disabled per module param
>[  140.264656] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.264660] [drm:intel_update_fbc], fbc disabled per module param
>[  140.281283] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.281288] [drm:intel_update_fbc], fbc disabled per module param
>[  140.297945] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.297950] [drm:intel_update_fbc], fbc disabled per module param
>[  140.314512] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.314517] [drm:intel_update_fbc], fbc disabled per module param
>[  140.331118] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.331123] [drm:intel_update_fbc], fbc disabled per module param
>[  140.347829] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.347833] [drm:intel_update_fbc], fbc disabled per module param
>[  140.364399] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.364404] [drm:intel_update_fbc], fbc disabled per module param
>[  140.381055] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.381059] [drm:intel_update_fbc], fbc disabled per module param
>[  140.397664] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.397669] [drm:intel_update_fbc], fbc disabled per module param
>[  140.414259] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.414264] [drm:intel_update_fbc], fbc disabled per module param
>[  140.430921] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.430926] [drm:intel_update_fbc], fbc disabled per module param
>[  140.447570] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.447575] [drm:intel_update_fbc], fbc disabled per module param
>[  140.464194] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.464198] [drm:intel_update_fbc], fbc disabled per module param
>[  140.480796] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.480801] [drm:intel_update_fbc], fbc disabled per module param
>[  140.497391] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.497395] [drm:intel_update_fbc], fbc disabled per module param
>[  140.514080] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.514084] [drm:intel_update_fbc], fbc disabled per module param
>[  140.530708] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.530713] [drm:intel_update_fbc], fbc disabled per module param
>[  140.547342] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.547346] [drm:intel_update_fbc], fbc disabled per module param
>[  140.563964] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.563968] [drm:intel_update_fbc], fbc disabled per module param
>[  140.580473] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.580478] [drm:intel_update_fbc], fbc disabled per module param
>[  140.597257] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.597261] [drm:intel_update_fbc], fbc disabled per module param
>[  140.613869] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.613873] [drm:intel_update_fbc], fbc disabled per module param
>[  140.630453] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.630457] [drm:intel_update_fbc], fbc disabled per module param
>[  140.647143] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.647147] [drm:intel_update_fbc], fbc disabled per module param
>[  140.663685] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.663690] [drm:intel_update_fbc], fbc disabled per module param
>[  140.680367] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.680371] [drm:intel_update_fbc], fbc disabled per module param
>[  140.696931] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.696936] [drm:intel_update_fbc], fbc disabled per module param
>[  140.713596] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.713601] [drm:intel_update_fbc], fbc disabled per module param
>[  140.730261] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.730265] [drm:intel_update_fbc], fbc disabled per module param
>[  140.746811] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.746817] [drm:intel_update_fbc], fbc disabled per module param
>[  140.763506] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.763510] [drm:intel_update_fbc], fbc disabled per module param
>[  140.780174] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.780179] [drm:intel_update_fbc], fbc disabled per module param
>[  140.796766] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.796770] [drm:intel_update_fbc], fbc disabled per module param
>[  140.813395] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.813399] [drm:intel_update_fbc], fbc disabled per module param
>[  140.829948] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.829953] [drm:intel_update_fbc], fbc disabled per module param
>[  140.846592] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.846598] [drm:intel_update_fbc], fbc disabled per module param
>[  140.863309] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.863314] [drm:intel_update_fbc], fbc disabled per module param
>[  140.879864] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.879868] [drm:intel_update_fbc], fbc disabled per module param
>[  140.896536] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.896541] [drm:intel_update_fbc], fbc disabled per module param
>[  140.913112] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.913117] [drm:intel_update_fbc], fbc disabled per module param
>[  140.929740] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.929744] [drm:intel_update_fbc], fbc disabled per module param
>[  140.946396] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.946402] [drm:intel_update_fbc], fbc disabled per module param
>[  140.963048] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.963053] [drm:intel_update_fbc], fbc disabled per module param
>[  140.979651] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.979656] [drm:intel_update_fbc], fbc disabled per module param
>[  140.996303] [drm:intel_update_fbc], fbc set to per-chip default
>[  140.996307] [drm:intel_update_fbc], fbc disabled per module param
>[  141.012910] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.012915] [drm:intel_update_fbc], fbc disabled per module param
>[  141.029495] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.029499] [drm:intel_update_fbc], fbc disabled per module param
>[  141.046222] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.046227] [drm:intel_update_fbc], fbc disabled per module param
>[  141.062793] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.062798] [drm:intel_update_fbc], fbc disabled per module param
>[  141.079440] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.079444] [drm:intel_update_fbc], fbc disabled per module param
>[  141.096025] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.096029] [drm:intel_update_fbc], fbc disabled per module param
>[  141.112652] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.112657] [drm:intel_update_fbc], fbc disabled per module param
>[  141.129245] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.129250] [drm:intel_update_fbc], fbc disabled per module param
>[  141.145962] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.145967] [drm:intel_update_fbc], fbc disabled per module param
>[  141.162589] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.162594] [drm:intel_update_fbc], fbc disabled per module param
>[  141.179168] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.179173] [drm:intel_update_fbc], fbc disabled per module param
>[  141.195845] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.195849] [drm:intel_update_fbc], fbc disabled per module param
>[  141.212433] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.212437] [drm:intel_update_fbc], fbc disabled per module param
>[  141.229078] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.229083] [drm:intel_update_fbc], fbc disabled per module param
>[  141.245735] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.245739] [drm:intel_update_fbc], fbc disabled per module param
>[  141.262310] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.262315] [drm:intel_update_fbc], fbc disabled per module param
>[  141.278964] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.278968] [drm:intel_update_fbc], fbc disabled per module param
>[  141.295648] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.295653] [drm:intel_update_fbc], fbc disabled per module param
>[  141.312284] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.312288] [drm:intel_update_fbc], fbc disabled per module param
>[  141.328824] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.328829] [drm:intel_update_fbc], fbc disabled per module param
>[  141.345500] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.345505] [drm:intel_update_fbc], fbc disabled per module param
>[  141.362174] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.362179] [drm:intel_update_fbc], fbc disabled per module param
>[  141.378758] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.378762] [drm:intel_update_fbc], fbc disabled per module param
>[  141.395337] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.395342] [drm:intel_update_fbc], fbc disabled per module param
>[  141.412018] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.412022] [drm:intel_update_fbc], fbc disabled per module param
>[  141.428676] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.428681] [drm:intel_update_fbc], fbc disabled per module param
>[  141.445276] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.445280] [drm:intel_update_fbc], fbc disabled per module param
>[  141.461850] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.461855] [drm:intel_update_fbc], fbc disabled per module param
>[  141.478514] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.478519] [drm:intel_update_fbc], fbc disabled per module param
>[  141.495160] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.495165] [drm:intel_update_fbc], fbc disabled per module param
>[  141.511818] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.511823] [drm:intel_update_fbc], fbc disabled per module param
>[  141.528415] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.528419] [drm:intel_update_fbc], fbc disabled per module param
>[  141.545046] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.545050] [drm:intel_update_fbc], fbc disabled per module param
>[  141.561671] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.561675] [drm:intel_update_fbc], fbc disabled per module param
>[  141.578274] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.578279] [drm:intel_update_fbc], fbc disabled per module param
>[  141.594927] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.594931] [drm:intel_update_fbc], fbc disabled per module param
>[  141.611495] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.611500] [drm:intel_update_fbc], fbc disabled per module param
>[  141.628110] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.628114] [drm:intel_update_fbc], fbc disabled per module param
>[  141.644811] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.644816] [drm:intel_update_fbc], fbc disabled per module param
>[  141.661466] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.661470] [drm:intel_update_fbc], fbc disabled per module param
>[  141.678068] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.678072] [drm:intel_update_fbc], fbc disabled per module param
>[  141.694650] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.694655] [drm:intel_update_fbc], fbc disabled per module param
>[  141.711278] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.711283] [drm:intel_update_fbc], fbc disabled per module param
>[  141.727954] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.727958] [drm:intel_update_fbc], fbc disabled per module param
>[  141.744558] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.744563] [drm:intel_update_fbc], fbc disabled per module param
>[  141.761215] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.761219] [drm:intel_update_fbc], fbc disabled per module param
>[  141.777791] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.777796] [drm:intel_update_fbc], fbc disabled per module param
>[  141.794472] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.794476] [drm:intel_update_fbc], fbc disabled per module param
>[  141.811099] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.811103] [drm:intel_update_fbc], fbc disabled per module param
>[  141.827725] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.827729] [drm:intel_update_fbc], fbc disabled per module param
>[  141.844340] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.844345] [drm:intel_update_fbc], fbc disabled per module param
>[  141.860983] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.860987] [drm:intel_update_fbc], fbc disabled per module param
>[  141.877587] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.877592] [drm:intel_update_fbc], fbc disabled per module param
>[  141.894272] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.894277] [drm:intel_update_fbc], fbc disabled per module param
>[  141.910842] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.910847] [drm:intel_update_fbc], fbc disabled per module param
>[  141.923280] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  141.927496] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.927500] [drm:intel_update_fbc], fbc disabled per module param
>[  141.977381] [drm:intel_update_fbc], fbc set to per-chip default
>[  141.977385] [drm:intel_update_fbc], fbc disabled per module param
>[  141.977797] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  141.977804] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  141.977807] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  141.977810] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  141.977813] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  141.977817] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  141.977827] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  141.977832] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  141.977839] [drm:ironlake_edp_backlight_off], 
>[  142.178033] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  142.178040] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  142.178046] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  143.009397] [drm:intel_dp_link_down], 
>[  143.078910] [drm:intel_update_fbc], no output, disabling
>[  143.078928] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  143.078934] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  143.078937] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  143.078941] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  143.078946] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  143.078950] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  143.078955] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  143.078959] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  143.078963] [drm:intel_modeset_check_state], [CRTC:3]
>[  143.078966] [drm:intel_modeset_check_state], [CRTC:5]
>[  143.085825] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  143.085831] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  143.085835] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  143.085838] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  143.085842] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  143.085845] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  143.085848] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  143.085855] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  143.085862] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  143.085867] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  143.085872] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  143.085875] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  143.085883] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  143.085886] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  143.085891] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  143.085894] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  143.085907] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  143.085911] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  143.138175] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  143.138182] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  143.138189] [drm:intel_update_fbc], no output, disabling
>[  143.138194] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:11:1366x768]
>[  143.138199] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  143.138204] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  143.138208] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  143.138215] [drm:ironlake_edp_pll_on], 
>[  143.190085] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  143.241996] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  143.242001] [drm:intel_update_fbc], fbc set to per-chip default
>[  143.242003] [drm:intel_update_fbc], fbc disabled per module param
>[  143.242007] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  143.242012] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  143.242017] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  143.242027] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  143.242032] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  143.542893] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  143.543624] [drm:intel_dp_start_link_train], clock recovery OK
>[  143.543625] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  143.543628] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  143.543632] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  143.543639] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  143.543643] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  143.883892] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  143.883903] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  143.935821] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  143.936031] [drm:ironlake_edp_backlight_on], 
>[  143.976711] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  143.986685] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  143.986701] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  143.986707] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  143.986711] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  143.986716] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  143.986721] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  143.986726] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  143.986731] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  143.986736] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  143.986741] [drm:intel_modeset_check_state], [CRTC:3]
>[  143.986744] [drm:intel_modeset_check_state], [CRTC:5]
>[  143.986748] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  143.986753] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  152.589327] [drm:i915_driver_open], 
>[  152.589353] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  152.589362] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  152.589367] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  152.589372] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  152.589392] [drm:i915_driver_open], 
>[  152.589551] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  152.589561] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  152.589579] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  152.589583] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  152.589588] [drm:intel_dp_detect], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  152.589591] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  152.589604] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  152.589820] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  152.590037] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  152.590042] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  152.590060] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  152.590067] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  152.590071] [drm:drm_mode_debug_printmodeline], Modeline 30:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  152.590077] [drm:drm_mode_debug_printmodeline], Modeline 31:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  152.590087] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  152.636901] [drm:drm_mode_addfb], [FB:32]
>[  152.672797] [drm:drm_mode_addfb], [FB:33]
>[  152.672860] [drm:drm_mode_setcrtc], [CRTC:3]
>[  152.672869] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  152.672873] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  152.672882] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  152.672891] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  152.682655] [drm:intel_update_fbc], fbc set to per-chip default
>[  152.682659] [drm:intel_update_fbc], fbc disabled per module param
>[  153.696845] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.696850] [drm:intel_update_fbc], fbc disabled per module param
>[  153.696878] [drm:drm_mode_addfb], [FB:34]
>[  153.696980] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.713488] [drm:drm_mode_addfb], [FB:32]
>[  153.713523] [drm:intel_update_fbc], 
>[  153.713525] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.713529] fbc set to per-chip default
>[  153.713531] [drm:intel_update_fbc], fbc disabled per module param
>[  153.730116] [drm:drm_mode_addfb], [FB:33]
>[  153.730124] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.730129] [drm:intel_update_fbc], fbc disabled per module param
>[  153.730156] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.746746] [drm:drm_mode_addfb], [FB:34]
>[  153.746782] [drm:intel_update_fbc], 
>[  153.746784] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.746789] fbc set to per-chip default
>[  153.746791] [drm:intel_update_fbc], fbc disabled per module param
>[  153.763357] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.763362] [drm:intel_update_fbc], fbc disabled per module param
>[  153.763373] [drm:drm_mode_addfb], [FB:32]
>[  153.763407] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.779999] [drm:drm_mode_addfb], [FB:33]
>[  153.780034] [drm:intel_crtc_page_flip], 
>[  153.780038] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.780043] [drm:intel_update_fbc], fbc disabled per module param
>[  153.780048] flip queue: crtc already busy
>[  153.796629] [drm:drm_mode_addfb], [FB:34]
>[  153.796661] [drm:intel_crtc_page_flip], 
>[  153.796665] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.796670] [drm:intel_update_fbc], fbc disabled per module param
>[  153.796674] flip queue: crtc already busy
>[  153.813269] [drm:intel_update_fbc], 
>[  153.813274] [drm:drm_mode_addfb], [FB:32]
>[  153.813281] fbc set to per-chip default
>[  153.813283] [drm:intel_update_fbc], fbc disabled per module param
>[  153.813321] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.829903] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.829907] [drm:intel_update_fbc], fbc disabled per module param
>[  153.829919] [drm:drm_mode_addfb], [FB:33]
>[  153.829956] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.846514] [drm:drm_mode_addfb], [FB:34]
>[  153.846552] [drm:intel_crtc_page_flip], 
>[  153.846554] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.846560] [drm:intel_update_fbc], fbc disabled per module param
>[  153.846562] flip queue: crtc already busy
>[  153.863141] [drm:drm_mode_addfb], [FB:32]
>[  153.863152] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.863156] [drm:intel_update_fbc], fbc disabled per module param
>[  153.863174] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.879771] [drm:drm_mode_addfb], [FB:33]
>[  153.879809] [drm:intel_crtc_page_flip], 
>[  153.879811] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.879817] [drm:intel_update_fbc], fbc disabled per module param
>[  153.879820] flip queue: crtc already busy
>[  153.896383] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.896388] [drm:intel_update_fbc], fbc disabled per module param
>[  153.896399] [drm:drm_mode_addfb], [FB:34]
>[  153.896434] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.913030] [drm:drm_mode_addfb], [FB:32]
>[  153.913067] [drm:intel_update_fbc], 
>[  153.913068] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.913073] fbc set to per-chip default
>[  153.913075] [drm:intel_update_fbc], fbc disabled per module param
>[  153.929655] [drm:drm_mode_addfb], [FB:33]
>[  153.929689] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.929694] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.929700] [drm:intel_update_fbc], fbc disabled per module param
>[  153.946310] [drm:drm_mode_addfb], [FB:34]
>[  153.946339] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.946344] [drm:intel_update_fbc], fbc disabled per module param
>[  153.946354] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.962916] [drm:drm_mode_addfb], [FB:32]
>[  153.962952] [drm:intel_update_fbc], 
>[  153.962954] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.962958] fbc set to per-chip default
>[  153.962960] [drm:intel_update_fbc], fbc disabled per module param
>[  153.979525] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.979530] [drm:intel_update_fbc], fbc disabled per module param
>[  153.979541] [drm:drm_mode_addfb], [FB:33]
>[  153.979578] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  153.996145] [drm:drm_mode_addfb], [FB:34]
>[  153.996184] [drm:intel_crtc_page_flip], 
>[  153.996185] [drm:intel_update_fbc], fbc set to per-chip default
>[  153.996191] [drm:intel_update_fbc], fbc disabled per module param
>[  153.996194] flip queue: crtc already busy
>[  154.012797] [drm:drm_mode_addfb], [FB:32]
>[  154.012812] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.012816] [drm:intel_update_fbc], fbc disabled per module param
>[  154.012831] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.029461] [drm:drm_mode_addfb], [FB:33]
>[  154.029496] [drm:intel_update_fbc], 
>[  154.029498] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.029503] fbc set to per-chip default
>[  154.029506] [drm:intel_update_fbc], fbc disabled per module param
>[  154.046059] [drm:drm_mode_addfb], [FB:34]
>[  154.046095] [drm:intel_update_fbc], 
>[  154.046096] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.046101] fbc set to per-chip default
>[  154.046103] [drm:intel_update_fbc], fbc disabled per module param
>[  154.062695] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.062700] [drm:intel_update_fbc], fbc disabled per module param
>[  154.062712] [drm:drm_mode_addfb], [FB:32]
>[  154.062746] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.079312] [drm:drm_mode_addfb], [FB:33]
>[  154.079350] [drm:intel_crtc_page_flip], 
>[  154.079351] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.079357] [drm:intel_update_fbc], fbc disabled per module param
>[  154.079360] flip queue: crtc already busy
>[  154.095940] [drm:drm_mode_addfb], [FB:34]
>[  154.095972] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.095977] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.095983] [drm:intel_update_fbc], fbc disabled per module param
>[  154.112529] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.112533] [drm:intel_update_fbc], fbc disabled per module param
>[  154.112551] [drm:drm_mode_addfb], [FB:32]
>[  154.112592] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.129208] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.129213] [drm:intel_update_fbc], fbc disabled per module param
>[  154.129224] [drm:drm_mode_addfb], [FB:33]
>[  154.129261] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.145829] [drm:drm_mode_addfb], [FB:34]
>[  154.145866] [drm:intel_crtc_page_flip], 
>[  154.145868] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.145874] [drm:intel_update_fbc], fbc disabled per module param
>[  154.145877] flip queue: crtc already busy
>[  154.162453] [drm:drm_mode_addfb], [FB:32]
>[  154.162488] [drm:intel_crtc_page_flip], 
>[  154.162492] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.162497] [drm:intel_update_fbc], fbc disabled per module param
>[  154.162502] flip queue: crtc already busy
>[  154.179082] [drm:drm_mode_addfb], [FB:33]
>[  154.179091] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.179095] [drm:intel_update_fbc], fbc disabled per module param
>[  154.179123] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.195707] [drm:intel_update_fbc], 
>[  154.195709] [drm:drm_mode_addfb], [FB:34]
>[  154.195714] fbc set to per-chip default
>[  154.195716] [drm:intel_update_fbc], fbc disabled per module param
>[  154.195745] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.212304] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.212309] [drm:intel_update_fbc], fbc disabled per module param
>[  154.212325] [drm:drm_mode_addfb], [FB:32]
>[  154.212366] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.228968] [drm:drm_mode_addfb], [FB:33]
>[  154.229006] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.229010] [drm:intel_update_fbc], fbc disabled per module param
>[  154.229026] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.245596] [drm:drm_mode_addfb], [FB:34]
>[  154.245605] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.245610] [drm:intel_update_fbc], fbc disabled per module param
>[  154.245637] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.262221] [drm:intel_update_fbc], 
>[  154.262223] [drm:drm_mode_addfb], [FB:32]
>[  154.262228] fbc set to per-chip default
>[  154.262230] [drm:intel_update_fbc], fbc disabled per module param
>[  154.262259] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.278838] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.278842] [drm:intel_update_fbc], fbc disabled per module param
>[  154.278854] [drm:drm_mode_addfb], [FB:33]
>[  154.278907] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.295483] [drm:drm_mode_addfb], [FB:34]
>[  154.295519] [drm:intel_update_fbc], 
>[  154.295520] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.295526] fbc set to per-chip default
>[  154.295528] [drm:intel_update_fbc], fbc disabled per module param
>[  154.312110] [drm:drm_mode_addfb], [FB:32]
>[  154.312120] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.312124] [drm:intel_update_fbc], fbc disabled per module param
>[  154.312145] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.328740] [drm:drm_mode_addfb], [FB:33]
>[  154.328774] [drm:intel_update_fbc], 
>[  154.328775] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.328781] fbc set to per-chip default
>[  154.328784] [drm:intel_update_fbc], fbc disabled per module param
>[  154.345352] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.345357] [drm:intel_update_fbc], fbc disabled per module param
>[  154.345369] [drm:drm_mode_addfb], [FB:34]
>[  154.345403] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.361994] [drm:drm_mode_addfb], [FB:32]
>[  154.362004] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.362008] [drm:intel_update_fbc], fbc disabled per module param
>[  154.362028] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.378623] [drm:drm_mode_addfb], [FB:33]
>[  154.378633] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.378637] [drm:intel_update_fbc], fbc disabled per module param
>[  154.378656] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.395255] [drm:drm_mode_addfb], [FB:34]
>[  154.395291] [drm:intel_update_fbc], 
>[  154.395293] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.395297] fbc set to per-chip default
>[  154.395299] [drm:intel_update_fbc], fbc disabled per module param
>[  154.411851] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.411856] [drm:intel_update_fbc], fbc disabled per module param
>[  154.411871] [drm:drm_mode_addfb], [FB:32]
>[  154.411913] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.428512] [drm:drm_mode_addfb], [FB:33]
>[  154.428548] [drm:intel_update_fbc], 
>[  154.428550] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.428554] fbc set to per-chip default
>[  154.428556] [drm:intel_update_fbc], fbc disabled per module param
>[  154.445139] [drm:drm_mode_addfb], [FB:34]
>[  154.445174] [drm:intel_update_fbc], 
>[  154.445176] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.445181] fbc set to per-chip default
>[  154.445183] [drm:intel_update_fbc], fbc disabled per module param
>[  154.461765] [drm:drm_mode_addfb], [FB:32]
>[  154.461798] [drm:intel_crtc_page_flip], 
>[  154.461802] [drm:intel_update_fbc], flip queue: crtc already busy
>[  154.461808] fbc set to per-chip default
>[  154.461811] [drm:intel_update_fbc], fbc disabled per module param
>[  154.478429] [drm:drm_mode_addfb], [FB:33]
>[  154.478467] [drm:intel_crtc_page_flip], 
>[  154.478469] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.478475] [drm:intel_update_fbc], fbc disabled per module param
>[  154.478478] flip queue: crtc already busy
>[  154.495007] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.495012] [drm:intel_update_fbc], fbc disabled per module param
>[  154.495023] [drm:drm_mode_addfb], [FB:34]
>[  154.495057] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.511647] [drm:intel_update_fbc], 
>[  154.511649] [drm:drm_mode_addfb], [FB:32]
>[  154.511654] fbc set to per-chip default
>[  154.511656] [drm:intel_update_fbc], fbc disabled per module param
>[  154.511685] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.528312] [drm:drm_mode_addfb], [FB:33]
>[  154.528349] [drm:intel_crtc_page_flip], 
>[  154.528350] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.528356] [drm:intel_update_fbc], fbc disabled per module param
>[  154.528359] flip queue: crtc already busy
>[  154.544910] [drm:drm_mode_addfb], [FB:34]
>[  154.544944] [drm:intel_update_fbc], 
>[  154.544946] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.544951] fbc set to per-chip default
>[  154.544954] [drm:intel_update_fbc], fbc disabled per module param
>[  154.561566] [drm:drm_mode_addfb], [FB:32]
>[  154.561600] [drm:intel_crtc_page_flip], 
>[  154.561601] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.561607] [drm:intel_update_fbc], fbc disabled per module param
>[  154.561609] flip queue: crtc already busy
>[  154.578158] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.578162] [drm:intel_update_fbc], fbc disabled per module param
>[  154.578174] [drm:drm_mode_addfb], [FB:33]
>[  154.578208] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.594793] [drm:drm_mode_addfb], [FB:34]
>[  154.594828] [drm:intel_crtc_page_flip], 
>[  154.594832] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.594837] [drm:intel_update_fbc], fbc disabled per module param
>[  154.594841] flip queue: crtc already busy
>[  154.611445] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.611451] [drm:drm_mode_addfb], [FB:32]
>[  154.611458] [drm:intel_update_fbc], fbc disabled per module param
>[  154.611492] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.628037] [drm:intel_update_fbc], 
>[  154.628042] [drm:drm_mode_addfb], fbc set to per-chip default
>[  154.628049] [drm:intel_update_fbc], fbc disabled per module param
>[  154.628053] [FB:33]
>[  154.628086] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.644677] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.644682] [drm:intel_update_fbc], fbc disabled per module param
>[  154.644696] [drm:drm_mode_addfb], [FB:34]
>[  154.644731] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.661291] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.661295] [drm:intel_update_fbc], fbc disabled per module param
>[  154.661308] [drm:drm_mode_addfb], [FB:32]
>[  154.661345] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.677938] [drm:drm_mode_addfb], [FB:33]
>[  154.677970] [drm:intel_crtc_page_flip], 
>[  154.677974] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.677979] [drm:intel_update_fbc], fbc disabled per module param
>[  154.677983] flip queue: crtc already busy
>[  154.694563] [drm:drm_mode_addfb], [FB:34]
>[  154.694574] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.694579] [drm:intel_update_fbc], fbc disabled per module param
>[  154.694598] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.711192] [drm:drm_mode_addfb], [FB:32]
>[  154.711224] [drm:intel_crtc_page_flip], 
>[  154.711228] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.711232] [drm:intel_update_fbc], fbc disabled per module param
>[  154.711237] flip queue: crtc already busy
>[  154.727806] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.727811] [drm:intel_update_fbc], fbc disabled per module param
>[  154.727822] [drm:drm_mode_addfb], [FB:33]
>[  154.727858] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.744451] [drm:drm_mode_addfb], [FB:34]
>[  154.744487] [drm:intel_update_fbc], 
>[  154.744489] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.744493] fbc set to per-chip default
>[  154.744495] [drm:intel_update_fbc], fbc disabled per module param
>[  154.761082] [drm:drm_mode_addfb], 
>[  154.761087] [drm:intel_update_fbc], [FB:32]
>[  154.761092] fbc set to per-chip default
>[  154.761094] [drm:intel_update_fbc], fbc disabled per module param
>[  154.761123] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.777742] [drm:drm_mode_addfb], [FB:33]
>[  154.777778] [drm:intel_update_fbc], 
>[  154.777780] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.777785] fbc set to per-chip default
>[  154.777787] [drm:intel_update_fbc], fbc disabled per module param
>[  154.794319] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.794324] [drm:intel_update_fbc], fbc disabled per module param
>[  154.794335] [drm:drm_mode_addfb], [FB:34]
>[  154.794370] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.810980] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.810986] [drm:intel_update_fbc], fbc disabled per module param
>[  154.811002] [drm:drm_mode_addfb], [FB:32]
>[  154.811042] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.827614] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.827622] [drm:drm_mode_addfb], [FB:33]
>[  154.827628] [drm:intel_update_fbc], fbc disabled per module param
>[  154.827662] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.844149] [drm:drm_mode_addfb], [FB:34]
>[  154.844186] [drm:intel_update_fbc], 
>[  154.844188] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.844194] fbc set to per-chip default
>[  154.844196] [drm:intel_update_fbc], fbc disabled per module param
>[  154.860833] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.860838] [drm:intel_update_fbc], fbc disabled per module param
>[  154.860851] [drm:drm_mode_addfb], [FB:32]
>[  154.860913] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.877479] [drm:drm_mode_addfb], [FB:33]
>[  154.877515] [drm:intel_update_fbc], 
>[  154.877517] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.877522] fbc set to per-chip default
>[  154.877523] [drm:intel_update_fbc], fbc disabled per module param
>[  154.894104] [drm:drm_mode_addfb], [FB:34]
>[  154.894114] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.894119] [drm:intel_update_fbc], fbc disabled per module param
>[  154.894137] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.910768] [drm:drm_mode_addfb], [FB:32]
>[  154.910814] [drm:intel_update_fbc], 
>[  154.910819] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.910825] fbc set to per-chip default
>[  154.910828] [drm:intel_update_fbc], fbc disabled per module param
>[  154.927362] [drm:drm_mode_addfb], [FB:33]
>[  154.927397] [drm:intel_crtc_page_flip], 
>[  154.927401] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.927406] [drm:intel_update_fbc], fbc disabled per module param
>[  154.927410] flip queue: crtc already busy
>[  154.943989] [drm:drm_mode_addfb], [FB:34]
>[  154.944023] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.944028] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.944035] [drm:intel_update_fbc], fbc disabled per module param
>[  154.960636] [drm:intel_update_fbc], fbc set to per-chip default
>[  154.960641] [drm:intel_update_fbc], fbc disabled per module param
>[  154.960652] [drm:drm_mode_addfb], [FB:32]
>[  154.960686] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.977249] [drm:drm_mode_addfb], [FB:33]
>[  154.977285] [drm:intel_update_fbc], 
>[  154.977286] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  154.977291] fbc set to per-chip default
>[  154.977293] [drm:intel_update_fbc], fbc disabled per module param
>[  154.993855] [drm:intel_update_fbc], 
>[  154.993859] [drm:drm_mode_addfb], [FB:34]
>[  154.993866] fbc set to per-chip default
>[  154.993868] [drm:intel_update_fbc], fbc disabled per module param
>[  154.993902] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.010502] [drm:drm_mode_addfb], [FB:32]
>[  155.010513] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.010518] [drm:intel_update_fbc], fbc disabled per module param
>[  155.010535] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.027135] [drm:drm_mode_addfb], [FB:33]
>[  155.027170] [drm:intel_update_fbc], 
>[  155.027172] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.027177] fbc set to per-chip default
>[  155.027179] [drm:intel_update_fbc], fbc disabled per module param
>[  155.043745] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.043750] [drm:intel_update_fbc], fbc disabled per module param
>[  155.043762] [drm:drm_mode_addfb], [FB:34]
>[  155.043799] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.060386] [drm:intel_update_fbc], 
>[  155.060388] [drm:drm_mode_addfb], [FB:32]
>[  155.060392] fbc set to per-chip default
>[  155.060394] [drm:intel_update_fbc], fbc disabled per module param
>[  155.060424] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.077017] [drm:drm_mode_addfb], [FB:33]
>[  155.077028] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.077032] [drm:intel_update_fbc], fbc disabled per module param
>[  155.077053] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.093633] [drm:drm_mode_addfb], [FB:34]
>[  155.093665] [drm:intel_crtc_page_flip], 
>[  155.093668] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.093673] [drm:intel_update_fbc], fbc disabled per module param
>[  155.093677] flip queue: crtc already busy
>[  155.110275] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.110280] [drm:intel_update_fbc], fbc disabled per module param
>[  155.110293] [drm:drm_mode_addfb], [FB:32]
>[  155.110328] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.126906] [drm:drm_mode_addfb], [FB:33]
>[  155.126941] [drm:intel_update_fbc], 
>[  155.126943] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.126948] fbc set to per-chip default
>[  155.126950] [drm:intel_update_fbc], fbc disabled per module param
>[  155.143531] [drm:drm_mode_addfb], [FB:34]
>[  155.143541] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.143545] [drm:intel_update_fbc], fbc disabled per module param
>[  155.143572] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.160136] [drm:drm_mode_addfb], [FB:32]
>[  155.160168] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.160173] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.160179] [drm:intel_update_fbc], fbc disabled per module param
>[  155.176790] [drm:drm_mode_addfb], [FB:33]
>[  155.176825] [drm:intel_crtc_page_flip], 
>[  155.176829] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.176834] [drm:intel_update_fbc], fbc disabled per module param
>[  155.176838] flip queue: crtc already busy
>[  155.193401] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.193406] [drm:intel_update_fbc], fbc disabled per module param
>[  155.193419] [drm:drm_mode_addfb], [FB:34]
>[  155.193456] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.210071] [drm:drm_mode_addfb], [FB:32]
>[  155.210108] [drm:intel_update_fbc], 
>[  155.210109] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.210114] fbc set to per-chip default
>[  155.210116] [drm:intel_update_fbc], fbc disabled per module param
>[  155.226687] [drm:drm_mode_addfb], [FB:33]
>[  155.226721] [drm:intel_update_fbc], 
>[  155.226723] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.226729] fbc set to per-chip default
>[  155.226731] [drm:intel_update_fbc], fbc disabled per module param
>[  155.243305] [drm:drm_mode_addfb], [FB:34]
>[  155.243341] [drm:intel_update_fbc], 
>[  155.243342] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.243347] fbc set to per-chip default
>[  155.243349] [drm:intel_update_fbc], fbc disabled per module param
>[  155.259916] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.259921] [drm:intel_update_fbc], fbc disabled per module param
>[  155.259932] [drm:drm_mode_addfb], [FB:32]
>[  155.259966] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.276561] [drm:drm_mode_addfb], [FB:33]
>[  155.276596] [drm:intel_update_fbc], 
>[  155.276598] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.276603] fbc set to per-chip default
>[  155.276605] [drm:intel_update_fbc], fbc disabled per module param
>[  155.293214] [drm:drm_mode_addfb], [FB:34]
>[  155.293242] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.293247] [drm:intel_update_fbc], fbc disabled per module param
>[  155.293257] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.309819] [drm:drm_mode_addfb], [FB:32]
>[  155.309856] [drm:intel_crtc_page_flip], 
>[  155.309858] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.309864] [drm:intel_update_fbc], fbc disabled per module param
>[  155.309866] flip queue: crtc already busy
>[  155.326429] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.326434] [drm:intel_update_fbc], fbc disabled per module param
>[  155.326446] [drm:drm_mode_addfb], [FB:33]
>[  155.326480] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.343078] [drm:drm_mode_addfb], [FB:34]
>[  155.343114] [drm:intel_update_fbc], 
>[  155.343116] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.343120] fbc set to per-chip default
>[  155.343122] [drm:intel_update_fbc], fbc disabled per module param
>[  155.359700] [drm:drm_mode_addfb], [FB:32]
>[  155.359735] [drm:intel_update_fbc], 
>[  155.359737] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.359742] fbc set to per-chip default
>[  155.359745] [drm:intel_update_fbc], fbc disabled per module param
>[  155.376333] [drm:drm_mode_addfb], [FB:33]
>[  155.376369] [drm:intel_crtc_page_flip], 
>[  155.376371] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.376377] [drm:intel_update_fbc], fbc disabled per module param
>[  155.376380] flip queue: crtc already busy
>[  155.392942] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.392947] [drm:intel_update_fbc], fbc disabled per module param
>[  155.392960] [drm:drm_mode_addfb], [FB:34]
>[  155.393014] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.409599] [drm:intel_update_fbc], 
>[  155.409604] [drm:drm_mode_addfb], [FB:32]
>[  155.409610] fbc set to per-chip default
>[  155.409612] [drm:intel_update_fbc], fbc disabled per module param
>[  155.409648] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.426217] [drm:drm_mode_addfb], [FB:33]
>[  155.426251] [drm:intel_update_fbc], 
>[  155.426253] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.426259] fbc set to per-chip default
>[  155.426261] [drm:intel_update_fbc], fbc disabled per module param
>[  155.442869] [drm:drm_mode_addfb], [FB:34]
>[  155.442901] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.442905] [drm:intel_update_fbc], fbc disabled per module param
>[  155.442918] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.459507] [drm:drm_mode_addfb], [FB:32]
>[  155.459544] [drm:intel_update_fbc], 
>[  155.459546] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.459551] fbc set to per-chip default
>[  155.459552] [drm:intel_update_fbc], fbc disabled per module param
>[  155.476085] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.476089] [drm:intel_update_fbc], fbc disabled per module param
>[  155.476102] [drm:drm_mode_addfb], [FB:33]
>[  155.476135] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.492762] [drm:drm_mode_addfb], [FB:34]
>[  155.492803] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.492808] [drm:intel_update_fbc], fbc disabled per module param
>[  155.492904] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.509357] [drm:drm_mode_addfb], [FB:32]
>[  155.509367] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.509371] [drm:intel_update_fbc], fbc disabled per module param
>[  155.509399] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.525988] [drm:drm_mode_addfb], [FB:33]
>[  155.526024] [drm:intel_update_fbc], 
>[  155.526026] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.526030] fbc set to per-chip default
>[  155.526032] [drm:intel_update_fbc], fbc disabled per module param
>[  155.542614] [drm:drm_mode_addfb], [FB:34]
>[  155.542623] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.542627] [drm:intel_update_fbc], fbc disabled per module param
>[  155.542655] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.559245] [drm:drm_mode_addfb], [FB:32]
>[  155.559280] [drm:intel_update_fbc], 
>[  155.559281] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.559286] fbc set to per-chip default
>[  155.559288] [drm:intel_update_fbc], fbc disabled per module param
>[  155.575882] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.575887] [drm:intel_update_fbc], fbc disabled per module param
>[  155.575898] [drm:drm_mode_addfb], [FB:33]
>[  155.575932] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.592512] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.592516] [drm:intel_update_fbc], fbc disabled per module param
>[  155.592521] [drm:drm_mode_addfb], [FB:34]
>[  155.592560] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.595642] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  155.609137] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.609141] [drm:intel_update_fbc], fbc disabled per module param
>[  155.646666] [drm:drm_mode_addfb], [FB:32]
>[  155.646701] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  155.659022] [drm:intel_update_fbc], fbc set to per-chip default
>[  155.659027] [drm:intel_update_fbc], fbc disabled per module param
>[  155.659348] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  155.659352] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  155.659354] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  155.659356] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  155.659358] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  155.659360] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  155.659369] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  155.659373] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  155.659378] [drm:ironlake_edp_backlight_off], 
>[  155.859430] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  155.859437] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  155.859443] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  156.656867] [drm:intel_dp_link_down], 
>[  156.726381] [drm:intel_update_fbc], no output, disabling
>[  156.726400] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  156.726405] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  156.726408] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  156.726413] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  156.726417] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  156.726422] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  156.726426] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  156.726430] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  156.726434] [drm:intel_modeset_check_state], [CRTC:3]
>[  156.726437] [drm:intel_modeset_check_state], [CRTC:5]
>[  156.733234] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  156.733240] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  156.733244] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  156.733247] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  156.733251] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  156.733255] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  156.733258] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  156.733265] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  156.733272] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  156.733276] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  156.733280] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  156.733284] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  156.733292] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  156.733296] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  156.733300] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  156.733303] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  156.733316] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  156.733320] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  156.785645] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  156.785652] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  156.785658] [drm:intel_update_fbc], no output, disabling
>[  156.785663] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:11:1366x768]
>[  156.785669] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  156.785673] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  156.785678] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  156.785685] [drm:ironlake_edp_pll_on], 
>[  156.837556] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  156.889465] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  156.889470] [drm:intel_update_fbc], fbc set to per-chip default
>[  156.889473] [drm:intel_update_fbc], fbc disabled per module param
>[  156.889477] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  156.889481] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  156.889487] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  156.889497] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  156.889501] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  157.190362] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  157.191095] [drm:intel_dp_start_link_train], clock recovery OK
>[  157.191096] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  157.191099] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  157.191103] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  157.191110] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  157.191114] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  157.531362] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  157.531373] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  157.583346] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  157.583557] [drm:ironlake_edp_backlight_on], 
>[  157.624225] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  157.634158] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  157.634173] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  157.634179] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  157.634183] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  157.634188] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  157.634193] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  157.634198] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  157.634203] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  157.634208] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  157.634213] [drm:intel_modeset_check_state], [CRTC:3]
>[  157.634216] [drm:intel_modeset_check_state], [CRTC:5]
>[  157.634221] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  157.634225] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  163.768465] [drm:i915_driver_open], 
>[  163.768492] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  163.768502] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  163.768507] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  163.768511] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  163.768548] [drm:i915_driver_open], 
>[  163.768845] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  163.768856] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  163.768874] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  163.768878] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  163.768883] [drm:intel_dp_detect], DPCD: 11 0a 81 01 00 00 01 80 02 01 00 00 0f 07 00
>[  163.768886] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  163.768897] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  163.769109] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  163.769318] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  163.769321] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  163.769339] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  163.769346] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  163.769350] [drm:drm_mode_debug_printmodeline], Modeline 30:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  163.769356] [drm:drm_mode_debug_printmodeline], Modeline 31:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  163.769365] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  163.815779] [drm:drm_mode_addfb], [FB:32]
>[  163.852497] [drm:drm_mode_addfb], [FB:33]
>[  163.852561] [drm:drm_mode_setcrtc], [CRTC:3]
>[  163.852569] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  163.852574] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  163.852582] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  163.852591] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  163.870426] [drm:intel_update_fbc], fbc set to per-chip default
>[  163.870430] [drm:intel_update_fbc], fbc disabled per module param
>[  164.883419] [drm:intel_update_fbc], 
>[  164.883421] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.883426] fbc set to per-chip default
>[  164.883427] [drm:intel_update_fbc], fbc disabled per module param
>[  164.900012] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.900016] [drm:intel_update_fbc], fbc disabled per module param
>[  164.900028] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.916621] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.916626] [drm:intel_update_fbc], fbc disabled per module param
>[  164.916661] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.933285] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.933302] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.933306] [drm:intel_update_fbc], fbc disabled per module param
>[  164.949909] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.949922] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.949927] [drm:intel_update_fbc], fbc disabled per module param
>[  164.966503] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.966508] [drm:intel_update_fbc], fbc disabled per module param
>[  164.966542] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.983132] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.983137] [drm:intel_update_fbc], fbc disabled per module param
>[  164.983167] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  164.999788] [drm:intel_update_fbc], fbc set to per-chip default
>[  164.999793] [drm:intel_update_fbc], fbc disabled per module param
>[  164.999814] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.016456] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.016471] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.016476] [drm:intel_update_fbc], fbc disabled per module param
>[  165.033053] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.033068] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.033073] [drm:intel_update_fbc], fbc disabled per module param
>[  165.049645] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.049650] [drm:intel_update_fbc], fbc disabled per module param
>[  165.049681] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.066323] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.066328] [drm:intel_update_fbc], fbc disabled per module param
>[  165.066340] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.082909] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.082914] [drm:intel_update_fbc], fbc disabled per module param
>[  165.082924] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.099537] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.099541] [drm:intel_update_fbc], fbc disabled per module param
>[  165.099559] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.116185] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.116190] [drm:intel_update_fbc], fbc disabled per module param
>[  165.116273] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.132776] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.132782] [drm:intel_update_fbc], fbc disabled per module param
>[  165.132819] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.149454] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.149465] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.149470] [drm:intel_update_fbc], fbc disabled per module param
>[  165.166039] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.166045] [drm:intel_update_fbc], fbc disabled per module param
>[  165.166066] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.182717] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.182722] [drm:intel_update_fbc], fbc disabled per module param
>[  165.182743] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.199339] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.199356] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.199360] [drm:intel_update_fbc], fbc disabled per module param
>[  165.215967] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.215972] [drm:intel_update_fbc], fbc disabled per module param
>[  165.216002] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.232596] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.232607] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.232612] [drm:intel_update_fbc], fbc disabled per module param
>[  165.249218] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.249234] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.249239] [drm:intel_update_fbc], fbc disabled per module param
>[  165.265883] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.265901] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.265906] [drm:intel_update_fbc], fbc disabled per module param
>[  165.282444] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.282449] [drm:intel_update_fbc], fbc disabled per module param
>[  165.282481] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.299110] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.299126] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.299130] [drm:intel_update_fbc], fbc disabled per module param
>[  165.315767] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.315780] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.315785] [drm:intel_update_fbc], fbc disabled per module param
>[  165.332365] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.332379] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.332383] [drm:intel_update_fbc], fbc disabled per module param
>[  165.348959] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.348964] [drm:intel_update_fbc], fbc disabled per module param
>[  165.348996] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.365654] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.365671] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.365675] [drm:intel_update_fbc], fbc disabled per module param
>[  165.382239] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.382244] [drm:intel_update_fbc], fbc disabled per module param
>[  165.382255] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.398864] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.398869] [drm:intel_update_fbc], fbc disabled per module param
>[  165.398879] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.415541] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.415556] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.415561] [drm:intel_update_fbc], fbc disabled per module param
>[  165.432100] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.432105] [drm:intel_update_fbc], fbc disabled per module param
>[  165.432136] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.448730] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.448735] [drm:intel_update_fbc], fbc disabled per module param
>[  165.448761] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.465420] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.465435] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.465440] [drm:intel_update_fbc], fbc disabled per module param
>[  165.482007] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.482012] [drm:intel_update_fbc], fbc disabled per module param
>[  165.482023] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.498649] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.498667] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.498671] [drm:intel_update_fbc], fbc disabled per module param
>[  165.515277] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.515292] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.515296] [drm:intel_update_fbc], fbc disabled per module param
>[  165.531904] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.531919] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.531924] [drm:intel_update_fbc], fbc disabled per module param
>[  165.548499] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.548504] [drm:intel_update_fbc], fbc disabled per module param
>[  165.548535] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.565166] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.565177] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.565182] [drm:intel_update_fbc], fbc disabled per module param
>[  165.581780] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.581785] [drm:intel_update_fbc], fbc disabled per module param
>[  165.581795] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.598362] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.598366] [drm:intel_update_fbc], fbc disabled per module param
>[  165.598426] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.615025] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.615030] [drm:intel_update_fbc], fbc disabled per module param
>[  165.615061] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.631642] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.631647] [drm:intel_update_fbc], fbc disabled per module param
>[  165.631677] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.648270] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.648275] [drm:intel_update_fbc], fbc disabled per module param
>[  165.648354] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.664935] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.664947] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.664952] [drm:intel_update_fbc], fbc disabled per module param
>[  165.681551] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.681556] [drm:intel_update_fbc], fbc disabled per module param
>[  165.681566] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.698231] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.698239] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.698243] [drm:intel_update_fbc], fbc disabled per module param
>[  165.714784] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.714788] [drm:intel_update_fbc], fbc disabled per module param
>[  165.714819] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.731446] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.731464] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.731468] [drm:intel_update_fbc], fbc disabled per module param
>[  165.748105] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.748127] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.748136] [drm:intel_update_fbc], fbc disabled per module param
>[  165.764662] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.764667] [drm:intel_update_fbc], fbc disabled per module param
>[  165.764688] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.781297] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.781302] [drm:intel_update_fbc], fbc disabled per module param
>[  165.781333] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.797993] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.798010] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.798014] [drm:intel_update_fbc], fbc disabled per module param
>[  165.814576] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.814581] [drm:intel_update_fbc], fbc disabled per module param
>[  165.814591] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.831215] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.831234] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.831239] [drm:intel_update_fbc], fbc disabled per module param
>[  165.847844] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.847863] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.847868] [drm:intel_update_fbc], fbc disabled per module param
>[  165.864439] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.864444] [drm:intel_update_fbc], fbc disabled per module param
>[  165.864475] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.881105] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.881117] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.881121] [drm:intel_update_fbc], fbc disabled per module param
>[  165.897706] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.897710] [drm:intel_update_fbc], fbc disabled per module param
>[  165.897724] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.914349] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.914354] [drm:intel_update_fbc], fbc disabled per module param
>[  165.914364] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.930990] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.931006] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.931011] [drm:intel_update_fbc], fbc disabled per module param
>[  165.947581] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.947586] [drm:intel_update_fbc], fbc disabled per module param
>[  165.947617] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.964247] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.964263] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.964267] [drm:intel_update_fbc], fbc disabled per module param
>[  165.980872] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.980891] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.980895] [drm:intel_update_fbc], fbc disabled per module param
>[  165.997474] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  165.997491] [drm:intel_update_fbc], fbc set to per-chip default
>[  165.997496] [drm:intel_update_fbc], fbc disabled per module param
>[  166.014167] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.014180] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.014184] [drm:intel_update_fbc], fbc disabled per module param
>[  166.030722] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.030727] [drm:intel_update_fbc], fbc disabled per module param
>[  166.030760] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.047353] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.047357] [drm:intel_update_fbc], fbc disabled per module param
>[  166.047374] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.064013] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.064032] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.064037] [drm:intel_update_fbc], fbc disabled per module param
>[  166.080609] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.080614] [drm:intel_update_fbc], fbc disabled per module param
>[  166.080648] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.097283] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.097300] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.097304] [drm:intel_update_fbc], fbc disabled per module param
>[  166.113898] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.113916] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.113921] [drm:intel_update_fbc], fbc disabled per module param
>[  166.130526] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.130542] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.130547] [drm:intel_update_fbc], fbc disabled per module param
>[  166.147157] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.147173] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.147177] [drm:intel_update_fbc], fbc disabled per module param
>[  166.163785] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.163799] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.163804] [drm:intel_update_fbc], fbc disabled per module param
>[  166.180378] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.180383] [drm:intel_update_fbc], fbc disabled per module param
>[  166.180417] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.196987] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.196991] [drm:intel_update_fbc], fbc disabled per module param
>[  166.197031] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.213705] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.213719] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.213723] [drm:intel_update_fbc], fbc disabled per module param
>[  166.230294] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.230298] [drm:intel_update_fbc], fbc disabled per module param
>[  166.230309] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.246896] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.246900] [drm:intel_update_fbc], fbc disabled per module param
>[  166.246931] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.263558] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.263570] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.263575] [drm:intel_update_fbc], fbc disabled per module param
>[  166.280183] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.280211] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.280220] [drm:intel_update_fbc], fbc disabled per module param
>[  166.296781] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.296786] [drm:intel_update_fbc], fbc disabled per module param
>[  166.296810] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.313408] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.313412] [drm:intel_update_fbc], fbc disabled per module param
>[  166.313447] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.330070] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.330088] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.330092] [drm:intel_update_fbc], fbc disabled per module param
>[  166.346651] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.346655] [drm:intel_update_fbc], fbc disabled per module param
>[  166.346693] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.363295] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.363300] [drm:intel_update_fbc], fbc disabled per module param
>[  166.363326] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.379922] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.379927] [drm:intel_update_fbc], fbc disabled per module param
>[  166.379957] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.396548] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.396553] [drm:intel_update_fbc], fbc disabled per module param
>[  166.396584] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.413216] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.413227] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.413232] [drm:intel_update_fbc], fbc disabled per module param
>[  166.429869] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.429885] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.429890] [drm:intel_update_fbc], fbc disabled per module param
>[  166.446471] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.446484] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.446489] [drm:intel_update_fbc], fbc disabled per module param
>[  166.463063] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.463068] [drm:intel_update_fbc], fbc disabled per module param
>[  166.463101] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.479691] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.479696] [drm:intel_update_fbc], fbc disabled per module param
>[  166.479726] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.496357] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.496369] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.496373] [drm:intel_update_fbc], fbc disabled per module param
>[  166.512972] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.512977] [drm:intel_update_fbc], fbc disabled per module param
>[  166.512988] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.529644] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.529659] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.529664] [drm:intel_update_fbc], fbc disabled per module param
>[  166.546205] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.546210] [drm:intel_update_fbc], fbc disabled per module param
>[  166.546241] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.562865] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.562869] [drm:intel_update_fbc], fbc disabled per module param
>[  166.562894] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.579471] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.579489] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.579494] [drm:intel_update_fbc], fbc disabled per module param
>[  166.596127] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.596139] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.596144] [drm:intel_update_fbc], fbc disabled per module param
>[  166.612754] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.612759] [drm:intel_update_fbc], fbc disabled per module param
>[  166.612790] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.629385] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.629397] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.629401] [drm:intel_update_fbc], fbc disabled per module param
>[  166.645999] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.646004] [drm:intel_update_fbc], fbc disabled per module param
>[  166.646015] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.662613] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.662617] [drm:intel_update_fbc], fbc disabled per module param
>[  166.662632] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.679232] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.679237] [drm:intel_update_fbc], fbc disabled per module param
>[  166.679268] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.695897] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.695910] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.695914] [drm:intel_update_fbc], fbc disabled per module param
>[  166.712513] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.712518] [drm:intel_update_fbc], fbc disabled per module param
>[  166.712529] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.729187] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.729207] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.729211] [drm:intel_update_fbc], fbc disabled per module param
>[  166.745746] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.745751] [drm:intel_update_fbc], fbc disabled per module param
>[  166.745782] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.762384] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.762388] [drm:intel_update_fbc], fbc disabled per module param
>[  166.762411] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.768442] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0007
>[  166.779024] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.779029] [drm:intel_update_fbc], fbc disabled per module param
>[  166.819406] [drm:intel_crtc_page_flip], flip queue: crtc already busy
>[  166.828923] [drm:intel_update_fbc], fbc set to per-chip default
>[  166.828928] [drm:intel_update_fbc], fbc disabled per module param
>[  166.829358] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  166.829363] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  166.829365] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  166.829367] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  166.829370] [drm:intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  166.829377] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  166.829388] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd000f
>[  166.829393] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  166.829399] [drm:ironlake_edp_backlight_off], 
>[  167.030190] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  167.030197] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  167.030202] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  167.844579] [drm:intel_dp_link_down], 
>[  167.914091] [drm:intel_update_fbc], no output, disabling
>[  167.914110] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  167.914115] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  167.914118] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  167.914123] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  167.914127] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  167.914132] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  167.914136] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  167.914141] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  167.914145] [drm:intel_modeset_check_state], [CRTC:3]
>[  167.914148] [drm:intel_modeset_check_state], [CRTC:5]
>[  167.921036] [drm:intel_crtc_set_config], [CRTC:3] [FB:12] #connectors=1 (x y) (0 0)
>[  167.921042] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  167.921045] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  167.921049] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  167.921052] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  167.921055] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  167.921059] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  167.921065] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  167.921072] [drm:intel_dp_mode_fixup], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  167.921077] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 1 clock 270000 bpp 24
>[  167.921081] [drm:intel_dp_mode_fixup], DP link bw required 165600 available 216000
>[  167.921085] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  167.921092] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 6
>[  167.921096] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 6)
>[  167.921101] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  167.921103] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  167.921117] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  167.921121] [drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000
>[  167.973356] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  167.973363] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  167.973370] [drm:intel_update_fbc], no output, disabling
>[  167.973375] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:11:1366x768]
>[  167.973380] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  167.973385] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  167.973389] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  167.973396] [drm:ironlake_edp_pll_on], 
>[  168.025266] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.077173] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.077179] [drm:intel_update_fbc], fbc set to per-chip default
>[  168.077181] [drm:intel_update_fbc], fbc disabled per module param
>[  168.077185] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  168.077190] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  168.077195] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  168.077205] [drm:ironlake_edp_panel_vdd_on], PCH_PP_STATUS: 0x00000000 PCH_PP_CONTROL: 0xabcd0008
>[  168.077210] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  168.378075] [drm:intel_dp_start_link_train], training pattern 1 signal levels 00000000
>[  168.378808] [drm:intel_dp_start_link_train], clock recovery OK
>[  168.378811] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  168.378815] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  168.378820] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  168.378829] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  168.378834] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  168.719073] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  168.719084] [drm:ironlake_panel_vdd_off_sync], PCH_PP_STATUS: 0x80000008 PCH_PP_CONTROL: 0xabcd0003
>[  168.771002] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  168.771212] [drm:ironlake_edp_backlight_on], 
>[  168.811892] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  168.821894] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  168.821908] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  168.821913] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  168.821916] [drm:intel_modeset_check_state], [ENCODER:18:TMDS-18]
>[  168.821920] [drm:intel_modeset_check_state], [ENCODER:20:TMDS-20]
>[  168.821925] [drm:intel_modeset_check_state], [ENCODER:22:TMDS-22]
>[  168.821929] [drm:intel_modeset_check_state], [ENCODER:24:TMDS-24]
>[  168.821934] [drm:intel_modeset_check_state], [ENCODER:26:TMDS-26]
>[  168.821939] [drm:intel_modeset_check_state], [ENCODER:28:TMDS-28]
>[  168.821943] [drm:intel_modeset_check_state], [CRTC:3]
>[  168.821946] [drm:intel_modeset_check_state], [CRTC:5]
>[  168.821949] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  168.821953] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]

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Attachments on bug 59999: 73801 | 73802

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