Attachment 74922 Details for Bug 54089 – Fix-SNB-RC6-init-sequence

[patch] Fix-SNB-RC6-init-sequence

0001-drm-i915-Fix-SNB-RC6-init-sequence.patch (text/plain), 5.19 KB, created by Rodrigo Vivi on 2013-02-16 03:46:49 UTC

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Creator: Rodrigo Vivi

Created: 2013-02-16 03:46:49 UTC

Size: 5.19 KB

patch

obsolete

>From 7c3ec1cbcfdec354c0941343921a966f8fff035e Mon Sep 17 00:00:00 2001
>From: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>Date: Sat, 16 Feb 2013 00:55:48 -0200
>Subject: [PATCH] drm/i915: Fix SNB RC6 init sequence.
>
>According to SNB PM Programming guide this is the correct setup.
>Altough this doesn't seems to save so much power as the current version,
>this is an attempt to fix RC6 bugs such as gpu hungs and rc6 disabled after
>suspend-resume.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++----
> drivers/gpu/drm/i915/intel_pm.c | 53 +++++++++--------------------------------
> 2 files changed, 19 insertions(+), 46 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index e2b592a..3ae08d1 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4181,7 +4181,7 @@
> #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
> 
> #define GEN6_RPNSWREQ				0xA008
>-#define   GEN6_TURBO_DISABLE			(1<<31)
>+#define   GEN6_TURBO_DISABLE			(0<<31)
> #define   GEN6_FREQUENCY(x)			((x)<<25)
> #define   GEN6_OFFSET(x)			((x)<<19)
> #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
>@@ -4253,9 +4253,13 @@
> #define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
> #define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
> #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
>-#define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_RP_UP_THRESHOLD | \
>+#define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_MBOX_EVENT | \
>+						 GEN6_PM_THERMAL_EVENT | \
>+						 GEN6_PM_RP_DOWN_TIMEOUT | \
>+						 GEN6_PM_RP_UP_THRESHOLD | \
> 						 GEN6_PM_RP_DOWN_THRESHOLD | \
>-						 GEN6_PM_RP_DOWN_TIMEOUT)
>+						 GEN6_PM_RP_UP_EI_EXPIRED | \
>+						 GEN6_PM_RP_DOWN_EI_EXPIRED)
> 
> #define GEN6_GT_GFX_RC6_LOCKED			0x138104
> #define GEN6_GT_GFX_RC6				0x138108
>@@ -4265,7 +4269,7 @@
> #define GEN6_PCODE_MAILBOX			0x138124
> #define   GEN6_PCODE_READY			(1<<31)
> #define   GEN6_READ_OC_PARAMS			0xc
>-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
>+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x9
> #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
> #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
> #define	  GEN6_PCODE_READ_RC6VIDS		0x5
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index f024e7d..d1997b7 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2596,6 +2596,7 @@ static void gen6_enable_rps(struct drm_device *dev)
> 		   GEN6_RC_CTL_HW_ENABLE);
> 
> 	I915_WRITE(GEN6_RPNSWREQ,
>+		   GEN6_TURBO_DISABLE |
> 		   GEN6_FREQUENCY(10) |
> 		   GEN6_OFFSET(0) |
> 		   GEN6_AGGRESSIVE_TURBO);
>@@ -2604,59 +2605,27 @@ static void gen6_enable_rps(struct drm_device *dev)
> 
> 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
> 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
>-		   dev_priv->rps.max_delay << 24 |
>-		   dev_priv->rps.min_delay << 16);
>+		   18 << 24 |
>+		   6 << 16);
> 
>-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
>-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
>-	I915_WRITE(GEN6_RP_UP_EI, 66000);
>-	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
>+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
>+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
>+	I915_WRITE(GEN6_RP_UP_EI, 100000);
>+	I915_WRITE(GEN6_RP_DOWN_EI, 300000);
> 
> 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> 	I915_WRITE(GEN6_RP_CONTROL,
> 		   GEN6_RP_MEDIA_TURBO |
>-		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
>+		   GEN6_RP_MEDIA_HW_MODE |
> 		   GEN6_RP_MEDIA_IS_GFX |
> 		   GEN6_RP_ENABLE |
> 		   GEN6_RP_UP_BUSY_AVG |
>-		   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
>+		   GEN7_RP_DOWN_IDLE_AVG);
> 
>-	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
>-	if (!ret) {
>-		pcu_mbox = 0;
>-		ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
>-		if (ret && pcu_mbox & (1<<31)) { /* OC supported */
>-			dev_priv->rps.max_delay = pcu_mbox & 0xff;
>-			DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
>-		}
>-	} else {
>-		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
>-	}
>-
>-	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
>+	sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
> 
> 	/* requires MSI enabled */
> 	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
>-	spin_lock_irq(&dev_priv->rps.lock);
>-	WARN_ON(dev_priv->rps.pm_iir != 0);
>-	I915_WRITE(GEN6_PMIMR, 0);
>-	spin_unlock_irq(&dev_priv->rps.lock);
>-	/* enable all PM interrupts */
>-	I915_WRITE(GEN6_PMINTRMSK, 0);
>-
>-	rc6vids = 0;
>-	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
>-	if (IS_GEN6(dev) && ret) {
>-		DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
>-	} else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
>-		DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
>-			  GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
>-		rc6vids &= 0xffff00;
>-		rc6vids |= GEN6_ENCODE_RC6_VID(450);
>-		ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
>-		if (ret)
>-			DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
>-	}
> 
> 	gen6_gt_force_wake_put(dev_priv);
> }
>@@ -4474,7 +4443,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
> 		return -ETIMEDOUT;
> 	}
> 
>-	I915_WRITE(GEN6_PCODE_DATA, 0);
>+//	I915_WRITE(GEN6_PCODE_DATA, 0);
> 
> 	return 0;
> }
>-- 
>1.7.11.7
>

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Attachments on bug 54089: 66140 | 66941 | 68407 | 69241 | 69253 | 69299 | 74922

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