Attachment 75163 Details for Bug 61158 – netconsole.log

netconsole.log

netconsole.log (text/plain), 208.19 KB, created by shui yangwei on 2013-02-20 08:28:15 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: shui yangwei

Created: 2013-02-20 08:28:15 UTC

Size: 208.19 KB

patch

obsolete

>[  280.301405] netpoll: netconsole: local port 6665
>[  280.301430] netpoll: netconsole: local IP 0.0.0.0
>[  280.301452] netpoll: netconsole: interface 'em1'
>[  280.301474] netpoll: netconsole: remote port 6666
>[  280.301495] netpoll: netconsole: remote IP 10.239.47.97
>[  280.301517] netpoll: netconsole: remote ethernet address 4c:72:b9:21:53:bb
>[  280.301548] netpoll: netconsole: local IP 10.239.47.178
>[  280.301648] console [netcon0] enabled
>[  280.301666] netconsole: network logging started
>[  335.222343] [drm:i915_driver_open], 
>[  335.222399] [drm:intel_crtc_set_config], [CRTC:3] [FB:18] #connectors=1 (x y) (0 0)
>[  335.222442] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  335.222481] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  335.222512] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  335.222580] [drm:i915_driver_open], 
>[  335.222765] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[  335.222808] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3]
>[  335.222852] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  335.222884] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  335.222920] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  335.222965] [drm:intel_crt_detect], CRT not detected via hotplug
>[  335.223220] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  335.223265] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  335.223306] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  335.223346] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  335.223779] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  335.223819] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  335.223863] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  335.223901] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  335.223949] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  335.223978] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  335.224012] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  335.224058] [drm:intel_crt_detect], CRT not detected via hotplug
>[  335.224248] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  335.224288] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  335.224329] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  335.224369] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  335.224821] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  335.224860] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  335.224901] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  335.224940] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  335.224984] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  335.225013] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:HDMI-A-1]
>[  335.225208] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  335.225293] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  335.225332] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:HDMI-A-1] disconnected
>[  335.225374] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  335.225403] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:HDMI-A-1]
>[  335.225577] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  335.225672] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  335.225746] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:HDMI-A-1] disconnected
>[  335.225877] [drm:drm_mode_getconnector], [CONNECTOR:14:?]
>[  335.225915] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:14:DP-1]
>[  335.226339] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[  335.227091] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.246811] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.266527] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.266568] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[  335.267316] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.287038] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.306748] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[  335.306920] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[  335.306957] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[  335.307117] [drm:drm_mode_debug_printmodeline], Modeline 163:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[  335.307187] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[  335.307235] [drm:drm_mode_debug_printmodeline], Modeline 160:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[  335.307313] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[  335.307366] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:14:DP-1] probed modes :
>[  335.307423] [drm:drm_mode_debug_printmodeline], Modeline 16:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  335.307519] [drm:drm_mode_debug_printmodeline], Modeline 79:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  335.307596] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  335.307670] [drm:drm_mode_debug_printmodeline], Modeline 71:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  335.307747] [drm:drm_mode_debug_printmodeline], Modeline 70:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  335.307860] [drm:drm_mode_debug_printmodeline], Modeline 69:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  335.307950] [drm:drm_mode_debug_printmodeline], Modeline 78:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  335.308046] [drm:drm_mode_debug_printmodeline], Modeline 73:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  335.308140] [drm:drm_mode_debug_printmodeline], Modeline 72:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  335.308240] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  335.308337] [drm:drm_mode_debug_printmodeline], Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  335.308439] [drm:drm_mode_debug_printmodeline], Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  335.308537] [drm:drm_mode_debug_printmodeline], Modeline 95:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  335.308610] [drm:drm_mode_debug_printmodeline], Modeline 93:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  335.308683] [drm:drm_mode_debug_printmodeline], Modeline 81:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  335.308790] [drm:drm_mode_debug_printmodeline], Modeline 65:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  335.308888] [drm:drm_mode_debug_printmodeline], Modeline 64:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  335.308987] [drm:drm_mode_debug_printmodeline], Modeline 63:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  335.309088] [drm:drm_mode_debug_printmodeline], Modeline 62:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  335.309188] [drm:drm_mode_debug_printmodeline], Modeline 24:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  335.309289] [drm:drm_mode_debug_printmodeline], Modeline 68:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  335.309388] [drm:drm_mode_debug_printmodeline], Modeline 67:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  335.309488] [drm:drm_mode_debug_printmodeline], Modeline 66:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  335.309575] [drm:drm_mode_debug_printmodeline], Modeline 77:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  335.309650] [drm:drm_mode_debug_printmodeline], Modeline 58:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  335.309723] [drm:drm_mode_debug_printmodeline], Modeline 57:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  335.309801] [drm:drm_mode_debug_printmodeline], Modeline 56:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  335.312902] [drm:drm_mode_debug_printmodeline], Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  335.315948] [drm:drm_mode_debug_printmodeline], Modeline 54:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  335.318996] [drm:drm_mode_debug_printmodeline], Modeline 31:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  335.322043] [drm:drm_mode_debug_printmodeline], Modeline 23:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  335.325083] [drm:drm_mode_debug_printmodeline], Modeline 61:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  335.328119] [drm:drm_mode_debug_printmodeline], Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  335.331145] [drm:drm_mode_debug_printmodeline], Modeline 59:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  335.334255] [drm:drm_mode_debug_printmodeline], Modeline 53:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  335.337315] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  335.340403] [drm:drm_mode_debug_printmodeline], Modeline 75:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  335.343612] [drm:drm_mode_debug_printmodeline], Modeline 55:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  335.346791] [drm:drm_mode_debug_printmodeline], Modeline 51:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  335.349916] [drm:drm_mode_debug_printmodeline], Modeline 50:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  335.353058] [drm:drm_mode_debug_printmodeline], Modeline 22:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  335.356174] [drm:drm_mode_debug_printmodeline], Modeline 21:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  335.359282] [drm:drm_mode_debug_printmodeline], Modeline 49:"1280x768" 85 117500 1280 1360 1496 1712 768 771 778 809 0x40 0x6
>[  335.362398] [drm:drm_mode_debug_printmodeline], Modeline 48:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x9
>[  335.365510] [drm:drm_mode_debug_printmodeline], Modeline 47:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  335.368640] [drm:drm_mode_debug_printmodeline], Modeline 92:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  335.371737] [drm:drm_mode_debug_printmodeline], Modeline 82:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  335.374820] [drm:drm_mode_debug_printmodeline], Modeline 46:"1024x768" 85 94500 1024 1072 1168 1376 768 769 772 808 0x40 0x5
>[  335.377951] [drm:drm_mode_debug_printmodeline], Modeline 32:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  335.381053] [drm:drm_mode_debug_printmodeline], Modeline 45:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  335.384147] [drm:drm_mode_debug_printmodeline], Modeline 33:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  335.387221] [drm:drm_mode_debug_printmodeline], Modeline 44:"1024x768i" 86 44900 1024 1032 1208 1264 768 768 772 817 0x40 0x15
>[  335.390322] [drm:drm_mode_debug_printmodeline], Modeline 74:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  335.393407] [drm:drm_mode_debug_printmodeline], Modeline 42:"800x600" 85 56250 800 832 896 1048 600 601 604 631 0x40 0x5
>[  335.396005] [drm:drm_mode_debug_printmodeline], Modeline 41:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  335.398549] [drm:drm_mode_debug_printmodeline], Modeline 34:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  335.401087] [drm:drm_mode_debug_printmodeline], Modeline 27:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  335.403659] [drm:drm_mode_debug_printmodeline], Modeline 40:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  335.406180] [drm:drm_mode_debug_printmodeline], Modeline 90:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  335.408754] [drm:drm_mode_debug_printmodeline], Modeline 43:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  335.411270] [drm:drm_mode_debug_printmodeline], Modeline 84:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  335.413809] [drm:drm_mode_debug_printmodeline], Modeline 39:"640x480" 85 36000 640 696 752 832 480 481 484 509 0x40 0xa
>[  335.416324] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  335.418866] [drm:drm_mode_debug_printmodeline], Modeline 28:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  335.421380] [drm:drm_mode_debug_printmodeline], Modeline 29:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  335.423904] [drm:drm_mode_debug_printmodeline], Modeline 87:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  335.426462] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 85 35500 720 756 828 936 400 401 404 446 0x40 0x6
>[  335.428982] [drm:drm_mode_debug_printmodeline], Modeline 30:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  335.431519] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x400" 85 31500 640 672 736 832 400 401 404 445 0x40 0x6
>[  335.434051] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x350" 85 31500 640 672 736 832 350 382 385 445 0x40 0x9
>[  335.436601] [drm:drm_mode_getconnector], [CONNECTOR:14:?]
>[  336.355903] [drm:drm_mode_addfb], [FB:19]
>[  336.358486] [drm:drm_mode_setcrtc], [CRTC:3]
>[  336.360967] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  336.363428] [drm:intel_crtc_set_config], [CRTC:3] [FB:19] #connectors=1 (x y) (0 0)
>[  336.365891] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  336.368375] [drm:ironlake_update_plane], Writing base 00FE7000 00000000 0 0 10240
>[  346.485182] [drm:drm_mode_addfb], [FB:20]
>[  346.487746] [drm:drm_mode_setcrtc], [CRTC:3]
>[  346.490213] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  346.492659] [drm:intel_crtc_set_config], [CRTC:3] [FB:20] #connectors=1 (x y) (0 0)
>[  346.495128] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  346.497635] [drm:drm_mode_debug_printmodeline], Modeline 17:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[  346.500173] [drm:drm_mode_debug_printmodeline], Modeline 83:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  346.502718] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  346.505247] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  346.507749] [drm:drm_mode_debug_printmodeline], Modeline 83:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  346.510316] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  346.512950] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 267027KHz
>[  346.515573] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  346.518205] [drm:intel_dp_mode_fixup], DP link bw required 640865 available 864000
>[  346.520824] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  346.523644] [drm:intel_dp_link_down], 
>[  346.587670] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  346.590765] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  346.594242] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  346.597288] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  346.600343] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  346.603358] [drm:drm_mode_debug_printmodeline], Modeline 83:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  346.606456] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  346.609501] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  346.612848] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 4
>[  346.667636] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  346.670683] [drm:ironlake_update_plane], Writing base 01F87000 00000000 0 0 8192
>[  346.725610] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  346.728645] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:83:2048x1536]
>[  346.731702] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  346.734715] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  346.737736] [drm:ironlake_write_eld], ELD on pipe A
>[  346.740765] [drm:ironlake_write_eld], Audio directed to unknown port
>[  346.743791] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  346.746836] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 14, cursor: 6
>[  346.749879] [drm:ironlake_check_srwm], watermark 1: display plane 130, fbc lines 4, cursor 6
>[  346.752922] [drm:ironlake_check_srwm], watermark 2: display plane 361, fbc lines 5, cursor 14
>[  346.807576] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  346.862551] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  346.865892] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  346.868907] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  346.872078] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  346.875090] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  346.878089] [drm:ironlake_fdi_link_train], FDI train done
>[  346.881089] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  346.884103] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  346.888727] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  346.892419] [drm:intel_dp_start_link_train], clock recovery OK
>[  346.895516] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  346.899113] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  346.919535] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  346.922630] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  346.925264] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  346.927885] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  346.930494] [drm:intel_modeset_check_state], [CRTC:3]
>[  346.933117] [drm:intel_modeset_check_state], [CRTC:5]
>[  357.031074] [drm:drm_mode_addfb], [FB:83]
>[  357.033600] [drm:drm_mode_setcrtc], [CRTC:3]
>[  357.036041] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  357.038423] [drm:intel_crtc_set_config], [CRTC:3] [FB:83] #connectors=1 (x y) (0 0)
>[  357.040819] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  357.043217] [drm:drm_mode_debug_printmodeline], Modeline 83:"2048x1536" 60 267027 2048 2200 2424 2800 1536 1537 1540 1589 0x0 0x6
>[  357.045653] [drm:drm_mode_debug_printmodeline], Modeline 85:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  357.048112] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  357.050577] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  357.053010] [drm:drm_mode_debug_printmodeline], Modeline 85:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  357.055532] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  357.058043] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 234000KHz
>[  357.060577] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  357.063130] [drm:intel_dp_mode_fixup], DP link bw required 561600 available 864000
>[  357.065687] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  357.068410] [drm:intel_dp_link_down], 
>[  357.130199] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  357.132864] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  357.135924] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  357.138594] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  357.141260] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  357.143921] [drm:drm_mode_debug_printmodeline], Modeline 85:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  357.146649] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  357.149376] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  357.152404] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  357.207168] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  357.209901] [drm:ironlake_update_plane], Writing base 02B87000 00000000 0 0 7680
>[  357.264147] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  357.266804] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:85:1920x1440]
>[  357.269383] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  357.271943] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  357.274506] [drm:ironlake_write_eld], ELD on pipe A
>[  357.277080] [drm:ironlake_write_eld], Audio directed to unknown port
>[  357.279645] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  357.282196] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 13, cursor: 6
>[  357.284753] [drm:ironlake_check_srwm], watermark 1: display plane 122, fbc lines 4, cursor 6
>[  357.287314] [drm:ironlake_check_srwm], watermark 2: display plane 242, fbc lines 5, cursor 10
>[  357.342109] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  357.396118] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  357.399105] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  357.401670] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  357.404358] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  357.406874] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  357.409377] [drm:ironlake_fdi_link_train], FDI train done
>[  357.411856] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  357.414367] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  357.418505] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  357.422299] [drm:intel_dp_start_link_train], clock recovery OK
>[  357.425469] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  357.429086] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  357.450071] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  357.452679] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  357.455161] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  357.457597] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  357.460067] [drm:intel_modeset_check_state], [CRTC:3]
>[  357.462444] [drm:intel_modeset_check_state], [CRTC:5]
>[  367.559094] [drm:drm_mode_addfb], [FB:85]
>[  367.561557] [drm:drm_mode_setcrtc], [CRTC:3]
>[  367.563950] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  367.566286] [drm:intel_crtc_set_config], [CRTC:3] [FB:85] #connectors=1 (x y) (0 0)
>[  367.568636] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  367.570979] [drm:drm_mode_debug_printmodeline], Modeline 85:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[  367.573360] [drm:drm_mode_debug_printmodeline], Modeline 86:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  367.575746] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  367.578115] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  367.580481] [drm:drm_mode_debug_printmodeline], Modeline 86:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  367.582864] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  367.585291] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 218250KHz
>[  367.587685] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  367.590083] [drm:intel_dp_mode_fixup], DP link bw required 523800 available 864000
>[  367.592483] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  367.595080] [drm:intel_dp_link_down], 
>[  367.656723] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  367.659599] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  367.662930] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  367.665801] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  367.668672] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  367.671539] [drm:drm_mode_debug_printmodeline], Modeline 86:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  367.674601] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  367.677524] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  367.680777] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  367.735655] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  367.738229] [drm:ironlake_update_plane], Writing base 03613000 00000000 0 0 7424
>[  367.792660] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  367.795187] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:86:1856x1392]
>[  367.797653] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  367.800121] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  367.802604] [drm:ironlake_write_eld], ELD on pipe A
>[  367.805071] [drm:ironlake_write_eld], Audio directed to unknown port
>[  367.807541] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  367.810015] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 12, cursor: 6
>[  367.812494] [drm:ironlake_check_srwm], watermark 1: display plane 118, fbc lines 4, cursor 6
>[  367.814977] [drm:ironlake_check_srwm], watermark 2: display plane 234, fbc lines 5, cursor 10
>[  367.869600] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  367.923604] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  367.926436] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  367.928895] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  367.931509] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  367.934065] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  367.936548] [drm:ironlake_fdi_link_train], FDI train done
>[  367.939007] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  367.941501] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  367.945635] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  367.949412] [drm:intel_dp_start_link_train], clock recovery OK
>[  367.952576] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  367.956109] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  367.976605] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  367.979169] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  367.981708] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  367.984176] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  367.986596] [drm:intel_modeset_check_state], [CRTC:3]
>[  367.988993] [drm:intel_modeset_check_state], [CRTC:5]
>[  378.084140] [drm:drm_mode_addfb], [FB:86]
>[  378.086730] [drm:drm_mode_setcrtc], [CRTC:3]
>[  378.089150] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  378.091567] [drm:intel_crtc_set_config], [CRTC:3] [FB:86] #connectors=1 (x y) (0 0)
>[  378.093948] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  378.096323] [drm:drm_mode_debug_printmodeline], Modeline 86:"1856x1392" 60 218250 1856 1952 2176 2528 1392 1393 1396 1439 0x40 0x6
>[  378.098728] [drm:drm_mode_debug_printmodeline], Modeline 88:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  378.101156] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  378.103585] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  378.105971] [drm:drm_mode_debug_printmodeline], Modeline 88:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  378.108382] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  378.110807] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 261000KHz
>[  378.113233] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  378.115652] [drm:intel_dp_mode_fixup], DP link bw required 626400 available 864000
>[  378.118068] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  378.120642] [drm:intel_dp_link_down], 
>[  378.180133] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  378.183018] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  378.186374] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  378.189273] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  378.192196] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  378.195116] [drm:drm_mode_debug_printmodeline], Modeline 88:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  378.198097] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  378.201065] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  378.204352] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 4
>[  378.259099] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  378.262107] [drm:ironlake_update_plane], Writing base 03FEE000 00000000 0 0 7168
>[  378.317073] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  378.320141] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:88:1792x1344]
>[  378.323218] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  378.326265] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  378.329357] [drm:ironlake_write_eld], ELD on pipe A
>[  378.332432] [drm:ironlake_write_eld], Audio directed to unknown port
>[  378.335504] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  378.338575] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 14, cursor: 6
>[  378.341655] [drm:ironlake_check_srwm], watermark 1: display plane 157, fbc lines 4, cursor 10
>[  378.344748] [drm:ironlake_check_srwm], watermark 2: display plane 338, fbc lines 6, cursor 14
>[  378.400039] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  378.455014] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  378.458386] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  378.461427] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  378.464629] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  378.467674] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  378.470743] [drm:ironlake_fdi_link_train], FDI train done
>[  378.473805] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  378.476898] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  378.481608] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  378.485386] [drm:intel_dp_start_link_train], clock recovery OK
>[  378.488552] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  378.492094] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  378.509000] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  378.512130] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  378.514729] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  378.517289] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  378.519804] [drm:intel_modeset_check_state], [CRTC:3]
>[  378.522294] [drm:intel_modeset_check_state], [CRTC:5]
>[  388.617713] [drm:drm_mode_addfb], [FB:88]
>[  388.620269] [drm:drm_mode_setcrtc], [CRTC:3]
>[  388.622711] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  388.625040] [drm:intel_crtc_set_config], [CRTC:3] [FB:88] #connectors=1 (x y) (0 0)
>[  388.627366] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  388.629703] [drm:drm_mode_debug_printmodeline], Modeline 88:"1792x1344" 75 261000 1792 1888 2104 2456 1344 1345 1348 1417 0x40 0x6
>[  388.632066] [drm:drm_mode_debug_printmodeline], Modeline 89:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  388.634416] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  388.636779] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  388.639092] [drm:drm_mode_debug_printmodeline], Modeline 89:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  388.641430] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  388.643790] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 204750KHz
>[  388.646146] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  388.648508] [drm:intel_dp_mode_fixup], DP link bw required 491400 available 518400
>[  388.650896] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  388.653444] [drm:intel_dp_link_down], 
>[  388.704691] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  388.707144] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  388.709984] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  388.712442] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  388.714906] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  388.717372] [drm:drm_mode_debug_printmodeline], Modeline 89:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  388.719891] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  388.722408] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  388.725241] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  388.779668] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  388.782225] [drm:ironlake_update_plane], Writing base 0491E000 00000000 0 0 7168
>[  388.836639] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  388.839215] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:89:1792x1344]
>[  388.841668] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  388.844127] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  388.846598] [drm:ironlake_write_eld], ELD on pipe A
>[  388.849058] [drm:ironlake_write_eld], Audio directed to unknown port
>[  388.851519] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  388.853987] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  388.856456] [drm:ironlake_check_srwm], watermark 1: display plane 114, fbc lines 4, cursor 6
>[  388.858931] [drm:ironlake_check_srwm], watermark 2: display plane 226, fbc lines 5, cursor 10
>[  388.913564] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  388.967587] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  388.970417] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  388.972870] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  388.975473] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  388.977921] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  388.980379] [drm:ironlake_fdi_link_train], FDI train done
>[  388.982827] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  388.985307] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  388.989450] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  388.993213] [drm:intel_dp_start_link_train], clock recovery OK
>[  388.996358] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  388.999870] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  389.020497] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  389.023582] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  389.026142] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  389.028662] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  389.031140] [drm:intel_modeset_check_state], [CRTC:3]
>[  389.033593] [drm:intel_modeset_check_state], [CRTC:5]
>[  399.128815] [drm:drm_mode_addfb], [FB:89]
>[  399.131338] [drm:drm_mode_setcrtc], [CRTC:3]
>[  399.133739] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  399.136093] [drm:intel_crtc_set_config], [CRTC:3] [FB:89] #connectors=1 (x y) (0 0)
>[  399.138470] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  399.140817] [drm:drm_mode_debug_printmodeline], Modeline 89:"1792x1344" 60 204750 1792 1920 2120 2448 1344 1345 1348 1394 0x40 0x6
>[  399.143210] [drm:drm_mode_debug_printmodeline], Modeline 91:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  399.145628] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  399.148008] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  399.150376] [drm:drm_mode_debug_printmodeline], Modeline 91:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  399.152758] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  399.155162] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 198022KHz
>[  399.157564] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  399.159948] [drm:intel_dp_mode_fixup], DP link bw required 475253 available 518400
>[  399.162335] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  399.164881] [drm:intel_dp_link_down], 
>[  399.248106] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  399.250981] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  399.254276] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  399.257137] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  399.260007] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  399.262887] [drm:drm_mode_debug_printmodeline], Modeline 91:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  399.265815] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  399.268745] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  399.271983] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  399.326072] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.329017] [drm:ironlake_update_plane], Writing base 0524E000 00000000 0 0 8192
>[  399.383101] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.385682] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:91:2048x1152]
>[  399.388195] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  399.390673] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  399.393178] [drm:ironlake_write_eld], ELD on pipe A
>[  399.395663] [drm:ironlake_write_eld], Audio directed to unknown port
>[  399.398146] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  399.400640] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  399.403143] [drm:ironlake_check_srwm], watermark 1: display plane 120, fbc lines 3, cursor 6
>[  399.405643] [drm:ironlake_check_srwm], watermark 2: display plane 258, fbc lines 5, cursor 10
>[  399.460064] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.514043] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.516936] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  399.519449] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  399.522093] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  399.524565] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  399.527058] [drm:ironlake_fdi_link_train], FDI train done
>[  399.529543] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  399.532060] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  399.536211] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  399.539965] [drm:intel_dp_start_link_train], clock recovery OK
>[  399.543085] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  399.546588] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  399.566977] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  399.570187] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  399.572757] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  399.575277] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  399.577757] [drm:intel_modeset_check_state], [CRTC:3]
>[  399.580211] [drm:intel_modeset_check_state], [CRTC:5]
>[  409.675245] [drm:drm_mode_addfb], [FB:91]
>[  409.677731] [drm:drm_mode_setcrtc], [CRTC:3]
>[  409.680125] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  409.682468] [drm:intel_crtc_set_config], [CRTC:3] [FB:91] #connectors=1 (x y) (0 0)
>[  409.684850] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  409.687215] [drm:drm_mode_debug_printmodeline], Modeline 91:"2048x1152" 60 198022 2048 2184 2408 2768 1152 1153 1156 1192 0x0 0x6
>[  409.689620] [drm:drm_mode_debug_printmodeline], Modeline 96:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  409.692054] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  409.694450] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  409.696837] [drm:drm_mode_debug_printmodeline], Modeline 96:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  409.699239] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  409.701670] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 281250KHz
>[  409.704043] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  409.706393] [drm:intel_dp_mode_fixup], DP link bw required 675000 available 864000
>[  409.708778] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  409.711304] [drm:intel_dp_link_down], 
>[  409.790656] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  409.793108] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  409.795971] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  409.798440] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  409.800912] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  409.803397] [drm:drm_mode_debug_printmodeline], Modeline 96:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  409.805925] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  409.808457] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  409.811300] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 4
>[  409.865603] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  409.868165] [drm:ironlake_update_plane], Writing base 05B4E000 00000000 0 0 7680
>[  409.922578] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  409.925157] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:96:1920x1200]
>[  409.927755] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  409.930363] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  409.932986] [drm:ironlake_write_eld], ELD on pipe A
>[  409.935593] [drm:ironlake_write_eld], Audio directed to unknown port
>[  409.938115] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  409.940622] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 15, cursor: 6
>[  409.943130] [drm:ironlake_check_srwm], watermark 1: display plane 169, fbc lines 4, cursor 10
>[  409.945650] [drm:ironlake_check_srwm], watermark 2: display plane 362, fbc lines 6, cursor 14
>[  410.000594] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  410.054552] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  410.057404] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  410.059873] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  410.062526] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  410.065015] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  410.067487] [drm:ironlake_fdi_link_train], FDI train done
>[  410.069958] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  410.072448] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  410.076571] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  410.080364] [drm:intel_dp_start_link_train], clock recovery OK
>[  410.083526] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  410.087074] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  410.103463] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  410.106691] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  410.109282] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  410.111833] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  410.114348] [drm:intel_modeset_check_state], [CRTC:3]
>[  410.116840] [drm:intel_modeset_check_state], [CRTC:5]
>[  420.211952] [drm:drm_mode_addfb], [FB:96]
>[  420.214448] [drm:drm_mode_setcrtc], [CRTC:3]
>[  420.216812] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  420.219159] [drm:intel_crtc_set_config], [CRTC:3] [FB:96] #connectors=1 (x y) (0 0)
>[  420.221511] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  420.223856] [drm:drm_mode_debug_printmodeline], Modeline 96:"1920x1200" 85 281250 1920 2064 2272 2624 1200 1203 1209 1262 0x40 0x6
>[  420.226229] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  420.228584] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  420.230944] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  420.233318] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  420.235663] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  420.238025] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 245250KHz
>[  420.240391] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  420.242741] [drm:intel_dp_mode_fixup], DP link bw required 588600 available 864000
>[  420.245086] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  420.247633] [drm:intel_dp_link_down], 
>[  420.297137] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  420.299565] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  420.302360] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  420.304703] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  420.307055] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  420.309416] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  420.311813] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  420.314204] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  420.316909] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  420.371152] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  420.373657] [drm:ironlake_update_plane], Writing base 06418000 00000000 0 0 7680
>[  420.428122] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  420.430652] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:97:1920x1200]
>[  420.433112] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  420.435581] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  420.438084] [drm:ironlake_write_eld], ELD on pipe A
>[  420.440572] [drm:ironlake_write_eld], Audio directed to unknown port
>[  420.443070] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  420.445569] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 13, cursor: 6
>[  420.448075] [drm:ironlake_check_srwm], watermark 1: display plane 122, fbc lines 4, cursor 6
>[  420.450577] [drm:ironlake_check_srwm], watermark 2: display plane 332, fbc lines 5, cursor 14
>[  420.505077] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  420.559050] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  420.561900] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  420.564372] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  420.567026] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  420.569511] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  420.571992] [drm:ironlake_fdi_link_train], FDI train done
>[  420.574460] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  420.576955] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  420.581080] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  420.584873] [drm:intel_dp_start_link_train], clock recovery OK
>[  420.588045] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  420.591579] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  420.609961] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  420.613188] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  420.615761] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  420.618296] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  420.620794] [drm:intel_modeset_check_state], [CRTC:3]
>[  420.623258] [drm:intel_modeset_check_state], [CRTC:5]
>[  430.718703] [drm:drm_mode_addfb], [FB:97]
>[  430.721219] [drm:drm_mode_setcrtc], [CRTC:3]
>[  430.723695] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  430.726086] [drm:intel_crtc_set_config], [CRTC:3] [FB:97] #connectors=1 (x y) (0 0)
>[  430.728493] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  430.730909] [drm:drm_mode_debug_printmodeline], Modeline 97:"1920x1200" 75 245250 1920 2056 2264 2608 1200 1203 1209 1255 0x40 0x6
>[  430.733341] [drm:drm_mode_debug_printmodeline], Modeline 98:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  430.735778] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  430.738203] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  430.740616] [drm:drm_mode_debug_printmodeline], Modeline 98:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  430.743025] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  430.745470] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 193250KHz
>[  430.747913] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  430.750335] [drm:intel_dp_mode_fixup], DP link bw required 463800 available 518400
>[  430.752755] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  430.755365] [drm:intel_dp_link_down], 
>[  430.798680] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  430.801048] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  430.803760] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  430.806079] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  430.808406] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  430.810732] [drm:drm_mode_debug_printmodeline], Modeline 98:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  430.813098] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  430.815465] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  430.818151] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  430.871636] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  430.874097] [drm:ironlake_update_plane], Writing base 06CE2000 00000000 0 0 7680
>[  430.927607] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  430.930102] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:98:1920x1200]
>[  430.932540] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  430.934975] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  430.937458] [drm:ironlake_write_eld], ELD on pipe A
>[  430.939916] [drm:ironlake_write_eld], Audio directed to unknown port
>[  430.942378] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  430.944900] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  430.947375] [drm:ironlake_check_srwm], watermark 1: display plane 117, fbc lines 3, cursor 6
>[  430.949854] [drm:ironlake_check_srwm], watermark 2: display plane 242, fbc lines 5, cursor 10
>[  431.004579] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  431.058552] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  431.061391] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  431.063830] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  431.066425] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  431.068862] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  431.071301] [drm:ironlake_fdi_link_train], FDI train done
>[  431.073737] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  431.076186] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  431.080316] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  431.084073] [drm:intel_dp_start_link_train], clock recovery OK
>[  431.087195] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  431.090692] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  431.111461] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  431.114555] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  431.117121] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  431.119655] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  431.122142] [drm:intel_modeset_check_state], [CRTC:3]
>[  431.124601] [drm:intel_modeset_check_state], [CRTC:5]
>[  441.218078] [drm:drm_mode_addfb], [FB:98]
>[  441.220577] [drm:drm_mode_setcrtc], [CRTC:3]
>[  441.222971] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  441.225342] [drm:intel_crtc_set_config], [CRTC:3] [FB:98] #connectors=1 (x y) (0 0)
>[  441.227711] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  441.230074] [drm:drm_mode_debug_printmodeline], Modeline 98:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  441.232483] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  441.234881] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  441.237278] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  441.239640] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  441.242036] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  441.244439] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 148500KHz
>[  441.246849] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  441.249249] [drm:intel_dp_mode_fixup], DP link bw required 356400 available 518400
>[  441.251630] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  441.254181] [drm:intel_dp_link_down], 
>[  441.320175] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  441.322609] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  441.325410] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  441.327776] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  441.330156] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  441.332531] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  441.334961] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  441.337390] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  441.340125] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  441.394123] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  441.396674] [drm:ironlake_update_plane], Writing base 075AC000 00000000 0 0 7680
>[  441.451102] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  441.453676] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:99:1920x1080]
>[  441.456198] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  441.458690] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  441.461216] [drm:ironlake_write_eld], ELD on pipe A
>[  441.463713] [drm:ironlake_write_eld], Audio directed to unknown port
>[  441.466220] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  441.468725] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  441.471236] [drm:ironlake_check_srwm], watermark 1: display plane 91, fbc lines 3, cursor 6
>[  441.473761] [drm:ironlake_check_srwm], watermark 2: display plane 202, fbc lines 4, cursor 10
>[  441.528040] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  441.582018] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  441.584928] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  441.587440] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  441.590094] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  441.592574] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  441.595084] [drm:ironlake_fdi_link_train], FDI train done
>[  441.597564] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  441.600093] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  441.604238] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  441.608005] [drm:intel_dp_start_link_train], clock recovery OK
>[  441.611149] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  441.614665] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  441.637950] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  441.641046] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  441.643620] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  441.646153] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  441.648645] [drm:intel_modeset_check_state], [CRTC:3]
>[  441.651100] [drm:intel_modeset_check_state], [CRTC:5]
>[  451.747005] [drm:drm_mode_addfb], [FB:99]
>[  451.749487] [drm:drm_mode_setcrtc], [CRTC:3]
>[  451.751893] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  451.754239] [drm:intel_crtc_set_config], [CRTC:3] [FB:99] #connectors=1 (x y) (0 0)
>[  451.756633] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  451.759002] [drm:drm_mode_debug_printmodeline], Modeline 99:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  451.761412] [drm:drm_mode_debug_printmodeline], Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  451.763816] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  451.766211] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  451.768589] [drm:drm_mode_debug_printmodeline], Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  451.770994] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  451.773389] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 148500KHz
>[  451.775798] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  451.778189] [drm:intel_dp_mode_fixup], DP link bw required 356400 available 518400
>[  451.780574] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  451.783137] [drm:intel_dp_link_down], 
>[  451.848567] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  451.851432] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  451.854732] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  451.857607] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  451.860502] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  451.863410] [drm:drm_mode_debug_printmodeline], Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  451.866371] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  451.869317] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  451.872583] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  451.926630] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  451.929143] [drm:ironlake_update_plane], Writing base 07D95000 00000000 0 0 7680
>[  451.983590] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  451.986153] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:100:1920x1080]
>[  451.988672] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  451.991167] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  451.993670] [drm:ironlake_write_eld], ELD on pipe A
>[  451.996172] [drm:ironlake_write_eld], Audio directed to unknown port
>[  451.998676] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  452.001192] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  452.003699] [drm:ironlake_check_srwm], watermark 1: display plane 91, fbc lines 3, cursor 6
>[  452.006227] [drm:ironlake_check_srwm], watermark 2: display plane 202, fbc lines 4, cursor 10
>[  452.060527] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  452.114496] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  452.117418] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  452.119946] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  452.122618] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  452.125111] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  452.127625] [drm:ironlake_fdi_link_train], FDI train done
>[  452.130132] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  452.132669] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  452.136848] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  452.140640] [drm:intel_dp_start_link_train], clock recovery OK
>[  452.143795] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  452.147307] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  452.168514] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  452.171082] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  452.173550] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  452.176025] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  452.178431] [drm:intel_modeset_check_state], [CRTC:3]
>[  452.180800] [drm:intel_modeset_check_state], [CRTC:5]
>[  462.274240] [drm:drm_mode_addfb], [FB:100]
>[  462.276703] [drm:drm_mode_setcrtc], [CRTC:3]
>[  462.279104] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  462.281436] [drm:intel_crtc_set_config], [CRTC:3] [FB:100] #connectors=1 (x y) (0 0)
>[  462.283803] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  462.286164] [drm:drm_mode_debug_printmodeline], Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.288541] [drm:drm_mode_debug_printmodeline], Modeline 101:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  462.290918] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  462.293315] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  462.295660] [drm:drm_mode_debug_printmodeline], Modeline 101:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  462.298031] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  462.300418] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  462.302819] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  462.305206] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  462.307595] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  462.310145] [drm:intel_dp_link_down], 
>[  462.378056] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  462.380885] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  462.384132] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  462.386987] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  462.389837] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  462.392692] [drm:drm_mode_debug_printmodeline], Modeline 101:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  462.395595] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  462.398500] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  462.401713] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  462.456022] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  462.458956] [drm:ironlake_update_plane], Writing base 0857E000 00000000 0 0 7680
>[  462.512997] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  462.515952] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:101:1920x1080]
>[  462.519081] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  462.522090] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  462.525121] [drm:ironlake_write_eld], ELD on pipe A
>[  462.528134] [drm:ironlake_write_eld], Audio directed to unknown port
>[  462.531156] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  462.534179] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  462.537199] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
>[  462.540234] [drm:ironlake_check_srwm], watermark 2: display plane 102, fbc lines 3, cursor 6
>[  462.594963] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  462.649939] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  462.653253] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  462.656264] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  462.659444] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  462.662457] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  462.665474] [drm:ironlake_fdi_link_train], FDI train done
>[  462.668484] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  462.671529] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  462.676238] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  462.680020] [drm:intel_dp_start_link_train], clock recovery OK
>[  462.683191] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  462.686722] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  462.731912] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  462.735017] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  462.737603] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  462.740148] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  462.742653] [drm:intel_modeset_check_state], [CRTC:3]
>[  462.745135] [drm:intel_modeset_check_state], [CRTC:5]
>[  472.838274] [drm:drm_mode_addfb], [FB:101]
>[  472.840799] [drm:drm_mode_setcrtc], [CRTC:3]
>[  472.843219] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  472.845608] [drm:intel_crtc_set_config], [CRTC:3] [FB:101] #connectors=1 (x y) (0 0)
>[  472.848013] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  472.850426] [drm:drm_mode_debug_printmodeline], Modeline 101:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  472.852840] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  472.855265] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  472.857682] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  472.860076] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  472.862477] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  472.864916] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  472.867339] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  472.869821] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  472.872234] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  472.874802] [drm:intel_dp_link_down], 
>[  472.948571] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  473.052561] ------------[ cut here ]------------
>[  473.055044] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  473.057459] Hardware name: OptiPlex 980                 
>[  473.059877] pipe_off wait timed out
>[  473.062254] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  473.070301] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  473.072916] Call Trace:
>[  473.075557]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  473.078184]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  473.080830]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  473.083497]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  473.086165]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  473.088848]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  473.091496]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  473.094162]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  473.096821]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  473.099478]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  473.102088]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  473.104703]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  473.107313]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  473.109912]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  473.112519]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  473.115131]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  473.117750]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  473.120376]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  473.123000]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  473.125624]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  473.128254]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  473.130879]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  473.133489]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  473.136070] ---[ end trace ca8f0eea49311cd8 ]---
>[  473.144520] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  473.147183] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  473.150169] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  473.152733] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  473.155269] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  473.157795] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  473.160370] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  473.162952] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  473.165829] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  473.220490] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  473.223163] [drm:ironlake_update_plane], Writing base 08D67000 00000000 0 0 7680
>[  473.277461] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  473.280136] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:102:1920x1080i]
>[  473.282723] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  473.285293] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  473.287842] [drm:ironlake_write_eld], ELD on pipe A
>[  473.290353] [drm:ironlake_write_eld], Audio directed to unknown port
>[  473.292867] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  473.295376] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  473.297882] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
>[  473.300386] [drm:ironlake_check_srwm], watermark 2: display plane 102, fbc lines 3, cursor 6
>[  473.355431] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  473.409405] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  473.412270] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  473.414736] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  473.417397] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  473.419858] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  473.422302] [drm:ironlake_fdi_link_train], FDI train done
>[  473.424716] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  473.427143] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  473.431206] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  473.434939] [drm:intel_dp_start_link_train], clock recovery OK
>[  473.438084] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  473.441581] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  473.466388] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  473.469003] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  473.471625] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  473.474251] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  473.476855] [drm:intel_modeset_check_state], [CRTC:3]
>[  473.479452] [drm:intel_modeset_check_state], [CRTC:5]
>[  483.572756] [drm:drm_mode_addfb], [FB:102]
>[  483.575380] [drm:drm_mode_setcrtc], [CRTC:3]
>[  483.577914] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  483.580395] [drm:intel_crtc_set_config], [CRTC:3] [FB:102] #connectors=1 (x y) (0 0)
>[  483.582890] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  483.585384] [drm:drm_mode_debug_printmodeline], Modeline 102:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  483.587947] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  483.590524] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  483.593109] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  483.595709] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  483.598357] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  483.601009] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 74250KHz
>[  483.603698] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  483.606379] [drm:intel_dp_mode_fixup], DP link bw required 178200 available 259200
>[  483.609060] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  483.611899] [drm:intel_dp_link_down], 
>[  483.673979] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  483.777978] ------------[ cut here ]------------
>[  483.780668] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  483.783266] Hardware name: OptiPlex 980                 
>[  483.785812] pipe_off wait timed out
>[  483.788335] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  483.796813] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  483.799593] Call Trace:
>[  483.802379]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  483.805146]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  483.807913]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  483.810674]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  483.813435]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  483.816115]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  483.818713]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  483.821253]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  483.823767]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  483.826272]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  483.828771]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  483.831287]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  483.833801]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  483.836302]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  483.838804]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  483.841302]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  483.843804]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  483.846301]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  483.848798]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  483.851290]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  483.853771]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  483.856248]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  483.858727]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  483.861205] ---[ end trace ca8f0eea49311cd9 ]---
>[  483.869899] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  483.872504] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  483.875464] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  483.877997] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  483.880549] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  483.883111] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  483.885716] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  483.888346] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  483.891270] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  483.945895] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  483.948657] [drm:ironlake_update_plane], Writing base 09550000 00000000 0 0 7680
>[  484.002881] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  484.005608] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:103:1920x1080i]
>[  484.008255] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  484.010892] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  484.013494] [drm:ironlake_write_eld], ELD on pipe A
>[  484.016061] [drm:ironlake_write_eld], Audio directed to unknown port
>[  484.018644] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  484.021232] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  484.023822] [drm:ironlake_check_srwm], watermark 1: display plane 47, fbc lines 3, cursor 6
>[  484.026339] [drm:ironlake_check_srwm], watermark 2: display plane 102, fbc lines 3, cursor 6
>[  484.080810] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  484.134825] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  484.137689] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  484.140171] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  484.142794] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  484.145257] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  484.147719] [drm:ironlake_fdi_link_train], FDI train done
>[  484.150157] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  484.152610] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  484.156689] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  484.160430] [drm:intel_dp_start_link_train], clock recovery OK
>[  484.163583] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  484.167092] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  484.187718] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  484.190922] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  484.193562] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  484.196200] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  484.198819] [drm:intel_modeset_check_state], [CRTC:3]
>[  484.201426] [drm:intel_modeset_check_state], [CRTC:5]
>[  494.293858] [drm:drm_mode_addfb], [FB:103]
>[  494.296483] [drm:drm_mode_setcrtc], [CRTC:3]
>[  494.299009] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  494.301450] [drm:intel_crtc_set_config], [CRTC:3] [FB:103] #connectors=1 (x y) (0 0)
>[  494.303964] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  494.306499] [drm:drm_mode_debug_printmodeline], Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  494.309069] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  494.311678] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  494.314297] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  494.316920] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  494.319580] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  494.322260] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 229500KHz
>[  494.324971] [drm:intel_dp_mode_fixup], DP link bw 0a lane count 4 clock 270000 bpp 24
>[  494.327676] [drm:intel_dp_mode_fixup], DP link bw required 550800 available 864000
>[  494.330360] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  494.333180] [drm:intel_dp_link_down], 
>[  494.403333] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  494.508288] ------------[ cut here ]------------
>[  494.511660] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  494.514894] Hardware name: OptiPlex 980                 
>[  494.518064] pipe_off wait timed out
>[  494.521198] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  494.531769] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  494.535236] Call Trace:
>[  494.538704]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  494.542170]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  494.545625]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  494.549068]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  494.552516]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  494.555881]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  494.559124]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  494.562288]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  494.565426]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  494.568544]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  494.571657]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  494.574770]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  494.577894]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  494.581011]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  494.584126]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  494.587231]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  494.590336]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  494.593437]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  494.596524]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  494.599614]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  494.602682]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  494.605787]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  494.608871]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  494.611947] ---[ end trace ca8f0eea49311cda ]---
>[  494.618242] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  494.621343] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  494.624872] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  494.628003] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  494.631161] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  494.634318] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  494.637561] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  494.640797] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  494.644340] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  494.699205] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  494.702436] [drm:ironlake_update_plane], Writing base 09D39000 00000000 0 0 6400
>[  494.757182] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  494.760393] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:104:1600x1200]
>[  494.763651] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  494.766863] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  494.770055] [drm:ironlake_write_eld], ELD on pipe A
>[  494.773209] [drm:ironlake_write_eld], Audio directed to unknown port
>[  494.776373] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  494.779531] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 13, cursor: 6
>[  494.782687] [drm:ironlake_check_srwm], watermark 1: display plane 139, fbc lines 4, cursor 10
>[  494.785849] [drm:ironlake_check_srwm], watermark 2: display plane 302, fbc lines 6, cursor 14
>[  494.841145] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  494.896122] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  494.899526] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  494.902055] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  494.904728] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  494.907224] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  494.909725] [drm:ironlake_fdi_link_train], FDI train done
>[  494.912193] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  494.914685] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  494.918811] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  494.922572] [drm:intel_dp_start_link_train], clock recovery OK
>[  494.925724] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  494.929240] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  494.946210] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  494.948847] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  494.951420] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  494.953993] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  494.956547] [drm:intel_modeset_check_state], [CRTC:3]
>[  494.959084] [drm:intel_modeset_check_state], [CRTC:5]
>[  505.052064] [drm:drm_mode_addfb], [FB:104]
>[  505.054702] [drm:drm_mode_setcrtc], [CRTC:3]
>[  505.057255] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  505.059755] [drm:intel_crtc_set_config], [CRTC:3] [FB:104] #connectors=1 (x y) (0 0)
>[  505.062269] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  505.064793] [drm:drm_mode_debug_printmodeline], Modeline 104:"1600x1200" 85 229500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  505.067323] [drm:drm_mode_debug_printmodeline], Modeline 105:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  505.069839] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  505.072365] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  505.074937] [drm:drm_mode_debug_printmodeline], Modeline 105:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  505.077511] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  505.080130] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 202500KHz
>[  505.082775] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  505.085400] [drm:intel_dp_mode_fixup], DP link bw required 486000 available 518400
>[  505.088092] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  505.090893] [drm:intel_dp_link_down], 
>[  505.136735] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  505.140155] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  505.143684] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  505.146809] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  505.149904] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  505.152990] [drm:drm_mode_debug_printmodeline], Modeline 105:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  505.156131] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  505.159271] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  505.162713] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  505.217700] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  505.220865] [drm:ironlake_update_plane], Writing base 0A48C000 00000000 0 0 6400
>[  505.275674] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  505.278813] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:105:1600x1200]
>[  505.281958] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  505.285102] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  505.288171] [drm:ironlake_write_eld], ELD on pipe A
>[  505.291140] [drm:ironlake_write_eld], Audio directed to unknown port
>[  505.294009] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  505.296876] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  505.299720] [drm:ironlake_check_srwm], watermark 1: display plane 102, fbc lines 4, cursor 6
>[  505.302571] [drm:ironlake_check_srwm], watermark 2: display plane 275, fbc lines 5, cursor 14
>[  505.357735] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  505.411692] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  505.414392] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  505.416702] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  505.419154] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  505.421452] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  505.423728] [drm:ironlake_fdi_link_train], FDI train done
>[  505.425998] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  505.428291] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  505.432245] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  505.435793] [drm:intel_dp_start_link_train], clock recovery OK
>[  505.438727] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  505.442106] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  505.458660] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  505.461118] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  505.463590] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  505.466044] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  505.468499] [drm:intel_modeset_check_state], [CRTC:3]
>[  505.470940] [drm:intel_modeset_check_state], [CRTC:5]
>[  515.563473] [drm:drm_mode_addfb], [FB:105]
>[  515.565962] [drm:drm_mode_setcrtc], [CRTC:3]
>[  515.568355] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  515.570688] [drm:intel_crtc_set_config], [CRTC:3] [FB:105] #connectors=1 (x y) (0 0)
>[  515.573041] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  515.575384] [drm:drm_mode_debug_printmodeline], Modeline 105:"1600x1200" 75 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  515.577759] [drm:drm_mode_debug_printmodeline], Modeline 106:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  515.580118] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  515.582473] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  515.584805] [drm:drm_mode_debug_printmodeline], Modeline 106:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  515.587156] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  515.589519] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 189000KHz
>[  515.591884] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  515.594237] [drm:intel_dp_mode_fixup], DP link bw required 453600 available 518400
>[  515.596621] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  515.599138] [drm:intel_dp_link_down], 
>[  515.666275] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  515.668720] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  515.671476] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  515.673792] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  515.676139] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  515.678486] [drm:drm_mode_debug_printmodeline], Modeline 106:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  515.680873] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  515.683267] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  515.685961] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  515.740241] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  515.742731] [drm:ironlake_update_plane], Writing base 0ABDF000 00000000 0 0 6400
>[  515.797245] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  515.799770] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:106:1600x1200]
>[  515.802244] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  515.804687] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  515.807153] [drm:ironlake_write_eld], ELD on pipe A
>[  515.809570] [drm:ironlake_write_eld], Audio directed to unknown port
>[  515.811966] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  515.814380] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  515.816802] [drm:ironlake_check_srwm], watermark 1: display plane 102, fbc lines 4, cursor 6
>[  515.819218] [drm:ironlake_check_srwm], watermark 2: display plane 202, fbc lines 5, cursor 10
>[  515.873225] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  515.927207] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  515.929991] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  515.932389] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  515.934945] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  515.937343] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  515.939749] [drm:ironlake_fdi_link_train], FDI train done
>[  515.942188] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  515.944636] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  515.948765] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  515.952482] [drm:intel_dp_start_link_train], clock recovery OK
>[  515.955588] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  515.959060] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  515.978097] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  515.981289] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  515.983779] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  515.986247] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  515.988642] [drm:intel_modeset_check_state], [CRTC:3]
>[  515.991011] [drm:intel_modeset_check_state], [CRTC:5]
>[  526.083617] [drm:drm_mode_addfb], [FB:106]
>[  526.086068] [drm:drm_mode_setcrtc], [CRTC:3]
>[  526.088436] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  526.090758] [drm:intel_crtc_set_config], [CRTC:3] [FB:106] #connectors=1 (x y) (0 0)
>[  526.093073] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  526.095410] [drm:drm_mode_debug_printmodeline], Modeline 106:"1600x1200" 70 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  526.097768] [drm:drm_mode_debug_printmodeline], Modeline 107:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  526.100111] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  526.102440] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  526.104759] [drm:drm_mode_debug_printmodeline], Modeline 107:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  526.107098] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  526.109430] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 175500KHz
>[  526.111793] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  526.114139] [drm:intel_dp_mode_fixup], DP link bw required 421200 available 518400
>[  526.116467] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  526.118950] [drm:intel_dp_link_down], 
>[  526.180718] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  526.183543] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  526.186855] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  526.189685] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  526.192542] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  526.195389] [drm:drm_mode_debug_printmodeline], Modeline 107:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  526.198294] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  526.201194] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  526.204408] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  526.258683] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  526.261602] [drm:ironlake_update_plane], Writing base 0B332000 00000000 0 0 6400
>[  526.315660] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  526.318602] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:107:1600x1200]
>[  526.321615] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  526.324614] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  526.327637] [drm:ironlake_write_eld], ELD on pipe A
>[  526.330655] [drm:ironlake_write_eld], Audio directed to unknown port
>[  526.333614] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  526.336573] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  526.339536] [drm:ironlake_check_srwm], watermark 1: display plane 102, fbc lines 4, cursor 6
>[  526.342508] [drm:ironlake_check_srwm], watermark 2: display plane 202, fbc lines 5, cursor 10
>[  526.397624] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  526.451601] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  526.454853] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  526.457801] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  526.460913] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  526.463856] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  526.466814] [drm:ironlake_fdi_link_train], FDI train done
>[  526.469760] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  526.472741] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  526.477375] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  526.481113] [drm:intel_dp_start_link_train], clock recovery OK
>[  526.484336] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  526.487827] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  526.506586] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  526.509785] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  526.512351] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  526.514881] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  526.517368] [drm:intel_modeset_check_state], [CRTC:3]
>[  526.519828] [drm:intel_modeset_check_state], [CRTC:5]
>[  536.612632] [drm:drm_mode_addfb], [FB:107]
>[  536.615122] [drm:drm_mode_setcrtc], [CRTC:3]
>[  536.617512] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  536.619868] [drm:intel_crtc_set_config], [CRTC:3] [FB:107] #connectors=1 (x y) (0 0)
>[  536.622257] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  536.624659] [drm:drm_mode_debug_printmodeline], Modeline 107:"1600x1200" 65 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  536.627031] [drm:drm_mode_debug_printmodeline], Modeline 108:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  536.629398] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  536.631754] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  536.634087] [drm:drm_mode_debug_printmodeline], Modeline 108:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  536.636429] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  536.638792] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 162000KHz
>[  536.641148] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  536.643506] [drm:intel_dp_mode_fixup], DP link bw required 388800 available 518400
>[  536.645853] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  536.648364] [drm:intel_dp_link_down], 
>[  536.708283] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  536.710703] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  536.713521] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  536.715948] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  536.718381] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  536.720817] [drm:drm_mode_debug_printmodeline], Modeline 108:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  536.723294] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  536.725773] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  536.728563] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  536.782221] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  536.784727] [drm:ironlake_update_plane], Writing base 0BA85000 00000000 0 0 6400
>[  536.838230] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  536.840774] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:108:1600x1200]
>[  536.843273] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  536.845745] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  536.848219] [drm:ironlake_write_eld], ELD on pipe A
>[  536.850692] [drm:ironlake_write_eld], Audio directed to unknown port
>[  536.853161] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  536.855632] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  536.858113] [drm:ironlake_check_srwm], watermark 1: display plane 99, fbc lines 3, cursor 6
>[  536.860590] [drm:ironlake_check_srwm], watermark 2: display plane 202, fbc lines 5, cursor 10
>[  536.915168] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  536.969174] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  536.972034] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  536.974512] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  536.977118] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  536.979566] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  536.982028] [drm:ironlake_fdi_link_train], FDI train done
>[  536.984484] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  536.986951] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  536.991068] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  536.994804] [drm:intel_dp_start_link_train], clock recovery OK
>[  536.997908] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  537.001397] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  537.022080] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  537.025156] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  537.027712] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  537.030230] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  537.032716] [drm:intel_modeset_check_state], [CRTC:3]
>[  537.035169] [drm:intel_modeset_check_state], [CRTC:5]
>[  547.126954] [drm:drm_mode_addfb], [FB:108]
>[  547.129447] [drm:drm_mode_setcrtc], [CRTC:3]
>[  547.131834] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  547.134187] [drm:intel_crtc_set_config], [CRTC:3] [FB:108] #connectors=1 (x y) (0 0)
>[  547.136570] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  547.138945] [drm:drm_mode_debug_printmodeline], Modeline 108:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  547.141326] [drm:drm_mode_debug_printmodeline], Modeline 109:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  547.143748] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  547.146149] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  547.148530] [drm:drm_mode_debug_printmodeline], Modeline 109:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  547.150928] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  547.153342] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 214750KHz
>[  547.155768] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  547.158133] [drm:intel_dp_mode_fixup], DP link bw required 515400 available 518400
>[  547.160456] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  547.162999] [drm:intel_dp_link_down], 
>[  547.218750] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  547.221166] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  547.224006] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  547.226445] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  547.228898] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  547.231349] [drm:drm_mode_debug_printmodeline], Modeline 109:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  547.233842] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  547.236338] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  547.239147] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  547.292718] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  547.295243] [drm:ironlake_update_plane], Writing base 0C1D8000 00000000 0 0 6720
>[  547.349693] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  547.352236] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:109:1680x1050]
>[  547.354653] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  547.357078] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  547.359520] [drm:ironlake_write_eld], ELD on pipe A
>[  547.361951] [drm:ironlake_write_eld], Audio directed to unknown port
>[  547.364383] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  547.366814] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 12, cursor: 6
>[  547.369249] [drm:ironlake_check_srwm], watermark 1: display plane 107, fbc lines 4, cursor 6
>[  547.371697] [drm:ironlake_check_srwm], watermark 2: display plane 291, fbc lines 5, cursor 14
>[  547.426665] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  547.480639] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  547.483459] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  547.485880] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  547.488459] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  547.490881] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  547.493304] [drm:ironlake_fdi_link_train], FDI train done
>[  547.495716] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  547.498166] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  547.502278] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  547.506014] [drm:intel_dp_start_link_train], clock recovery OK
>[  547.509146] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  547.512636] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  547.527579] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  547.530657] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  547.533218] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  547.535735] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  547.538229] [drm:intel_modeset_check_state], [CRTC:3]
>[  547.540684] [drm:intel_modeset_check_state], [CRTC:5]
>[  557.632623] [drm:drm_mode_addfb], [FB:109]
>[  557.635099] [drm:drm_mode_setcrtc], [CRTC:3]
>[  557.637480] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  557.639828] [drm:intel_crtc_set_config], [CRTC:3] [FB:109] #connectors=1 (x y) (0 0)
>[  557.642211] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  557.644591] [drm:drm_mode_debug_printmodeline], Modeline 109:"1680x1050" 85 214750 1680 1808 1984 2288 1050 1053 1059 1105 0x40 0x6
>[  557.646977] [drm:drm_mode_debug_printmodeline], Modeline 110:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  557.649367] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  557.651764] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  557.654132] [drm:drm_mode_debug_printmodeline], Modeline 110:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  557.656505] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  557.658885] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 187000KHz
>[  557.661285] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  557.663671] [drm:intel_dp_mode_fixup], DP link bw required 448800 available 518400
>[  557.666045] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  557.668580] [drm:intel_dp_link_down], 
>[  557.730199] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  557.733038] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  557.736339] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  557.739203] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  557.742080] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  557.744960] [drm:drm_mode_debug_printmodeline], Modeline 110:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  557.747893] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  557.750816] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  557.754053] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  557.808166] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  557.811121] [drm:ironlake_update_plane], Writing base 0C893000 00000000 0 0 6720
>[  557.865140] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  557.868118] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:110:1680x1050]
>[  557.871123] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  557.874153] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  557.877206] [drm:ironlake_write_eld], ELD on pipe A
>[  557.880233] [drm:ironlake_write_eld], Audio directed to unknown port
>[  557.883262] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  557.886297] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 11, cursor: 6
>[  557.889341] [drm:ironlake_check_srwm], watermark 1: display plane 107, fbc lines 4, cursor 6
>[  557.892390] [drm:ironlake_check_srwm], watermark 2: display plane 212, fbc lines 5, cursor 10
>[  557.947156] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  558.001134] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  558.004034] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  558.006531] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  558.009166] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  558.011646] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  558.014130] [drm:ironlake_fdi_link_train], FDI train done
>[  558.016611] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  558.019114] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  558.023263] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  558.027008] [drm:intel_dp_start_link_train], clock recovery OK
>[  558.030132] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  558.033631] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  558.052069] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  558.055136] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  558.057688] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  558.060201] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  558.062675] [drm:intel_modeset_check_state], [CRTC:3]
>[  558.065123] [drm:intel_modeset_check_state], [CRTC:5]
>[  568.156948] [drm:drm_mode_addfb], [FB:110]
>[  568.159433] [drm:drm_mode_setcrtc], [CRTC:3]
>[  568.161818] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  568.164150] [drm:intel_crtc_set_config], [CRTC:3] [FB:110] #connectors=1 (x y) (0 0)
>[  568.166531] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  568.168893] [drm:drm_mode_debug_printmodeline], Modeline 110:"1680x1050" 75 187000 1680 1800 1976 2272 1050 1053 1059 1099 0x40 0x6
>[  568.171269] [drm:drm_mode_debug_printmodeline], Modeline 111:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  568.173645] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  568.176016] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  568.178359] [drm:drm_mode_debug_printmodeline], Modeline 111:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  568.180732] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  568.183087] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 146250KHz
>[  568.185474] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  568.187862] [drm:intel_dp_mode_fixup], DP link bw required 351000 available 518400
>[  568.190230] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  568.192744] [drm:intel_dp_link_down], 
>[  568.254689] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  568.257521] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  568.260828] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  568.263672] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  568.266536] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  568.269405] [drm:drm_mode_debug_printmodeline], Modeline 111:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  568.272320] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  568.275240] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  568.278470] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  568.332656] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  568.335590] [drm:ironlake_update_plane], Writing base 0CF4E000 00000000 0 0 6720
>[  568.389631] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  568.392593] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:111:1680x1050]
>[  568.395612] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  568.398638] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  568.401671] [drm:ironlake_write_eld], ELD on pipe A
>[  568.404690] [drm:ironlake_write_eld], Audio directed to unknown port
>[  568.407747] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  568.407798] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  568.407801] [drm:ironlake_check_srwm], watermark 1: display plane 89, fbc lines 3, cursor 6
>[  568.407804] [drm:ironlake_check_srwm], watermark 2: display plane 199, fbc lines 4, cursor 10
>[  568.459601] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  568.513577] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  568.516844] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  568.519817] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  568.522942] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  568.525916] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  568.528900] [drm:ironlake_fdi_link_train], FDI train done
>[  568.531871] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  568.534875] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  568.539534] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  568.543299] [drm:intel_dp_start_link_train], clock recovery OK
>[  568.546426] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  568.549930] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  568.570562] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  568.573786] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  568.576350] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  568.578874] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  568.581369] [drm:intel_modeset_check_state], [CRTC:3]
>[  568.583836] [drm:intel_modeset_check_state], [CRTC:5]
>[  578.674166] [drm:drm_mode_addfb], [FB:111]
>[  578.676641] [drm:drm_mode_setcrtc], [CRTC:3]
>[  578.679033] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  578.681389] [drm:intel_crtc_set_config], [CRTC:3] [FB:111] #connectors=1 (x y) (0 0)
>[  578.683732] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  578.686094] [drm:drm_mode_debug_printmodeline], Modeline 111:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  578.688470] [drm:drm_mode_debug_printmodeline], Modeline 112:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  578.690846] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  578.693220] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  578.695548] [drm:drm_mode_debug_printmodeline], Modeline 112:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  578.697914] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  578.700291] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 131481KHz
>[  578.702675] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  578.705038] [drm:intel_dp_mode_fixup], DP link bw required 315555 available 518400
>[  578.707393] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  578.709922] [drm:intel_dp_link_down], 
>[  578.771183] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  578.774035] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  578.777335] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  578.780205] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  578.783085] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  578.785961] [drm:drm_mode_debug_printmodeline], Modeline 112:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  578.788891] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  578.791821] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  578.795045] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  578.849150] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  578.852086] [drm:ironlake_update_plane], Writing base 0D609000 00000000 0 0 6720
>[  578.906220] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  578.908728] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:112:1680x945]
>[  578.911211] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  578.913667] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  578.916146] [drm:ironlake_write_eld], ELD on pipe A
>[  578.918603] [drm:ironlake_write_eld], Audio directed to unknown port
>[  578.921060] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  578.923529] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  578.925984] [drm:ironlake_check_srwm], watermark 1: display plane 80, fbc lines 3, cursor 6
>[  578.928455] [drm:ironlake_check_srwm], watermark 2: display plane 179, fbc lines 4, cursor 10
>[  578.983172] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  579.037122] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  579.039994] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  579.042474] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  579.045078] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  579.047523] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  579.049982] [drm:ironlake_fdi_link_train], FDI train done
>[  579.052435] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  579.054907] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  579.059023] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  579.062752] [drm:intel_dp_start_link_train], clock recovery OK
>[  579.065850] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  579.069323] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  579.090055] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  579.093130] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  579.095661] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  579.098158] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  579.100620] [drm:intel_modeset_check_state], [CRTC:3]
>[  579.103058] [drm:intel_modeset_check_state], [CRTC:5]
>[  589.192323] [drm:drm_mode_addfb], [FB:112]
>[  589.194808] [drm:drm_mode_setcrtc], [CRTC:3]
>[  589.197179] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  589.199518] [drm:intel_crtc_set_config], [CRTC:3] [FB:112] #connectors=1 (x y) (0 0)
>[  589.201871] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  589.204231] [drm:drm_mode_debug_printmodeline], Modeline 112:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  589.206595] [drm:drm_mode_debug_printmodeline], Modeline 113:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  589.208960] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  589.211326] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  589.213670] [drm:drm_mode_debug_printmodeline], Modeline 113:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  589.216044] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  589.218471] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 179500KHz
>[  589.220833] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  589.223184] [drm:intel_dp_mode_fixup], DP link bw required 430800 available 518400
>[  589.225533] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  589.228042] [drm:intel_dp_link_down], 
>[  589.273730] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  589.276144] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  589.278957] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  589.281378] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  589.283795] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  589.286225] [drm:drm_mode_debug_printmodeline], Modeline 113:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  589.288695] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  589.291166] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  589.293940] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  589.347725] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  589.350225] [drm:ironlake_update_plane], Writing base 0DC18000 00000000 0 0 5632
>[  589.404718] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  589.407225] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:113:1400x1050]
>[  589.409702] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  589.412150] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  589.414612] [drm:ironlake_write_eld], ELD on pipe A
>[  589.417066] [drm:ironlake_write_eld], Audio directed to unknown port
>[  589.419515] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  589.421968] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  589.424420] [drm:ironlake_check_srwm], watermark 1: display plane 90, fbc lines 4, cursor 6
>[  589.426878] [drm:ironlake_check_srwm], watermark 2: display plane 244, fbc lines 5, cursor 14
>[  589.481647] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  589.535623] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  589.538468] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  589.540939] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  589.543542] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  589.545992] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  589.548434] [drm:ironlake_fdi_link_train], FDI train done
>[  589.550881] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  589.553344] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  589.557445] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  589.561176] [drm:intel_dp_start_link_train], clock recovery OK
>[  589.564317] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  589.568441] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  589.583604] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  589.586127] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  589.588504] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  589.590848] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  589.593169] [drm:intel_modeset_check_state], [CRTC:3]
>[  589.595458] [drm:intel_modeset_check_state], [CRTC:5]
>[  599.684527] [drm:drm_mode_addfb], [FB:113]
>[  599.686922] [drm:drm_mode_setcrtc], [CRTC:3]
>[  599.689228] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  599.691489] [drm:intel_crtc_set_config], [CRTC:3] [FB:113] #connectors=1 (x y) (0 0)
>[  599.693777] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  599.696045] [drm:drm_mode_debug_printmodeline], Modeline 113:"1400x1050" 85 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6
>[  599.698357] [drm:drm_mode_debug_printmodeline], Modeline 114:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  599.700646] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  599.702950] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  599.705210] [drm:drm_mode_debug_printmodeline], Modeline 114:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  599.707495] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  599.709808] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 156000KHz
>[  599.712123] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  599.714409] [drm:intel_dp_mode_fixup], DP link bw required 374400 available 518400
>[  599.716714] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  599.719223] [drm:intel_dp_link_down], 
>[  599.767187] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  599.769985] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  599.773261] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  599.776086] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  599.778909] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  599.781471] [drm:drm_mode_debug_printmodeline], Modeline 114:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  599.783816] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  599.786160] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  599.788813] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  599.842231] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  599.844686] [drm:ironlake_update_plane], Writing base 0E1BC000 00000000 0 0 5632
>[  599.898210] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  599.900661] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:114:1400x1050]
>[  599.903059] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  599.905470] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  599.907891] [drm:ironlake_write_eld], ELD on pipe A
>[  599.910302] [drm:ironlake_write_eld], Audio directed to unknown port
>[  599.912715] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  599.915141] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  599.917556] [drm:ironlake_check_srwm], watermark 1: display plane 90, fbc lines 4, cursor 6
>[  599.919976] [drm:ironlake_check_srwm], watermark 2: display plane 177, fbc lines 5, cursor 10
>[  599.974178] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  600.028124] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  600.030931] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  600.033333] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  600.035894] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  600.038306] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  600.040713] [drm:ironlake_fdi_link_train], FDI train done
>[  600.043113] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  600.045551] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  600.049652] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  600.053401] [drm:intel_dp_start_link_train], clock recovery OK
>[  600.056529] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  600.060021] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  600.077062] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  600.080143] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  600.082689] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  600.085195] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  600.087667] [drm:intel_modeset_check_state], [CRTC:3]
>[  600.090110] [drm:intel_modeset_check_state], [CRTC:5]
>[  610.179483] [drm:drm_mode_addfb], [FB:114]
>[  610.181953] [drm:drm_mode_setcrtc], [CRTC:3]
>[  610.184325] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  610.186659] [drm:intel_crtc_set_config], [CRTC:3] [FB:114] #connectors=1 (x y) (0 0)
>[  610.189003] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  610.191372] [drm:drm_mode_debug_printmodeline], Modeline 114:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  610.193730] [drm:drm_mode_debug_printmodeline], Modeline 115:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  610.196092] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  610.198455] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  610.200785] [drm:drm_mode_debug_printmodeline], Modeline 115:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  610.203154] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  610.205521] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 121750KHz
>[  610.207897] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  610.210257] [drm:intel_dp_mode_fixup], DP link bw required 292200 available 518400
>[  610.212599] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  610.215121] [drm:intel_dp_link_down], 
>[  610.262764] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  610.265173] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  610.267982] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  610.270394] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  610.272814] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  610.275236] [drm:drm_mode_debug_printmodeline], Modeline 115:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  610.277699] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  610.280172] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  610.282948] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  610.336723] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  610.339222] [drm:ironlake_update_plane], Writing base 0E760000 00000000 0 0 5632
>[  610.393712] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  610.396250] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:115:1400x1050]
>[  610.398726] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  610.401183] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  610.403657] [drm:ironlake_write_eld], ELD on pipe A
>[  610.406110] [drm:ironlake_write_eld], Audio directed to unknown port
>[  610.408566] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  610.411035] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  610.413490] [drm:ironlake_check_srwm], watermark 1: display plane 75, fbc lines 3, cursor 6
>[  610.415958] [drm:ironlake_check_srwm], watermark 2: display plane 166, fbc lines 4, cursor 10
>[  610.470650] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  610.524629] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  610.527504] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  610.529976] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  610.532582] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  610.535015] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  610.537474] [drm:ironlake_fdi_link_train], FDI train done
>[  610.539924] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  610.542395] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  610.546498] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  610.550239] [drm:intel_dp_start_link_train], clock recovery OK
>[  610.553342] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  610.556855] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  610.577562] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  610.580593] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  610.583081] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  610.585499] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  610.587880] [drm:intel_modeset_check_state], [CRTC:3]
>[  610.590238] [drm:intel_modeset_check_state], [CRTC:5]
>[  620.679210] [drm:drm_mode_addfb], [FB:115]
>[  620.681737] [drm:drm_mode_setcrtc], [CRTC:3]
>[  620.684104] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  620.686439] [drm:intel_crtc_set_config], [CRTC:3] [FB:115] #connectors=1 (x y) (0 0)
>[  620.688770] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  620.691120] [drm:drm_mode_debug_printmodeline], Modeline 115:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  620.693484] [drm:drm_mode_debug_printmodeline], Modeline 116:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  620.695849] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  620.698239] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  620.700572] [drm:drm_mode_debug_printmodeline], Modeline 116:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  620.702939] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  620.705260] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 118963KHz
>[  620.707626] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  620.709987] [drm:intel_dp_mode_fixup], DP link bw required 285512 available 518400
>[  620.712344] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  620.714870] [drm:intel_dp_link_down], 
>[  620.780182] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  620.884139] ------------[ cut here ]------------
>[  620.887090] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  620.889475] Hardware name: OptiPlex 980                 
>[  620.891829] pipe_off wait timed out
>[  620.894147] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  620.901920] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  620.904481] Call Trace:
>[  620.907070]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  620.909656]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  620.912285]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  620.914911]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  620.917530]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  620.920184]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  620.922787]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  620.925405]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  620.928020]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  620.930621]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  620.933224]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  620.935831]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  620.938434]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  620.941041]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  620.943634]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  620.946273]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  620.948911]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  620.951557]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  620.954149]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  620.956787]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  620.959444]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  620.962087]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  620.964714]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  620.967316] ---[ end trace ca8f0eea49311cdb ]---
>[  620.978150] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  620.980829] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  620.983859] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  620.986436] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  620.988993] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  620.991547] [drm:drm_mode_debug_printmodeline], Modeline 116:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  620.994136] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  620.996740] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  620.999637] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  621.054118] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  621.056813] [drm:ironlake_update_plane], Writing base 0ED04000 00000000 0 0 6400
>[  621.111094] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  621.113775] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:116:1600x900]
>[  621.116411] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  621.119009] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  621.121585] [drm:ironlake_write_eld], ELD on pipe A
>[  621.124138] [drm:ironlake_write_eld], Audio directed to unknown port
>[  621.126692] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  621.129239] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  621.131781] [drm:ironlake_check_srwm], watermark 1: display plane 73, fbc lines 3, cursor 6
>[  621.134327] [drm:ironlake_check_srwm], watermark 2: display plane 162, fbc lines 4, cursor 10
>[  621.189057] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  621.243036] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  621.245980] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  621.248514] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  621.251163] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  621.253634] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  621.256104] [drm:ironlake_fdi_link_train], FDI train done
>[  621.258563] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  621.261029] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  621.265144] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  621.269048] [drm:intel_dp_start_link_train], clock recovery OK
>[  621.272189] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  621.275694] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  621.297043] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  621.299648] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  621.302177] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  621.304755] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  621.307276] [drm:intel_modeset_check_state], [CRTC:3]
>[  621.309773] [drm:intel_modeset_check_state], [CRTC:5]
>[  631.400208] [drm:drm_mode_addfb], [FB:116]
>[  631.402825] [drm:drm_mode_setcrtc], [CRTC:3]
>[  631.405350] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  631.407817] [drm:intel_crtc_set_config], [CRTC:3] [FB:116] #connectors=1 (x y) (0 0)
>[  631.410299] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  631.412815] [drm:drm_mode_debug_printmodeline], Modeline 116:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  631.415338] [drm:drm_mode_debug_printmodeline], Modeline 117:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  631.417912] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  631.420470] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  631.423042] [drm:drm_mode_debug_printmodeline], Modeline 117:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  631.425656] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  631.428287] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 157500KHz
>[  631.430978] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  631.433632] [drm:intel_dp_mode_fixup], DP link bw required 378000 available 518400
>[  631.436270] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  631.439070] [drm:intel_dp_link_down], 
>[  631.498591] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  631.603545] ------------[ cut here ]------------
>[  631.606410] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  631.609018] Hardware name: OptiPlex 980                 
>[  631.611581] pipe_off wait timed out
>[  631.614123] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  631.622563] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  631.625354] Call Trace:
>[  631.628159]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  631.630949]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  631.633732]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  631.636514]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  631.639298]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  631.642006]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  631.644625]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  631.647182]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  631.649714]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  631.652231]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  631.654749]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  631.657267]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  631.659794]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  631.662313]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  631.664838]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  631.667343]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  631.669848]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  631.672352]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  631.674859]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  631.677357]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  631.679840]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  631.682325]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  631.684804]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  631.687285] ---[ end trace ca8f0eea49311cdc ]---
>[  631.691599] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  631.694185] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  631.697141] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  631.699681] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  631.702233] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  631.704798] [drm:drm_mode_debug_printmodeline], Modeline 117:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  631.707406] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  631.710035] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  631.712964] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  631.767568] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  631.770265] [drm:ironlake_update_plane], Writing base 0F283000 00000000 0 0 5120
>[  631.824504] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  631.827202] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:117:1280x1024]
>[  631.829861] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  631.832471] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  631.835052] [drm:ironlake_write_eld], ELD on pipe A
>[  631.837613] [drm:ironlake_write_eld], Audio directed to unknown port
>[  631.840169] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  631.842694] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  631.845267] [drm:ironlake_check_srwm], watermark 1: display plane 82, fbc lines 4, cursor 6
>[  631.847842] [drm:ironlake_check_srwm], watermark 2: display plane 214, fbc lines 5, cursor 14
>[  631.902509] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  631.956447] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  631.959448] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  631.962000] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  631.964656] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  631.967132] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  631.969622] [drm:ironlake_fdi_link_train], FDI train done
>[  631.972087] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  631.974569] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  631.978684] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  631.982440] [drm:intel_dp_start_link_train], clock recovery OK
>[  631.985592] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  631.989112] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  632.004427] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  632.007047] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  632.009568] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  632.012111] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  632.014637] [drm:intel_modeset_check_state], [CRTC:3]
>[  632.017138] [drm:intel_modeset_check_state], [CRTC:5]
>[  642.105177] [drm:drm_mode_addfb], [FB:117]
>[  642.107786] [drm:drm_mode_setcrtc], [CRTC:3]
>[  642.110317] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  642.112776] [drm:intel_crtc_set_config], [CRTC:3] [FB:117] #connectors=1 (x y) (0 0)
>[  642.115276] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  642.117790] [drm:drm_mode_debug_printmodeline], Modeline 117:"1280x1024" 85 157500 1280 1344 1504 1728 1024 1025 1028 1072 0x40 0x5
>[  642.120335] [drm:drm_mode_debug_printmodeline], Modeline 118:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  642.122877] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  642.125443] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  642.128009] [drm:drm_mode_debug_printmodeline], Modeline 118:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  642.130624] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  642.133284] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 135000KHz
>[  642.135949] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  642.138597] [drm:intel_dp_mode_fixup], DP link bw required 324000 available 518400
>[  642.141251] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  642.144047] [drm:intel_dp_link_down], 
>[  642.186011] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  642.189197] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  642.192832] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  642.196014] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  642.199167] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  642.202319] [drm:drm_mode_debug_printmodeline], Modeline 118:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  642.205522] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  642.208724] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  642.212233] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  642.266975] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  642.270198] [drm:ironlake_update_plane], Writing base 0F783000 00000000 0 0 5120
>[  642.324951] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  642.328154] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:118:1280x1024]
>[  642.331384] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  642.334590] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  642.337713] [drm:ironlake_write_eld], ELD on pipe A
>[  642.340743] [drm:ironlake_write_eld], Audio directed to unknown port
>[  642.343676] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  642.346597] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  642.349496] [drm:ironlake_check_srwm], watermark 1: display plane 82, fbc lines 4, cursor 6
>[  642.352400] [drm:ironlake_check_srwm], watermark 2: display plane 162, fbc lines 5, cursor 10
>[  642.406917] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  642.460892] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  642.464108] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  642.466980] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  642.470007] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  642.472849] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  642.475705] [drm:ironlake_fdi_link_train], FDI train done
>[  642.478543] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  642.481412] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  642.485886] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  642.489438] [drm:intel_dp_start_link_train], clock recovery OK
>[  642.492370] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  642.496225] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  642.512879] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  642.515832] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  642.518767] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  642.521688] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  642.524550] [drm:intel_modeset_check_state], [CRTC:3]
>[  642.527420] [drm:intel_modeset_check_state], [CRTC:5]
>[  652.615872] [drm:drm_mode_addfb], [FB:118]
>[  652.618314] [drm:drm_mode_setcrtc], [CRTC:3]
>[  652.620695] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  652.623024] [drm:intel_crtc_set_config], [CRTC:3] [FB:118] #connectors=1 (x y) (0 0)
>[  652.625347] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  652.627690] [drm:drm_mode_debug_printmodeline], Modeline 118:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  652.630041] [drm:drm_mode_debug_printmodeline], Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  652.632377] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  652.634712] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  652.637026] [drm:drm_mode_debug_printmodeline], Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  652.639358] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  652.641708] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 108000KHz
>[  652.644043] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  652.646375] [drm:intel_dp_mode_fixup], DP link bw required 259200 available 259200
>[  652.648698] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  652.651188] [drm:intel_dp_link_down], 
>[  652.700578] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  652.702966] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  652.705764] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  652.708166] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  652.710582] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  652.713000] [drm:drm_mode_debug_printmodeline], Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  652.715463] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  652.717934] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  652.720708] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  652.774522] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  652.777054] [drm:ironlake_update_plane], Writing base 00FE7000 00000000 0 0 5120
>[  652.831542] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  652.834038] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:119:1280x1024]
>[  652.836494] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  652.838959] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  652.841452] [drm:ironlake_write_eld], ELD on pipe A
>[  652.843912] [drm:ironlake_write_eld], Audio directed to unknown port
>[  652.846380] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  652.848856] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  652.851315] [drm:ironlake_check_srwm], watermark 1: display plane 67, fbc lines 3, cursor 6
>[  652.853797] [drm:ironlake_check_srwm], watermark 2: display plane 148, fbc lines 4, cursor 10
>[  652.908470] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  652.962469] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  652.965306] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  652.967788] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  652.970406] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  652.972848] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  652.975314] [drm:ironlake_fdi_link_train], FDI train done
>[  652.977765] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  652.980249] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  652.984365] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  652.988064] [drm:intel_dp_start_link_train], clock recovery OK
>[  652.991161] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  652.995125] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  653.015450] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  653.017983] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  653.020368] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  653.022719] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  653.025036] [drm:intel_modeset_check_state], [CRTC:3]
>[  653.027325] [drm:intel_modeset_check_state], [CRTC:5]
>[  663.114655] [drm:drm_mode_addfb], [FB:119]
>[  663.117057] [drm:drm_mode_setcrtc], [CRTC:3]
>[  663.119361] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  663.121644] [drm:intel_crtc_set_config], [CRTC:3] [FB:119] #connectors=1 (x y) (0 0)
>[  663.123907] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  663.126196] [drm:drm_mode_debug_printmodeline], Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  663.128484] [drm:drm_mode_debug_printmodeline], Modeline 120:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  663.130796] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  663.133089] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  663.135358] [drm:drm_mode_debug_printmodeline], Modeline 120:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  663.137657] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  663.139956] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 157000KHz
>[  663.142271] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  663.144602] [drm:intel_dp_mode_fixup], DP link bw required 376800 available 518400
>[  663.146891] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  663.149411] [drm:intel_dp_link_down], 
>[  663.211001] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  663.315037] ------------[ cut here ]------------
>[  663.317393] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  663.319690] Hardware name: OptiPlex 980                 
>[  663.321987] pipe_off wait timed out
>[  663.324287] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  663.332082] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  663.334610] Call Trace:
>[  663.337162]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  663.339722]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  663.342289]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  663.344863]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  663.347454]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  663.350051]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  663.352630]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  663.355214]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  663.357791]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  663.360366]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  663.362944]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  663.365538]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  663.368111]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  663.370680]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  663.373245]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  663.375828]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  663.378411]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  663.380988]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  663.383576]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  663.386161]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  663.388759]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  663.391346]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  663.393930]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  663.396480] ---[ end trace ca8f0eea49311cdd ]---
>[  663.402997] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  663.405643] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  663.408617] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  663.411179] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  663.413718] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  663.416241] [drm:drm_mode_debug_printmodeline], Modeline 120:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  663.418805] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  663.421385] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  663.424259] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  663.477967] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  663.480619] [drm:ironlake_update_plane], Writing base 014E7000 00000000 0 0 5760
>[  663.534939] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  663.537604] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:120:1440x900]
>[  663.540183] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  663.542740] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  663.545278] [drm:ironlake_write_eld], ELD on pipe A
>[  663.547782] [drm:ironlake_write_eld], Audio directed to unknown port
>[  663.550291] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  663.552796] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  663.555308] [drm:ironlake_check_srwm], watermark 1: display plane 92, fbc lines 4, cursor 6
>[  663.557815] [drm:ironlake_check_srwm], watermark 2: display plane 182, fbc lines 5, cursor 10
>[  663.611909] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  663.665883] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  663.668742] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  663.671217] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  663.673876] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  663.676349] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  663.678799] [drm:ironlake_fdi_link_train], FDI train done
>[  663.681222] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  663.683671] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  663.687736] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  663.691490] [drm:intel_dp_start_link_train], clock recovery OK
>[  663.694757] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  663.698283] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  663.714795] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  663.717987] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  663.720623] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  663.723259] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  663.725876] [drm:intel_modeset_check_state], [CRTC:3]
>[  663.728477] [drm:intel_modeset_check_state], [CRTC:5]
>[  673.816145] [drm:drm_mode_addfb], [FB:120]
>[  673.818797] [drm:drm_mode_setcrtc], [CRTC:3]
>[  673.821340] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  673.823839] [drm:intel_crtc_set_config], [CRTC:3] [FB:120] #connectors=1 (x y) (0 0)
>[  673.826338] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  673.828852] [drm:drm_mode_debug_printmodeline], Modeline 120:"1440x900" 85 157000 1440 1544 1696 1952 900 903 909 948 0x40 0x6
>[  673.831411] [drm:drm_mode_debug_printmodeline], Modeline 121:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  673.833986] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  673.836579] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  673.839191] [drm:drm_mode_debug_printmodeline], Modeline 121:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  673.841847] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  673.844528] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 136750KHz
>[  673.847224] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  673.849915] [drm:intel_dp_mode_fixup], DP link bw required 328200 available 518400
>[  673.852598] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  673.855421] [drm:intel_dp_link_down], 
>[  673.904513] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  673.907203] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  673.910252] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  673.912825] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  673.915405] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  673.917953] [drm:drm_mode_debug_printmodeline], Modeline 121:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  673.920547] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  673.923167] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  673.926068] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  673.980441] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  673.983143] [drm:ironlake_update_plane], Writing base 019D9000 00000000 0 0 5760
>[  674.037459] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  674.040133] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:121:1440x900]
>[  674.042775] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  674.045392] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  674.047931] [drm:ironlake_write_eld], ELD on pipe A
>[  674.050396] [drm:ironlake_write_eld], Audio directed to unknown port
>[  674.052795] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  674.055191] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  674.057568] [drm:ironlake_check_srwm], watermark 1: display plane 84, fbc lines 3, cursor 6
>[  674.059961] [drm:ironlake_check_srwm], watermark 2: display plane 182, fbc lines 5, cursor 10
>[  674.114380] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  674.168359] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  674.171155] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  674.173555] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  674.176072] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  674.178413] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  674.180769] [drm:ironlake_fdi_link_train], FDI train done
>[  674.183104] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  674.185473] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  674.189448] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  674.192991] [drm:intel_dp_start_link_train], clock recovery OK
>[  674.195934] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  674.199299] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  674.216294] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  674.219264] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  674.221706] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  674.224139] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  674.226532] [drm:intel_modeset_check_state], [CRTC:3]
>[  674.228920] [drm:intel_modeset_check_state], [CRTC:5]
>[  684.316140] [drm:drm_mode_addfb], [FB:121]
>[  684.318571] [drm:drm_mode_setcrtc], [CRTC:3]
>[  684.320917] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  684.323233] [drm:intel_crtc_set_config], [CRTC:3] [FB:121] #connectors=1 (x y) (0 0)
>[  684.325531] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  684.327858] [drm:drm_mode_debug_printmodeline], Modeline 121:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  684.330211] [drm:drm_mode_debug_printmodeline], Modeline 122:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  684.332562] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  684.334911] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  684.337211] [drm:drm_mode_debug_printmodeline], Modeline 122:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  684.339536] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  684.341868] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 106500KHz
>[  684.344248] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  684.346584] [drm:intel_dp_mode_fixup], DP link bw required 255600 available 259200
>[  684.348946] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  684.351472] [drm:intel_dp_link_down], 
>[  684.394998] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  684.397435] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  684.400269] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  684.402713] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  684.405163] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  684.407616] [drm:drm_mode_debug_printmodeline], Modeline 122:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  684.410114] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  684.412613] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  684.415423] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  684.469973] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  684.472454] [drm:ironlake_update_plane], Writing base 01ECB000 00000000 0 0 5760
>[  684.525945] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  684.528446] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:122:1440x900]
>[  684.530894] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  684.533339] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  684.535801] [drm:ironlake_write_eld], ELD on pipe A
>[  684.538258] [drm:ironlake_write_eld], Audio directed to unknown port
>[  684.540712] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  684.543167] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  684.545623] [drm:ironlake_check_srwm], watermark 1: display plane 66, fbc lines 3, cursor 6
>[  684.548096] [drm:ironlake_check_srwm], watermark 2: display plane 146, fbc lines 4, cursor 10
>[  684.602888] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  684.656861] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  684.659701] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  684.662143] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  684.664743] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  684.667185] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  684.669634] [drm:ironlake_fdi_link_train], FDI train done
>[  684.672075] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  684.674539] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  684.678677] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  684.682411] [drm:intel_dp_start_link_train], clock recovery OK
>[  684.685535] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  684.689015] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  684.709798] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  684.712878] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  684.715436] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  684.717961] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  684.720445] [drm:intel_modeset_check_state], [CRTC:3]
>[  684.722906] [drm:intel_modeset_check_state], [CRTC:5]
>[  694.810525] [drm:drm_mode_addfb], [FB:122]
>[  694.813031] [drm:drm_mode_setcrtc], [CRTC:3]
>[  694.815430] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  694.817809] [drm:intel_crtc_set_config], [CRTC:3] [FB:122] #connectors=1 (x y) (0 0)
>[  694.820184] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  694.822535] [drm:drm_mode_debug_printmodeline], Modeline 122:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  694.824939] [drm:drm_mode_debug_printmodeline], Modeline 123:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  694.827336] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  694.829742] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  694.832115] [drm:drm_mode_debug_printmodeline], Modeline 123:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  694.834505] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  694.836914] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 148500KHz
>[  694.839326] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  694.841716] [drm:intel_dp_mode_fixup], DP link bw required 356400 available 518400
>[  694.844103] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  694.846664] [drm:intel_dp_link_down], 
>[  694.910419] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  695.014435] ------------[ cut here ]------------
>[  695.016894] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  695.019282] Hardware name: OptiPlex 980                 
>[  695.021679] pipe_off wait timed out
>[  695.024030] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  695.031914] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  695.034505] Call Trace:
>[  695.037114]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  695.039718]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  695.042344]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  695.044986]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  695.047640]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  695.050298]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  695.052921]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  695.055565]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  695.058190]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  695.060818]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  695.063447]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  695.066076]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  695.068698]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  695.071321]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  695.073940]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  695.076560]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  695.079180]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  695.081806]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  695.084428]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  695.087056]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  695.089702]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  695.092327]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  695.094950]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  695.097537] ---[ end trace ca8f0eea49311cde ]---
>[  695.110385] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  695.113066] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  695.116102] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  695.118680] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  695.121243] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  695.123792] [drm:drm_mode_debug_printmodeline], Modeline 123:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  695.126383] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  695.128991] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  695.131891] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  695.186354] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  695.189046] [drm:ironlake_update_plane], Writing base 023BD000 00000000 0 0 5120
>[  695.243372] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  695.246085] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:123:1280x960]
>[  695.248747] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  695.251337] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  695.253900] [drm:ironlake_write_eld], ELD on pipe A
>[  695.256440] [drm:ironlake_write_eld], Audio directed to unknown port
>[  695.258966] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  695.261497] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 9, cursor: 6
>[  695.264014] [drm:ironlake_check_srwm], watermark 1: display plane 82, fbc lines 4, cursor 6
>[  695.266546] [drm:ironlake_check_srwm], watermark 2: display plane 162, fbc lines 5, cursor 10
>[  695.321293] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  695.375272] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  695.378206] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  695.380731] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  695.383372] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  695.385837] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  695.388301] [drm:ironlake_fdi_link_train], FDI train done
>[  695.390761] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  695.393233] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  695.397329] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  695.401056] [drm:intel_dp_start_link_train], clock recovery OK
>[  695.404311] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  695.407809] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  695.424208] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  695.427524] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  695.430144] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  695.432754] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  695.435343] [drm:intel_modeset_check_state], [CRTC:3]
>[  695.437922] [drm:intel_modeset_check_state], [CRTC:5]
>[  705.526034] [drm:drm_mode_addfb], [FB:123]
>[  705.528627] [drm:drm_mode_setcrtc], [CRTC:3]
>[  705.531135] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  705.533601] [drm:intel_crtc_set_config], [CRTC:3] [FB:123] #connectors=1 (x y) (0 0)
>[  705.536116] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  705.538606] [drm:drm_mode_debug_printmodeline], Modeline 123:"1280x960" 85 148500 1280 1344 1504 1728 960 961 964 1011 0x40 0x5
>[  705.541153] [drm:drm_mode_debug_printmodeline], Modeline 124:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  705.543714] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  705.546292] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  705.548889] [drm:drm_mode_debug_printmodeline], Modeline 124:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  705.551524] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  705.554183] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 108000KHz
>[  705.556854] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  705.559511] [drm:intel_dp_mode_fixup], DP link bw required 259200 available 259200
>[  705.562153] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  705.564962] [drm:intel_dp_link_down], 
>[  705.604837] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  705.608230] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  705.611907] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  705.615118] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  705.618274] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  705.621411] [drm:drm_mode_debug_printmodeline], Modeline 124:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  705.624594] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  705.627786] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  705.631277] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  705.685801] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  705.688996] [drm:ironlake_update_plane], Writing base 0286D000 00000000 0 0 5120
>[  705.743777] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  705.746951] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:124:1280x960]
>[  705.750163] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  705.753345] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  705.756451] [drm:ironlake_write_eld], ELD on pipe A
>[  705.759462] [drm:ironlake_write_eld], Audio directed to unknown port
>[  705.762374] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  705.765258] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 7, cursor: 6
>[  705.768143] [drm:ironlake_check_srwm], watermark 1: display plane 67, fbc lines 3, cursor 6
>[  705.771035] [drm:ironlake_check_srwm], watermark 2: display plane 148, fbc lines 4, cursor 10
>[  705.825742] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  705.879718] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  705.882864] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  705.885748] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  705.888748] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  705.891579] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  705.894413] [drm:ironlake_fdi_link_train], FDI train done
>[  705.897229] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  705.900068] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  705.904519] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  705.908031] [drm:intel_dp_start_link_train], clock recovery OK
>[  705.910946] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  705.914272] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  705.934702] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  705.937637] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  705.940073] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  705.942506] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  705.944926] [drm:intel_modeset_check_state], [CRTC:3]
>[  705.947344] [drm:intel_modeset_check_state], [CRTC:5]
>[  716.031683] [drm:drm_mode_addfb], [FB:124]
>[  716.034135] [drm:drm_mode_setcrtc], [CRTC:3]
>[  716.036493] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  716.038805] [drm:intel_crtc_set_config], [CRTC:3] [FB:124] #connectors=1 (x y) (0 0)
>[  716.041161] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  716.043430] [drm:drm_mode_debug_printmodeline], Modeline 124:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  716.045761] [drm:drm_mode_debug_printmodeline], Modeline 125:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  716.048104] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  716.050448] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  716.052766] [drm:drm_mode_debug_printmodeline], Modeline 125:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  716.055101] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  716.057449] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 85885KHz
>[  716.059870] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  716.062201] [drm:intel_dp_mode_fixup], DP link bw required 206124 available 259200
>[  716.064534] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  716.067041] [drm:intel_dp_link_down], 
>[  716.134325] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  716.238281] ------------[ cut here ]------------
>[  716.241322] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  716.244184] Hardware name: OptiPlex 980                 
>[  716.247020] pipe_off wait timed out
>[  716.249846] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  716.259441] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  716.262573] Call Trace:
>[  716.265736]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  716.268900]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  716.272084]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  716.275286]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  716.278505]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  716.281734]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  716.284924]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  716.288132]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  716.291333]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  716.294536]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  716.297741]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  716.300953]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  716.304144]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  716.307348]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  716.310552]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  716.313757]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  716.316969]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  716.320201]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  716.323431]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  716.326657]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  716.329891]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  716.333115]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  716.336322]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  716.339503] ---[ end trace ca8f0eea49311cdf ]---
>[  716.348234] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  716.351413] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  716.355008] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  716.358177] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  716.361339] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  716.364480] [drm:drm_mode_debug_printmodeline], Modeline 125:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  716.367677] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  716.370874] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  716.374361] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  716.429198] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  716.432387] [drm:ironlake_update_plane], Writing base 02D1D000 00000000 0 0 5504
>[  716.487173] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  716.490389] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:125:1366x768]
>[  716.493601] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  716.496788] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  716.499938] [drm:ironlake_write_eld], ELD on pipe A
>[  716.503054] [drm:ironlake_write_eld], Audio directed to unknown port
>[  716.506173] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  716.509302] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  716.512494] [drm:ironlake_check_srwm], watermark 1: display plane 53, fbc lines 3, cursor 6
>[  716.515611] [drm:ironlake_check_srwm], watermark 2: display plane 118, fbc lines 4, cursor 10
>[  716.571137] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  716.626114] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  716.629539] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  716.632627] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  716.635833] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  716.638867] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  716.641919] [drm:ironlake_fdi_link_train], FDI train done
>[  716.644934] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  716.647978] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  716.652643] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  716.656358] [drm:intel_dp_start_link_train], clock recovery OK
>[  716.659478] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  716.662960] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  716.684098] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  716.687419] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  716.690031] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  716.692642] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  716.695239] [drm:intel_modeset_check_state], [CRTC:3]
>[  716.697811] [drm:intel_modeset_check_state], [CRTC:5]
>[  726.782179] [drm:drm_mode_addfb], [FB:125]
>[  726.784827] [drm:drm_mode_setcrtc], [CRTC:3]
>[  726.787332] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  726.789802] [drm:intel_crtc_set_config], [CRTC:3] [FB:125] #connectors=1 (x y) (0 0)
>[  726.792275] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  726.794783] [drm:drm_mode_debug_printmodeline], Modeline 125:"1366x768" 60 85885 1366 1439 1583 1800 768 769 772 795 0x0 0x6
>[  726.797313] [drm:drm_mode_debug_printmodeline], Modeline 126:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  726.799885] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  726.802447] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  726.805047] [drm:drm_mode_debug_printmodeline], Modeline 126:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  726.807684] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  726.810330] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 85500KHz
>[  726.813003] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  726.815656] [drm:intel_dp_mode_fixup], DP link bw required 205200 available 259200
>[  726.818311] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  726.821102] [drm:intel_dp_link_down], 
>[  726.878721] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  726.983727] ------------[ cut here ]------------
>[  726.986410] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  726.989005] Hardware name: OptiPlex 980                 
>[  726.991540] pipe_off wait timed out
>[  726.994056] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  727.002452] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  727.005220] Call Trace:
>[  727.007994]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  727.010752]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  727.013506]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  727.016268]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  727.019021]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  727.021706]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  727.024299]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  727.026836]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  727.029345]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  727.031845]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  727.034335]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  727.036832]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  727.039330]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  727.041823]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  727.044312]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  727.046792]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  727.049277]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  727.051751]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  727.054221]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  727.056681]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  727.059099]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  727.061557]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  727.064019]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  727.066483] ---[ end trace ca8f0eea49311ce0 ]---
>[  727.074730] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  727.077281] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  727.080203] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  727.082697] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  727.085209] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  727.087730] [drm:drm_mode_debug_printmodeline], Modeline 126:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  727.090300] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  727.092879] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  727.095762] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  727.149659] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  727.152319] [drm:ironlake_update_plane], Writing base 03125000 00000000 0 0 5440
>[  727.206634] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  727.209290] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:126:1360x768]
>[  727.211891] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  727.214449] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  727.216981] [drm:ironlake_write_eld], ELD on pipe A
>[  727.219486] [drm:ironlake_write_eld], Audio directed to unknown port
>[  727.221998] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  727.224517] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  727.227035] [drm:ironlake_check_srwm], watermark 1: display plane 53, fbc lines 3, cursor 6
>[  727.229554] [drm:ironlake_check_srwm], watermark 2: display plane 117, fbc lines 4, cursor 10
>[  727.283598] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  727.337576] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  727.340493] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  727.342995] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  727.345618] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  727.348064] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  727.350527] [drm:ironlake_fdi_link_train], FDI train done
>[  727.352962] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  727.355408] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  727.359491] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  727.363189] [drm:intel_dp_start_link_train], clock recovery OK
>[  727.366299] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  727.369762] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  727.390510] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  727.393664] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  727.396257] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  727.398851] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  727.401420] [drm:intel_modeset_check_state], [CRTC:3]
>[  727.403975] [drm:intel_modeset_check_state], [CRTC:5]
>[  737.490051] [drm:drm_mode_addfb], [FB:126]
>[  737.492624] [drm:drm_mode_setcrtc], [CRTC:3]
>[  737.495109] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  737.497560] [drm:intel_crtc_set_config], [CRTC:3] [FB:126] #connectors=1 (x y) (0 0)
>[  737.500037] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  737.502519] [drm:drm_mode_debug_printmodeline], Modeline 126:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  737.505034] [drm:drm_mode_debug_printmodeline], Modeline 127:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  737.507562] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  737.510109] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  737.512670] [drm:drm_mode_debug_printmodeline], Modeline 127:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  737.515283] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  737.517917] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 122500KHz
>[  737.520655] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 4 clock 162000 bpp 24
>[  737.523299] [drm:intel_dp_mode_fixup], DP link bw required 294000 available 518400
>[  737.525935] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  737.528718] [drm:intel_dp_link_down], 
>[  737.586133] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  737.691088] ------------[ cut here ]------------
>[  737.694366] WARNING: at drivers/gpu/drm/i915/intel_display.c:966 intel_wait_for_pipe_off+0x158/0x175 [i915]()
>[  737.696951] Hardware name: OptiPlex 980                 
>[  737.699482] pipe_off wait timed out
>[  737.701992] Modules linked in: netconsole configfs ip6t_REJECT ipt_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 xt_tcpudp nf_conntrack_ipv4 ip6table_filter nf_defrag_ipv4 ip6_tables xt_state nf_conntrack iptable_filter ip_tables x_tables snd_hda_codec_hdmi snd_hda_codec_realtek coretemp snd_hda_intel snd_hda_codec snd_hwdep hwmon ppdev iTCO_wdt iTCO_vendor_support acpi_cpufreq snd_seq snd_seq_device snd_pcm snd_timer snd parport_pc freq_table soundcore parport snd_page_alloc i2c_i801 lpc_ich mperf kvm_intel kvm e1000e serio_raw wmi mfd_core dcdbas microcode pcspkr uinput ipv6 i915 drm_kms_helper drm i2c_algo_bit button i2c_core video dm_mirror dm_region_hash dm_log dm_mod [last unloaded: netconsole]
>[  737.710372] Pid: 3752, comm: testdisplay Tainted: G        W    3.8.0-rc6_next_queued_debug_20130220+ #3
>[  737.713140] Call Trace:
>[  737.715917]  [<ffffffffa00cd100>] ? intel_wait_for_pipe_off+0xf9/0x175 [i915]
>[  737.718681]  [<ffffffff81030d4c>] warn_slowpath_common+0x83/0x9b
>[  737.721447]  [<ffffffff81030e07>] warn_slowpath_fmt+0x46/0x48
>[  737.724208]  [<ffffffffa00cd15f>] intel_wait_for_pipe_off+0x158/0x175 [i915]
>[  737.726962]  [<ffffffffa00cd2a9>] intel_disable_pipe+0x12d/0x139 [i915]
>[  737.729648]  [<ffffffffa00cda78>] ironlake_crtc_disable+0xce/0x781 [i915]
>[  737.732238]  [<ffffffff81033745>] ? vprintk+0x1d/0x1f
>[  737.734765]  [<ffffffffa0056651>] ? drm_ut_debug_printk+0x57/0x5e [drm]
>[  737.737280]  [<ffffffffa00d4a7f>] intel_set_mode+0x3ea/0x800 [i915]
>[  737.739776]  [<ffffffffa0060c6a>] ? drm_mode_debug_printmodeline+0x8c/0x8e [drm]
>[  737.742267]  [<ffffffffa00d54a3>] intel_crtc_set_config+0x60e/0x756 [i915]
>[  737.744757]  [<ffffffffa005be33>] drm_mode_set_config_internal+0x27/0x53 [drm]
>[  737.747250]  [<ffffffffa005eadb>] drm_mode_setcrtc+0x40e/0x466 [drm]
>[  737.749740]  [<ffffffffa005178f>] drm_ioctl+0x2dd/0x3a9 [drm]
>[  737.752231]  [<ffffffffa005e6cd>] ? drm_mode_setplane+0x353/0x353 [drm]
>[  737.754702]  [<ffffffff816c4d06>] ? __schedule+0x813/0x8c5
>[  737.757187]  [<ffffffff813b3e94>] ? put_ldisc+0xab/0xb2
>[  737.759660]  [<ffffffff81120eec>] do_vfs_ioctl+0x467/0x4a8
>[  737.762139]  [<ffffffff816cd327>] ? sysret_check+0x1b/0x56
>[  737.764602]  [<ffffffff81120f8b>] sys_ioctl+0x5e/0x83
>[  737.767070]  [<ffffffff8133d0de>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>[  737.769543]  [<ffffffff81059c3d>] ? finish_task_switch+0x4c/0xf6
>[  737.771991]  [<ffffffff816cd302>] system_call_fastpath+0x16/0x1b
>[  737.774441] ---[ end trace ca8f0eea49311ce1 ]---
>[  737.781100] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  737.783666] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  737.786602] [drm:intel_choose_pipe_bpp_dither], clamping display bpc (was -1) to EDID reported max of 10
>[  737.789102] [drm:intel_choose_pipe_bpp_dither], setting pipe bpc to 8 (max display bpc 8)
>[  737.791626] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  737.794164] [drm:drm_mode_debug_printmodeline], Modeline 127:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  737.796751] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  737.799352] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  737.802263] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 2
>[  737.856071] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  737.858756] [drm:ironlake_update_plane], Writing base 03521000 00000000 0 0 5120
>[  737.913046] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  737.915728] [drm:intel_crtc_mode_set], [ENCODER:13:TMDS-13] set [MODE:127:1280x800]
>[  737.918352] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[  737.920942] [drm:intel_write_eld], ELD on [CONNECTOR:14:DP-1], [ENCODER:13:TMDS-13]
>[  737.923503] [drm:ironlake_write_eld], ELD on pipe A
>[  737.926042] [drm:ironlake_write_eld], Audio directed to unknown port
>[  737.928581] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[  737.931116] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 8, cursor: 6
>[  737.933637] [drm:ironlake_check_srwm], watermark 1: display plane 75, fbc lines 3, cursor 6
>[  737.936176] [drm:ironlake_check_srwm], watermark 2: display plane 162, fbc lines 5, cursor 10
>[  737.991013] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  738.044988] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  738.047923] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
>[  738.050454] [drm:ironlake_fdi_link_train], FDI train 1 done.
>[  738.053109] [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
>[  738.055579] [drm:ironlake_fdi_link_train], FDI train 2 done.
>[  738.058058] [drm:ironlake_fdi_link_train], FDI train done
>[  738.060522] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  738.062989] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  738.067091] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  738.070826] [drm:intel_dp_start_link_train], clock recovery OK
>[  738.074071] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  738.077565] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successfull
>[  738.093924] [drm:intel_connector_check_state], [CONNECTOR:14:DP-1]
>[  738.097241] [drm:intel_modeset_check_state], [ENCODER:8:DAC-8]
>[  738.099855] [drm:intel_modeset_check_state], [ENCODER:9:TMDS-9]
>[  738.102469] [drm:intel_modeset_check_state], [ENCODER:13:TMDS-13]
>[  738.104969] [drm:intel_modeset_check_state], [CRTC:3]
>[  738.107504] [drm:intel_modeset_check_state], [CRTC:5]
>[  748.193961] [drm:drm_mode_addfb], [FB:127]
>[  748.196576] [drm:drm_mode_setcrtc], [CRTC:3]
>[  748.199076] [drm:drm_mode_setcrtc], [CONNECTOR:14:DP-1]
>[  748.201563] [drm:intel_crtc_set_config], [CRTC:3] [FB:127] #connectors=1 (x y) (0 0)
>[  748.204063] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  748.206553] [drm:drm_mode_debug_printmodeline], Modeline 127:"1280x800" 85 122500 1280 1360 1496 1712 800 803 809 843 0x40 0x6
>[  748.209082] [drm:drm_mode_debug_printmodeline], Modeline 128:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  748.211637] [drm:intel_modeset_stage_output_state], [CONNECTOR:14:DP-1] to [CRTC:3]
>[  748.214208] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  748.216803] [drm:drm_mode_debug_printmodeline], Modeline 128:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  748.219444] [drm:intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  748.222103] [drm:intel_dp_mode_fixup], DP link computation with max lane count 4 max bw 0a pixel clock 106500KHz
>[  748.224789] [drm:intel_dp_mode_fixup], DP link bw 06 lane count 2 clock 162000 bpp 24
>[  748.227450] [drm:intel_dp_mode_fixup], DP link bw required 255600 available 259200
>[  748.230089] [drm:intel_modeset_adjusted_mode], [CRTC:3]
>[  748.232901] [drm:intel_dp_link_down],

Actions: View

Attachments on bug 61158: 75163

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.