Attachment 77743 Details for Bug 57567 – additional fix

[patch] additional fix

0001-drm-radeon-properly-lock-disp-in-mc_stop-resume-for-.patch (text/plain), 4.44 KB, created by Alex Deucher on 2013-04-10 14:01:42 UTC

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Creator: Alex Deucher

Created: 2013-04-10 14:01:42 UTC

Size: 4.44 KB

patch

obsolete

>From 289c182c07b367ad6e4052d97a2478dbca24f632 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Wed, 10 Apr 2013 09:58:42 -0400
>Subject: [PATCH] drm/radeon: properly lock disp in mc_stop/resume for
> evergreen+
>
>Need to wait for the new addresses to take affect before
>re-enabling the MC.
>
>May fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=57567
>https://bugs.freedesktop.org/show_bug.cgi?id=43655
>https://bugzilla.kernel.org/show_bug.cgi?id=56441
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Cc: stable@vger.kernel.org
>---
> drivers/gpu/drm/radeon/evergreen.c     |   47 +++++++++++++++++++++++++++++---
> drivers/gpu/drm/radeon/evergreen_reg.h |    2 +
> 2 files changed, 45 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
>index 497068a..f6c17b3 100644
>--- a/drivers/gpu/drm/radeon/evergreen.c
>+++ b/drivers/gpu/drm/radeon/evergreen.c
>@@ -1565,18 +1565,14 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
> 				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
> 					radeon_wait_for_vblank(rdev, i);
> 					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
>-					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> 					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
>-					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> 				}
> 			} else {
> 				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
> 				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
> 					radeon_wait_for_vblank(rdev, i);
> 					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
>-					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
> 					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
>-					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
> 				}
> 			}
> 			/* wait for the next frame */
>@@ -1605,6 +1601,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
> 	}
> 	/* wait for the MC to settle */
> 	udelay(100);
>+
>+	/* lock double buffered regs */
>+	for (i = 0; i < rdev->num_crtc; i++) {
>+		if (save->crtc_enabled[i]) {
>+			tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
>+			if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
>+				tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
>+				WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
>+			}
>+			tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
>+			if (!(tmp & 1)) {
>+				tmp |= 1;
>+				WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
>+			}
>+		}
>+	}
> }
> 
> void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
>@@ -1626,6 +1638,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
> 	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
> 	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
> 
>+	/* unlock regs and wait for update */
>+	for (i = 0; i < rdev->num_crtc; i++) {
>+		if (save->crtc_enabled[i]) {
>+			tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
>+			if ((tmp & 0x3) != 0) {
>+				tmp &= ~0x3;
>+				WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
>+			}
>+			tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
>+			if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
>+				tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
>+				WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
>+			}
>+			tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
>+			if (tmp & 1) {
>+				tmp &= ~1;
>+				WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
>+			}
>+			for (j = 0; j < rdev->usec_timeout; j++) {
>+				tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
>+				if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
>+					break;
>+				udelay(1);
>+			}
>+		}
>+	}
>+
> 	/* unblackout the MC */
> 	tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
> 	tmp &= ~BLACKOUT_MODE_MASK;
>diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
>index f585be1..881aba2 100644
>--- a/drivers/gpu/drm/radeon/evergreen_reg.h
>+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
>@@ -226,6 +226,8 @@
> #define EVERGREEN_CRTC_STATUS_HV_COUNT                  0x6ea0
> #define EVERGREEN_MASTER_UPDATE_MODE                    0x6ef8
> #define EVERGREEN_CRTC_UPDATE_LOCK                      0x6ed4
>+#define EVERGREEN_MASTER_UPDATE_LOCK                    0x6ef4
>+#define EVERGREEN_MASTER_UPDATE_MODE                    0x6ef8
> 
> #define EVERGREEN_DC_GPIO_HPD_MASK                      0x64b0
> #define EVERGREEN_DC_GPIO_HPD_A                         0x64b4
>-- 
>1.7.7.5
>

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