Attachment 80567 Details for Bug 65438 – xfce with RADEON_DUMP_SHADERS=1

xfce with RADEON_DUMP_SHADERS=1

xfce.log (text/plain), 327.39 KB, created by hadack on 2013-06-09 14:53:00 UTC

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Creator: hadack

Created: 2013-06-09 14:53:00 UTC

Size: 327.39 KB

patch

obsolete

>xauth:  file /home/hadack/.serverauth.25167 does not exist
>
>
>X.Org X Server 1.14.1
>Release Date: 2013-04-17
>X Protocol Version 11, Revision 0
>Build Operating System: Slackware 14.0 Slackware Linux Project
>Current Operating System: Linux schuttler 3.10.0-rc4 #1 SMP Sun Jun 2 17:10:20 CEST 2013 x86_64
>Kernel command line: BOOT_IMAGE=linux-test ro root=801 vt.default_utf8=1 1
>Build Date: 17 April 2013  07:39:13PM
> 
>Current version of pixman: 0.30.0
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Sun Jun  9 16:43:00 2013
>(==) Using config directory: "/etc/X11/xorg.conf.d"
>(==) Using system config directory "/usr/share/X11/xorg.conf.d"
>Initializing built-in extension Generic Event Extension
>Initializing built-in extension SHAPE
>Initializing built-in extension MIT-SHM
>Initializing built-in extension XInputExtension
>Initializing built-in extension XTEST
>Initializing built-in extension BIG-REQUESTS
>Initializing built-in extension SYNC
>Initializing built-in extension XKEYBOARD
>Initializing built-in extension XC-MISC
>Initializing built-in extension XINERAMA
>Initializing built-in extension XFIXES
>Initializing built-in extension RENDER
>Initializing built-in extension RANDR
>Initializing built-in extension COMPOSITE
>Initializing built-in extension DAMAGE
>Initializing built-in extension MIT-SCREEN-SAVER
>Initializing built-in extension DOUBLE-BUFFER
>Initializing built-in extension RECORD
>Initializing built-in extension DPMS
>Initializing built-in extension X-Resource
>Initializing built-in extension XVideo
>Initializing built-in extension XVideo-MotionCompensation
>Initializing built-in extension XFree86-VidModeExtension
>Initializing built-in extension XFree86-DGA
>Initializing built-in extension XFree86-DRI
>Initializing built-in extension DRI2
>Loading extension GLX
>(II) [KMS] Kernel modesetting enabled.
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0]
>  0: MOV OUT[0], CONST[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820100
>bf8c007f
>c2000503
>c2008502
>c2010501
>c2018500
>bf8c007f
>7e000203
>7e020202
>7e040201
>7e060200
>f800180f
>03020100
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800700
>bf8c007f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0]
>  0: MOV OUT[0], CONST[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800100
>bf8c007f
>c2020102
>c2028103
>bf8c007f
>7e000205
>d25e0000
>02020004
>c2020100
>c2000101
>bf8c007f
>7e020200
>d25e0001
>02020204
>f8001c0f
>00010001
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0..3]
>  0: MOV OUT[0], CONST[3]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800100
>bf8c007f
>c202010e
>c202810f
>bf8c007f
>7e000205
>d25e0000
>02020004
>c202010c
>c200010d
>bf8c007f
>7e020200
>d25e0001
>02020204
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = fmul float %30, %11
>  %35 = fmul float %30, %12
>  %36 = fmul float %30, %13
>  %37 = fmul float %30, %14
>  %38 = fmul float %31, %15
>  %39 = fadd float %38, %34
>  %40 = fmul float %31, %16
>  %41 = fadd float %40, %35
>  %42 = fmul float %31, %17
>  %43 = fadd float %42, %36
>  %44 = fmul float %31, %18
>  %45 = fadd float %44, %37
>  %46 = fmul float %32, %19
>  %47 = fadd float %46, %39
>  %48 = fmul float %32, %20
>  %49 = fadd float %48, %41
>  %50 = fmul float %32, %21
>  %51 = fadd float %50, %43
>  %52 = fmul float %32, %22
>  %53 = fadd float %52, %45
>  %54 = fmul float %33, %23
>  %55 = fadd float %54, %47
>  %56 = fmul float %33, %24
>  %57 = fadd float %56, %49
>  %58 = fmul float %33, %25
>  %59 = fadd float %58, %51
>  %60 = fmul float %33, %26
>  %61 = fadd float %60, %53
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] INT32 {0, 3, 1, 2}
>IMM[1] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: USEQ TEMP[0].x, CONST[1].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   USNE TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx
>  3:   USNE TEMP[1].x, CONST[0].xxxx, IMM[0].yyyy
>  4:   AND TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>  5:   UIF TEMP[0].xxxx :0
>  6:     MOV TEMP[0].w, IMM[1].xxxx
>  7:     MOV TEMP[1].xy, IN[0].xyyy
>  8:     TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
>  9:     MOV TEMP[0].xyz, TEMP[1].zyxz
> 10:     MOV TEMP[0], TEMP[0]
> 11:   ELSE :0
> 12:     MOV TEMP[1].w, IMM[1].xxxx
> 13:     MOV TEMP[2].xy, IN[0].xyyy
> 14:     TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
> 15:     MOV TEMP[1].xyz, TEMP[2].xyzx
> 16:     MOV TEMP[0], TEMP[1]
> 17:   ENDIF
> 18: ELSE :0
> 19:   USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].zzzz
> 20:   UIF TEMP[1].xxxx :0
> 21:     MOV TEMP[1].x, IMM[1].xxxx
> 22:     MOV TEMP[2].xy, IN[0].xyyy
> 23:     TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
> 24:     MOV TEMP[1].yzw, TEMP[2].yxyz
> 25:     MOV TEMP[0], TEMP[1]
> 26:   ELSE :0
> 27:     USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].xxxx
> 28:     UIF TEMP[1].xxxx :0
> 29:       MOV TEMP[1].x, IMM[1].xxxx
> 30:       MOV TEMP[2].xy, IN[0].xyyy
> 31:       TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
> 32:       MOV TEMP[1].yzw, TEMP[2].yzyx
> 33:       MOV TEMP[0], TEMP[1]
> 34:     ELSE :0
> 35:       USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].wwww
> 36:       UIF TEMP[1].xxxx :0
> 37:         MOV TEMP[1].w, IMM[1].xxxx
> 38:         MOV TEMP[2].xy, IN[0].xyyy
> 39:         TEX TEMP[2].yzw, TEMP[2], SAMP[0], 2D
> 40:         MOV TEMP[1].xyz, TEMP[2].yzwy
> 41:         MOV TEMP[0], TEMP[1]
> 42:       ELSE :0
> 43:         USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].yyyy
> 44:         UIF TEMP[1].xxxx :0
> 45:           MOV TEMP[1].w, IMM[1].xxxx
> 46:           MOV TEMP[2].xy, IN[0].xyyy
> 47:           TEX TEMP[2].yzw, TEMP[2], SAMP[0], 2D
> 48:           MOV TEMP[1].xyz, TEMP[2].wzyw
> 49:           MOV TEMP[0], TEMP[1]
> 50:         ENDIF
> 51:       ENDIF
> 52:     ENDIF
> 53:   ENDIF
> 54: ENDIF
> 55: MOV OUT[0], TEMP[0]
> 56: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = bitcast float %23 to i32
>  %31 = icmp eq i32 %30, 0
>  %32 = sext i1 %31 to i32
>  %33 = bitcast i32 %32 to float
>  %34 = bitcast float %33 to i32
>  %35 = icmp ne i32 %34, 0
>  %36 = bitcast float %22 to i32
>  br i1 %35, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %37 = icmp ne i32 %36, 0
>  %38 = sext i1 %37 to i32
>  %39 = bitcast i32 %38 to float
>  %40 = bitcast float %22 to i32
>  %41 = icmp ne i32 %40, 3
>  %42 = sext i1 %41 to i32
>  %43 = bitcast i32 %42 to float
>  %44 = bitcast float %39 to i32
>  %45 = bitcast float %43 to i32
>  %46 = and i32 %44, %45
>  %47 = bitcast i32 %46 to float
>  %48 = bitcast float %47 to i32
>  %49 = icmp ne i32 %48, 0
>  %50 = bitcast float %28 to i32
>  %51 = bitcast float %29 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %. = select i1 %49, float %57, float %55
>  %.27 = select i1 %49, float %55, float %57
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %58 = icmp eq i32 %36, 1
>  %59 = sext i1 %58 to i32
>  %60 = bitcast i32 %59 to float
>  %61 = bitcast float %60 to i32
>  %62 = icmp ne i32 %61, 0
>  br i1 %62, label %IF16, label %ELSE17
>
>ENDIF:                                            ; preds = %IF25, %ELSE23, %IF22, %IF19, %IF16, %IF
>  %temp.0 = phi float [ %., %IF ], [ 1.000000e+00, %IF16 ], [ 1.000000e+00, %IF19 ], [ %100, %IF22 ], [ %116, %IF25 ], [ %33, %ELSE23 ]
>  %temp1.0 = phi float [ %56, %IF ], [ %72, %IF16 ], [ %88, %IF19 ], [ %101, %IF22 ], [ %115, %IF25 ], [ 0.000000e+00, %ELSE23 ]
>  %temp2.0 = phi float [ %.27, %IF ], [ %73, %IF16 ], [ %87, %IF19 ], [ %102, %IF22 ], [ %114, %IF25 ], [ 0.000000e+00, %ELSE23 ]
>  %temp3.0 = phi float [ 1.000000e+00, %IF ], [ %74, %IF16 ], [ %86, %IF19 ], [ 1.000000e+00, %IF22 ], [ 1.000000e+00, %IF25 ], [ 0.000000e+00, %ELSE23 ]
>  %63 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0)
>  %64 = bitcast i32 %63 to float
>  %65 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0)
>  %66 = bitcast i32 %65 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %64, float %66, float %64, float %66)
>  ret void
>
>IF16:                                             ; preds = %ELSE
>  %67 = bitcast float %28 to i32
>  %68 = bitcast float %29 to i32
>  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
>  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
>  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  br label %ENDIF
>
>ELSE17:                                           ; preds = %ELSE
>  %75 = bitcast float %22 to i32
>  %76 = icmp eq i32 %75, 0
>  %77 = sext i1 %76 to i32
>  %78 = bitcast i32 %77 to float
>  %79 = bitcast float %78 to i32
>  %80 = icmp ne i32 %79, 0
>  br i1 %80, label %IF19, label %ELSE20
>
>IF19:                                             ; preds = %ELSE17
>  %81 = bitcast float %28 to i32
>  %82 = bitcast float %29 to i32
>  %83 = insertelement <2 x i32> undef, i32 %81, i32 0
>  %84 = insertelement <2 x i32> %83, i32 %82, i32 1
>  %85 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %84, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %86 = extractelement <4 x float> %85, i32 0
>  %87 = extractelement <4 x float> %85, i32 1
>  %88 = extractelement <4 x float> %85, i32 2
>  br label %ENDIF
>
>ELSE20:                                           ; preds = %ELSE17
>  %89 = bitcast float %22 to i32
>  %90 = icmp eq i32 %89, 2
>  %91 = sext i1 %90 to i32
>  %92 = bitcast i32 %91 to float
>  %93 = bitcast float %92 to i32
>  %94 = icmp ne i32 %93, 0
>  br i1 %94, label %IF22, label %ELSE23
>
>IF22:                                             ; preds = %ELSE20
>  %95 = bitcast float %28 to i32
>  %96 = bitcast float %29 to i32
>  %97 = insertelement <2 x i32> undef, i32 %95, i32 0
>  %98 = insertelement <2 x i32> %97, i32 %96, i32 1
>  %99 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %98, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %100 = extractelement <4 x float> %99, i32 1
>  %101 = extractelement <4 x float> %99, i32 2
>  %102 = extractelement <4 x float> %99, i32 3
>  br label %ENDIF
>
>ELSE23:                                           ; preds = %ELSE20
>  %103 = bitcast float %22 to i32
>  %104 = icmp eq i32 %103, 3
>  %105 = sext i1 %104 to i32
>  %106 = bitcast i32 %105 to float
>  %107 = bitcast float %106 to i32
>  %108 = icmp ne i32 %107, 0
>  br i1 %108, label %IF25, label %ENDIF
>
>IF25:                                             ; preds = %ELSE23
>  %109 = bitcast float %28 to i32
>  %110 = bitcast float %29 to i32
>  %111 = insertelement <2 x i32> undef, i32 %109, i32 0
>  %112 = insertelement <2 x i32> %111, i32 %110, i32 1
>  %113 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %112, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %114 = extractelement <4 x float> %113, i32 1
>  %115 = extractelement <4 x float> %113, i32 2
>  %116 = extractelement <4 x float> %113, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c0820100
>bf8c007f
>c2010500
>c2000504
>bf8c007f
>d1040000
>02010000
>d2000007
>00018280
>d1040000
>02010107
>7e000202
>7e020202
>be802400
>8980007e
>bf880042
>d1040002
>02010300
>d2000014
>00098280
>d1040002
>02010114
>be822402
>8982027e
>bf880030
>d1040004
>02010101
>d2000014
>00118280
>d1040004
>02010114
>be842404
>8984047e
>bf88001f
>d1040006
>02010501
>d2000014
>00198280
>d1040006
>02010114
>be862406
>8986067e
>bf88000e
>d1040014
>02010701
>7e140280
>7e12030a
>7e18030a
>be942414
>8994147e
>f0800e00
>00430b02
>bf8c0770
>7e1402f2
>7e12030b
>7e0e030d
>88fe147e
>be862506
>89fe067e
>f0800e00
>00430702
>bf8c0770
>7e1402f2
>7e180308
>88fe067e
>be842504
>89fe047e
>f0800700
>00430a02
>bf8c0770
>7e0e02f2
>7e12030b
>88fe047e
>be822502
>bf8c070f
>89fe027e
>f0800700
>00430802
>bf8c0770
>7e0e02f2
>7e180308
>88fe027e
>be802500
>89fe007e
>d10a0002
>02010701
>d10a0004
>02010100
>87820204
>f0800700
>00430b02
>bf8c0770
>d2000009
>000a170d
>d2000007
>000a1b0b
>7e1402f2
>88fe007e
>5e001509
>5e021907
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0]
>DCL CONST[2]
>DCL CONST[4..5]
>DCL TEMP[0..9], LOCAL
>IMM[0] INT32 {10, -10, 0, 1}
>IMM[1] UINT32 {4294967295, 0, 0, 0}
>IMM[2] INT32 {2, 3, 0, 0}
>IMM[3] FLT32 {    1.0000,     0.5000,     0.0000,     2.0000}
>IMM[4] FLT32 {    0.0010,     0.0000,     0.0000,     0.0000}
>  0: ISLT TEMP[0].x, CONST[5].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   MOV TEMP[0].xy, IN[0].zwww
>  3:   TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  4:   MOV TEMP[0], TEMP[0]
>  5: ELSE :0
>  6:   MOV TEMP[1].x, IMM[1].xxxx
>  7:   UADD TEMP[2].x, CONST[5].xxxx, IMM[0].yyyy
>  8:   MUL TEMP[3].xy, IN[0].zwww, CONST[2].xyyy
>  9:   MOV TEMP[4].xy, TEMP[3].xyxx
> 10:   USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].zzzz
> 11:   UIF TEMP[5].xxxx :0
> 12:     MOV TEMP[5].xy, TEMP[3].xyxx
> 13:   ELSE :0
> 14:     USEQ TEMP[6].x, TEMP[2].xxxx, IMM[0].wwww
> 15:     UIF TEMP[6].xxxx :0
> 16:       FRC TEMP[6].xy, TEMP[3].xyyy
> 17:       RCP TEMP[7].x, CONST[2].xxxx
> 18:       RCP TEMP[7].y, CONST[2].yyyy
> 19:       FLR TEMP[3].xy, TEMP[3].xyyy
> 20:       MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[3].xyyy
> 21:     ELSE :0
> 22:       USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].xxxx
> 23:       UIF TEMP[3].xxxx :0
> 24:         SGE TEMP[3].x, TEMP[4].xxxx, IMM[3].xxxx
> 25:         F2I TEMP[3].x, -TEMP[3]
> 26:         UIF TEMP[3].xxxx :0
> 27:           MUL TEMP[3].x, CONST[2].zzzz, CONST[2].xxxx
> 28:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 29:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[3].xxxx
> 30:         ELSE :0
> 31:           SLT TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz
> 32:           F2I TEMP[3].x, -TEMP[3]
> 33:           UIF TEMP[3].xxxx :0
> 34:             MOV TEMP[4].x, IMM[3].zzzz
> 35:           ENDIF
> 36:         ENDIF
> 37:         SGE TEMP[3].x, TEMP[4].yyyy, IMM[3].xxxx
> 38:         F2I TEMP[3].x, -TEMP[3]
> 39:         UIF TEMP[3].xxxx :0
> 40:           MUL TEMP[3].x, CONST[2].wwww, CONST[2].yyyy
> 41:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 42:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 43:           MOV TEMP[4].y, TEMP[3].xxxx
> 44:         ELSE :0
> 45:           SLT TEMP[3].x, TEMP[4].yyyy, IMM[3].zzzz
> 46:           F2I TEMP[3].x, -TEMP[3]
> 47:           UIF TEMP[3].xxxx :0
> 48:             MOV TEMP[4].y, IMM[3].zzzz
> 49:           ENDIF
> 50:         ENDIF
> 51:         RCP TEMP[3].x, CONST[2].xxxx
> 52:         RCP TEMP[3].y, CONST[2].yyyy
> 53:         MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[3].xyyy
> 54:       ELSE :0
> 55:         USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].yyyy
> 56:         UIF TEMP[3].xxxx :0
> 57:           FLR TEMP[3].x, TEMP[4].xxxx
> 58:           ABS TEMP[3].x, TEMP[3].xxxx
> 59:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 60:           FRC TEMP[3].x, TEMP[3].xxxx
> 61:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 62:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 63:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 64:           F2I TEMP[3].x, -TEMP[3]
> 65:           UIF TEMP[3].xxxx :0
> 66:             FRC TEMP[3].x, TEMP[4].xxxx
> 67:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 68:             RCP TEMP[6].x, CONST[2].xxxx
> 69:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 70:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[3].xxxx
> 71:           ELSE :0
> 72:             FRC TEMP[3].x, TEMP[4].xxxx
> 73:             RCP TEMP[6].x, CONST[2].xxxx
> 74:             MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx
> 75:           ENDIF
> 76:           FLR TEMP[3].x, TEMP[4].yyyy
> 77:           ABS TEMP[3].x, TEMP[3].xxxx
> 78:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 79:           FRC TEMP[3].x, TEMP[3].xxxx
> 80:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 81:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 82:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 83:           F2I TEMP[3].x, -TEMP[3]
> 84:           UIF TEMP[3].xxxx :0
> 85:             FRC TEMP[3].x, TEMP[4].yyyy
> 86:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 87:             RCP TEMP[6].x, CONST[2].yyyy
> 88:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 89:             ADD TEMP[3].x, IMM[3].wwww, -TEMP[3].xxxx
> 90:             MOV TEMP[4].y, TEMP[3].xxxx
> 91:           ELSE :0
> 92:             FRC TEMP[3].x, TEMP[4].yyyy
> 93:             RCP TEMP[6].x, CONST[2].yyyy
> 94:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 95:             MOV TEMP[4].y, TEMP[3].xxxx
> 96:           ENDIF
> 97:         ENDIF
> 98:       ENDIF
> 99:     ENDIF
>100:     MOV TEMP[5].xy, TEMP[4].xyxx
>101:   ENDIF
>102:   MOV TEMP[2].xy, TEMP[5].xyxx
>103:   USEQ TEMP[3].x, CONST[5].xxxx, IMM[0].xxxx
>104:   UIF TEMP[3].xxxx :0
>105:     SGE TEMP[3].x, TEMP[5].xxxx, IMM[3].zzzz
>106:     F2I TEMP[3].x, -TEMP[3]
>107:     SLT TEMP[4].x, TEMP[5].xxxx, IMM[3].xxxx
>108:     F2I TEMP[4].x, -TEMP[4]
>109:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>110:     SGE TEMP[4].x, TEMP[5].yyyy, IMM[3].zzzz
>111:     F2I TEMP[4].x, -TEMP[4]
>112:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>113:     SLT TEMP[4].x, TEMP[5].yyyy, IMM[3].xxxx
>114:     F2I TEMP[4].x, -TEMP[4]
>115:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>116:     NOT TEMP[3].x, TEMP[3].xxxx
>117:     UIF TEMP[3].xxxx :0
>118:       MOV TEMP[3].xyz, IMM[3].zzzz
>119:       MOV TEMP[3].w, IMM[3].zzzz
>120:       MOV TEMP[3], TEMP[3]
>121:       MOV TEMP[1].x, IMM[1].yyyy
>122:     ELSE :0
>123:       FRC TEMP[4].xy, TEMP[5].xyyy
>124:       RCP TEMP[5].x, CONST[2].xxxx
>125:       RCP TEMP[5].y, CONST[2].yyyy
>126:       MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy
>127:     ENDIF
>128:   ENDIF
>129:   UIF TEMP[1].xxxx :0
>130:     MOV TEMP[2].xy, TEMP[2].xyyy
>131:     TEX TEMP[2], TEMP[2], SAMP[1], 2D
>132:     MOV TEMP[3], TEMP[2]
>133:   ENDIF
>134:   MOV TEMP[0], TEMP[3]
>135: ENDIF
>136: ISLT TEMP[2].x, CONST[4].xxxx, IMM[0].xxxx
>137: UIF TEMP[2].xxxx :0
>138:   MOV TEMP[2].xy, IN[0].xyyy
>139:   TEX TEMP[2], TEMP[2], SAMP[0], 2D
>140:   MOV TEMP[2].w, TEMP[2]
>141: ELSE :0
>142:   MOV TEMP[3].x, IMM[1].xxxx
>143:   UADD TEMP[4].x, CONST[4].xxxx, IMM[0].yyyy
>144:   MUL TEMP[5].xy, IN[0].xyyy, CONST[0].xyyy
>145:   MOV TEMP[6].xy, TEMP[5].xyxx
>146:   USEQ TEMP[7].x, TEMP[4].xxxx, IMM[0].zzzz
>147:   UIF TEMP[7].xxxx :0
>148:     MOV TEMP[7].xy, TEMP[5].xyxx
>149:   ELSE :0
>150:     USEQ TEMP[8].x, TEMP[4].xxxx, IMM[0].wwww
>151:     UIF TEMP[8].xxxx :0
>152:       FRC TEMP[8].xy, TEMP[5].xyyy
>153:       RCP TEMP[9].x, CONST[0].xxxx
>154:       RCP TEMP[9].y, CONST[0].yyyy
>155:       FLR TEMP[5].xy, TEMP[5].xyyy
>156:       MAD TEMP[6].xy, TEMP[8].xyyy, TEMP[9].xyyy, TEMP[5].xyyy
>157:     ELSE :0
>158:       USEQ TEMP[5].x, TEMP[4].xxxx, IMM[2].xxxx
>159:       UIF TEMP[5].xxxx :0
>160:         SGE TEMP[5].x, TEMP[6].xxxx, IMM[3].xxxx
>161:         F2I TEMP[5].x, -TEMP[5]
>162:         UIF TEMP[5].xxxx :0
>163:           MUL TEMP[5].x, CONST[0].zzzz, CONST[0].xxxx
>164:           MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy
>165:           ADD TEMP[6].x, IMM[3].xxxx, -TEMP[5].xxxx
>166:         ELSE :0
>167:           SLT TEMP[5].x, TEMP[6].xxxx, IMM[3].zzzz
>168:           F2I TEMP[5].x, -TEMP[5]
>169:           UIF TEMP[5].xxxx :0
>170:             MOV TEMP[6].x, IMM[3].zzzz
>171:           ENDIF
>172:         ENDIF
>173:         SGE TEMP[5].x, TEMP[6].yyyy, IMM[3].xxxx
>174:         F2I TEMP[5].x, -TEMP[5]
>175:         UIF TEMP[5].xxxx :0
>176:           MUL TEMP[5].x, CONST[0].wwww, CONST[0].yyyy
>177:           MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].yyyy
>178:           ADD TEMP[5].x, IMM[3].xxxx, -TEMP[5].xxxx
>179:           MOV TEMP[6].y, TEMP[5].xxxx
>180:         ELSE :0
>181:           SLT TEMP[5].x, TEMP[6].yyyy, IMM[3].zzzz
>182:           F2I TEMP[5].x, -TEMP[5]
>183:           UIF TEMP[5].xxxx :0
>184:             MOV TEMP[6].y, IMM[3].zzzz
>185:           ENDIF
>186:         ENDIF
>187:         RCP TEMP[5].x, CONST[0].xxxx
>188:         RCP TEMP[5].y, CONST[0].yyyy
>189:         MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[5].xyyy
>190:       ELSE :0
>191:         USEQ TEMP[4].x, TEMP[4].xxxx, IMM[2].yyyy
>192:         UIF TEMP[4].xxxx :0
>193:           FLR TEMP[4].x, TEMP[6].xxxx
>194:           ABS TEMP[4].x, TEMP[4].xxxx
>195:           MUL TEMP[4].x, TEMP[4].xxxx, IMM[3].yyyy
>196:           FRC TEMP[4].x, TEMP[4].xxxx
>197:           MUL TEMP[4].x, IMM[3].wwww, TEMP[4].xxxx
>198:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx
>199:           SLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx
>200:           F2I TEMP[4].x, -TEMP[4]
>201:           UIF TEMP[4].xxxx :0
>202:             FRC TEMP[4].x, TEMP[6].xxxx
>203:             ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx
>204:             RCP TEMP[5].x, CONST[0].xxxx
>205:             MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>206:             ADD TEMP[6].x, IMM[3].wwww, -TEMP[4].xxxx
>207:           ELSE :0
>208:             FRC TEMP[4].x, TEMP[6].xxxx
>209:             RCP TEMP[5].x, CONST[0].xxxx
>210:             MUL TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx
>211:           ENDIF
>212:           FLR TEMP[4].x, TEMP[6].yyyy
>213:           ABS TEMP[4].x, TEMP[4].xxxx
>214:           MUL TEMP[4].x, TEMP[4].xxxx, IMM[3].yyyy
>215:           FRC TEMP[4].x, TEMP[4].xxxx
>216:           MUL TEMP[4].x, IMM[3].wwww, TEMP[4].xxxx
>217:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx
>218:           SLT TEMP[4].x, TEMP[4].xxxx, IMM[4].xxxx
>219:           F2I TEMP[4].x, -TEMP[4]
>220:           UIF TEMP[4].xxxx :0
>221:             FRC TEMP[4].x, TEMP[6].yyyy
>222:             ADD TEMP[4].x, IMM[3].xxxx, -TEMP[4].xxxx
>223:             RCP TEMP[5].x, CONST[0].yyyy
>224:             MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>225:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[4].xxxx
>226:             MOV TEMP[6].y, TEMP[4].xxxx
>227:           ELSE :0
>228:             FRC TEMP[4].x, TEMP[6].yyyy
>229:             RCP TEMP[5].x, CONST[0].yyyy
>230:             MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>231:             MOV TEMP[6].y, TEMP[4].xxxx
>232:           ENDIF
>233:         ENDIF
>234:       ENDIF
>235:     ENDIF
>236:     MOV TEMP[7].xy, TEMP[6].xyxx
>237:   ENDIF
>238:   MOV TEMP[1].xy, TEMP[7].xyxx
>239:   USEQ TEMP[4].x, CONST[4].xxxx, IMM[0].xxxx
>240:   UIF TEMP[4].xxxx :0
>241:     SGE TEMP[4].x, TEMP[7].xxxx, IMM[3].zzzz
>242:     F2I TEMP[4].x, -TEMP[4]
>243:     SLT TEMP[5].x, TEMP[7].xxxx, IMM[3].xxxx
>244:     F2I TEMP[5].x, -TEMP[5]
>245:     AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>246:     SGE TEMP[5].x, TEMP[7].yyyy, IMM[3].zzzz
>247:     F2I TEMP[5].x, -TEMP[5]
>248:     AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>249:     SLT TEMP[5].x, TEMP[7].yyyy, IMM[3].xxxx
>250:     F2I TEMP[5].x, -TEMP[5]
>251:     AND TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx
>252:     NOT TEMP[4].x, TEMP[4].xxxx
>253:     UIF TEMP[4].xxxx :0
>254:       MOV TEMP[4].xyz, IMM[3].zzzz
>255:       MOV TEMP[4].w, IMM[3].zzzz
>256:       MOV TEMP[4], TEMP[4]
>257:       MOV TEMP[3].x, IMM[1].yyyy
>258:     ELSE :0
>259:       FRC TEMP[5].xy, TEMP[7].xyyy
>260:       RCP TEMP[6].x, CONST[0].xxxx
>261:       RCP TEMP[6].y, CONST[0].yyyy
>262:       MUL TEMP[1].xy, TEMP[5].xyyy, TEMP[6].xyyy
>263:     ENDIF
>264:   ENDIF
>265:   UIF TEMP[3].xxxx :0
>266:     MOV TEMP[1].xy, TEMP[1].xyyy
>267:     TEX TEMP[1], TEMP[1], SAMP[0], 2D
>268:     MOV TEMP[4], TEMP[1]
>269:   ENDIF
>270:   MOV TEMP[2].w, TEMP[4]
>271: ENDIF
>272: MUL TEMP[0], TEMP[0], TEMP[2].wwww
>273: MOV OUT[0], TEMP[0]
>274: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %32 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
>  %38 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %43 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %44 = bitcast float %31 to i32
>  %45 = icmp slt i32 %44, 10
>  %46 = sext i1 %45 to i32
>  %47 = bitcast i32 %46 to float
>  %48 = bitcast float %47 to i32
>  %49 = icmp ne i32 %48, 0
>  br i1 %49, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %50 = bitcast float %42 to i32
>  %51 = bitcast float %43 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %37, <16 x i8> %39, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %59 = bitcast float %31 to i32
>  %60 = add i32 %59, -10
>  %61 = bitcast i32 %60 to float
>  %62 = fmul float %42, %26
>  %63 = fmul float %43, %27
>  %64 = bitcast float %61 to i32
>  %65 = icmp eq i32 %64, 0
>  %66 = sext i1 %65 to i32
>  %67 = bitcast i32 %66 to float
>  %68 = bitcast float %67 to i32
>  %69 = icmp ne i32 %68, 0
>  br i1 %69, label %ENDIF40, label %ELSE42
>
>ENDIF:                                            ; preds = %IF77, %ENDIF70, %IF
>  %temp3.0 = phi float [ %58, %IF ], [ %249, %IF77 ], [ 0.000000e+00, %ENDIF70 ]
>  %temp2.0 = phi float [ %57, %IF ], [ %248, %IF77 ], [ 0.000000e+00, %ENDIF70 ]
>  %temp1.0 = phi float [ %56, %IF ], [ %247, %IF77 ], [ %temp13.3, %ENDIF70 ]
>  %temp.0 = phi float [ %55, %IF ], [ %246, %IF77 ], [ %temp12.0, %ENDIF70 ]
>  %70 = bitcast float %30 to i32
>  %71 = icmp slt i32 %70, 10
>  %72 = sext i1 %71 to i32
>  %73 = bitcast i32 %72 to float
>  %74 = bitcast float %73 to i32
>  %75 = icmp ne i32 %74, 0
>  br i1 %75, label %IF80, label %ELSE81
>
>ELSE42:                                           ; preds = %ELSE
>  %76 = bitcast float %61 to i32
>  %77 = icmp eq i32 %76, 1
>  %78 = sext i1 %77 to i32
>  %79 = bitcast i32 %78 to float
>  %80 = bitcast float %79 to i32
>  %81 = icmp ne i32 %80, 0
>  br i1 %81, label %IF44, label %ELSE45
>
>ENDIF40:                                          ; preds = %IF68, %ELSE69, %ELSE48, %ENDIF55, %IF44, %ELSE
>  %temp13.0 = phi float [ %63, %ELSE ], [ %93, %IF44 ], [ %147, %ENDIF55 ], [ %63, %ELSE48 ], [ %63, %ELSE69 ], [ %63, %IF68 ]
>  %temp20.0 = phi float [ %62, %ELSE ], [ %95, %IF44 ], [ %148, %ENDIF55 ], [ %62, %ELSE48 ], [ %temp16.5, %ELSE69 ], [ %temp16.5, %IF68 ]
>  %temp21.0 = phi float [ %63, %ELSE ], [ %97, %IF44 ], [ %149, %ENDIF55 ], [ %63, %ELSE48 ], [ %193, %IF68 ], [ %195, %ELSE69 ]
>  %82 = bitcast float %31 to i32
>  %83 = icmp eq i32 %82, 10
>  %84 = sext i1 %83 to i32
>  %85 = bitcast i32 %84 to float
>  %86 = bitcast float %85 to i32
>  %87 = icmp ne i32 %86, 0
>  br i1 %87, label %IF71, label %ENDIF70
>
>IF44:                                             ; preds = %ELSE42
>  %88 = call float @llvm.AMDIL.fraction.(float %62)
>  %89 = call float @llvm.AMDIL.fraction.(float %63)
>  %90 = fdiv float 1.000000e+00, %26
>  %91 = fdiv float 1.000000e+00, %27
>  %92 = call float @floor(float %62)
>  %93 = call float @floor(float %63)
>  %94 = fmul float %88, %90
>  %95 = fadd float %94, %92
>  %96 = fmul float %89, %91
>  %97 = fadd float %96, %93
>  br label %ENDIF40
>
>ELSE45:                                           ; preds = %ELSE42
>  %98 = bitcast float %61 to i32
>  %99 = icmp eq i32 %98, 2
>  %100 = sext i1 %99 to i32
>  %101 = bitcast i32 %100 to float
>  %102 = bitcast float %101 to i32
>  %103 = icmp ne i32 %102, 0
>  br i1 %103, label %IF47, label %ELSE48
>
>IF47:                                             ; preds = %ELSE45
>  %104 = fcmp uge float %62, 1.000000e+00
>  %105 = select i1 %104, float 1.000000e+00, float 0.000000e+00
>  %106 = fsub float -0.000000e+00, %105
>  %107 = fptosi float %106 to i32
>  %108 = bitcast i32 %107 to float
>  %109 = bitcast float %108 to i32
>  %110 = icmp ne i32 %109, 0
>  br i1 %110, label %IF50, label %ELSE51
>
>ELSE48:                                           ; preds = %ELSE45
>  %111 = bitcast float %61 to i32
>  %112 = icmp eq i32 %111, 3
>  %113 = sext i1 %112 to i32
>  %114 = bitcast i32 %113 to float
>  %115 = bitcast float %114 to i32
>  %116 = icmp ne i32 %115, 0
>  br i1 %116, label %IF62, label %ENDIF40
>
>IF50:                                             ; preds = %IF47
>  %117 = fmul float %28, %26
>  %118 = fmul float %117, 5.000000e-01
>  %119 = fsub float -0.000000e+00, %118
>  %120 = fadd float 1.000000e+00, %119
>  br label %ENDIF49
>
>ELSE51:                                           ; preds = %IF47
>  %121 = fcmp ult float %62, 0.000000e+00
>  %122 = select i1 %121, float 1.000000e+00, float 0.000000e+00
>  %123 = fsub float -0.000000e+00, %122
>  %124 = fptosi float %123 to i32
>  %125 = bitcast i32 %124 to float
>  %126 = bitcast float %125 to i32
>  %127 = icmp ne i32 %126, 0
>  %. = select i1 %127, float 0.000000e+00, float %62
>  br label %ENDIF49
>
>ENDIF49:                                          ; preds = %ELSE51, %IF50
>  %temp16.2 = phi float [ %120, %IF50 ], [ %., %ELSE51 ]
>  %128 = fcmp uge float %63, 1.000000e+00
>  %129 = select i1 %128, float 1.000000e+00, float 0.000000e+00
>  %130 = fsub float -0.000000e+00, %129
>  %131 = fptosi float %130 to i32
>  %132 = bitcast i32 %131 to float
>  %133 = bitcast float %132 to i32
>  %134 = icmp ne i32 %133, 0
>  br i1 %134, label %IF56, label %ELSE57
>
>IF56:                                             ; preds = %ENDIF49
>  %135 = fmul float %29, %27
>  %136 = fmul float %135, 5.000000e-01
>  %137 = fsub float -0.000000e+00, %136
>  %138 = fadd float 1.000000e+00, %137
>  br label %ENDIF55
>
>ELSE57:                                           ; preds = %ENDIF49
>  %139 = fcmp ult float %63, 0.000000e+00
>  %140 = select i1 %139, float 1.000000e+00, float 0.000000e+00
>  %141 = fsub float -0.000000e+00, %140
>  %142 = fptosi float %141 to i32
>  %143 = bitcast i32 %142 to float
>  %144 = bitcast float %143 to i32
>  %145 = icmp ne i32 %144, 0
>  %.121 = select i1 %145, float 0.000000e+00, float %63
>  br label %ENDIF55
>
>ENDIF55:                                          ; preds = %ELSE57, %IF56
>  %temp17.2 = phi float [ %138, %IF56 ], [ %.121, %ELSE57 ]
>  %146 = fdiv float 1.000000e+00, %26
>  %147 = fdiv float 1.000000e+00, %27
>  %148 = fmul float %temp16.2, %146
>  %149 = fmul float %temp17.2, %147
>  br label %ENDIF40
>
>IF62:                                             ; preds = %ELSE48
>  %150 = call float @floor(float %62)
>  %151 = call float @fabs(float %150)
>  %152 = fmul float %151, 5.000000e-01
>  %153 = call float @llvm.AMDIL.fraction.(float %152)
>  %154 = fmul float 2.000000e+00, %153
>  %155 = fsub float -0.000000e+00, %154
>  %156 = fadd float 1.000000e+00, %155
>  %157 = fcmp ult float %156, 0x3F50624DE0000000
>  %158 = select i1 %157, float 1.000000e+00, float 0.000000e+00
>  %159 = fsub float -0.000000e+00, %158
>  %160 = fptosi float %159 to i32
>  %161 = bitcast i32 %160 to float
>  %162 = bitcast float %161 to i32
>  %163 = icmp ne i32 %162, 0
>  %164 = call float @llvm.AMDIL.fraction.(float %62)
>  br i1 %163, label %IF65, label %ELSE66
>
>IF65:                                             ; preds = %IF62
>  %165 = fsub float -0.000000e+00, %164
>  %166 = fadd float 1.000000e+00, %165
>  %167 = fdiv float 1.000000e+00, %26
>  %168 = fmul float %166, %167
>  %169 = fsub float -0.000000e+00, %168
>  %170 = fadd float 2.000000e+00, %169
>  br label %ENDIF64
>
>ELSE66:                                           ; preds = %IF62
>  %171 = fdiv float 1.000000e+00, %26
>  %172 = fmul float %164, %171
>  br label %ENDIF64
>
>ENDIF64:                                          ; preds = %ELSE66, %IF65
>  %temp16.5 = phi float [ %170, %IF65 ], [ %172, %ELSE66 ]
>  %173 = call float @floor(float %63)
>  %174 = call float @fabs(float %173)
>  %175 = fmul float %174, 5.000000e-01
>  %176 = call float @llvm.AMDIL.fraction.(float %175)
>  %177 = fmul float 2.000000e+00, %176
>  %178 = fsub float -0.000000e+00, %177
>  %179 = fadd float 1.000000e+00, %178
>  %180 = fcmp ult float %179, 0x3F50624DE0000000
>  %181 = select i1 %180, float 1.000000e+00, float 0.000000e+00
>  %182 = fsub float -0.000000e+00, %181
>  %183 = fptosi float %182 to i32
>  %184 = bitcast i32 %183 to float
>  %185 = bitcast float %184 to i32
>  %186 = icmp ne i32 %185, 0
>  %187 = call float @llvm.AMDIL.fraction.(float %63)
>  br i1 %186, label %IF68, label %ELSE69
>
>IF68:                                             ; preds = %ENDIF64
>  %188 = fsub float -0.000000e+00, %187
>  %189 = fadd float 1.000000e+00, %188
>  %190 = fdiv float 1.000000e+00, %27
>  %191 = fmul float %189, %190
>  %192 = fsub float -0.000000e+00, %191
>  %193 = fadd float 2.000000e+00, %192
>  br label %ENDIF40
>
>ELSE69:                                           ; preds = %ENDIF64
>  %194 = fdiv float 1.000000e+00, %27
>  %195 = fmul float %187, %194
>  br label %ENDIF40
>
>IF71:                                             ; preds = %ENDIF40
>  %196 = fcmp uge float %temp20.0, 0.000000e+00
>  %197 = select i1 %196, float 1.000000e+00, float 0.000000e+00
>  %198 = fsub float -0.000000e+00, %197
>  %199 = fptosi float %198 to i32
>  %200 = bitcast i32 %199 to float
>  %201 = fcmp ult float %temp20.0, 1.000000e+00
>  %202 = select i1 %201, float 1.000000e+00, float 0.000000e+00
>  %203 = fsub float -0.000000e+00, %202
>  %204 = fptosi float %203 to i32
>  %205 = bitcast i32 %204 to float
>  %206 = bitcast float %200 to i32
>  %207 = bitcast float %205 to i32
>  %208 = and i32 %206, %207
>  %209 = bitcast i32 %208 to float
>  %210 = fcmp uge float %temp21.0, 0.000000e+00
>  %211 = select i1 %210, float 1.000000e+00, float 0.000000e+00
>  %212 = fsub float -0.000000e+00, %211
>  %213 = fptosi float %212 to i32
>  %214 = bitcast i32 %213 to float
>  %215 = bitcast float %209 to i32
>  %216 = bitcast float %214 to i32
>  %217 = and i32 %215, %216
>  %218 = bitcast i32 %217 to float
>  %219 = fcmp ult float %temp21.0, 1.000000e+00
>  %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00
>  %221 = fsub float -0.000000e+00, %220
>  %222 = fptosi float %221 to i32
>  %223 = bitcast i32 %222 to float
>  %224 = bitcast float %218 to i32
>  %225 = bitcast float %223 to i32
>  %226 = and i32 %224, %225
>  %227 = bitcast i32 %226 to float
>  %228 = bitcast float %227 to i32
>  %229 = xor i32 %228, -1
>  %230 = bitcast i32 %229 to float
>  %231 = bitcast float %230 to i32
>  %232 = icmp ne i32 %231, 0
>  br i1 %232, label %ENDIF70, label %ELSE75
>
>ENDIF70:                                          ; preds = %ELSE75, %IF71, %ENDIF40
>  %temp8.0 = phi float [ %temp20.0, %ENDIF40 ], [ %239, %ELSE75 ], [ %temp20.0, %IF71 ]
>  %temp9.0 = phi float [ %temp21.0, %ENDIF40 ], [ %240, %ELSE75 ], [ %temp21.0, %IF71 ]
>  %temp12.0 = phi float [ %85, %ENDIF40 ], [ %230, %ELSE75 ], [ 0.000000e+00, %IF71 ]
>  %temp13.3 = phi float [ %temp13.0, %ENDIF40 ], [ %temp13.0, %ELSE75 ], [ 0.000000e+00, %IF71 ]
>  %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF40 ], [ 0xFFFFFFFFE0000000, %ELSE75 ], [ 0.000000e+00, %IF71 ]
>  %233 = bitcast float %temp4.0 to i32
>  %234 = icmp ne i32 %233, 0
>  br i1 %234, label %IF77, label %ENDIF
>
>ELSE75:                                           ; preds = %IF71
>  %235 = call float @llvm.AMDIL.fraction.(float %temp20.0)
>  %236 = call float @llvm.AMDIL.fraction.(float %temp21.0)
>  %237 = fdiv float 1.000000e+00, %26
>  %238 = fdiv float 1.000000e+00, %27
>  %239 = fmul float %235, %237
>  %240 = fmul float %236, %238
>  br label %ENDIF70
>
>IF77:                                             ; preds = %ENDIF70
>  %241 = bitcast float %temp8.0 to i32
>  %242 = bitcast float %temp9.0 to i32
>  %243 = insertelement <2 x i32> undef, i32 %241, i32 0
>  %244 = insertelement <2 x i32> %243, i32 %242, i32 1
>  %245 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %244, <32 x i8> %37, <16 x i8> %39, i32 2)
>  %246 = extractelement <4 x float> %245, i32 0
>  %247 = extractelement <4 x float> %245, i32 1
>  %248 = extractelement <4 x float> %245, i32 2
>  %249 = extractelement <4 x float> %245, i32 3
>  br label %ENDIF
>
>IF80:                                             ; preds = %ENDIF
>  %250 = bitcast float %40 to i32
>  %251 = bitcast float %41 to i32
>  %252 = insertelement <2 x i32> undef, i32 %250, i32 0
>  %253 = insertelement <2 x i32> %252, i32 %251, i32 1
>  %254 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %253, <32 x i8> %33, <16 x i8> %35, i32 2)
>  %255 = extractelement <4 x float> %254, i32 3
>  br label %ENDIF79
>
>ELSE81:                                           ; preds = %ENDIF
>  %256 = bitcast float %30 to i32
>  %257 = add i32 %256, -10
>  %258 = bitcast i32 %257 to float
>  %259 = fmul float %40, %22
>  %260 = fmul float %41, %23
>  %261 = bitcast float %258 to i32
>  %262 = icmp eq i32 %261, 0
>  %263 = sext i1 %262 to i32
>  %264 = bitcast i32 %263 to float
>  %265 = bitcast float %264 to i32
>  %266 = icmp ne i32 %265, 0
>  br i1 %266, label %ENDIF82, label %ELSE84
>
>ENDIF79:                                          ; preds = %IF119, %ENDIF112, %IF80
>  %temp11.2 = phi float [ %255, %IF80 ], [ %445, %IF119 ], [ 0.000000e+00, %ENDIF112 ]
>  %267 = fmul float %temp.0, %temp11.2
>  %268 = fmul float %temp1.0, %temp11.2
>  %269 = fmul float %temp2.0, %temp11.2
>  %270 = fmul float %temp3.0, %temp11.2
>  %271 = call i32 @llvm.SI.packf16(float %267, float %268)
>  %272 = bitcast i32 %271 to float
>  %273 = call i32 @llvm.SI.packf16(float %269, float %270)
>  %274 = bitcast i32 %273 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %272, float %274, float %272, float %274)
>  ret void
>
>ELSE84:                                           ; preds = %ELSE81
>  %275 = bitcast float %258 to i32
>  %276 = icmp eq i32 %275, 1
>  %277 = sext i1 %276 to i32
>  %278 = bitcast i32 %277 to float
>  %279 = bitcast float %278 to i32
>  %280 = icmp ne i32 %279, 0
>  br i1 %280, label %IF86, label %ELSE87
>
>ENDIF82:                                          ; preds = %IF110, %ELSE111, %ELSE90, %ENDIF97, %IF86, %ELSE81
>  %temp28.0 = phi float [ %259, %ELSE81 ], [ %294, %IF86 ], [ %347, %ENDIF97 ], [ %259, %ELSE90 ], [ %temp24.5, %ELSE111 ], [ %temp24.5, %IF110 ]
>  %temp29.0 = phi float [ %260, %ELSE81 ], [ %296, %IF86 ], [ %348, %ENDIF97 ], [ %260, %ELSE90 ], [ %392, %IF110 ], [ %394, %ELSE111 ]
>  %281 = bitcast float %30 to i32
>  %282 = icmp eq i32 %281, 10
>  %283 = sext i1 %282 to i32
>  %284 = bitcast i32 %283 to float
>  %285 = bitcast float %284 to i32
>  %286 = icmp ne i32 %285, 0
>  br i1 %286, label %IF113, label %ENDIF112
>
>IF86:                                             ; preds = %ELSE84
>  %287 = call float @llvm.AMDIL.fraction.(float %259)
>  %288 = call float @llvm.AMDIL.fraction.(float %260)
>  %289 = fdiv float 1.000000e+00, %22
>  %290 = fdiv float 1.000000e+00, %23
>  %291 = call float @floor(float %259)
>  %292 = call float @floor(float %260)
>  %293 = fmul float %287, %289
>  %294 = fadd float %293, %291
>  %295 = fmul float %288, %290
>  %296 = fadd float %295, %292
>  br label %ENDIF82
>
>ELSE87:                                           ; preds = %ELSE84
>  %297 = bitcast float %258 to i32
>  %298 = icmp eq i32 %297, 2
>  %299 = sext i1 %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = bitcast float %300 to i32
>  %302 = icmp ne i32 %301, 0
>  br i1 %302, label %IF89, label %ELSE90
>
>IF89:                                             ; preds = %ELSE87
>  %303 = fcmp uge float %259, 1.000000e+00
>  %304 = select i1 %303, float 1.000000e+00, float 0.000000e+00
>  %305 = fsub float -0.000000e+00, %304
>  %306 = fptosi float %305 to i32
>  %307 = bitcast i32 %306 to float
>  %308 = bitcast float %307 to i32
>  %309 = icmp ne i32 %308, 0
>  br i1 %309, label %IF92, label %ELSE93
>
>ELSE90:                                           ; preds = %ELSE87
>  %310 = bitcast float %258 to i32
>  %311 = icmp eq i32 %310, 3
>  %312 = sext i1 %311 to i32
>  %313 = bitcast i32 %312 to float
>  %314 = bitcast float %313 to i32
>  %315 = icmp ne i32 %314, 0
>  br i1 %315, label %IF104, label %ENDIF82
>
>IF92:                                             ; preds = %IF89
>  %316 = fmul float %24, %22
>  %317 = fmul float %316, 5.000000e-01
>  %318 = fsub float -0.000000e+00, %317
>  %319 = fadd float 1.000000e+00, %318
>  br label %ENDIF91
>
>ELSE93:                                           ; preds = %IF89
>  %320 = fcmp ult float %259, 0.000000e+00
>  %321 = select i1 %320, float 1.000000e+00, float 0.000000e+00
>  %322 = fsub float -0.000000e+00, %321
>  %323 = fptosi float %322 to i32
>  %324 = bitcast i32 %323 to float
>  %325 = bitcast float %324 to i32
>  %326 = icmp ne i32 %325, 0
>  %.122 = select i1 %326, float 0.000000e+00, float %259
>  br label %ENDIF91
>
>ENDIF91:                                          ; preds = %ELSE93, %IF92
>  %temp24.2 = phi float [ %319, %IF92 ], [ %.122, %ELSE93 ]
>  %327 = fcmp uge float %260, 1.000000e+00
>  %328 = select i1 %327, float 1.000000e+00, float 0.000000e+00
>  %329 = fsub float -0.000000e+00, %328
>  %330 = fptosi float %329 to i32
>  %331 = bitcast i32 %330 to float
>  %332 = bitcast float %331 to i32
>  %333 = icmp ne i32 %332, 0
>  br i1 %333, label %IF98, label %ELSE99
>
>IF98:                                             ; preds = %ENDIF91
>  %334 = fmul float %25, %23
>  %335 = fmul float %334, 5.000000e-01
>  %336 = fsub float -0.000000e+00, %335
>  %337 = fadd float 1.000000e+00, %336
>  br label %ENDIF97
>
>ELSE99:                                           ; preds = %ENDIF91
>  %338 = fcmp ult float %260, 0.000000e+00
>  %339 = select i1 %338, float 1.000000e+00, float 0.000000e+00
>  %340 = fsub float -0.000000e+00, %339
>  %341 = fptosi float %340 to i32
>  %342 = bitcast i32 %341 to float
>  %343 = bitcast float %342 to i32
>  %344 = icmp ne i32 %343, 0
>  %.123 = select i1 %344, float 0.000000e+00, float %260
>  br label %ENDIF97
>
>ENDIF97:                                          ; preds = %ELSE99, %IF98
>  %temp25.2 = phi float [ %337, %IF98 ], [ %.123, %ELSE99 ]
>  %345 = fdiv float 1.000000e+00, %22
>  %346 = fdiv float 1.000000e+00, %23
>  %347 = fmul float %temp24.2, %345
>  %348 = fmul float %temp25.2, %346
>  br label %ENDIF82
>
>IF104:                                            ; preds = %ELSE90
>  %349 = call float @floor(float %259)
>  %350 = call float @fabs(float %349)
>  %351 = fmul float %350, 5.000000e-01
>  %352 = call float @llvm.AMDIL.fraction.(float %351)
>  %353 = fmul float 2.000000e+00, %352
>  %354 = fsub float -0.000000e+00, %353
>  %355 = fadd float 1.000000e+00, %354
>  %356 = fcmp ult float %355, 0x3F50624DE0000000
>  %357 = select i1 %356, float 1.000000e+00, float 0.000000e+00
>  %358 = fsub float -0.000000e+00, %357
>  %359 = fptosi float %358 to i32
>  %360 = bitcast i32 %359 to float
>  %361 = bitcast float %360 to i32
>  %362 = icmp ne i32 %361, 0
>  %363 = call float @llvm.AMDIL.fraction.(float %259)
>  br i1 %362, label %IF107, label %ELSE108
>
>IF107:                                            ; preds = %IF104
>  %364 = fsub float -0.000000e+00, %363
>  %365 = fadd float 1.000000e+00, %364
>  %366 = fdiv float 1.000000e+00, %22
>  %367 = fmul float %365, %366
>  %368 = fsub float -0.000000e+00, %367
>  %369 = fadd float 2.000000e+00, %368
>  br label %ENDIF106
>
>ELSE108:                                          ; preds = %IF104
>  %370 = fdiv float 1.000000e+00, %22
>  %371 = fmul float %363, %370
>  br label %ENDIF106
>
>ENDIF106:                                         ; preds = %ELSE108, %IF107
>  %temp24.5 = phi float [ %369, %IF107 ], [ %371, %ELSE108 ]
>  %372 = call float @floor(float %260)
>  %373 = call float @fabs(float %372)
>  %374 = fmul float %373, 5.000000e-01
>  %375 = call float @llvm.AMDIL.fraction.(float %374)
>  %376 = fmul float 2.000000e+00, %375
>  %377 = fsub float -0.000000e+00, %376
>  %378 = fadd float 1.000000e+00, %377
>  %379 = fcmp ult float %378, 0x3F50624DE0000000
>  %380 = select i1 %379, float 1.000000e+00, float 0.000000e+00
>  %381 = fsub float -0.000000e+00, %380
>  %382 = fptosi float %381 to i32
>  %383 = bitcast i32 %382 to float
>  %384 = bitcast float %383 to i32
>  %385 = icmp ne i32 %384, 0
>  %386 = call float @llvm.AMDIL.fraction.(float %260)
>  br i1 %385, label %IF110, label %ELSE111
>
>IF110:                                            ; preds = %ENDIF106
>  %387 = fsub float -0.000000e+00, %386
>  %388 = fadd float 1.000000e+00, %387
>  %389 = fdiv float 1.000000e+00, %23
>  %390 = fmul float %388, %389
>  %391 = fsub float -0.000000e+00, %390
>  %392 = fadd float 2.000000e+00, %391
>  br label %ENDIF82
>
>ELSE111:                                          ; preds = %ENDIF106
>  %393 = fdiv float 1.000000e+00, %23
>  %394 = fmul float %386, %393
>  br label %ENDIF82
>
>IF113:                                            ; preds = %ENDIF82
>  %395 = fcmp uge float %temp28.0, 0.000000e+00
>  %396 = select i1 %395, float 1.000000e+00, float 0.000000e+00
>  %397 = fsub float -0.000000e+00, %396
>  %398 = fptosi float %397 to i32
>  %399 = bitcast i32 %398 to float
>  %400 = fcmp ult float %temp28.0, 1.000000e+00
>  %401 = select i1 %400, float 1.000000e+00, float 0.000000e+00
>  %402 = fsub float -0.000000e+00, %401
>  %403 = fptosi float %402 to i32
>  %404 = bitcast i32 %403 to float
>  %405 = bitcast float %399 to i32
>  %406 = bitcast float %404 to i32
>  %407 = and i32 %405, %406
>  %408 = bitcast i32 %407 to float
>  %409 = fcmp uge float %temp29.0, 0.000000e+00
>  %410 = select i1 %409, float 1.000000e+00, float 0.000000e+00
>  %411 = fsub float -0.000000e+00, %410
>  %412 = fptosi float %411 to i32
>  %413 = bitcast i32 %412 to float
>  %414 = bitcast float %408 to i32
>  %415 = bitcast float %413 to i32
>  %416 = and i32 %414, %415
>  %417 = bitcast i32 %416 to float
>  %418 = fcmp ult float %temp29.0, 1.000000e+00
>  %419 = select i1 %418, float 1.000000e+00, float 0.000000e+00
>  %420 = fsub float -0.000000e+00, %419
>  %421 = fptosi float %420 to i32
>  %422 = bitcast i32 %421 to float
>  %423 = bitcast float %417 to i32
>  %424 = bitcast float %422 to i32
>  %425 = and i32 %423, %424
>  %426 = bitcast i32 %425 to float
>  %427 = bitcast float %426 to i32
>  %428 = xor i32 %427, -1
>  %429 = bitcast i32 %428 to float
>  %430 = bitcast float %429 to i32
>  %431 = icmp ne i32 %430, 0
>  br i1 %431, label %ENDIF112, label %ELSE117
>
>ENDIF112:                                         ; preds = %ELSE117, %IF113, %ENDIF82
>  %temp12.3 = phi float [ 0xFFFFFFFFE0000000, %ENDIF82 ], [ 0xFFFFFFFFE0000000, %ELSE117 ], [ 0.000000e+00, %IF113 ]
>  %temp5.0 = phi float [ %temp29.0, %ENDIF82 ], [ %439, %ELSE117 ], [ %temp29.0, %IF113 ]
>  %temp4.2 = phi float [ %temp28.0, %ENDIF82 ], [ %438, %ELSE117 ], [ %temp28.0, %IF113 ]
>  %432 = bitcast float %temp12.3 to i32
>  %433 = icmp ne i32 %432, 0
>  br i1 %433, label %IF119, label %ENDIF79
>
>ELSE117:                                          ; preds = %IF113
>  %434 = call float @llvm.AMDIL.fraction.(float %temp28.0)
>  %435 = call float @llvm.AMDIL.fraction.(float %temp29.0)
>  %436 = fdiv float 1.000000e+00, %22
>  %437 = fdiv float 1.000000e+00, %23
>  %438 = fmul float %434, %436
>  %439 = fmul float %435, %437
>  br label %ENDIF112
>
>IF119:                                            ; preds = %ENDIF112
>  %440 = bitcast float %temp4.2 to i32
>  %441 = bitcast float %temp5.0 to i32
>  %442 = insertelement <2 x i32> undef, i32 %440, i32 0
>  %443 = insertelement <2 x i32> %442, i32 %441, i32 1
>  %444 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %443, <32 x i8> %33, <16 x i8> %35, i32 2)
>  %445 = extractelement <4 x float> %444, i32 3
>  br label %ENDIF79
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8340300
>c8350301
>c8300200
>c8310201
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840304
>c0c60508
>c0900100
>bf8c007f
>c20b2110
>c20ba10b
>c20f210a
>c20c2109
>c20ca108
>c2002103
>c200a102
>c2032101
>c203a100
>c20d2114
>bf8c007f
>d1020014
>0201141a
>d2000000
>00518280
>d1040014
>02010100
>be942414
>8994147e
>bf880101
>7e10021a
>7e1e0218
>7e1c0219
>100a1f0d
>10001d0c
>4a1610ca
>d1040018
>0201010b
>d2000009
>00618280
>d1040018
>02010109
>7e020305
>be982418
>8998187e
>bf8800a8
>d104001a
>0201030b
>d2000009
>00698280
>d104001a
>02010109
>be9a241a
>899a1a7e
>bf880090
>d104001c
>0201050b
>d2000009
>00718280
>d104001c
>02010109
>be9c241c
>899c1c7e
>bf880045
>d1040020
>0201070b
>7e020305
>7e120300
>bea02420
>89a0207e
>bf88003c
>7e124900
>d2060109
>02010109
>101212f0
>7e124109
>06121309
>081212f2
>7e1402ff
>3a83126f
>d0020022
>02021509
>d2000009
>0089e480
>d2060009
>22010109
>7e121109
>d1040022
>02010109
>7e144100
>bea22422
>89a2227e
>7e12550e
>1012130a
>bea22522
>89fe227e
>7e12550e
>081414f2
>1012130a
>081212f4
>88fe227e
>7e144905
>d206010a
>0201010a
>101414f0
>7e14410a
>0614150a
>081414f2
>7e1602ff
>3a83126f
>d0020022
>0202170a
>d200000a
>0089e480
>d206000a
>2201010a
>7e14110a
>d1040022
>0201010a
>7e144105
>bea22422
>89a2227e
>7e16550f
>1002170a
>bea22522
>89fe227e
>7e16550f
>081414f2
>1014170a
>080214f4
>88fe227e
>88fe207e
>7e140305
>be9c251c
>89fe1c7e
>bf88003e
>d00c0020
>0201e500
>d2000009
>0081e480
>d2060009
>22010109
>7e121109
>d1040020
>02010109
>bea02420
>89a0207e
>d0020022
>02010100
>d2000009
>0089e480
>d2060009
>22010109
>7e121109
>d10a0022
>02010109
>d2000009
>00890100
>bea02520
>89fe207e
>7e12021e
>10121d09
>d2820009
>03c9e309
>88fe207e
>d00c001e
>0201e505
>d200000a
>0079e480
>d206000a
>2201010a
>7e14110a
>d104001e
>0201010a
>be9e241e
>899e1e7e
>d0020020
>02010105
>d200000a
>0081e480
>d206000a
>2201010a
>7e14110a
>d10a0020
>0201010a
>d200000b
>00810105
>be9e251e
>89fe1e7e
>7e140217
>10141f0a
>d282000b
>03c9e30a
>88fe1e7e
>7e14550f
>1002150b
>7e16550e
>10121709
>88fe1c7e
>be9a251a
>89fe1a7e
>7e144905
>7e12550f
>7e084105
>d2820001
>042a1304
>7e084900
>7e0a550e
>7e0c4100
>d2820009
>04120b06
>88fe1a7e
>7e0a030a
>7e000309
>88fe187e
>d1040018
>02011508
>d2000008
>00618280
>7e2002c1
>be982418
>8998187e
>bf880032
>d002001a
>0201e500
>d2000008
>0069e480
>d2060008
>22010108
>7e101108
>d00c001a
>02010100
>d2000009
>0069e480
>d2060009
>22010109
>7e121109
>36101109
>d00c001a
>02010101
>d2000009
>0069e480
>d2060009
>22010109
>7e121109
>36101308
>d002001a
>0201e501
>d2000009
>0069e480
>d2060009
>22010109
>7e121109
>36101308
>3a2410c1
>d104001a
>02018308
>7e200280
>7e220310
>7e100310
>be9a241a
>899a1a7e
>7e10550f
>7e124101
>10021109
>7e10550e
>7e124100
>10001109
>7e2002c1
>7e220305
>7e100312
>88fe1a7e
>7e0a0311
>88fe187e
>d10a0018
>02010110
>7e0c0280
>7e0e0306
>be982418
>8998187e
>f0800f00
>00430800
>bf8c0770
>7e0a0309
>7e0c030a
>7e0e030b
>88fe187e
>be942514
>7e1c0216
>89fe147e
>f0800f00
>0043040c
>bf8c0770
>7e100304
>88fe147e
>c0840300
>c0c60500
>d1020002
>0201150e
>d2000000
>00098280
>d1040002
>02010100
>bf8c007f
>be822402
>8982027e
>bf8800f3
>7e1a0206
>7e180207
>10021b03
>10001902
>4a221cca
>d1040004
>02010111
>d200000f
>00118280
>d1040004
>0201010f
>be842404
>8984047e
>bf8800a8
>d1040006
>02010311
>d200000f
>00198280
>d1040006
>0201010f
>bf8c070f
>be862406
>8986067e
>bf88008f
>d1040014
>02010511
>d200000f
>00518280
>d1040014
>0201010f
>be942414
>8994147e
>bf880044
>d1040016
>02010711
>7e200301
>7e1e0300
>be962416
>8996167e
>bf88003c
>7e1e4900
>d206010f
>0201010f
>101e1ef0
>7e1e410f
>061e1f0f
>081e1ef2
>7e2002ff
>3a83126f
>d0020018
>0202210f
>d200000f
>0061e480
>d206000f
>2201010f
>7e1e110f
>d1040018
>0201010f
>7e204100
>be982418
>8998187e
>7e1e550c
>101e1f10
>be982518
>89fe187e
>7e1e550c
>082020f2
>101e1f10
>081e1ef4
>88fe187e
>7e204901
>d2060110
>02010110
>102020f0
>7e204110
>06202110
>082020f2
>7e2202ff
>3a83126f
>d0020018
>02022310
>d2000010
>0061e480
>d2060010
>22010110
>7e201110
>d1040018
>02010110
>7e224101
>be982418
>8998187e
>7e20550d
>10202111
>be982518
>89fe187e
>7e20550d
>082222f2
>10202111
>082020f4
>88fe187e
>88fe167e
>be942514
>89fe147e
>bf88003e
>d00c0016
>0201e500
>d200000f
>0059e480
>d206000f
>2201010f
>7e1e110f
>d1040016
>0201010f
>be962416
>8996167e
>d0020018
>02010100
>d200000f
>0061e480
>d206000f
>2201010f
>7e1e110f
>d10a0018
>0201010f
>d200000f
>00610100
>be962516
>89fe167e
>7e1e0201
>101e190f
>d282000f
>03c9e30f
>88fe167e
>d00c0016
>0201e501
>d2000010
>0059e480
>d2060010
>22010110
>7e201110
>d1040016
>02010110
>be962416
>8996167e
>d0020018
>02010101
>d2000010
>0061e480
>d2060010
>22010110
>7e201110
>d10a0018
>02010110
>d2000010
>00610101
>be962516
>89fe167e
>7e200200
>10201b10
>d2820010
>03c9e310
>88fe167e
>7e22550d
>10202310
>7e22550c
>101e230f
>88fe147e
>be862506
>89fe067e
>7e1e4901
>7e20550d
>7e224101
>d2820010
>043e2111
>7e1e4900
>7e22550c
>7e004100
>d282000f
>043e2300
>88fe067e
>7e00030f
>7e020310
>88fe047e
>d1040000
>0201150e
>7e1c02c1
>be802400
>8980007e
>bf88002c
>d0020004
>0201e500
>d200000e
>0011e480
>d206000e
>2201010e
>7e1c110e
>d00c0004
>02010100
>d200000f
>0011e480
>d206000f
>2201010f
>7e1e110f
>361c1d0f
>d00c0004
>02010101
>d200000f
>0011e480
>d206000f
>2201010f
>7e1e110f
>361c1f0e
>d0020004
>0201e501
>d200000f
>0011e480
>d206000f
>2201010f
>7e1e110f
>361c1f0e
>d1040004
>0201830e
>7e1c0280
>be842404
>8984047e
>7e1a550d
>7e1c4101
>10021b0e
>7e18550c
>7e1a4100
>1000190d
>7e1c02c1
>88fe047e
>88fe007e
>d10a0000
>0201010e
>7e180280
>be802400
>8980007e
>f0800800
>00430c00
>bf8c0770
>88fe007e
>be822502
>89fe027e
>f0800800
>00430c02
>bf8c0770
>88fe027e
>10001907
>10021906
>5e000101
>10021905
>10041908
>5e020302
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[2].xyxx
>  1: MOV TEMP[0].zw, IN[1].yyxy
>  2: MOV OUT[1], TEMP[0]
>  3: MOV OUT[0], IN[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
>  %23 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %22, i32 0, i32 %5)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %24, float %25, float %19, float %20)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>c0800708
>bf8c0070
>e00c2000
>80000500
>bf8c0770
>f800020f
>02010605
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>
>** (mate-power-manager:25226): WARNING **: levels is 0!
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..1]
>DCL TEMP[0..1], LOCAL
>IMM[0] INT32 {0, 3, 1, 2}
>  0: USEQ TEMP[0].x, CONST[1].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   USNE TEMP[0].x, CONST[0].xxxx, IMM[0].xxxx
>  3:   USNE TEMP[1].x, CONST[0].xxxx, IMM[0].yyyy
>  4:   AND TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>  5:   UIF TEMP[0].xxxx :0
>  6:     MOV TEMP[0].xy, IN[0].xyyy
>  7:     TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  8:     MOV TEMP[0], TEMP[0].zyxw
>  9:   ELSE :0
> 10:     MOV TEMP[1].xy, IN[0].xyyy
> 11:     TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 12:     MOV TEMP[0], TEMP[1]
> 13:   ENDIF
> 14: ELSE :0
> 15:   USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].zzzz
> 16:   UIF TEMP[1].xxxx :0
> 17:     MOV TEMP[1].xy, IN[0].xyyy
> 18:     TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 19:     MOV TEMP[0], TEMP[1].wxyz
> 20:   ELSE :0
> 21:     USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].xxxx
> 22:     UIF TEMP[1].xxxx :0
> 23:       MOV TEMP[1].xy, IN[0].xyyy
> 24:       TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 25:       MOV TEMP[0], TEMP[1].wzyx
> 26:     ELSE :0
> 27:       USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].wwww
> 28:       UIF TEMP[1].xxxx :0
> 29:         MOV TEMP[1].xy, IN[0].xyyy
> 30:         TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 31:         MOV TEMP[0], TEMP[1].yzwx
> 32:       ELSE :0
> 33:         USEQ TEMP[1].x, CONST[0].xxxx, IMM[0].yyyy
> 34:         UIF TEMP[1].xxxx :0
> 35:           MOV TEMP[1].xy, IN[0].xyyy
> 36:           TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 37:           MOV TEMP[0], TEMP[1].wzyx
> 38:         ENDIF
> 39:       ENDIF
> 40:     ENDIF
> 41:   ENDIF
> 42: ENDIF
> 43: MOV OUT[0], TEMP[0]
> 44: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = bitcast float %23 to i32
>  %31 = icmp eq i32 %30, 0
>  %32 = sext i1 %31 to i32
>  %33 = bitcast i32 %32 to float
>  %34 = bitcast float %33 to i32
>  %35 = icmp ne i32 %34, 0
>  %36 = bitcast float %22 to i32
>  br i1 %35, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %37 = icmp ne i32 %36, 0
>  %38 = sext i1 %37 to i32
>  %39 = bitcast i32 %38 to float
>  %40 = bitcast float %22 to i32
>  %41 = icmp ne i32 %40, 3
>  %42 = sext i1 %41 to i32
>  %43 = bitcast i32 %42 to float
>  %44 = bitcast float %39 to i32
>  %45 = bitcast float %43 to i32
>  %46 = and i32 %44, %45
>  %47 = bitcast i32 %46 to float
>  %48 = bitcast float %47 to i32
>  %49 = icmp ne i32 %48, 0
>  %50 = bitcast float %28 to i32
>  %51 = bitcast float %29 to i32
>  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
>  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
>  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %55 = extractelement <4 x float> %54, i32 0
>  %56 = extractelement <4 x float> %54, i32 1
>  %57 = extractelement <4 x float> %54, i32 2
>  %58 = extractelement <4 x float> %54, i32 3
>  %. = select i1 %49, float %57, float %55
>  %.23 = select i1 %49, float %55, float %57
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %59 = icmp eq i32 %36, 1
>  %60 = sext i1 %59 to i32
>  %61 = bitcast i32 %60 to float
>  %62 = bitcast float %61 to i32
>  %63 = icmp ne i32 %62, 0
>  br i1 %63, label %IF12, label %ELSE13
>
>ENDIF:                                            ; preds = %IF21, %ELSE19, %IF18, %IF15, %IF12, %IF
>  %temp.0 = phi float [ %., %IF ], [ %76, %IF12 ], [ %91, %IF15 ], [ %104, %IF18 ], [ %121, %IF21 ], [ %33, %ELSE19 ]
>  %temp1.0 = phi float [ %56, %IF ], [ %73, %IF12 ], [ %90, %IF15 ], [ %105, %IF18 ], [ %120, %IF21 ], [ 0.000000e+00, %ELSE19 ]
>  %temp2.0 = phi float [ %.23, %IF ], [ %74, %IF12 ], [ %89, %IF15 ], [ %106, %IF18 ], [ %119, %IF21 ], [ 0.000000e+00, %ELSE19 ]
>  %temp3.0 = phi float [ %58, %IF ], [ %75, %IF12 ], [ %88, %IF15 ], [ %103, %IF18 ], [ %118, %IF21 ], [ 0.000000e+00, %ELSE19 ]
>  %64 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0)
>  %65 = bitcast i32 %64 to float
>  %66 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0)
>  %67 = bitcast i32 %66 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %65, float %67, float %65, float %67)
>  ret void
>
>IF12:                                             ; preds = %ELSE
>  %68 = bitcast float %28 to i32
>  %69 = bitcast float %29 to i32
>  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
>  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
>  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %73 = extractelement <4 x float> %72, i32 0
>  %74 = extractelement <4 x float> %72, i32 1
>  %75 = extractelement <4 x float> %72, i32 2
>  %76 = extractelement <4 x float> %72, i32 3
>  br label %ENDIF
>
>ELSE13:                                           ; preds = %ELSE
>  %77 = bitcast float %22 to i32
>  %78 = icmp eq i32 %77, 0
>  %79 = sext i1 %78 to i32
>  %80 = bitcast i32 %79 to float
>  %81 = bitcast float %80 to i32
>  %82 = icmp ne i32 %81, 0
>  br i1 %82, label %IF15, label %ELSE16
>
>IF15:                                             ; preds = %ELSE13
>  %83 = bitcast float %28 to i32
>  %84 = bitcast float %29 to i32
>  %85 = insertelement <2 x i32> undef, i32 %83, i32 0
>  %86 = insertelement <2 x i32> %85, i32 %84, i32 1
>  %87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %86, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %88 = extractelement <4 x float> %87, i32 0
>  %89 = extractelement <4 x float> %87, i32 1
>  %90 = extractelement <4 x float> %87, i32 2
>  %91 = extractelement <4 x float> %87, i32 3
>  br label %ENDIF
>
>ELSE16:                                           ; preds = %ELSE13
>  %92 = bitcast float %22 to i32
>  %93 = icmp eq i32 %92, 2
>  %94 = sext i1 %93 to i32
>  %95 = bitcast i32 %94 to float
>  %96 = bitcast float %95 to i32
>  %97 = icmp ne i32 %96, 0
>  br i1 %97, label %IF18, label %ELSE19
>
>IF18:                                             ; preds = %ELSE16
>  %98 = bitcast float %28 to i32
>  %99 = bitcast float %29 to i32
>  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
>  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
>  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %103 = extractelement <4 x float> %102, i32 0
>  %104 = extractelement <4 x float> %102, i32 1
>  %105 = extractelement <4 x float> %102, i32 2
>  %106 = extractelement <4 x float> %102, i32 3
>  br label %ENDIF
>
>ELSE19:                                           ; preds = %ELSE16
>  %107 = bitcast float %22 to i32
>  %108 = icmp eq i32 %107, 3
>  %109 = sext i1 %108 to i32
>  %110 = bitcast i32 %109 to float
>  %111 = bitcast float %110 to i32
>  %112 = icmp ne i32 %111, 0
>  br i1 %112, label %IF21, label %ENDIF
>
>IF21:                                             ; preds = %ELSE19
>  %113 = bitcast float %28 to i32
>  %114 = bitcast float %29 to i32
>  %115 = insertelement <2 x i32> undef, i32 %113, i32 0
>  %116 = insertelement <2 x i32> %115, i32 %114, i32 1
>  %117 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %116, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %118 = extractelement <4 x float> %117, i32 0
>  %119 = extractelement <4 x float> %117, i32 1
>  %120 = extractelement <4 x float> %117, i32 2
>  %121 = extractelement <4 x float> %117, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c0820100
>bf8c007f
>c2010500
>c2000504
>bf8c007f
>d1040000
>02010000
>d200000b
>00018280
>d1040000
>0201010b
>7e000202
>7e020202
>be802400
>8980007e
>bf880042
>d1040002
>02010300
>d2000014
>00098280
>d1040002
>02010114
>be822402
>8982027e
>bf880031
>d1040004
>02010101
>d2000014
>00118280
>d1040004
>02010114
>be842404
>8984047e
>bf88001f
>d1040006
>02010501
>d2000014
>00198280
>d1040006
>02010114
>be862406
>8986067e
>bf88000e
>d1040014
>02010701
>7e140280
>7e28030a
>7e10030a
>be942414
>8994147e
>f0800f00
>00430a02
>bf8c0770
>7e28030b
>7e10030c
>7e16030d
>88fe147e
>be862506
>89fe067e
>f0800f00
>00430a02
>bf8c0770
>7e28030d
>7e10030c
>88fe067e
>be842504
>89fe047e
>f0800f00
>00430a02
>bf8c0770
>7e28030b
>7e10030c
>7e16030d
>88fe047e
>be822502
>bf8c070f
>89fe027e
>f0800f00
>00430802
>bf8c0770
>7e280309
>88fe027e
>be802500
>89fe007e
>d10a0002
>02010701
>d10a0004
>02010100
>87820204
>f0800f00
>00430702
>bf8c0770
>d2000014
>000a0f09
>d200000b
>000a1307
>88fe007e
>5e001514
>5e02110b
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = fmul float %30, %11
>  %35 = fmul float %30, %12
>  %36 = fmul float %30, %13
>  %37 = fmul float %30, %14
>  %38 = fmul float %31, %15
>  %39 = fadd float %38, %34
>  %40 = fmul float %31, %16
>  %41 = fadd float %40, %35
>  %42 = fmul float %31, %17
>  %43 = fadd float %42, %36
>  %44 = fmul float %31, %18
>  %45 = fadd float %44, %37
>  %46 = fmul float %32, %19
>  %47 = fadd float %46, %39
>  %48 = fmul float %32, %20
>  %49 = fadd float %48, %41
>  %50 = fmul float %32, %21
>  %51 = fadd float %50, %43
>  %52 = fmul float %32, %22
>  %53 = fadd float %52, %45
>  %54 = fmul float %33, %23
>  %55 = fadd float %54, %47
>  %56 = fmul float %33, %24
>  %57 = fadd float %56, %49
>  %58 = fmul float %33, %25
>  %59 = fadd float %58, %51
>  %60 = fmul float %33, %26
>  %61 = fadd float %60, %53
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %55, float %57, float %59, float %61)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL CONST[2]
>DCL TEMP[0..7], LOCAL
>IMM[0] INT32 {10, -10, 0, 1}
>IMM[1] UINT32 {4294967295, 0, 0, 0}
>IMM[2] INT32 {2, 3, 0, 0}
>IMM[3] FLT32 {    1.0000,     0.5000,     0.0000,     2.0000}
>IMM[4] FLT32 {    0.0010,     0.0000,     0.0000,     0.0000}
>  0: ISLT TEMP[0].x, CONST[2].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   MOV TEMP[0].xy, IN[0].xyyy
>  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  4:   MOV TEMP[0], TEMP[0]
>  5: ELSE :0
>  6:   MOV TEMP[1].x, IMM[1].xxxx
>  7:   UADD TEMP[2].x, CONST[2].xxxx, IMM[0].yyyy
>  8:   MUL TEMP[3].xy, IN[0].xyyy, CONST[0].xyyy
>  9:   MOV TEMP[4].xy, TEMP[3].xyxx
> 10:   USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].zzzz
> 11:   UIF TEMP[5].xxxx :0
> 12:     MOV TEMP[5].xy, TEMP[3].xyxx
> 13:   ELSE :0
> 14:     USEQ TEMP[6].x, TEMP[2].xxxx, IMM[0].wwww
> 15:     UIF TEMP[6].xxxx :0
> 16:       FRC TEMP[6].xy, TEMP[3].xyyy
> 17:       RCP TEMP[7].x, CONST[0].xxxx
> 18:       RCP TEMP[7].y, CONST[0].yyyy
> 19:       FLR TEMP[3].xy, TEMP[3].xyyy
> 20:       MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[3].xyyy
> 21:     ELSE :0
> 22:       USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].xxxx
> 23:       UIF TEMP[3].xxxx :0
> 24:         SGE TEMP[3].x, TEMP[4].xxxx, IMM[3].xxxx
> 25:         F2I TEMP[3].x, -TEMP[3]
> 26:         UIF TEMP[3].xxxx :0
> 27:           MUL TEMP[3].x, CONST[0].zzzz, CONST[0].xxxx
> 28:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 29:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[3].xxxx
> 30:         ELSE :0
> 31:           SLT TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz
> 32:           F2I TEMP[3].x, -TEMP[3]
> 33:           UIF TEMP[3].xxxx :0
> 34:             MOV TEMP[4].x, IMM[3].zzzz
> 35:           ENDIF
> 36:         ENDIF
> 37:         SGE TEMP[3].x, TEMP[4].yyyy, IMM[3].xxxx
> 38:         F2I TEMP[3].x, -TEMP[3]
> 39:         UIF TEMP[3].xxxx :0
> 40:           MUL TEMP[3].x, CONST[0].wwww, CONST[0].yyyy
> 41:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 42:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 43:           MOV TEMP[4].y, TEMP[3].xxxx
> 44:         ELSE :0
> 45:           SLT TEMP[3].x, TEMP[4].yyyy, IMM[3].zzzz
> 46:           F2I TEMP[3].x, -TEMP[3]
> 47:           UIF TEMP[3].xxxx :0
> 48:             MOV TEMP[4].y, IMM[3].zzzz
> 49:           ENDIF
> 50:         ENDIF
> 51:         RCP TEMP[3].x, CONST[0].xxxx
> 52:         RCP TEMP[3].y, CONST[0].yyyy
> 53:         MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[3].xyyy
> 54:       ELSE :0
> 55:         USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].yyyy
> 56:         UIF TEMP[3].xxxx :0
> 57:           FLR TEMP[3].x, TEMP[4].xxxx
> 58:           ABS TEMP[3].x, TEMP[3].xxxx
> 59:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 60:           FRC TEMP[3].x, TEMP[3].xxxx
> 61:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 62:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 63:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 64:           F2I TEMP[3].x, -TEMP[3]
> 65:           UIF TEMP[3].xxxx :0
> 66:             FRC TEMP[3].x, TEMP[4].xxxx
> 67:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 68:             RCP TEMP[6].x, CONST[0].xxxx
> 69:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 70:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[3].xxxx
> 71:           ELSE :0
> 72:             FRC TEMP[3].x, TEMP[4].xxxx
> 73:             RCP TEMP[6].x, CONST[0].xxxx
> 74:             MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx
> 75:           ENDIF
> 76:           FLR TEMP[3].x, TEMP[4].yyyy
> 77:           ABS TEMP[3].x, TEMP[3].xxxx
> 78:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 79:           FRC TEMP[3].x, TEMP[3].xxxx
> 80:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 81:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 82:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 83:           F2I TEMP[3].x, -TEMP[3]
> 84:           UIF TEMP[3].xxxx :0
> 85:             FRC TEMP[3].x, TEMP[4].yyyy
> 86:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 87:             RCP TEMP[6].x, CONST[0].yyyy
> 88:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 89:             ADD TEMP[3].x, IMM[3].wwww, -TEMP[3].xxxx
> 90:             MOV TEMP[4].y, TEMP[3].xxxx
> 91:           ELSE :0
> 92:             FRC TEMP[3].x, TEMP[4].yyyy
> 93:             RCP TEMP[6].x, CONST[0].yyyy
> 94:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 95:             MOV TEMP[4].y, TEMP[3].xxxx
> 96:           ENDIF
> 97:         ENDIF
> 98:       ENDIF
> 99:     ENDIF
>100:     MOV TEMP[5].xy, TEMP[4].xyxx
>101:   ENDIF
>102:   MOV TEMP[2].xy, TEMP[5].xyxx
>103:   USEQ TEMP[3].x, CONST[2].xxxx, IMM[0].xxxx
>104:   UIF TEMP[3].xxxx :0
>105:     SGE TEMP[3].x, TEMP[5].xxxx, IMM[3].zzzz
>106:     F2I TEMP[3].x, -TEMP[3]
>107:     SLT TEMP[4].x, TEMP[5].xxxx, IMM[3].xxxx
>108:     F2I TEMP[4].x, -TEMP[4]
>109:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>110:     SGE TEMP[4].x, TEMP[5].yyyy, IMM[3].zzzz
>111:     F2I TEMP[4].x, -TEMP[4]
>112:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>113:     SLT TEMP[4].x, TEMP[5].yyyy, IMM[3].xxxx
>114:     F2I TEMP[4].x, -TEMP[4]
>115:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>116:     NOT TEMP[3].x, TEMP[3].xxxx
>117:     UIF TEMP[3].xxxx :0
>118:       MOV TEMP[3].xyz, IMM[3].zzzz
>119:       MOV TEMP[3].w, IMM[3].zzzz
>120:       MOV TEMP[3], TEMP[3]
>121:       MOV TEMP[1].x, IMM[1].yyyy
>122:     ELSE :0
>123:       FRC TEMP[4].xy, TEMP[5].xyyy
>124:       RCP TEMP[5].x, CONST[0].xxxx
>125:       RCP TEMP[5].y, CONST[0].yyyy
>126:       MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy
>127:     ENDIF
>128:   ENDIF
>129:   UIF TEMP[1].xxxx :0
>130:     MOV TEMP[2].xy, TEMP[2].xyyy
>131:     TEX TEMP[2], TEMP[2], SAMP[0], 2D
>132:     MOV TEMP[3], TEMP[2]
>133:   ENDIF
>134:   MOV TEMP[0], TEMP[3]
>135: ENDIF
>136: MOV OUT[0], TEMP[0]
>137: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %27 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %33 = bitcast float %26 to i32
>  %34 = icmp slt i32 %33, 10
>  %35 = sext i1 %34 to i32
>  %36 = bitcast i32 %35 to float
>  %37 = bitcast float %36 to i32
>  %38 = icmp ne i32 %37, 0
>  br i1 %38, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %39 = bitcast float %31 to i32
>  %40 = bitcast float %32 to i32
>  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
>  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %48 = bitcast float %26 to i32
>  %49 = add i32 %48, -10
>  %50 = bitcast i32 %49 to float
>  %51 = fmul float %31, %22
>  %52 = fmul float %32, %23
>  %53 = bitcast float %50 to i32
>  %54 = icmp eq i32 %53, 0
>  %55 = sext i1 %54 to i32
>  %56 = bitcast i32 %55 to float
>  %57 = bitcast float %56 to i32
>  %58 = icmp ne i32 %57, 0
>  br i1 %58, label %ENDIF32, label %ELSE34
>
>ENDIF:                                            ; preds = %IF69, %ENDIF62, %IF
>  %temp3.0 = phi float [ %47, %IF ], [ %236, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp2.0 = phi float [ %46, %IF ], [ %235, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp1.0 = phi float [ %45, %IF ], [ %234, %IF69 ], [ %temp13.3, %ENDIF62 ]
>  %temp.0 = phi float [ %44, %IF ], [ %233, %IF69 ], [ %temp12.0, %ENDIF62 ]
>  %59 = call i32 @llvm.SI.packf16(float %temp.0, float %temp1.0)
>  %60 = bitcast i32 %59 to float
>  %61 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0)
>  %62 = bitcast i32 %61 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62)
>  ret void
>
>ELSE34:                                           ; preds = %ELSE
>  %63 = bitcast float %50 to i32
>  %64 = icmp eq i32 %63, 1
>  %65 = sext i1 %64 to i32
>  %66 = bitcast i32 %65 to float
>  %67 = bitcast float %66 to i32
>  %68 = icmp ne i32 %67, 0
>  br i1 %68, label %IF36, label %ELSE37
>
>ENDIF32:                                          ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE
>  %temp13.0 = phi float [ %52, %ELSE ], [ %80, %IF36 ], [ %134, %ENDIF47 ], [ %52, %ELSE40 ], [ %52, %ELSE61 ], [ %52, %IF60 ]
>  %temp20.0 = phi float [ %51, %ELSE ], [ %82, %IF36 ], [ %135, %ENDIF47 ], [ %51, %ELSE40 ], [ %temp16.5, %ELSE61 ], [ %temp16.5, %IF60 ]
>  %temp21.0 = phi float [ %52, %ELSE ], [ %84, %IF36 ], [ %136, %ENDIF47 ], [ %52, %ELSE40 ], [ %180, %IF60 ], [ %182, %ELSE61 ]
>  %69 = bitcast float %26 to i32
>  %70 = icmp eq i32 %69, 10
>  %71 = sext i1 %70 to i32
>  %72 = bitcast i32 %71 to float
>  %73 = bitcast float %72 to i32
>  %74 = icmp ne i32 %73, 0
>  br i1 %74, label %IF63, label %ENDIF62
>
>IF36:                                             ; preds = %ELSE34
>  %75 = call float @llvm.AMDIL.fraction.(float %51)
>  %76 = call float @llvm.AMDIL.fraction.(float %52)
>  %77 = fdiv float 1.000000e+00, %22
>  %78 = fdiv float 1.000000e+00, %23
>  %79 = call float @floor(float %51)
>  %80 = call float @floor(float %52)
>  %81 = fmul float %75, %77
>  %82 = fadd float %81, %79
>  %83 = fmul float %76, %78
>  %84 = fadd float %83, %80
>  br label %ENDIF32
>
>ELSE37:                                           ; preds = %ELSE34
>  %85 = bitcast float %50 to i32
>  %86 = icmp eq i32 %85, 2
>  %87 = sext i1 %86 to i32
>  %88 = bitcast i32 %87 to float
>  %89 = bitcast float %88 to i32
>  %90 = icmp ne i32 %89, 0
>  br i1 %90, label %IF39, label %ELSE40
>
>IF39:                                             ; preds = %ELSE37
>  %91 = fcmp uge float %51, 1.000000e+00
>  %92 = select i1 %91, float 1.000000e+00, float 0.000000e+00
>  %93 = fsub float -0.000000e+00, %92
>  %94 = fptosi float %93 to i32
>  %95 = bitcast i32 %94 to float
>  %96 = bitcast float %95 to i32
>  %97 = icmp ne i32 %96, 0
>  br i1 %97, label %IF42, label %ELSE43
>
>ELSE40:                                           ; preds = %ELSE37
>  %98 = bitcast float %50 to i32
>  %99 = icmp eq i32 %98, 3
>  %100 = sext i1 %99 to i32
>  %101 = bitcast i32 %100 to float
>  %102 = bitcast float %101 to i32
>  %103 = icmp ne i32 %102, 0
>  br i1 %103, label %IF54, label %ENDIF32
>
>IF42:                                             ; preds = %IF39
>  %104 = fmul float %24, %22
>  %105 = fmul float %104, 5.000000e-01
>  %106 = fsub float -0.000000e+00, %105
>  %107 = fadd float 1.000000e+00, %106
>  br label %ENDIF41
>
>ELSE43:                                           ; preds = %IF39
>  %108 = fcmp ult float %51, 0.000000e+00
>  %109 = select i1 %108, float 1.000000e+00, float 0.000000e+00
>  %110 = fsub float -0.000000e+00, %109
>  %111 = fptosi float %110 to i32
>  %112 = bitcast i32 %111 to float
>  %113 = bitcast float %112 to i32
>  %114 = icmp ne i32 %113, 0
>  %. = select i1 %114, float 0.000000e+00, float %51
>  br label %ENDIF41
>
>ENDIF41:                                          ; preds = %ELSE43, %IF42
>  %temp16.2 = phi float [ %107, %IF42 ], [ %., %ELSE43 ]
>  %115 = fcmp uge float %52, 1.000000e+00
>  %116 = select i1 %115, float 1.000000e+00, float 0.000000e+00
>  %117 = fsub float -0.000000e+00, %116
>  %118 = fptosi float %117 to i32
>  %119 = bitcast i32 %118 to float
>  %120 = bitcast float %119 to i32
>  %121 = icmp ne i32 %120, 0
>  br i1 %121, label %IF48, label %ELSE49
>
>IF48:                                             ; preds = %ENDIF41
>  %122 = fmul float %25, %23
>  %123 = fmul float %122, 5.000000e-01
>  %124 = fsub float -0.000000e+00, %123
>  %125 = fadd float 1.000000e+00, %124
>  br label %ENDIF47
>
>ELSE49:                                           ; preds = %ENDIF41
>  %126 = fcmp ult float %52, 0.000000e+00
>  %127 = select i1 %126, float 1.000000e+00, float 0.000000e+00
>  %128 = fsub float -0.000000e+00, %127
>  %129 = fptosi float %128 to i32
>  %130 = bitcast i32 %129 to float
>  %131 = bitcast float %130 to i32
>  %132 = icmp ne i32 %131, 0
>  %.71 = select i1 %132, float 0.000000e+00, float %52
>  br label %ENDIF47
>
>ENDIF47:                                          ; preds = %ELSE49, %IF48
>  %temp17.2 = phi float [ %125, %IF48 ], [ %.71, %ELSE49 ]
>  %133 = fdiv float 1.000000e+00, %22
>  %134 = fdiv float 1.000000e+00, %23
>  %135 = fmul float %temp16.2, %133
>  %136 = fmul float %temp17.2, %134
>  br label %ENDIF32
>
>IF54:                                             ; preds = %ELSE40
>  %137 = call float @floor(float %51)
>  %138 = call float @fabs(float %137)
>  %139 = fmul float %138, 5.000000e-01
>  %140 = call float @llvm.AMDIL.fraction.(float %139)
>  %141 = fmul float 2.000000e+00, %140
>  %142 = fsub float -0.000000e+00, %141
>  %143 = fadd float 1.000000e+00, %142
>  %144 = fcmp ult float %143, 0x3F50624DE0000000
>  %145 = select i1 %144, float 1.000000e+00, float 0.000000e+00
>  %146 = fsub float -0.000000e+00, %145
>  %147 = fptosi float %146 to i32
>  %148 = bitcast i32 %147 to float
>  %149 = bitcast float %148 to i32
>  %150 = icmp ne i32 %149, 0
>  %151 = call float @llvm.AMDIL.fraction.(float %51)
>  br i1 %150, label %IF57, label %ELSE58
>
>IF57:                                             ; preds = %IF54
>  %152 = fsub float -0.000000e+00, %151
>  %153 = fadd float 1.000000e+00, %152
>  %154 = fdiv float 1.000000e+00, %22
>  %155 = fmul float %153, %154
>  %156 = fsub float -0.000000e+00, %155
>  %157 = fadd float 2.000000e+00, %156
>  br label %ENDIF56
>
>ELSE58:                                           ; preds = %IF54
>  %158 = fdiv float 1.000000e+00, %22
>  %159 = fmul float %151, %158
>  br label %ENDIF56
>
>ENDIF56:                                          ; preds = %ELSE58, %IF57
>  %temp16.5 = phi float [ %157, %IF57 ], [ %159, %ELSE58 ]
>  %160 = call float @floor(float %52)
>  %161 = call float @fabs(float %160)
>  %162 = fmul float %161, 5.000000e-01
>  %163 = call float @llvm.AMDIL.fraction.(float %162)
>  %164 = fmul float 2.000000e+00, %163
>  %165 = fsub float -0.000000e+00, %164
>  %166 = fadd float 1.000000e+00, %165
>  %167 = fcmp ult float %166, 0x3F50624DE0000000
>  %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00
>  %169 = fsub float -0.000000e+00, %168
>  %170 = fptosi float %169 to i32
>  %171 = bitcast i32 %170 to float
>  %172 = bitcast float %171 to i32
>  %173 = icmp ne i32 %172, 0
>  %174 = call float @llvm.AMDIL.fraction.(float %52)
>  br i1 %173, label %IF60, label %ELSE61
>
>IF60:                                             ; preds = %ENDIF56
>  %175 = fsub float -0.000000e+00, %174
>  %176 = fadd float 1.000000e+00, %175
>  %177 = fdiv float 1.000000e+00, %23
>  %178 = fmul float %176, %177
>  %179 = fsub float -0.000000e+00, %178
>  %180 = fadd float 2.000000e+00, %179
>  br label %ENDIF32
>
>ELSE61:                                           ; preds = %ENDIF56
>  %181 = fdiv float 1.000000e+00, %23
>  %182 = fmul float %174, %181
>  br label %ENDIF32
>
>IF63:                                             ; preds = %ENDIF32
>  %183 = fcmp uge float %temp20.0, 0.000000e+00
>  %184 = select i1 %183, float 1.000000e+00, float 0.000000e+00
>  %185 = fsub float -0.000000e+00, %184
>  %186 = fptosi float %185 to i32
>  %187 = bitcast i32 %186 to float
>  %188 = fcmp ult float %temp20.0, 1.000000e+00
>  %189 = select i1 %188, float 1.000000e+00, float 0.000000e+00
>  %190 = fsub float -0.000000e+00, %189
>  %191 = fptosi float %190 to i32
>  %192 = bitcast i32 %191 to float
>  %193 = bitcast float %187 to i32
>  %194 = bitcast float %192 to i32
>  %195 = and i32 %193, %194
>  %196 = bitcast i32 %195 to float
>  %197 = fcmp uge float %temp21.0, 0.000000e+00
>  %198 = select i1 %197, float 1.000000e+00, float 0.000000e+00
>  %199 = fsub float -0.000000e+00, %198
>  %200 = fptosi float %199 to i32
>  %201 = bitcast i32 %200 to float
>  %202 = bitcast float %196 to i32
>  %203 = bitcast float %201 to i32
>  %204 = and i32 %202, %203
>  %205 = bitcast i32 %204 to float
>  %206 = fcmp ult float %temp21.0, 1.000000e+00
>  %207 = select i1 %206, float 1.000000e+00, float 0.000000e+00
>  %208 = fsub float -0.000000e+00, %207
>  %209 = fptosi float %208 to i32
>  %210 = bitcast i32 %209 to float
>  %211 = bitcast float %205 to i32
>  %212 = bitcast float %210 to i32
>  %213 = and i32 %211, %212
>  %214 = bitcast i32 %213 to float
>  %215 = bitcast float %214 to i32
>  %216 = xor i32 %215, -1
>  %217 = bitcast i32 %216 to float
>  %218 = bitcast float %217 to i32
>  %219 = icmp ne i32 %218, 0
>  br i1 %219, label %ENDIF62, label %ELSE67
>
>ENDIF62:                                          ; preds = %ELSE67, %IF63, %ENDIF32
>  %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp8.0 = phi float [ %temp20.0, %ENDIF32 ], [ %226, %ELSE67 ], [ %temp20.0, %IF63 ]
>  %temp9.0 = phi float [ %temp21.0, %ENDIF32 ], [ %227, %ELSE67 ], [ %temp21.0, %IF63 ]
>  %temp12.0 = phi float [ %72, %ENDIF32 ], [ %217, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp13.3 = phi float [ %temp13.0, %ENDIF32 ], [ %temp13.0, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %220 = bitcast float %temp4.0 to i32
>  %221 = icmp ne i32 %220, 0
>  br i1 %221, label %IF69, label %ENDIF
>
>ELSE67:                                           ; preds = %IF63
>  %222 = call float @llvm.AMDIL.fraction.(float %temp20.0)
>  %223 = call float @llvm.AMDIL.fraction.(float %temp21.0)
>  %224 = fdiv float 1.000000e+00, %22
>  %225 = fdiv float 1.000000e+00, %23
>  %226 = fmul float %222, %224
>  %227 = fmul float %223, %225
>  br label %ENDIF62
>
>IF69:                                             ; preds = %ENDIF62
>  %228 = bitcast float %temp8.0 to i32
>  %229 = bitcast float %temp9.0 to i32
>  %230 = insertelement <2 x i32> undef, i32 %228, i32 0
>  %231 = insertelement <2 x i32> %230, i32 %229, i32 1
>  %232 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %231, <32 x i8> %28, <16 x i8> %30, i32 2)
>  %233 = extractelement <4 x float> %232, i32 0
>  %234 = extractelement <4 x float> %232, i32 1
>  %235 = extractelement <4 x float> %232, i32 2
>  %236 = extractelement <4 x float> %232, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c08a0100
>bf8c007f
>c2031503
>c2039502
>c2011501
>c2019500
>c2021508
>bf8c007f
>d1020000
>02011404
>d2000000
>00018280
>d1040000
>02010100
>be802400
>8980007e
>bf880102
>7e140204
>7e120202
>7e100203
>100a1303
>10001102
>4a1a14ca
>d1040002
>0201010d
>d200000b
>00098280
>d1040002
>0201010b
>7e020305
>be822402
>8982027e
>bf8800a9
>d1040004
>0201030d
>d200000b
>00118280
>d1040004
>0201010b
>bf8c070f
>be842404
>8984047e
>bf880090
>d1040014
>0201050d
>d200000b
>00518280
>d1040014
>0201010b
>be942414
>8994147e
>bf880045
>d1040016
>0201070d
>7e020305
>7e160300
>be962416
>8996167e
>bf88003c
>7e164900
>d206010b
>0201010b
>101616f0
>7e16410b
>0616170b
>081616f2
>7e1802ff
>3a83126f
>d0020018
>0202190b
>d200000b
>0061e480
>d206000b
>2201010b
>7e16110b
>d1040018
>0201010b
>7e184100
>be982418
>8998187e
>7e165508
>1016170c
>be982518
>89fe187e
>7e165508
>081818f2
>1016170c
>081616f4
>88fe187e
>7e184905
>d206010c
>0201010c
>101818f0
>7e18410c
>0618190c
>081818f2
>7e1a02ff
>3a83126f
>d0020018
>02021b0c
>d200000c
>0061e480
>d206000c
>2201010c
>7e18110c
>d1040018
>0201010c
>7e184105
>be982418
>8998187e
>7e1a5509
>10021b0c
>be982518
>89fe187e
>7e1a5509
>081818f2
>10181b0c
>080218f4
>88fe187e
>88fe167e
>7e180305
>be942514
>89fe147e
>bf88003e
>d00c0016
>0201e500
>d200000b
>0059e480
>d206000b
>2201010b
>7e16110b
>d1040016
>0201010b
>be962416
>8996167e
>d0020018
>02010100
>d200000b
>0061e480
>d206000b
>2201010b
>7e16110b
>d10a0018
>0201010b
>d200000b
>00610100
>be962516
>89fe167e
>7e160207
>1016110b
>d282000b
>03c9e30b
>88fe167e
>d00c0016
>0201e505
>d200000c
>0059e480
>d206000c
>2201010c
>7e18110c
>d1040016
>0201010c
>be962416
>8996167e
>d0020018
>02010105
>d200000c
>0061e480
>d206000c
>2201010c
>7e18110c
>d10a0018
>0201010c
>d200000d
>00610105
>be962516
>89fe167e
>7e180206
>1018130c
>d282000d
>03c9e30c
>88fe167e
>7e185509
>1002190d
>7e1a5508
>10161b0b
>88fe147e
>be842504
>89fe047e
>7e184905
>7e165509
>7e084105
>d2820001
>04321704
>7e084900
>7e0a5508
>7e0c4100
>d282000b
>04120b06
>88fe047e
>7e0a030c
>7e00030b
>88fe027e
>d1040002
>0201150a
>d200000a
>00098280
>7e1c02c1
>be822402
>8982027e
>bf880032
>d0020004
>0201e500
>d200000a
>0011e480
>d206000a
>2201010a
>7e14110a
>d00c0004
>02010100
>d200000b
>0011e480
>d206000b
>2201010b
>7e16110b
>3614150b
>d00c0004
>02010101
>d200000b
>0011e480
>d206000b
>2201010b
>7e16110b
>3614170a
>d0020004
>0201e501
>d200000b
>0011e480
>d206000b
>2201010b
>7e16110b
>3614170a
>3a2014c1
>d1040004
>0201830a
>7e1e0280
>7e14030f
>7e1c030f
>be842404
>8984047e
>7e125509
>7e144101
>1002130a
>7e105508
>7e124100
>10001109
>7e1c02c1
>7e1e0305
>7e140310
>88fe047e
>7e0a030f
>88fe027e
>d10a0002
>0201010e
>7e0c0280
>7e0e0306
>be822402
>8982027e
>f0800f00
>00430a00
>bf8c0770
>7e0a030b
>7e0c030c
>7e0e030d
>88fe027e
>be802500
>89fe007e
>f0800f00
>00430402
>bf8c0770
>7e140304
>88fe007e
>5e000f06
>5e020b0a
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>  0: MUL TEMP[0].xy, IN[0].xyyy, CONST[0].xyyy
>  1: FRC TEMP[1].xy, TEMP[0].xyyy
>  2: RCP TEMP[2].x, CONST[0].xxxx
>  3: RCP TEMP[2].y, CONST[0].yyyy
>  4: FLR TEMP[0].xy, TEMP[0].xyyy
>  5: MAD TEMP[0].xy, TEMP[1].xyyy, TEMP[2].xyyy, TEMP[0].xyyy
>  6: MOV TEMP[0].xy, TEMP[0].xyyy
>  7: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  8: MOV OUT[0], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = fmul float %28, %22
>  %31 = fmul float %29, %23
>  %32 = call float @llvm.AMDIL.fraction.(float %30)
>  %33 = call float @llvm.AMDIL.fraction.(float %31)
>  %34 = fdiv float 1.000000e+00, %22
>  %35 = fdiv float 1.000000e+00, %23
>  %36 = call float @floor(float %30)
>  %37 = call float @floor(float %31)
>  %38 = fmul float %32, %34
>  %39 = fadd float %38, %36
>  %40 = fmul float %33, %35
>  %41 = fadd float %40, %37
>  %42 = bitcast float %39 to i32
>  %43 = bitcast float %41 to i32
>  %44 = insertelement <2 x i32> undef, i32 %42, i32 0
>  %45 = insertelement <2 x i32> %44, i32 %43, i32 1
>  %46 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %45, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %47 = extractelement <4 x float> %46, i32 0
>  %48 = extractelement <4 x float> %46, i32 1
>  %49 = extractelement <4 x float> %46, i32 2
>  %50 = extractelement <4 x float> %46, i32 3
>  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
>  %52 = bitcast i32 %51 to float
>  %53 = call i32 @llvm.SI.packf16(float %49, float %50)
>  %54 = bitcast i32 %53 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %52, float %54, float %52, float %54)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c0840100
>bf8c007f
>c2000901
>bf8c007f
>10060400
>7e044903
>7e064103
>7e085400
>d2820003
>040a0903
>c8100000
>c8110001
>c2000900
>bf8c007f
>10020800
>7e004901
>7e024101
>7e085400
>d2820002
>04020901
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0]
>  0: MOV OUT[0], CONST[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800100
>bf8c007f
>c2020102
>c2028103
>bf8c007f
>7e000205
>d25e0000
>02020004
>c2020100
>c2000101
>bf8c007f
>7e020200
>d25e0001
>02020204
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800700
>bf8c007f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL CONST[2..3]
>DCL TEMP[0..7], LOCAL
>IMM[0] INT32 {10, -10, 0, 1}
>IMM[1] UINT32 {4294967295, 0, 0, 0}
>IMM[2] INT32 {2, 3, 0, 0}
>IMM[3] FLT32 {    1.0000,     0.5000,     0.0000,     2.0000}
>IMM[4] FLT32 {    0.0010,     0.0000,     0.0000,     0.0000}
>  0: ISLT TEMP[0].x, CONST[3].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   MOV TEMP[0].xy, IN[0].xyyy
>  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  4:   MOV TEMP[0].w, TEMP[0]
>  5: ELSE :0
>  6:   MOV TEMP[1].x, IMM[1].xxxx
>  7:   UADD TEMP[2].x, CONST[3].xxxx, IMM[0].yyyy
>  8:   MUL TEMP[3].xy, IN[0].xyyy, CONST[0].xyyy
>  9:   MOV TEMP[4].xy, TEMP[3].xyxx
> 10:   USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].zzzz
> 11:   UIF TEMP[5].xxxx :0
> 12:     MOV TEMP[5].xy, TEMP[3].xyxx
> 13:   ELSE :0
> 14:     USEQ TEMP[6].x, TEMP[2].xxxx, IMM[0].wwww
> 15:     UIF TEMP[6].xxxx :0
> 16:       FRC TEMP[6].xy, TEMP[3].xyyy
> 17:       RCP TEMP[7].x, CONST[0].xxxx
> 18:       RCP TEMP[7].y, CONST[0].yyyy
> 19:       FLR TEMP[3].xy, TEMP[3].xyyy
> 20:       MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[3].xyyy
> 21:     ELSE :0
> 22:       USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].xxxx
> 23:       UIF TEMP[3].xxxx :0
> 24:         SGE TEMP[3].x, TEMP[4].xxxx, IMM[3].xxxx
> 25:         F2I TEMP[3].x, -TEMP[3]
> 26:         UIF TEMP[3].xxxx :0
> 27:           MUL TEMP[3].x, CONST[0].zzzz, CONST[0].xxxx
> 28:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 29:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[3].xxxx
> 30:         ELSE :0
> 31:           SLT TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz
> 32:           F2I TEMP[3].x, -TEMP[3]
> 33:           UIF TEMP[3].xxxx :0
> 34:             MOV TEMP[4].x, IMM[3].zzzz
> 35:           ENDIF
> 36:         ENDIF
> 37:         SGE TEMP[3].x, TEMP[4].yyyy, IMM[3].xxxx
> 38:         F2I TEMP[3].x, -TEMP[3]
> 39:         UIF TEMP[3].xxxx :0
> 40:           MUL TEMP[3].x, CONST[0].wwww, CONST[0].yyyy
> 41:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 42:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 43:           MOV TEMP[4].y, TEMP[3].xxxx
> 44:         ELSE :0
> 45:           SLT TEMP[3].x, TEMP[4].yyyy, IMM[3].zzzz
> 46:           F2I TEMP[3].x, -TEMP[3]
> 47:           UIF TEMP[3].xxxx :0
> 48:             MOV TEMP[4].y, IMM[3].zzzz
> 49:           ENDIF
> 50:         ENDIF
> 51:         RCP TEMP[3].x, CONST[0].xxxx
> 52:         RCP TEMP[3].y, CONST[0].yyyy
> 53:         MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[3].xyyy
> 54:       ELSE :0
> 55:         USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].yyyy
> 56:         UIF TEMP[3].xxxx :0
> 57:           FLR TEMP[3].x, TEMP[4].xxxx
> 58:           ABS TEMP[3].x, TEMP[3].xxxx
> 59:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 60:           FRC TEMP[3].x, TEMP[3].xxxx
> 61:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 62:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 63:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 64:           F2I TEMP[3].x, -TEMP[3]
> 65:           UIF TEMP[3].xxxx :0
> 66:             FRC TEMP[3].x, TEMP[4].xxxx
> 67:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 68:             RCP TEMP[6].x, CONST[0].xxxx
> 69:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 70:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[3].xxxx
> 71:           ELSE :0
> 72:             FRC TEMP[3].x, TEMP[4].xxxx
> 73:             RCP TEMP[6].x, CONST[0].xxxx
> 74:             MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx
> 75:           ENDIF
> 76:           FLR TEMP[3].x, TEMP[4].yyyy
> 77:           ABS TEMP[3].x, TEMP[3].xxxx
> 78:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 79:           FRC TEMP[3].x, TEMP[3].xxxx
> 80:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 81:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 82:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 83:           F2I TEMP[3].x, -TEMP[3]
> 84:           UIF TEMP[3].xxxx :0
> 85:             FRC TEMP[3].x, TEMP[4].yyyy
> 86:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 87:             RCP TEMP[6].x, CONST[0].yyyy
> 88:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 89:             ADD TEMP[3].x, IMM[3].wwww, -TEMP[3].xxxx
> 90:             MOV TEMP[4].y, TEMP[3].xxxx
> 91:           ELSE :0
> 92:             FRC TEMP[3].x, TEMP[4].yyyy
> 93:             RCP TEMP[6].x, CONST[0].yyyy
> 94:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 95:             MOV TEMP[4].y, TEMP[3].xxxx
> 96:           ENDIF
> 97:         ENDIF
> 98:       ENDIF
> 99:     ENDIF
>100:     MOV TEMP[5].xy, TEMP[4].xyxx
>101:   ENDIF
>102:   MOV TEMP[2].xy, TEMP[5].xyxx
>103:   USEQ TEMP[3].x, CONST[3].xxxx, IMM[0].xxxx
>104:   UIF TEMP[3].xxxx :0
>105:     SGE TEMP[3].x, TEMP[5].xxxx, IMM[3].zzzz
>106:     F2I TEMP[3].x, -TEMP[3]
>107:     SLT TEMP[4].x, TEMP[5].xxxx, IMM[3].xxxx
>108:     F2I TEMP[4].x, -TEMP[4]
>109:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>110:     SGE TEMP[4].x, TEMP[5].yyyy, IMM[3].zzzz
>111:     F2I TEMP[4].x, -TEMP[4]
>112:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>113:     SLT TEMP[4].x, TEMP[5].yyyy, IMM[3].xxxx
>114:     F2I TEMP[4].x, -TEMP[4]
>115:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>116:     NOT TEMP[3].x, TEMP[3].xxxx
>117:     UIF TEMP[3].xxxx :0
>118:       MOV TEMP[3].xyz, IMM[3].zzzz
>119:       MOV TEMP[3].w, IMM[3].zzzz
>120:       MOV TEMP[3], TEMP[3]
>121:       MOV TEMP[1].x, IMM[1].yyyy
>122:     ELSE :0
>123:       FRC TEMP[4].xy, TEMP[5].xyyy
>124:       RCP TEMP[5].x, CONST[0].xxxx
>125:       RCP TEMP[5].y, CONST[0].yyyy
>126:       MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy
>127:     ENDIF
>128:   ENDIF
>129:   UIF TEMP[1].xxxx :0
>130:     MOV TEMP[2].xy, TEMP[2].xyyy
>131:     TEX TEMP[2], TEMP[2], SAMP[0], 2D
>132:     MOV TEMP[3], TEMP[2]
>133:   ENDIF
>134:   MOV TEMP[0].w, TEMP[3]
>135: ENDIF
>136: MUL TEMP[0], CONST[2], TEMP[0].wwww
>137: MOV OUT[0], TEMP[0]
>138: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = bitcast float %30 to i32
>  %38 = icmp slt i32 %37, 10
>  %39 = sext i1 %38 to i32
>  %40 = bitcast i32 %39 to float
>  %41 = bitcast float %40 to i32
>  %42 = icmp ne i32 %41, 0
>  br i1 %42, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %43 = bitcast float %35 to i32
>  %44 = bitcast float %36 to i32
>  %45 = insertelement <2 x i32> undef, i32 %43, i32 0
>  %46 = insertelement <2 x i32> %45, i32 %44, i32 1
>  %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %48 = extractelement <4 x float> %47, i32 3
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %49 = bitcast float %30 to i32
>  %50 = add i32 %49, -10
>  %51 = bitcast i32 %50 to float
>  %52 = fmul float %35, %22
>  %53 = fmul float %36, %23
>  %54 = bitcast float %51 to i32
>  %55 = icmp eq i32 %54, 0
>  %56 = sext i1 %55 to i32
>  %57 = bitcast i32 %56 to float
>  %58 = bitcast float %57 to i32
>  %59 = icmp ne i32 %58, 0
>  br i1 %59, label %ENDIF32, label %ELSE34
>
>ENDIF:                                            ; preds = %IF69, %ENDIF62, %IF
>  %temp3.0 = phi float [ %48, %IF ], [ %238, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %60 = fmul float %26, %temp3.0
>  %61 = fmul float %27, %temp3.0
>  %62 = fmul float %28, %temp3.0
>  %63 = fmul float %29, %temp3.0
>  %64 = call i32 @llvm.SI.packf16(float %60, float %61)
>  %65 = bitcast i32 %64 to float
>  %66 = call i32 @llvm.SI.packf16(float %62, float %63)
>  %67 = bitcast i32 %66 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %65, float %67, float %65, float %67)
>  ret void
>
>ELSE34:                                           ; preds = %ELSE
>  %68 = bitcast float %51 to i32
>  %69 = icmp eq i32 %68, 1
>  %70 = sext i1 %69 to i32
>  %71 = bitcast i32 %70 to float
>  %72 = bitcast float %71 to i32
>  %73 = icmp ne i32 %72, 0
>  br i1 %73, label %IF36, label %ELSE37
>
>ENDIF32:                                          ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE
>  %temp20.0 = phi float [ %52, %ELSE ], [ %87, %IF36 ], [ %140, %ENDIF47 ], [ %52, %ELSE40 ], [ %temp16.5, %ELSE61 ], [ %temp16.5, %IF60 ]
>  %temp21.0 = phi float [ %53, %ELSE ], [ %89, %IF36 ], [ %141, %ENDIF47 ], [ %53, %ELSE40 ], [ %185, %IF60 ], [ %187, %ELSE61 ]
>  %74 = bitcast float %30 to i32
>  %75 = icmp eq i32 %74, 10
>  %76 = sext i1 %75 to i32
>  %77 = bitcast i32 %76 to float
>  %78 = bitcast float %77 to i32
>  %79 = icmp ne i32 %78, 0
>  br i1 %79, label %IF63, label %ENDIF62
>
>IF36:                                             ; preds = %ELSE34
>  %80 = call float @llvm.AMDIL.fraction.(float %52)
>  %81 = call float @llvm.AMDIL.fraction.(float %53)
>  %82 = fdiv float 1.000000e+00, %22
>  %83 = fdiv float 1.000000e+00, %23
>  %84 = call float @floor(float %52)
>  %85 = call float @floor(float %53)
>  %86 = fmul float %80, %82
>  %87 = fadd float %86, %84
>  %88 = fmul float %81, %83
>  %89 = fadd float %88, %85
>  br label %ENDIF32
>
>ELSE37:                                           ; preds = %ELSE34
>  %90 = bitcast float %51 to i32
>  %91 = icmp eq i32 %90, 2
>  %92 = sext i1 %91 to i32
>  %93 = bitcast i32 %92 to float
>  %94 = bitcast float %93 to i32
>  %95 = icmp ne i32 %94, 0
>  br i1 %95, label %IF39, label %ELSE40
>
>IF39:                                             ; preds = %ELSE37
>  %96 = fcmp uge float %52, 1.000000e+00
>  %97 = select i1 %96, float 1.000000e+00, float 0.000000e+00
>  %98 = fsub float -0.000000e+00, %97
>  %99 = fptosi float %98 to i32
>  %100 = bitcast i32 %99 to float
>  %101 = bitcast float %100 to i32
>  %102 = icmp ne i32 %101, 0
>  br i1 %102, label %IF42, label %ELSE43
>
>ELSE40:                                           ; preds = %ELSE37
>  %103 = bitcast float %51 to i32
>  %104 = icmp eq i32 %103, 3
>  %105 = sext i1 %104 to i32
>  %106 = bitcast i32 %105 to float
>  %107 = bitcast float %106 to i32
>  %108 = icmp ne i32 %107, 0
>  br i1 %108, label %IF54, label %ENDIF32
>
>IF42:                                             ; preds = %IF39
>  %109 = fmul float %24, %22
>  %110 = fmul float %109, 5.000000e-01
>  %111 = fsub float -0.000000e+00, %110
>  %112 = fadd float 1.000000e+00, %111
>  br label %ENDIF41
>
>ELSE43:                                           ; preds = %IF39
>  %113 = fcmp ult float %52, 0.000000e+00
>  %114 = select i1 %113, float 1.000000e+00, float 0.000000e+00
>  %115 = fsub float -0.000000e+00, %114
>  %116 = fptosi float %115 to i32
>  %117 = bitcast i32 %116 to float
>  %118 = bitcast float %117 to i32
>  %119 = icmp ne i32 %118, 0
>  %. = select i1 %119, float 0.000000e+00, float %52
>  br label %ENDIF41
>
>ENDIF41:                                          ; preds = %ELSE43, %IF42
>  %temp16.2 = phi float [ %112, %IF42 ], [ %., %ELSE43 ]
>  %120 = fcmp uge float %53, 1.000000e+00
>  %121 = select i1 %120, float 1.000000e+00, float 0.000000e+00
>  %122 = fsub float -0.000000e+00, %121
>  %123 = fptosi float %122 to i32
>  %124 = bitcast i32 %123 to float
>  %125 = bitcast float %124 to i32
>  %126 = icmp ne i32 %125, 0
>  br i1 %126, label %IF48, label %ELSE49
>
>IF48:                                             ; preds = %ENDIF41
>  %127 = fmul float %25, %23
>  %128 = fmul float %127, 5.000000e-01
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fadd float 1.000000e+00, %129
>  br label %ENDIF47
>
>ELSE49:                                           ; preds = %ENDIF41
>  %131 = fcmp ult float %53, 0.000000e+00
>  %132 = select i1 %131, float 1.000000e+00, float 0.000000e+00
>  %133 = fsub float -0.000000e+00, %132
>  %134 = fptosi float %133 to i32
>  %135 = bitcast i32 %134 to float
>  %136 = bitcast float %135 to i32
>  %137 = icmp ne i32 %136, 0
>  %.71 = select i1 %137, float 0.000000e+00, float %53
>  br label %ENDIF47
>
>ENDIF47:                                          ; preds = %ELSE49, %IF48
>  %temp17.2 = phi float [ %130, %IF48 ], [ %.71, %ELSE49 ]
>  %138 = fdiv float 1.000000e+00, %22
>  %139 = fdiv float 1.000000e+00, %23
>  %140 = fmul float %temp16.2, %138
>  %141 = fmul float %temp17.2, %139
>  br label %ENDIF32
>
>IF54:                                             ; preds = %ELSE40
>  %142 = call float @floor(float %52)
>  %143 = call float @fabs(float %142)
>  %144 = fmul float %143, 5.000000e-01
>  %145 = call float @llvm.AMDIL.fraction.(float %144)
>  %146 = fmul float 2.000000e+00, %145
>  %147 = fsub float -0.000000e+00, %146
>  %148 = fadd float 1.000000e+00, %147
>  %149 = fcmp ult float %148, 0x3F50624DE0000000
>  %150 = select i1 %149, float 1.000000e+00, float 0.000000e+00
>  %151 = fsub float -0.000000e+00, %150
>  %152 = fptosi float %151 to i32
>  %153 = bitcast i32 %152 to float
>  %154 = bitcast float %153 to i32
>  %155 = icmp ne i32 %154, 0
>  %156 = call float @llvm.AMDIL.fraction.(float %52)
>  br i1 %155, label %IF57, label %ELSE58
>
>IF57:                                             ; preds = %IF54
>  %157 = fsub float -0.000000e+00, %156
>  %158 = fadd float 1.000000e+00, %157
>  %159 = fdiv float 1.000000e+00, %22
>  %160 = fmul float %158, %159
>  %161 = fsub float -0.000000e+00, %160
>  %162 = fadd float 2.000000e+00, %161
>  br label %ENDIF56
>
>ELSE58:                                           ; preds = %IF54
>  %163 = fdiv float 1.000000e+00, %22
>  %164 = fmul float %156, %163
>  br label %ENDIF56
>
>ENDIF56:                                          ; preds = %ELSE58, %IF57
>  %temp16.5 = phi float [ %162, %IF57 ], [ %164, %ELSE58 ]
>  %165 = call float @floor(float %53)
>  %166 = call float @fabs(float %165)
>  %167 = fmul float %166, 5.000000e-01
>  %168 = call float @llvm.AMDIL.fraction.(float %167)
>  %169 = fmul float 2.000000e+00, %168
>  %170 = fsub float -0.000000e+00, %169
>  %171 = fadd float 1.000000e+00, %170
>  %172 = fcmp ult float %171, 0x3F50624DE0000000
>  %173 = select i1 %172, float 1.000000e+00, float 0.000000e+00
>  %174 = fsub float -0.000000e+00, %173
>  %175 = fptosi float %174 to i32
>  %176 = bitcast i32 %175 to float
>  %177 = bitcast float %176 to i32
>  %178 = icmp ne i32 %177, 0
>  %179 = call float @llvm.AMDIL.fraction.(float %53)
>  br i1 %178, label %IF60, label %ELSE61
>
>IF60:                                             ; preds = %ENDIF56
>  %180 = fsub float -0.000000e+00, %179
>  %181 = fadd float 1.000000e+00, %180
>  %182 = fdiv float 1.000000e+00, %23
>  %183 = fmul float %181, %182
>  %184 = fsub float -0.000000e+00, %183
>  %185 = fadd float 2.000000e+00, %184
>  br label %ENDIF32
>
>ELSE61:                                           ; preds = %ENDIF56
>  %186 = fdiv float 1.000000e+00, %23
>  %187 = fmul float %179, %186
>  br label %ENDIF32
>
>IF63:                                             ; preds = %ENDIF32
>  %188 = fcmp uge float %temp20.0, 0.000000e+00
>  %189 = select i1 %188, float 1.000000e+00, float 0.000000e+00
>  %190 = fsub float -0.000000e+00, %189
>  %191 = fptosi float %190 to i32
>  %192 = bitcast i32 %191 to float
>  %193 = fcmp ult float %temp20.0, 1.000000e+00
>  %194 = select i1 %193, float 1.000000e+00, float 0.000000e+00
>  %195 = fsub float -0.000000e+00, %194
>  %196 = fptosi float %195 to i32
>  %197 = bitcast i32 %196 to float
>  %198 = bitcast float %192 to i32
>  %199 = bitcast float %197 to i32
>  %200 = and i32 %198, %199
>  %201 = bitcast i32 %200 to float
>  %202 = fcmp uge float %temp21.0, 0.000000e+00
>  %203 = select i1 %202, float 1.000000e+00, float 0.000000e+00
>  %204 = fsub float -0.000000e+00, %203
>  %205 = fptosi float %204 to i32
>  %206 = bitcast i32 %205 to float
>  %207 = bitcast float %201 to i32
>  %208 = bitcast float %206 to i32
>  %209 = and i32 %207, %208
>  %210 = bitcast i32 %209 to float
>  %211 = fcmp ult float %temp21.0, 1.000000e+00
>  %212 = select i1 %211, float 1.000000e+00, float 0.000000e+00
>  %213 = fsub float -0.000000e+00, %212
>  %214 = fptosi float %213 to i32
>  %215 = bitcast i32 %214 to float
>  %216 = bitcast float %210 to i32
>  %217 = bitcast float %215 to i32
>  %218 = and i32 %216, %217
>  %219 = bitcast i32 %218 to float
>  %220 = bitcast float %219 to i32
>  %221 = xor i32 %220, -1
>  %222 = bitcast i32 %221 to float
>  %223 = bitcast float %222 to i32
>  %224 = icmp ne i32 %223, 0
>  br i1 %224, label %ENDIF62, label %ELSE67
>
>ENDIF62:                                          ; preds = %ELSE67, %IF63, %ENDIF32
>  %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp8.0 = phi float [ %temp20.0, %ENDIF32 ], [ %231, %ELSE67 ], [ %temp20.0, %IF63 ]
>  %temp9.0 = phi float [ %temp21.0, %ENDIF32 ], [ %232, %ELSE67 ], [ %temp21.0, %IF63 ]
>  %225 = bitcast float %temp4.0 to i32
>  %226 = icmp ne i32 %225, 0
>  br i1 %226, label %IF69, label %ENDIF
>
>ELSE67:                                           ; preds = %IF63
>  %227 = call float @llvm.AMDIL.fraction.(float %temp20.0)
>  %228 = call float @llvm.AMDIL.fraction.(float %temp21.0)
>  %229 = fdiv float 1.000000e+00, %22
>  %230 = fdiv float 1.000000e+00, %23
>  %231 = fmul float %227, %229
>  %232 = fmul float %228, %230
>  br label %ENDIF62
>
>IF69:                                             ; preds = %ENDIF62
>  %233 = bitcast float %temp8.0 to i32
>  %234 = bitcast float %temp9.0 to i32
>  %235 = insertelement <2 x i32> undef, i32 %233, i32 0
>  %236 = insertelement <2 x i32> %235, i32 %234, i32 1
>  %237 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %236, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %238 = extractelement <4 x float> %237, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c08c0100
>bf8c007f
>c201190b
>c201990a
>c2021909
>c2029908
>c20b1903
>c20b9902
>c2031901
>c2039900
>c20a190c
>bf8c007f
>d1020000
>02011414
>d2000000
>00018280
>d1040000
>02010100
>be802400
>8980007e
>bf8800f4
>7e0c0214
>7e0a0206
>7e080207
>10020b03
>10000902
>4a120cca
>d1040006
>02010109
>d2000007
>00198280
>d1040006
>02010107
>be862406
>8986067e
>bf8800a8
>d1040014
>02010309
>d2000007
>00518280
>d1040014
>02010107
>bf8c070f
>be942414
>8994147e
>bf88008f
>d1040018
>02010509
>d2000007
>00618280
>d1040018
>02010107
>be982418
>8998187e
>bf880044
>d104001a
>02010709
>7e100301
>7e0e0300
>be9a241a
>899a1a7e
>bf88003c
>7e0e4900
>d2060107
>02010107
>100e0ef0
>7e0e4107
>060e0f07
>080e0ef2
>7e1002ff
>3a83126f
>d002001c
>02021107
>d2000007
>0071e480
>d2060007
>22010107
>7e0e1107
>d104001c
>02010107
>7e104100
>be9c241c
>899c1c7e
>7e0e5504
>100e0f08
>be9c251c
>89fe1c7e
>7e0e5504
>081010f2
>100e0f08
>080e0ef4
>88fe1c7e
>7e104901
>d2060108
>02010108
>101010f0
>7e104108
>06101108
>081010f2
>7e1202ff
>3a83126f
>d002001c
>02021308
>d2000008
>0071e480
>d2060008
>22010108
>7e101108
>d104001c
>02010108
>7e124101
>be9c241c
>899c1c7e
>7e105505
>10101109
>be9c251c
>89fe1c7e
>7e105505
>081212f2
>10101109
>081010f4
>88fe1c7e
>88fe1a7e
>be982518
>89fe187e
>bf88003e
>d00c001a
>0201e500
>d2000007
>0069e480
>d2060007
>22010107
>7e0e1107
>d104001a
>02010107
>be9a241a
>899a1a7e
>d002001c
>02010100
>d2000007
>0071e480
>d2060007
>22010107
>7e0e1107
>d10a001c
>02010107
>d2000007
>00710100
>be9a251a
>89fe1a7e
>7e0e0217
>100e0907
>d2820007
>03c9e307
>88fe1a7e
>d00c001a
>0201e501
>d2000008
>0069e480
>d2060008
>22010108
>7e101108
>d104001a
>02010108
>be9a241a
>899a1a7e
>d002001c
>02010101
>d2000008
>0071e480
>d2060008
>22010108
>7e101108
>d10a001c
>02010108
>d2000008
>00710101
>be9a251a
>89fe1a7e
>7e100216
>10100b08
>d2820008
>03c9e308
>88fe1a7e
>7e125505
>10101308
>7e125504
>100e1307
>88fe187e
>be942514
>89fe147e
>7e0e4901
>7e105505
>7e124101
>d2820008
>041e1109
>7e0e4900
>7e125504
>7e004100
>d2820007
>041e1300
>88fe147e
>7e000307
>7e020308
>88fe067e
>d1040006
>02011506
>7e0c02c1
>be862406
>8986067e
>bf88002c
>d0020014
>0201e500
>d2000006
>0051e480
>d2060006
>22010106
>7e0c1106
>d00c0014
>02010100
>d2000007
>0051e480
>d2060007
>22010107
>7e0e1107
>360c0d07
>d00c0014
>02010101
>d2000007
>0051e480
>d2060007
>22010107
>7e0e1107
>360c0f06
>d0020014
>0201e501
>d2000007
>0051e480
>d2060007
>22010107
>7e0e1107
>360c0f06
>d1040014
>02018306
>7e0c0280
>be942414
>8994147e
>7e0a5505
>7e0c4101
>10020b06
>7e085504
>7e0a4100
>10000905
>7e0c02c1
>88fe147e
>88fe067e
>d10a0006
>02010106
>7e080280
>be862406
>8986067e
>f0800800
>00430400
>bf8c0770
>88fe067e
>be802500
>7e0c0202
>7e0a0203
>7e020204
>7e000205
>89fe007e
>f0800800
>00430402
>bf8c0770
>88fe007e
>10040906
>10060905
>5e040503
>10020901
>10000900
>5e000300
>f8001c0f
>02000200
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>
>(xfdesktop:25224): GLib-GIO-CRITICAL **: g_file_get_path: assertion `G_IS_FILE (file)' failed
>
>** (wrapper:25245): WARNING **: application.vala:256: Fehler beim Lesen der Datei Â»/home/hadack/.local/share/notes/Notizen/tmpÂ«: Ist ein Verzeichnis
>
>** (wrapper:25245): WARNING **: application.vala:256: Fehler beim Lesen der Datei Â»/home/hadack/.local/share/notes/Notizen/curÂ«: Ist ein Verzeichnis
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL IN[2], GENERIC[21], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL TEMP[0..14], LOCAL
>IMM[0] UINT32 {4294967295, 0, 0, 0}
>IMM[1] FLT32 {   -1.0000,     0.0001,    -0.5000,     0.5000}
>IMM[2] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].x, IMM[0].xxxx
>  1: ADD TEMP[1].x, IN[1].zzzz, IMM[1].xxxx
>  2: ABS TEMP[1].x, TEMP[1].xxxx
>  3: SGE TEMP[1].x, IMM[1].yyyy, TEMP[1].xxxx
>  4: F2I TEMP[1].x, -TEMP[1]
>  5: UIF TEMP[1].xxxx :0
>  6:   MOV TEMP[1].x, IMM[0].xxxx
>  7: ELSE :0
>  8:   MOV TEMP[1].x, IMM[0].yyyy
>  9: ENDIF
> 10: ADD TEMP[2].x, IN[0].zzzz, IMM[1].xxxx
> 11: ABS TEMP[2].x, TEMP[2].xxxx
> 12: SGE TEMP[2].x, IMM[1].yyyy, TEMP[2].xxxx
> 13: F2I TEMP[2].x, -TEMP[2]
> 14: UIF TEMP[2].xxxx :0
> 15:   MOV TEMP[2].x, IMM[0].xxxx
> 16: ELSE :0
> 17:   MOV TEMP[2].x, IMM[0].yyyy
> 18: ENDIF
> 19: USEQ TEMP[3].x, TEMP[1].xxxx, IMM[0].xxxx
> 20: UIF TEMP[3].xxxx :0
> 21:   MOV TEMP[3].x, IN[2].yyyy
> 22:   MOV TEMP[4].x, IN[2].yyyy
> 23: ELSE :0
> 24:   ADD TEMP[5].x, IN[0].yyyy, IMM[1].zzzz
> 25:   ADD TEMP[5].x, TEMP[5].xxxx, -IN[2].xxxx
> 26:   RCP TEMP[6].x, IN[1].wwww
> 27:   MAD TEMP[3].x, TEMP[5].xxxx, TEMP[6].xxxx, IN[2].yyyy
> 28:   ADD TEMP[5].x, IN[0].yyyy, IMM[1].wwww
> 29:   ADD TEMP[5].x, TEMP[5].xxxx, -IN[2].xxxx
> 30:   RCP TEMP[6].x, IN[1].wwww
> 31:   MAD TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx, IN[2].yyyy
> 32: ENDIF
> 33: USEQ TEMP[5].x, TEMP[2].xxxx
> IMM[0].xxxx
> 34: UIF TEMP[5].xxxx :0
> 35:   MOV TEMP[5].x, IN[1].yyyy
> 36:   MOV TEMP[6].x, IN[1].yyyy
> 37: ELSE :0
> 38:   ADD TEMP[7].x, IN[0].yyyy, IMM[1].zzzz
> 39:   ADD TEMP[7].x, TEMP[7].xxxx, -IN[1].xxxx
> 40:   RCP TEMP[8].x, IN[0].wwww
> 41:   MAD TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx, IN[1].yyyy
> 42:   ADD TEMP[7].x, IN[0].yyyy, IMM[1].wwww
> 43:   ADD TEMP[7].x, TEMP[7].xxxx, -IN[1].xxxx
> 44:   RCP TEMP[8].x, IN[0].wwww
> 45:   MAD TEMP[6].x, TEMP[7].xxxx, TEMP[8].xxxx, IN[1].yyyy
> 46: ENDIF
> 47: ADD TEMP[7].x, IN[0].xxxx, IMM[1].zzzz
> 48: SGE TEMP[7].x, TEMP[7].xxxx, TEMP[3].xxxx
> 49: F2I TEMP[7].x, -TEMP[7]
> 50: ADD TEMP[8].x, IN[0].xxxx, IMM[1].zzzz
> 51: SGE TEMP[8].x, TEMP[8].xxxx, TEMP[4].xxxx
> 52: F2I TEMP[8].x, -TEMP[8]
> 53: AND TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
> 54: ADD TEMP[8].x, IN[0].xxxx, IMM[1].wwww
> 55: SGE TEMP[8].x, TEMP[5].xxxx, TEMP[8].xxxx
> 56: F2I TEMP[8].x, -TEMP[8]
> 57: AND TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
> 58: ADD TEMP[8].x, IN[0].xxxx, IMM[1].wwww
> 59: SGE TEMP[8].x, TEMP[6].xxxx, TEMP[8].xxxx
> 60: F2I TEMP[8].x, -TEMP[8]
> 61: AND TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
> 62: ADD TEMP[8].x, IN[0].yyyy, IMM[1].zzzz
> 63: SGE TEMP[8].x, TEMP[8].xxxx, IN[2].wwww
> 64: F2I TEMP[8].x, -TEMP[8]
> 65: AND TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
> 66: ADD TEMP[8].x, IN[0].yyyy, IMM[1].wwww
> 67: SGE TEMP[8].x, IN[2].zzzz, TEMP[8].xxxx
> 68: F2I TEMP[8].x, -TEMP[8]
> 69: AND TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx
> 70: UIF TEMP[7].xxxx :0
> 71:   MOV TEMP[7].x, IMM[2].xxxx
> 72:   MOV TEMP[0].x, IMM[0].yyyy
> 73: ELSE :0
> 74:   ADD TEMP[8].x, IN[0].yyyy, IMM[1].wwww
> 75:   SLT TEMP[8].x, TEMP[8].xxxx, IN[2].wwww
> 76:   F2I TEMP[8].x, -TEMP[8]
> 77:   ADD TEMP[9].x, IN[0].yyyy, IMM[1].zzzz
> 78:   SLT TEMP[9].x, IN[2].zzzz, TEMP[9].xxxx
> 79:   F2I TEMP[9].x, -TEMP[9]
> 80:   OR TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
> 81:   UIF TEMP[8].xxxx :0
> 82:     MOV TEMP[7].x, IMM[2].yyyy
> 83:     MOV TEMP[0].x, IMM[0].yyyy
> 84:   ELSE :0
> 85:     ADD TEMP[8].x, IN[0].xxxx, IMM[1].zzzz
> 86:     SLT TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx
> 87:     F2I TEMP[5].x, -TEMP[5]
> 88:     ADD TEMP[8].x, IN[0].xxxx, IMM[1].zzzz
> 89:     SLT TEMP[6].x, TEMP[6].xxxx, TEMP[8].xxxx
> 90:     F2I TEMP[6].x, -TEMP[6]
> 91:     AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
> 92:     ADD TEMP[6].x, IN[0].xxxx, IMM[1].wwww
> 93:     SLT TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
> 94:     F2I TEMP[3].x, -TEMP[3]
> 95:     ADD TEMP[6].x, IN[0].xxxx, IMM[1].wwww
> 96:     SLT TEMP[4].x, TEMP[6].xxxx, TEMP[4].xxxx
> 97:     F2I TEMP[4].x, -TEMP[4]
> 98:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
> 99:     OR TEMP[3].x, TEMP[5].xxxx, TEMP[3].xxxx
>100:     UIF TEMP[3].xxxx :0
>101:       MOV TEMP[7].x, IMM[2].yyyy
>102:       MOV TEMP[0].x, IMM[0].yyyy
>103:     ENDIF
>104:   ENDIF
>105: ENDIF
>106: UIF TEMP[0].xxxx :0
>107:   ADD TEMP[3].x, IN[0].yyyy, IMM[1].zzzz
>108:   SGE TEMP[3].x, TEMP[3].xxxx, IN[2].wwww
>109:   F2I TEMP[3].x, -TEMP[3]
>110:   UIF TEMP[3].xxxx :0
>111:     ADD TEMP[3].x, IN[0].yyyy, IMM[1].zzzz
>112:   ELSE :0
>113:     MOV TEMP[3].x, IN[2].wwww
>114:   ENDIF
>115:   ADD TEMP[4].x, IN[0].yyyy, IMM[1].wwww
>116:   SGE TEMP[4].x, IN[2].zzzz, TEMP[4].xxxx
>117:   F2I TEMP[4].x, -TEMP[4]
>118:   UIF TEMP[4].xxxx :0
>119:     ADD TEMP[4].x, IN[0].yyyy, IMM[1].wwww
>120:   ELSE :0
>121:     MOV TEMP[4].x, IN[2].zzzz
>122:   ENDIF
>123:   ADD TEMP[5].x, IN[0].xxxx, IMM[1].zzzz
>124:   ADD TEMP[6].x, IN[0].xxxx, IMM[1].wwww
>125:   ADD TEMP[8].x, TEMP[4].xxxx, -TEMP[3].xxxx
>126:   MOV TEMP[0].x, TEMP[8].xxxx
>127:   USEQ TEMP[9].x, TEMP[1].xxxx, IMM[0].xxxx
>128:   ADD TEMP[10].x, IN[0].xxxx, IMM[1].zzzz
>129:   SLT TEMP[10].x, TEMP[10].xxxx, IN[2].yyyy
>130:   F2I TEMP[10].x, -TEMP[10]
>131:   ADD TEMP[11].x, IN[0].xxxx, IMM[1].wwww
>132:   SLT TEMP[11].x, IN[2].yyyy, TEMP[11].xxxx
>133:   F2I TEMP[11].x, -TEMP[11]
>134:   AND TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>135:   AND TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>136:   UIF TEMP[9].xxxx :0
>137:     MOV TEMP[5].x, IN[2].yyyy
>138:   ENDIF
>139:   USEQ TEMP[9].x, TEMP[2].xxxx, IMM[0].xxxx
>140:   ADD TEMP[10].x, IN[0].xxxx, IMM[1].zzzz
>141:   SLT TEMP[10].x, TEMP[10].xxxx, IN[1].yyyy
>142:   F2I TEMP[10].x, -TEMP[10]
>143:   ADD TEMP[11].x, IN[0].xxxx, IMM[1].wwww
>144:   SLT TEMP[11].x, IN[1].yyyy, TEMP[11].xxxx
>145:   F2I TEMP[11].x, -TEMP[11]
>146:   AND TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>147:   AND TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>148:   UIF TEMP[9].xxxx :0
>149:     MOV TEMP[6].x, IN[1].yyyy
>150:   ENDIF
>151:   SGE TEMP[9].x, TEMP[3].xxxx, TEMP[4].xxxx
>152:   F2I TEMP[9].x, -TEMP[9]
>153:   SGE TEMP[10].x, TEMP[5].xxxx, TEMP[6].xxxx
>154:   F2I TEMP[10].x, -TEMP[10]
>155:   OR TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>156:   UIF TEMP[9].xxxx :0
>157:     MOV TEMP[7].x, IMM[2].yyyy
>158:   ELSE :0
>159:     ADD TEMP[9].x, TEMP[6].xxxx, -TEMP[5].xxxx
>160:     MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
>161:     MOV TEMP[0].x, TEMP[8].xxxx
>162:     USEQ TEMP[9].x, TEMP[1].xxxx, IMM[0].xxxx
>163:     USEQ TEMP[10].x, TEMP[2].xxxx, IMM[0].xxxx
>164:     AND TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>165:     UIF TEMP[9].xxxx :0
>166:       MOV TEMP[7].x, TEMP[8].xxxx
>167:     ELSE :0
>168:       USNE TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
>169:       UIF TEMP[1].xxxx :0
>170:         ADD TEMP[1].x, TEMP[3].xxxx, -IN[2].xxxx
>171:         RCP TEMP[9].x, IN[1].wwww
>172:         MAD TEMP[1].x, TEMP[1].xxxx, TEMP[9].xxxx, IN[2].yyyy
>173:         ADD TEMP[9].x, TEMP[4].xxxx, -IN[2].xxxx
>174:         RCP TEMP[10].x, IN[1].wwww
>175:         MAD TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx, IN[2].yyyy
>176:         SLT TEMP[10].x, IN[1].wwww, IMM[2].yyyy
>177:         F2I TEMP[10].x, -TEMP[10]
>178:         SLT TEMP[11].x, TEMP[5].xxxx, TEMP[1].xxxx
>179:         F2I TEMP[11].x, -TEMP[11]
>180:         AND TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>181:         UIF TEMP[10].xxxx :0
>182:           ADD TEMP[10].x, TEMP[5].xxxx, -IN[2].yyyy
>183:           MAD TEMP[10].x, IN[1].wwww, TEMP[10].xxxx, IN[2].xxxx
>184:           SLT TEMP[11].x, TEMP[5].xxxx, TEMP[1].xxxx
>185:           F2I TEMP[11].x, -TEMP[11]
>186:           SLT TEMP[12].x, TEMP[3].xxxx, TEMP[10].xxxx
>187:           F2I TEMP[12].x, -TEMP[12]
>188:           AND TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx
>189:           UIF TEMP[11].xxxx :0
>190:             ADD TEMP[11].x, TEMP[1].xxxx, -TEMP[5].xxxx
>191:             MUL TEMP[11].x, IMM[1].wwww, TEMP[11].xxxx
>192:             ADD TEMP[12].x, TEMP[10].xxxx, -TEMP[3].xxxx
>193:             MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx
>194:             MOV TEMP[12].x, TEMP[11].xxxx
>195:             SLT TEMP[13].x, TEMP[6].xxxx, TEMP[1].xxxx
>196:             F2I TEMP[13].x, -TEMP[13]
>197:             UIF TEMP[13].xxxx :0
>198:               ADD TEMP[13].x, TEMP[1].xxxx, -TEMP[6].xxxx
>199:               MUL TEMP[13].x, IMM[1].wwww, TEMP[13].xxxx
>200:               ADD TEMP[14].x, TEMP[6].xxxx, -IN[2].yyyy
>201:               MAD TEMP[14].x, IN[1].wwww, TEMP[14].xxxx, IN[2].xxxx
>202:               ADD TEMP[14].x, TEMP[14].xxxx, -TEMP[3].xxxx
>203:               MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx
>204:               ADD TEMP[12].x, TEMP[11].xxxx, -TEMP[13].xxxx
>205:             ENDIF
>206:             SLT TEMP[11].x, TEMP[4].xxxx, TEMP[10].xxxx
>207:             F2I TEMP[11].x, -TEMP[11]
>208:             UIF TEMP[11].xxxx :0
>209:               ADD TEMP[11].x, TEMP[9].xxxx, -TEMP[5].xxxx
>210:               MUL TEMP[11].x, IMM[1].wwww, TEMP[11].xxxx
>211:               ADD TEMP[10].x, TEMP[10].xxxx, -TEMP[4].xxxx
>212:               MUL TEMP[10].x, TEMP[11].xxxx, TEMP[10].xxxx
>213:               ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[10].xxxx
>214:             ENDIF
>215:           ELSE :0
>216:             MOV TEMP[12].x, IMM[2].yyyy
>217:           ENDIF
>218:           ADD TEMP[10].x, TEMP[6].xxxx, -TEMP[5].xxxx
>219:           ADD TEMP[11].x, TEMP[4].xxxx, -TEMP[3].xxxx
>220:           MUL TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>221:           RCP TEMP[10].x, TEMP[10].xxxx
>222:           MUL TEMP[10].x, TEMP[12].xxxx, TEMP[10].xxxx
>223:           ADD TEMP[10].x, IMM[2].xxxx, -TEMP[10].xxxx
>224:           MUL TEMP[0].x, TEMP[8].xxxx, TEMP[10].xxxx
>225:         ELSE :0
>226:           SLT TEMP[8].x, IMM[2].yyyy, IN[1].wwww
>227:           F2I TEMP[8].x, -TEMP[8]
>228:           SLT TEMP[10].x, TEMP[5].xxxx, TEMP[9].xxxx
>229:           F2I TEMP[10].x, -TEMP[10]
>230:           AND TEMP[8].x, TEMP[8].xxxx, TEMP[10].xxxx
>231:           UIF TEMP[8].xxxx :0
>232:             ADD TEMP[8].x, TEMP[6].xxxx, -IN[2].yyyy
>233:             MAD TEMP[8].x, IN[1].wwww, TEMP[8].xxxx, IN[2].xxxx
>234:             SLT TEMP[10].x, TEMP[1].xxxx, TEMP[6].xxxx
>235:             F2I TEMP[10].x, -TEMP[10]
>236:             SLT TEMP[11].x, TEMP[3].xxxx, TEMP[8].xxxx
>237:             F2I TEMP[11].x, -TEMP[11]
>238:             AND TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>239:             UIF TEMP[10].xxxx :0
>240:               ADD TEMP[10].x, TEMP[6].xxxx, -TEMP[1].xxxx
>241:               MUL TEMP[10].x, IMM[1].wwww, TEMP[10].xxxx
>242:               ADD TEMP[11].x, TEMP[8].xxxx, -TEMP[3].xxxx
>243:               MUL TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
>244:               MOV TEMP[12].x, TEMP[10].xxxx
>245:               SLT TEMP[11].x, TEMP[1].xxxx, TEMP[5].xxxx
>246:               F2I TEMP[11].x, -TEMP[11]
>247:               UIF TEMP[11].xxxx :0
>248:                 ADD TEMP[1].x, TEMP[5].xxxx, -TEMP[1].xxxx
>249:                 MUL TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx
>250:                 ADD TEMP[11].x, TEMP[5].xxxx, -IN[2].yyyy
>251:                 MAD TEMP[11].x, IN[1].wwww, TEMP[11].xxxx, IN[2].xxxx
>252:                 ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[3].xxxx
>253:                 MUL TEMP[1].x, TEMP[1].xxxx, TEMP[11].xxxx
>254:                 ADD TEMP[12].x, TEMP[10].xxxx, -TEMP[1].xxxx
>255:               ENDIF
>256:               SLT TEMP[1].x, TEMP[4].xxxx, TEMP[8].xxxx
>257:               F2I TEMP[1].x, -TEMP[1]
>258:               UIF TEMP[1].xxxx :0
>259:                 ADD TEMP[1].x, TEMP[6].xxxx, -TEMP[9].xxxx
>260:                 MUL TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx
>261:                 ADD TEMP[8].x, TEMP[8].xxxx, -TEMP[4].xxxx
>262:                 MUL TEMP[1].x, TEMP[1].xxxx, TEMP[8].xxxx
>263:                 ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[1].xxxx
>264:               ENDIF
>265:             ELSE :0
>266:               MOV TEMP[12].x, IMM[2].yyyy
>267:             ENDIF
>268:             ADD TEMP[1].x, TEMP[6].xxxx, -TEMP[5].xxxx
>269:             ADD TEMP[8].x, TEMP[4].xxxx, -TEMP[3].xxxx
>270:             MUL TEMP[1].x, TEMP[1].xxxx, TEMP[8].xxxx
>271:             RCP TEMP[1].x, TEMP[1].xxxx
>272:             MUL TEMP[1].x, TEMP[12].xxxx, TEMP[1].xxxx
>273:             MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>274:           ENDIF
>275:         ENDIF
>276:       ENDIF
>277:       USNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx
>278:       UIF TEMP[1].xxxx :0
>279:         ADD TEMP[1].x, TEMP[3].xxxx, -IN[1].xxxx
>280:         RCP TEMP[2].x, IN[0].wwww
>281:         MAD TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx, IN[1].yyyy
>282:         ADD TEMP[2].x, TEMP[4].xxxx, -IN[1].xxxx
>283:         RCP TEMP[8].x, IN[0].wwww
>284:         MAD TEMP[2].x, TEMP[2].xxxx, TEMP[8].xxxx, IN[1].yyyy
>285:         SLT TEMP[8].x, IN[0].wwww, IMM[2].yyyy
>286:         F2I TEMP[8].x, -TEMP[8]
>287:         SLT TEMP[9].x, TEMP[2].xxxx, TEMP[6].xxxx
>288:         F2I TEMP[9].x, -TEMP[9]
>289:         AND TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
>290:         UIF TEMP[8].xxxx :0
>291:           ADD TEMP[8].x, TEMP[5].xxxx, -IN[1].yyyy
>292:           MAD TEMP[8].x, IN[0].wwww, TEMP[8].xxxx, IN[1].xxxx
>293:           SLT TEMP[9].x, TEMP[5].xxxx, TEMP[1].xxxx
>294:           F2I TEMP[9].x, -TEMP[9]
>295:           SLT TEMP[10].x, TEMP[3].xxxx, TEMP[8].xxxx
>296:           F2I TEMP[10].x, -TEMP[10]
>297:           AND TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>298:           UIF TEMP[9].xxxx :0
>299:             ADD TEMP[9].x, TEMP[1].xxxx, -TEMP[5].xxxx
>300:             MUL TEMP[9].x, IMM[1].wwww, TEMP[9].xxxx
>301:             ADD TEMP[10].x, TEMP[8].xxxx, -TEMP[3].xxxx
>302:             MUL TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
>303:             MOV TEMP[10].x, TEMP[9].xxxx
>304:             SLT TEMP[11].x, TEMP[6].xxxx, TEMP[1].xxxx
>305:             F2I TEMP[11].x, -TEMP[11]
>306:             UIF TEMP[11].xxxx :0
>307:               ADD TEMP[11].x, TEMP[1].xxxx, -TEMP[6].xxxx
>308:               MUL TEMP[11].x, IMM[1].wwww, TEMP[11].xxxx
>309:               ADD TEMP[12].x, TEMP[6].xxxx, -IN[1].yyyy
>310:               MAD TEMP[12].x, IN[0].wwww, TEMP[12].xxxx, IN[1].xxxx
>311:               ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[3].xxxx
>312:               MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx
>313:               ADD TEMP[10].x, TEMP[9].xxxx, -TEMP[11].xxxx
>314:             ENDIF
>315:             SLT TEMP[9].x, TEMP[4].xxxx, TEMP[8].xxxx
>316:             F2I TEMP[9].x, -TEMP[9]
>317:             UIF TEMP[9].xxxx :0
>318:               ADD TEMP[9].x, TEMP[2].xxxx, -TEMP[5].xxxx
>319:               MUL TEMP[9].x, IMM[1].wwww, TEMP[9].xxxx
>320:               ADD TEMP[8].x, TEMP[8].xxxx, -TEMP[4].xxxx
>321:               MUL TEMP[8].x, TEMP[9].xxxx, TEMP[8].xxxx
>322:               ADD TEMP[10].x, TEMP[10].xxxx, -TEMP[8].xxxx
>323:             ENDIF
>324:           ELSE :0
>325:             MOV TEMP[10].x, IMM[2].yyyy
>326:           ENDIF
>327:           ADD TEMP[8].x, TEMP[6].xxxx, -TEMP[5].xxxx
>328:           ADD TEMP[9].x, TEMP[4].xxxx, -TEMP[3].xxxx
>329:           MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
>330:           RCP TEMP[8].x, TEMP[8].xxxx
>331:           MUL TEMP[8].x, TEMP[10].xxxx, TEMP[8].xxxx
>332:           MUL TEMP[0].x, TEMP[0].xxxx, TEMP[8].xxxx
>333:         ELSE :0
>334:           SLT TEMP[8].x, IMM[2].yyyy, IN[0].wwww
>335:           F2I TEMP[8].x, -TEMP[8]
>336:           SLT TEMP[9].x, TEMP[1].xxxx, TEMP[6].xxxx
>337:           F2I TEMP[9].x, -TEMP[9]
>338:           AND TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
>339:           UIF TEMP[8].xxxx :0
>340:             ADD TEMP[8].x, TEMP[6].xxxx, -IN[1].yyyy
>341:             MAD TEMP[8].x, IN[0].wwww, TEMP[8].xxxx, IN[1].xxxx
>342:             SLT TEMP[9].x, TEMP[1].xxxx, TEMP[6].xxxx
>343:             F2I TEMP[9].x, -TEMP[9]
>344:             SLT TEMP[11].x, TEMP[3].xxxx, TEMP[8].xxxx
>345:             F2I TEMP[11].x, -TEMP[11]
>346:             AND TEMP[9].x, TEMP[9].xxxx, TEMP[11].xxxx
>347:             UIF TEMP[9].xxxx :0
>348:               ADD TEMP[9].x, TEMP[6].xxxx, -TEMP[1].xxxx
>349:               MUL TEMP[9].x, IMM[1].wwww, TEMP[9].xxxx
>350:               ADD TEMP[11].x, TEMP[8].xxxx, -TEMP[3].xxxx
>351:               MUL TEMP[9].x, TEMP[9].xxxx, TEMP[11].xxxx
>352:               MOV TEMP[10].x, TEMP[9].xxxx
>353:               SLT TEMP[11].x, TEMP[1].xxxx, TEMP[5].xxxx
>354:               F2I TEMP[11].x, -TEMP[11]
>355:               UIF TEMP[11].xxxx :0
>356:                 ADD TEMP[1].x, TEMP[5].xxxx, -TEMP[1].xxxx
>357:                 MUL TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx
>358:                 ADD TEMP[11].x, TEMP[5].xxxx, -IN[1].yyyy
>359:                 MAD TEMP[11].x, IN[0].wwww, TEMP[11].xxxx, IN[1].xxxx
>360:                 ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[3].xxxx
>361:                 MUL TEMP[1].x, TEMP[1].xxxx, TEMP[11].xxxx
>362:                 ADD TEMP[10].x, TEMP[9].xxxx, -TEMP[1].xxxx
>363:               ENDIF
>364:               SLT TEMP[1].x, TEMP[4].xxxx, TEMP[8].xxxx
>365:               F2I TEMP[1].x, -TEMP[1]
>366:               UIF TEMP[1].xxxx :0
>367:                 ADD TEMP[1].x, TEMP[6].xxxx, -TEMP[2].xxxx
>368:                 MUL TEMP[1].x, IMM[1].wwww, TEMP[1].xxxx
>369:                 ADD TEMP[2].x, TEMP[8].xxxx, -TEMP[4].xxxx
>370:                 MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
>371:                 ADD TEMP[10].x, TEMP[10].xxxx, -TEMP[1].xxxx
>372:               ENDIF
>373:             ELSE :0
>374:               MOV TEMP[10].x, IMM[2].yyyy
>375:             ENDIF
>376:             ADD TEMP[1].x, TEMP[6].xxxx, -TEMP[5].xxxx
>377:             ADD TEMP[2].x, TEMP[4].xxxx, -TEMP[3].xxxx
>378:             MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
>379:             RCP TEMP[1].x, TEMP[1].xxxx
>380:             MUL TEMP[1].x, TEMP[10].xxxx, TEMP[1].xxxx
>381:             ADD TEMP[1].x, IMM[2].xxxx, -TEMP[1].xxxx
>382:             MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>383:           ENDIF
>384:         ENDIF
>385:       ENDIF
>386:       MOV TEMP[7].x, TEMP[0].xxxx
>387:     ENDIF
>388:   ENDIF
>389: ENDIF
>390: MOV TEMP[0].xyz, IMM[2].yyyy
>391: MOV TEMP[0].w, TEMP[7].xxxx
>392: MOV OUT[0], TEMP[0]
>393: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %21 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %22 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %23 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %32 = fadd float %26, -1.000000e+00
>  %33 = call float @fabs(float %32)
>  %34 = fcmp uge float 0x3F1A36E2E0000000, %33
>  %35 = select i1 %34, float 1.000000e+00, float 0.000000e+00
>  %36 = fsub float -0.000000e+00, %35
>  %37 = fptosi float %36 to i32
>  %38 = bitcast i32 %37 to float
>  %39 = bitcast float %38 to i32
>  %40 = icmp ne i32 %39, 0
>  %. = select i1 %40, float 0xFFFFFFFFE0000000, float 0.000000e+00
>  %41 = fadd float %22, -1.000000e+00
>  %42 = call float @fabs(float %41)
>  %43 = fcmp uge float 0x3F1A36E2E0000000, %42
>  %44 = select i1 %43, float 1.000000e+00, float 0.000000e+00
>  %45 = fsub float -0.000000e+00, %44
>  %46 = fptosi float %45 to i32
>  %47 = bitcast i32 %46 to float
>  %48 = bitcast float %47 to i32
>  %49 = icmp ne i32 %48, 0
>  %temp8.0 = select i1 %49, float 0xFFFFFFFFE0000000, float 0.000000e+00
>  %50 = bitcast float %. to i32
>  %51 = icmp eq i32 %50, -1
>  %52 = sext i1 %51 to i32
>  %53 = bitcast i32 %52 to float
>  %54 = bitcast float %53 to i32
>  %55 = icmp ne i32 %54, 0
>  br i1 %55, label %ENDIF63, label %ELSE65
>
>ELSE65:                                           ; preds = %main_body
>  %56 = fadd float %21, -5.000000e-01
>  %57 = fsub float -0.000000e+00, %28
>  %58 = fadd float %56, %57
>  %59 = fdiv float 1.000000e+00, %27
>  %60 = fmul float %58, %59
>  %61 = fadd float %60, %29
>  %62 = fadd float %21, 5.000000e-01
>  %63 = fsub float -0.000000e+00, %28
>  %64 = fadd float %62, %63
>  %65 = fdiv float 1.000000e+00, %27
>  %66 = fmul float %64, %65
>  %67 = fadd float %66, %29
>  br label %ENDIF63
>
>ENDIF63:                                          ; preds = %main_body, %ELSE65
>  %temp16.0 = phi float [ %67, %ELSE65 ], [ %29, %main_body ]
>  %temp12.0 = phi float [ %61, %ELSE65 ], [ %29, %main_body ]
>  %68 = bitcast float %temp8.0 to i32
>  %69 = icmp eq i32 %68, -1
>  %70 = sext i1 %69 to i32
>  %71 = bitcast i32 %70 to float
>  %72 = bitcast float %71 to i32
>  %73 = icmp ne i32 %72, 0
>  br i1 %73, label %ENDIF66, label %ELSE68
>
>ELSE68:                                           ; preds = %ENDIF63
>  %74 = fadd float %21, -5.000000e-01
>  %75 = fsub float -0.000000e+00, %24
>  %76 = fadd float %74, %75
>  %77 = fdiv float 1.000000e+00, %23
>  %78 = fmul float %76, %77
>  %79 = fadd float %78, %25
>  %80 = fadd float %21, 5.000000e-01
>  %81 = fsub float -0.000000e+00, %24
>  %82 = fadd float %80, %81
>  %83 = fdiv float 1.000000e+00, %23
>  %84 = fmul float %82, %83
>  %85 = fadd float %84, %25
>  br label %ENDIF66
>
>ENDIF66:                                          ; preds = %ENDIF63, %ELSE68
>  %temp24.0 = phi float [ %85, %ELSE68 ], [ %25, %ENDIF63 ]
>  %temp20.0 = phi float [ %79, %ELSE68 ], [ %25, %ENDIF63 ]
>  %86 = fadd float %20, -5.000000e-01
>  %87 = fcmp uge float %86, %temp12.0
>  %88 = select i1 %87, float 1.000000e+00, float 0.000000e+00
>  %89 = fsub float -0.000000e+00, %88
>  %90 = fptosi float %89 to i32
>  %91 = bitcast i32 %90 to float
>  %92 = fadd float %20, -5.000000e-01
>  %93 = fcmp uge float %92, %temp16.0
>  %94 = select i1 %93, float 1.000000e+00, float 0.000000e+00
>  %95 = fsub float -0.000000e+00, %94
>  %96 = fptosi float %95 to i32
>  %97 = bitcast i32 %96 to float
>  %98 = bitcast float %91 to i32
>  %99 = bitcast float %97 to i32
>  %100 = and i32 %98, %99
>  %101 = bitcast i32 %100 to float
>  %102 = fadd float %20, 5.000000e-01
>  %103 = fcmp uge float %temp20.0, %102
>  %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00
>  %105 = fsub float -0.000000e+00, %104
>  %106 = fptosi float %105 to i32
>  %107 = bitcast i32 %106 to float
>  %108 = bitcast float %101 to i32
>  %109 = bitcast float %107 to i32
>  %110 = and i32 %108, %109
>  %111 = bitcast i32 %110 to float
>  %112 = fadd float %20, 5.000000e-01
>  %113 = fcmp uge float %temp24.0, %112
>  %114 = select i1 %113, float 1.000000e+00, float 0.000000e+00
>  %115 = fsub float -0.000000e+00, %114
>  %116 = fptosi float %115 to i32
>  %117 = bitcast i32 %116 to float
>  %118 = bitcast float %111 to i32
>  %119 = bitcast float %117 to i32
>  %120 = and i32 %118, %119
>  %121 = bitcast i32 %120 to float
>  %122 = fadd float %21, -5.000000e-01
>  %123 = fcmp uge float %122, %31
>  %124 = select i1 %123, float 1.000000e+00, float 0.000000e+00
>  %125 = fsub float -0.000000e+00, %124
>  %126 = fptosi float %125 to i32
>  %127 = bitcast i32 %126 to float
>  %128 = bitcast float %121 to i32
>  %129 = bitcast float %127 to i32
>  %130 = and i32 %128, %129
>  %131 = bitcast i32 %130 to float
>  %132 = fadd float %21, 5.000000e-01
>  %133 = fcmp uge float %30, %132
>  %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00
>  %135 = fsub float -0.000000e+00, %134
>  %136 = fptosi float %135 to i32
>  %137 = bitcast i32 %136 to float
>  %138 = bitcast float %131 to i32
>  %139 = bitcast float %137 to i32
>  %140 = and i32 %138, %139
>  %141 = bitcast i32 %140 to float
>  %142 = bitcast float %141 to i32
>  %143 = icmp ne i32 %142, 0
>  br i1 %143, label %ENDIF69, label %ELSE71
>
>ELSE71:                                           ; preds = %ENDIF66
>  %144 = fadd float %21, 5.000000e-01
>  %145 = fcmp ult float %144, %31
>  %146 = select i1 %145, float 1.000000e+00, float 0.000000e+00
>  %147 = fsub float -0.000000e+00, %146
>  %148 = fptosi float %147 to i32
>  %149 = bitcast i32 %148 to float
>  %150 = fadd float %21, -5.000000e-01
>  %151 = fcmp ult float %30, %150
>  %152 = select i1 %151, float 1.000000e+00, float 0.000000e+00
>  %153 = fsub float -0.000000e+00, %152
>  %154 = fptosi float %153 to i32
>  %155 = bitcast i32 %154 to float
>  %156 = bitcast float %149 to i32
>  %157 = bitcast float %155 to i32
>  %158 = or i32 %156, %157
>  %159 = bitcast i32 %158 to float
>  %160 = bitcast float %159 to i32
>  %161 = icmp ne i32 %160, 0
>  br i1 %161, label %ENDIF69, label %ELSE74
>
>ENDIF69:                                          ; preds = %ELSE74, %ELSE71, %ENDIF66
>  %temp28.0 = phi float [ 1.000000e+00, %ENDIF66 ], [ %.153, %ELSE74 ], [ 0.000000e+00, %ELSE71 ]
>  %temp.0 = phi float [ 0.000000e+00, %ENDIF66 ], [ %.154, %ELSE74 ], [ 0.000000e+00, %ELSE71 ]
>  %162 = bitcast float %temp.0 to i32
>  %163 = icmp ne i32 %162, 0
>  br i1 %163, label %IF79, label %ENDIF78
>
>ELSE74:                                           ; preds = %ELSE71
>  %164 = fadd float %20, -5.000000e-01
>  %165 = fcmp ult float %temp20.0, %164
>  %166 = select i1 %165, float 1.000000e+00, float 0.000000e+00
>  %167 = fsub float -0.000000e+00, %166
>  %168 = fptosi float %167 to i32
>  %169 = bitcast i32 %168 to float
>  %170 = fadd float %20, -5.000000e-01
>  %171 = fcmp ult float %temp24.0, %170
>  %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00
>  %173 = fsub float -0.000000e+00, %172
>  %174 = fptosi float %173 to i32
>  %175 = bitcast i32 %174 to float
>  %176 = bitcast float %169 to i32
>  %177 = bitcast float %175 to i32
>  %178 = and i32 %176, %177
>  %179 = bitcast i32 %178 to float
>  %180 = fadd float %20, 5.000000e-01
>  %181 = fcmp ult float %180, %temp12.0
>  %182 = select i1 %181, float 1.000000e+00, float 0.000000e+00
>  %183 = fsub float -0.000000e+00, %182
>  %184 = fptosi float %183 to i32
>  %185 = bitcast i32 %184 to float
>  %186 = fadd float %20, 5.000000e-01
>  %187 = fcmp ult float %186, %temp16.0
>  %188 = select i1 %187, float 1.000000e+00, float 0.000000e+00
>  %189 = fsub float -0.000000e+00, %188
>  %190 = fptosi float %189 to i32
>  %191 = bitcast i32 %190 to float
>  %192 = bitcast float %185 to i32
>  %193 = bitcast float %191 to i32
>  %194 = and i32 %192, %193
>  %195 = bitcast i32 %194 to float
>  %196 = bitcast float %179 to i32
>  %197 = bitcast float %195 to i32
>  %198 = or i32 %196, %197
>  %199 = bitcast i32 %198 to float
>  %200 = bitcast float %199 to i32
>  %201 = icmp ne i32 %200, 0
>  %.153 = select i1 %201, float 0.000000e+00, float %141
>  %.154 = select i1 %201, float 0.000000e+00, float 0xFFFFFFFFE0000000
>  br label %ENDIF69
>
>IF79:                                             ; preds = %ENDIF69
>  %202 = fadd float %21, -5.000000e-01
>  %203 = fcmp uge float %202, %31
>  %204 = select i1 %203, float 1.000000e+00, float 0.000000e+00
>  %205 = fsub float -0.000000e+00, %204
>  %206 = fptosi float %205 to i32
>  %207 = bitcast i32 %206 to float
>  %208 = bitcast float %207 to i32
>  %209 = icmp ne i32 %208, 0
>  %temp12.1 = select i1 %209, float %202, float %31
>  %210 = fadd float %21, 5.000000e-01
>  %211 = fcmp uge float %30, %210
>  %212 = select i1 %211, float 1.000000e+00, float 0.000000e+00
>  %213 = fsub float -0.000000e+00, %212
>  %214 = fptosi float %213 to i32
>  %215 = bitcast i32 %214 to float
>  %216 = bitcast float %215 to i32
>  %217 = icmp ne i32 %216, 0
>  %temp16.1 = select i1 %217, float %210, float %30
>  %218 = fadd float %20, -5.000000e-01
>  %219 = fadd float %20, 5.000000e-01
>  %220 = fsub float -0.000000e+00, %temp12.1
>  %221 = fadd float %temp16.1, %220
>  %222 = bitcast float %. to i32
>  %223 = icmp eq i32 %222, -1
>  %224 = sext i1 %223 to i32
>  %225 = bitcast i32 %224 to float
>  %226 = fadd float %20, -5.000000e-01
>  %227 = fcmp ult float %226, %29
>  %228 = select i1 %227, float 1.000000e+00, float 0.000000e+00
>  %229 = fsub float -0.000000e+00, %228
>  %230 = fptosi float %229 to i32
>  %231 = bitcast i32 %230 to float
>  %232 = fadd float %20, 5.000000e-01
>  %233 = fcmp ult float %29, %232
>  %234 = select i1 %233, float 1.000000e+00, float 0.000000e+00
>  %235 = fsub float -0.000000e+00, %234
>  %236 = fptosi float %235 to i32
>  %237 = bitcast i32 %236 to float
>  %238 = bitcast float %231 to i32
>  %239 = bitcast float %237 to i32
>  %240 = and i32 %238, %239
>  %241 = bitcast i32 %240 to float
>  %242 = bitcast float %225 to i32
>  %243 = bitcast float %241 to i32
>  %244 = and i32 %242, %243
>  %245 = bitcast i32 %244 to float
>  %246 = bitcast float %245 to i32
>  %247 = icmp ne i32 %246, 0
>  %.155 = select i1 %247, float %29, float %218
>  %248 = bitcast float %temp8.0 to i32
>  %249 = icmp eq i32 %248, -1
>  %250 = sext i1 %249 to i32
>  %251 = bitcast i32 %250 to float
>  %252 = fadd float %20, -5.000000e-01
>  %253 = fcmp ult float %252, %25
>  %254 = select i1 %253, float 1.000000e+00, float 0.000000e+00
>  %255 = fsub float -0.000000e+00, %254
>  %256 = fptosi float %255 to i32
>  %257 = bitcast i32 %256 to float
>  %258 = fadd float %20, 5.000000e-01
>  %259 = fcmp ult float %25, %258
>  %260 = select i1 %259, float 1.000000e+00, float 0.000000e+00
>  %261 = fsub float -0.000000e+00, %260
>  %262 = fptosi float %261 to i32
>  %263 = bitcast i32 %262 to float
>  %264 = bitcast float %257 to i32
>  %265 = bitcast float %263 to i32
>  %266 = and i32 %264, %265
>  %267 = bitcast i32 %266 to float
>  %268 = bitcast float %251 to i32
>  %269 = bitcast float %267 to i32
>  %270 = and i32 %268, %269
>  %271 = bitcast i32 %270 to float
>  %272 = bitcast float %271 to i32
>  %273 = icmp ne i32 %272, 0
>  %temp24.1 = select i1 %273, float %25, float %219
>  %274 = fcmp uge float %temp12.1, %temp16.1
>  %275 = select i1 %274, float 1.000000e+00, float 0.000000e+00
>  %276 = fsub float -0.000000e+00, %275
>  %277 = fptosi float %276 to i32
>  %278 = bitcast i32 %277 to float
>  %279 = fcmp uge float %.155, %temp24.1
>  %280 = select i1 %279, float 1.000000e+00, float 0.000000e+00
>  %281 = fsub float -0.000000e+00, %280
>  %282 = fptosi float %281 to i32
>  %283 = bitcast i32 %282 to float
>  %284 = bitcast float %278 to i32
>  %285 = bitcast float %283 to i32
>  %286 = or i32 %284, %285
>  %287 = bitcast i32 %286 to float
>  %288 = bitcast float %287 to i32
>  %289 = icmp ne i32 %288, 0
>  br i1 %289, label %ENDIF78, label %ELSE95
>
>ENDIF78:                                          ; preds = %ENDIF144, %ELSE131, %ENDIF132, %ENDIF99, %ELSE95, %IF79, %ENDIF69
>  %temp28.3 = phi float [ %temp28.0, %ENDIF69 ], [ 0.000000e+00, %IF79 ], [ %296, %ELSE95 ], [ %temp.3, %ENDIF99 ], [ %584, %ENDIF132 ], [ %654, %ENDIF144 ], [ %temp.3, %ELSE131 ]
>  %290 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %291 = bitcast i32 %290 to float
>  %292 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %temp28.3)
>  %293 = bitcast i32 %292 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %291, float %293, float %291, float %293)
>  ret void
>
>ELSE95:                                           ; preds = %IF79
>  %294 = fsub float -0.000000e+00, %.155
>  %295 = fadd float %temp24.1, %294
>  %296 = fmul float %221, %295
>  %297 = bitcast float %. to i32
>  %298 = icmp eq i32 %297, -1
>  %299 = sext i1 %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = bitcast float %temp8.0 to i32
>  %302 = icmp eq i32 %301, -1
>  %303 = sext i1 %302 to i32
>  %304 = bitcast i32 %303 to float
>  %305 = bitcast float %300 to i32
>  %306 = bitcast float %304 to i32
>  %307 = and i32 %305, %306
>  %308 = bitcast i32 %307 to float
>  %309 = bitcast float %308 to i32
>  %310 = icmp ne i32 %309, 0
>  br i1 %310, label %ENDIF78, label %ELSE98
>
>ELSE98:                                           ; preds = %ELSE95
>  %311 = bitcast float %. to i32
>  %312 = icmp ne i32 %311, -1
>  %313 = sext i1 %312 to i32
>  %314 = bitcast i32 %313 to float
>  %315 = bitcast float %314 to i32
>  %316 = icmp ne i32 %315, 0
>  br i1 %316, label %IF100, label %ENDIF99
>
>IF100:                                            ; preds = %ELSE98
>  %317 = fsub float -0.000000e+00, %28
>  %318 = fadd float %temp12.1, %317
>  %319 = fdiv float 1.000000e+00, %27
>  %320 = fmul float %318, %319
>  %321 = fadd float %320, %29
>  %322 = fsub float -0.000000e+00, %28
>  %323 = fadd float %temp16.1, %322
>  %324 = fdiv float 1.000000e+00, %27
>  %325 = fmul float %323, %324
>  %326 = fadd float %325, %29
>  %327 = fcmp ult float %27, 0.000000e+00
>  %328 = select i1 %327, float 1.000000e+00, float 0.000000e+00
>  %329 = fsub float -0.000000e+00, %328
>  %330 = fptosi float %329 to i32
>  %331 = bitcast i32 %330 to float
>  %332 = fcmp ult float %.155, %321
>  %333 = select i1 %332, float 1.000000e+00, float 0.000000e+00
>  %334 = fsub float -0.000000e+00, %333
>  %335 = fptosi float %334 to i32
>  %336 = bitcast i32 %335 to float
>  %337 = bitcast float %331 to i32
>  %338 = bitcast float %336 to i32
>  %339 = and i32 %337, %338
>  %340 = bitcast i32 %339 to float
>  %341 = bitcast float %340 to i32
>  %342 = icmp ne i32 %341, 0
>  br i1 %342, label %IF103, label %ELSE104
>
>ENDIF99:                                          ; preds = %ENDIF117, %ELSE104, %ENDIF105, %ELSE98
>  %temp.3 = phi float [ %296, %ELSE98 ], [ %407, %ENDIF105 ], [ %475, %ENDIF117 ], [ %296, %ELSE104 ]
>  %343 = bitcast float %temp8.0 to i32
>  %344 = icmp ne i32 %343, -1
>  %345 = sext i1 %344 to i32
>  %346 = bitcast i32 %345 to float
>  %347 = bitcast float %346 to i32
>  %348 = icmp ne i32 %347, 0
>  br i1 %348, label %IF127, label %ENDIF78
>
>IF103:                                            ; preds = %IF100
>  %349 = fsub float -0.000000e+00, %29
>  %350 = fadd float %.155, %349
>  %351 = fmul float %27, %350
>  %352 = fadd float %351, %28
>  %353 = fcmp ult float %.155, %321
>  %354 = select i1 %353, float 1.000000e+00, float 0.000000e+00
>  %355 = fsub float -0.000000e+00, %354
>  %356 = fptosi float %355 to i32
>  %357 = bitcast i32 %356 to float
>  %358 = fcmp ult float %temp12.1, %352
>  %359 = select i1 %358, float 1.000000e+00, float 0.000000e+00
>  %360 = fsub float -0.000000e+00, %359
>  %361 = fptosi float %360 to i32
>  %362 = bitcast i32 %361 to float
>  %363 = bitcast float %357 to i32
>  %364 = bitcast float %362 to i32
>  %365 = and i32 %363, %364
>  %366 = bitcast i32 %365 to float
>  %367 = bitcast float %366 to i32
>  %368 = icmp ne i32 %367, 0
>  br i1 %368, label %IF106, label %ENDIF105
>
>ELSE104:                                          ; preds = %IF100
>  %369 = fcmp ult float 0.000000e+00, %27
>  %370 = select i1 %369, float 1.000000e+00, float 0.000000e+00
>  %371 = fsub float -0.000000e+00, %370
>  %372 = fptosi float %371 to i32
>  %373 = bitcast i32 %372 to float
>  %374 = fcmp ult float %.155, %326
>  %375 = select i1 %374, float 1.000000e+00, float 0.000000e+00
>  %376 = fsub float -0.000000e+00, %375
>  %377 = fptosi float %376 to i32
>  %378 = bitcast i32 %377 to float
>  %379 = bitcast float %373 to i32
>  %380 = bitcast float %378 to i32
>  %381 = and i32 %379, %380
>  %382 = bitcast i32 %381 to float
>  %383 = bitcast float %382 to i32
>  %384 = icmp ne i32 %383, 0
>  br i1 %384, label %IF115, label %ENDIF99
>
>IF106:                                            ; preds = %IF103
>  %385 = fsub float -0.000000e+00, %.155
>  %386 = fadd float %321, %385
>  %387 = fmul float 5.000000e-01, %386
>  %388 = fsub float -0.000000e+00, %temp12.1
>  %389 = fadd float %352, %388
>  %390 = fmul float %387, %389
>  %391 = fcmp ult float %temp24.1, %321
>  %392 = select i1 %391, float 1.000000e+00, float 0.000000e+00
>  %393 = fsub float -0.000000e+00, %392
>  %394 = fptosi float %393 to i32
>  %395 = bitcast i32 %394 to float
>  %396 = bitcast float %395 to i32
>  %397 = icmp ne i32 %396, 0
>  br i1 %397, label %IF109, label %ENDIF108
>
>ENDIF105:                                         ; preds = %IF112, %ENDIF108, %IF103
>  %temp48.0 = phi float [ 0.000000e+00, %IF103 ], [ %434, %IF112 ], [ %temp48.1, %ENDIF108 ]
>  %398 = fsub float -0.000000e+00, %.155
>  %399 = fadd float %temp24.1, %398
>  %400 = fsub float -0.000000e+00, %temp12.1
>  %401 = fadd float %temp16.1, %400
>  %402 = fmul float %399, %401
>  %403 = fdiv float 1.000000e+00, %402
>  %404 = fmul float %temp48.0, %403
>  %405 = fsub float -0.000000e+00, %404
>  %406 = fadd float 1.000000e+00, %405
>  %407 = fmul float %296, %406
>  br label %ENDIF99
>
>IF109:                                            ; preds = %IF106
>  %408 = fsub float -0.000000e+00, %temp24.1
>  %409 = fadd float %321, %408
>  %410 = fmul float 5.000000e-01, %409
>  %411 = fsub float -0.000000e+00, %29
>  %412 = fadd float %temp24.1, %411
>  %413 = fmul float %27, %412
>  %414 = fadd float %413, %28
>  %415 = fsub float -0.000000e+00, %temp12.1
>  %416 = fadd float %414, %415
>  %417 = fmul float %410, %416
>  %418 = fsub float -0.000000e+00, %417
>  %419 = fadd float %390, %418
>  br label %ENDIF108
>
>ENDIF108:                                         ; preds = %IF106, %IF109
>  %temp48.1 = phi float [ %419, %IF109 ], [ %390, %IF106 ]
>  %420 = fcmp ult float %temp16.1, %352
>  %421 = select i1 %420, float 1.000000e+00, float 0.000000e+00
>  %422 = fsub float -0.000000e+00, %421
>  %423 = fptosi float %422 to i32
>  %424 = bitcast i32 %423 to float
>  %425 = bitcast float %424 to i32
>  %426 = icmp ne i32 %425, 0
>  br i1 %426, label %IF112, label %ENDIF105
>
>IF112:                                            ; preds = %ENDIF108
>  %427 = fsub float -0.000000e+00, %.155
>  %428 = fadd float %326, %427
>  %429 = fmul float 5.000000e-01, %428
>  %430 = fsub float -0.000000e+00, %temp16.1
>  %431 = fadd float %352, %430
>  %432 = fmul float %429, %431
>  %433 = fsub float -0.000000e+00, %432
>  %434 = fadd float %temp48.1, %433
>  br label %ENDIF105
>
>IF115:                                            ; preds = %ELSE104
>  %435 = fsub float -0.000000e+00, %29
>  %436 = fadd float %temp24.1, %435
>  %437 = fmul float %27, %436
>  %438 = fadd float %437, %28
>  %439 = fcmp ult float %321, %temp24.1
>  %440 = select i1 %439, float 1.000000e+00, float 0.000000e+00
>  %441 = fsub float -0.000000e+00, %440
>  %442 = fptosi float %441 to i32
>  %443 = bitcast i32 %442 to float
>  %444 = fcmp ult float %temp12.1, %438
>  %445 = select i1 %444, float 1.000000e+00, float 0.000000e+00
>  %446 = fsub float -0.000000e+00, %445
>  %447 = fptosi float %446 to i32
>  %448 = bitcast i32 %447 to float
>  %449 = bitcast float %443 to i32
>  %450 = bitcast float %448 to i32
>  %451 = and i32 %449, %450
>  %452 = bitcast i32 %451 to float
>  %453 = bitcast float %452 to i32
>  %454 = icmp ne i32 %453, 0
>  br i1 %454, label %IF118, label %ENDIF117
>
>IF118:                                            ; preds = %IF115
>  %455 = fsub float -0.000000e+00, %321
>  %456 = fadd float %temp24.1, %455
>  %457 = fmul float 5.000000e-01, %456
>  %458 = fsub float -0.000000e+00, %temp12.1
>  %459 = fadd float %438, %458
>  %460 = fmul float %457, %459
>  %461 = fcmp ult float %321, %.155
>  %462 = select i1 %461, float 1.000000e+00, float 0.000000e+00
>  %463 = fsub float -0.000000e+00, %462
>  %464 = fptosi float %463 to i32
>  %465 = bitcast i32 %464 to float
>  %466 = bitcast float %465 to i32
>  %467 = icmp ne i32 %466, 0
>  br i1 %467, label %IF121, label %ENDIF120
>
>ENDIF117:                                         ; preds = %IF124, %ENDIF120, %IF115
>  %temp48.3 = phi float [ 0.000000e+00, %IF115 ], [ %501, %IF124 ], [ %temp48.4, %ENDIF120 ]
>  %468 = fsub float -0.000000e+00, %.155
>  %469 = fadd float %temp24.1, %468
>  %470 = fsub float -0.000000e+00, %temp12.1
>  %471 = fadd float %temp16.1, %470
>  %472 = fmul float %469, %471
>  %473 = fdiv float 1.000000e+00, %472
>  %474 = fmul float %temp48.3, %473
>  %475 = fmul float %296, %474
>  br label %ENDIF99
>
>IF121:                                            ; preds = %IF118
>  %476 = fadd float %.155, %455
>  %477 = fmul float 5.000000e-01, %476
>  %478 = fsub float -0.000000e+00, %29
>  %479 = fadd float %.155, %478
>  %480 = fmul float %27, %479
>  %481 = fadd float %480, %28
>  %482 = fsub float -0.000000e+00, %temp12.1
>  %483 = fadd float %481, %482
>  %484 = fmul float %477, %483
>  %485 = fsub float -0.000000e+00, %484
>  %486 = fadd float %460, %485
>  br label %ENDIF120
>
>ENDIF120:                                         ; preds = %IF118, %IF121
>  %temp48.4 = phi float [ %486, %IF121 ], [ %460, %IF118 ]
>  %487 = fcmp ult float %temp16.1, %438
>  %488 = select i1 %487, float 1.000000e+00, float 0.000000e+00
>  %489 = fsub float -0.000000e+00, %488
>  %490 = fptosi float %489 to i32
>  %491 = bitcast i32 %490 to float
>  %492 = bitcast float %491 to i32
>  %493 = icmp ne i32 %492, 0
>  br i1 %493, label %IF124, label %ENDIF117
>
>IF124:                                            ; preds = %ENDIF120
>  %494 = fsub float -0.000000e+00, %326
>  %495 = fadd float %temp24.1, %494
>  %496 = fmul float 5.000000e-01, %495
>  %497 = fsub float -0.000000e+00, %temp16.1
>  %498 = fadd float %438, %497
>  %499 = fmul float %496, %498
>  %500 = fsub float -0.000000e+00, %499
>  %501 = fadd float %temp48.4, %500
>  br label %ENDIF117
>
>IF127:                                            ; preds = %ENDIF99
>  %502 = fsub float -0.000000e+00, %24
>  %503 = fadd float %temp12.1, %502
>  %504 = fdiv float 1.000000e+00, %23
>  %505 = fmul float %503, %504
>  %506 = fadd float %505, %25
>  %507 = fsub float -0.000000e+00, %24
>  %508 = fadd float %temp16.1, %507
>  %509 = fdiv float 1.000000e+00, %23
>  %510 = fmul float %508, %509
>  %511 = fadd float %510, %25
>  %512 = fcmp ult float %23, 0.000000e+00
>  %513 = select i1 %512, float 1.000000e+00, float 0.000000e+00
>  %514 = fsub float -0.000000e+00, %513
>  %515 = fptosi float %514 to i32
>  %516 = bitcast i32 %515 to float
>  %517 = fcmp ult float %511, %temp24.1
>  %518 = select i1 %517, float 1.000000e+00, float 0.000000e+00
>  %519 = fsub float -0.000000e+00, %518
>  %520 = fptosi float %519 to i32
>  %521 = bitcast i32 %520 to float
>  %522 = bitcast float %516 to i32
>  %523 = bitcast float %521 to i32
>  %524 = and i32 %522, %523
>  %525 = bitcast i32 %524 to float
>  %526 = bitcast float %525 to i32
>  %527 = icmp ne i32 %526, 0
>  br i1 %527, label %IF130, label %ELSE131
>
>IF130:                                            ; preds = %IF127
>  %528 = fsub float -0.000000e+00, %25
>  %529 = fadd float %.155, %528
>  %530 = fmul float %23, %529
>  %531 = fadd float %530, %24
>  %532 = fcmp ult float %.155, %506
>  %533 = select i1 %532, float 1.000000e+00, float 0.000000e+00
>  %534 = fsub float -0.000000e+00, %533
>  %535 = fptosi float %534 to i32
>  %536 = bitcast i32 %535 to float
>  %537 = fcmp ult float %temp12.1, %531
>  %538 = select i1 %537, float 1.000000e+00, float 0.000000e+00
>  %539 = fsub float -0.000000e+00, %538
>  %540 = fptosi float %539 to i32
>  %541 = bitcast i32 %540 to float
>  %542 = bitcast float %536 to i32
>  %543 = bitcast float %541 to i32
>  %544 = and i32 %542, %543
>  %545 = bitcast i32 %544 to float
>  %546 = bitcast float %545 to i32
>  %547 = icmp ne i32 %546, 0
>  br i1 %547, label %IF133, label %ENDIF132
>
>ELSE131:                                          ; preds = %IF127
>  %548 = fcmp ult float 0.000000e+00, %23
>  %549 = select i1 %548, float 1.000000e+00, float 0.000000e+00
>  %550 = fsub float -0.000000e+00, %549
>  %551 = fptosi float %550 to i32
>  %552 = bitcast i32 %551 to float
>  %553 = fcmp ult float %506, %temp24.1
>  %554 = select i1 %553, float 1.000000e+00, float 0.000000e+00
>  %555 = fsub float -0.000000e+00, %554
>  %556 = fptosi float %555 to i32
>  %557 = bitcast i32 %556 to float
>  %558 = bitcast float %552 to i32
>  %559 = bitcast float %557 to i32
>  %560 = and i32 %558, %559
>  %561 = bitcast i32 %560 to float
>  %562 = bitcast float %561 to i32
>  %563 = icmp ne i32 %562, 0
>  br i1 %563, label %IF142, label %ENDIF78
>
>IF133:                                            ; preds = %IF130
>  %564 = fsub float -0.000000e+00, %.155
>  %565 = fadd float %506, %564
>  %566 = fmul float 5.000000e-01, %565
>  %567 = fsub float -0.000000e+00, %temp12.1
>  %568 = fadd float %531, %567
>  %569 = fmul float %566, %568
>  %570 = fcmp ult float %temp24.1, %506
>  %571 = select i1 %570, float 1.000000e+00, float 0.000000e+00
>  %572 = fsub float -0.000000e+00, %571
>  %573 = fptosi float %572 to i32
>  %574 = bitcast i32 %573 to float
>  %575 = bitcast float %574 to i32
>  %576 = icmp ne i32 %575, 0
>  br i1 %576, label %IF136, label %ENDIF135
>
>ENDIF132:                                         ; preds = %IF139, %ENDIF135, %IF130
>  %temp40.0 = phi float [ 0.000000e+00, %IF130 ], [ %611, %IF139 ], [ %temp40.1, %ENDIF135 ]
>  %577 = fsub float -0.000000e+00, %.155
>  %578 = fadd float %temp24.1, %577
>  %579 = fsub float -0.000000e+00, %temp12.1
>  %580 = fadd float %temp16.1, %579
>  %581 = fmul float %578, %580
>  %582 = fdiv float 1.000000e+00, %581
>  %583 = fmul float %temp40.0, %582
>  %584 = fmul float %temp.3, %583
>  br label %ENDIF78
>
>IF136:                                            ; preds = %IF133
>  %585 = fsub float -0.000000e+00, %temp24.1
>  %586 = fadd float %506, %585
>  %587 = fmul float 5.000000e-01, %586
>  %588 = fsub float -0.000000e+00, %25
>  %589 = fadd float %temp24.1, %588
>  %590 = fmul float %23, %589
>  %591 = fadd float %590, %24
>  %592 = fsub float -0.000000e+00, %temp12.1
>  %593 = fadd float %591, %592
>  %594 = fmul float %587, %593
>  %595 = fsub float -0.000000e+00, %594
>  %596 = fadd float %569, %595
>  br label %ENDIF135
>
>ENDIF135:                                         ; preds = %IF133, %IF136
>  %temp40.1 = phi float [ %596, %IF136 ], [ %569, %IF133 ]
>  %597 = fcmp ult float %temp16.1, %531
>  %598 = select i1 %597, float 1.000000e+00, float 0.000000e+00
>  %599 = fsub float -0.000000e+00, %598
>  %600 = fptosi float %599 to i32
>  %601 = bitcast i32 %600 to float
>  %602 = bitcast float %601 to i32
>  %603 = icmp ne i32 %602, 0
>  br i1 %603, label %IF139, label %ENDIF132
>
>IF139:                                            ; preds = %ENDIF135
>  %604 = fsub float -0.000000e+00, %.155
>  %605 = fadd float %511, %604
>  %606 = fmul float 5.000000e-01, %605
>  %607 = fsub float -0.000000e+00, %temp16.1
>  %608 = fadd float %531, %607
>  %609 = fmul float %606, %608
>  %610 = fsub float -0.000000e+00, %609
>  %611 = fadd float %temp40.1, %610
>  br label %ENDIF132
>
>IF142:                                            ; preds = %ELSE131
>  %612 = fsub float -0.000000e+00, %25
>  %613 = fadd float %temp24.1, %612
>  %614 = fmul float %23, %613
>  %615 = fadd float %614, %24
>  %616 = fcmp ult float %506, %temp24.1
>  %617 = select i1 %616, float 1.000000e+00, float 0.000000e+00
>  %618 = fsub float -0.000000e+00, %617
>  %619 = fptosi float %618 to i32
>  %620 = bitcast i32 %619 to float
>  %621 = fcmp ult float %temp12.1, %615
>  %622 = select i1 %621, float 1.000000e+00, float 0.000000e+00
>  %623 = fsub float -0.000000e+00, %622
>  %624 = fptosi float %623 to i32
>  %625 = bitcast i32 %624 to float
>  %626 = bitcast float %620 to i32
>  %627 = bitcast float %625 to i32
>  %628 = and i32 %626, %627
>  %629 = bitcast i32 %628 to float
>  %630 = bitcast float %629 to i32
>  %631 = icmp ne i32 %630, 0
>  br i1 %631, label %IF145, label %ENDIF144
>
>IF145:                                            ; preds = %IF142
>  %632 = fsub float -0.000000e+00, %506
>  %633 = fadd float %temp24.1, %632
>  %634 = fmul float 5.000000e-01, %633
>  %635 = fsub float -0.000000e+00, %temp12.1
>  %636 = fadd float %615, %635
>  %637 = fmul float %634, %636
>  %638 = fcmp ult float %506, %.155
>  %639 = select i1 %638, float 1.000000e+00, float 0.000000e+00
>  %640 = fsub float -0.000000e+00, %639
>  %641 = fptosi float %640 to i32
>  %642 = bitcast i32 %641 to float
>  %643 = bitcast float %642 to i32
>  %644 = icmp ne i32 %643, 0
>  br i1 %644, label %IF148, label %ENDIF147
>
>ENDIF144:                                         ; preds = %IF151, %ENDIF147, %IF142
>  %temp40.3 = phi float [ 0.000000e+00, %IF142 ], [ %680, %IF151 ], [ %temp40.4, %ENDIF147 ]
>  %645 = fsub float -0.000000e+00, %.155
>  %646 = fadd float %temp24.1, %645
>  %647 = fsub float -0.000000e+00, %temp12.1
>  %648 = fadd float %temp16.1, %647
>  %649 = fmul float %646, %648
>  %650 = fdiv float 1.000000e+00, %649
>  %651 = fmul float %temp40.3, %650
>  %652 = fsub float -0.000000e+00, %651
>  %653 = fadd float 1.000000e+00, %652
>  %654 = fmul float %temp.3, %653
>  br label %ENDIF78
>
>IF148:                                            ; preds = %IF145
>  %655 = fadd float %.155, %632
>  %656 = fmul float 5.000000e-01, %655
>  %657 = fsub float -0.000000e+00, %25
>  %658 = fadd float %.155, %657
>  %659 = fmul float %23, %658
>  %660 = fadd float %659, %24
>  %661 = fsub float -0.000000e+00, %temp12.1
>  %662 = fadd float %660, %661
>  %663 = fmul float %656, %662
>  %664 = fsub float -0.000000e+00, %663
>  %665 = fadd float %637, %664
>  br label %ENDIF147
>
>ENDIF147:                                         ; preds = %IF145, %IF148
>  %temp40.4 = phi float [ %665, %IF148 ], [ %637, %IF145 ]
>  %666 = fcmp ult float %temp16.1, %615
>  %667 = select i1 %666, float 1.000000e+00, float 0.000000e+00
>  %668 = fsub float -0.000000e+00, %667
>  %669 = fptosi float %668 to i32
>  %670 = bitcast i32 %669 to float
>  %671 = bitcast float %670 to i32
>  %672 = icmp ne i32 %671, 0
>  br i1 %672, label %IF151, label %ENDIF144
>
>IF151:                                            ; preds = %ENDIF147
>  %673 = fsub float -0.000000e+00, %511
>  %674 = fadd float %temp24.1, %673
>  %675 = fmul float 5.000000e-01, %674
>  %676 = fsub float -0.000000e+00, %temp16.1
>  %677 = fadd float %615, %676
>  %678 = fmul float %675, %677
>  %679 = fsub float -0.000000e+00, %678
>  %680 = fadd float %temp40.4, %679
>  br label %ENDIF144
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>SI CODE:
>befe0a7e
>befc0306
>c82c0b00
>c82d0b01
>c8240a00
>c8250a01
>c81c0900
>c81d0901
>c8200800
>c8210801
>c8280700
>c8290701
>c8080500
>c8090501
>c80c0400
>c80d0401
>c8100300
>c8110301
>c8300100
>c8310101
>c8140000
>c8150001
>c8180200
>c8190201
>060c0cf3
>d2060106
>02010106
>7e1a02ff
>38d1b717
>d0060000
>02021b06
>d2000006
>0001e480
>d2060006
>22010106
>7e0c1106
>d10a0000
>02010106
>d2000006
>00018280
>c8380600
>c8390601
>06001cf3
>d2060100
>02010100
>d0060000
>02021b00
>d2000000
>0001e480
>d2060000
>22010100
>7e001100
>d10a0000
>02010100
>d200000d
>00018280
>d1040000
>0201830d
>d2000000
>00018280
>d1040000
>02010100
>7e020307
>7e1c0307
>be802400
>8980007e
>060018f0
>08021100
>7e00550a
>d2820001
>041e0101
>061c18f1
>081c110e
>d282000e
>041e010e
>88fe007e
>d1040000
>02018306
>d2000000
>00018280
>d1040000
>02010100
>7e1e0302
>7e200302
>be802400
>8980007e
>060018f0
>081e0700
>7e005504
>d282000f
>040a010f
>062018f1
>08200710
>d2820010
>040a0110
>88fe007e
>06000af1
>d00c0000
>02020300
>d2000011
>0001e480
>d2060011
>22010111
>7e221111
>d00c0000
>02021d00
>d2000000
>0001e480
>d2060000
>22010100
>7e001100
>36002300
>06220af0
>d00c0000
>02022310
>d2000012
>0001e480
>d2060012
>22010112
>7e241112
>36002500
>d00c0000
>0202230f
>d2000011
>0001e480
>d2060011
>22010111
>7e221111
>36002300
>062218f1
>d00c0000
>02021711
>d2000011
>0001e480
>d2060011
>22010111
>7e221111
>36002300
>062218f0
>d00c0000
>02022309
>d2000011
>0001e480
>d2060011
>22010111
>7e221111
>36222300
>d1040000
>02010111
>7e240280
>7e0002f2
>be802400
>8980007e
>bf880040
>060018f1
>d0020002
>02020109
>d2000000
>0009e480
>d2060000
>22010100
>7e001100
>062418f0
>d0020002
>02021712
>d2000012
>0009e480
>d2060012
>22010112
>7e241112
>38000112
>d1040002
>02010100
>7e240280
>7e000312
>be822402
>8982027e
>bf880027
>06000af0
>d0020004
>02020300
>d2000001
>0011e480
>d2060001
>22010101
>7e021101
>d0020004
>02021d00
>d2000000
>0011e480
>d2060000
>22010100
>7e001100
>36000300
>06020af1
>d0020004
>0202030f
>d200000e
>0011e480
>d206000e
>2201010e
>7e1c110e
>d0020004
>02020310
>d2000001
>0011e480
>d2060001
>22010101
>7e021101
>36021d01
>38000101
>d10a0004
>02010100
>d2000000
>00110111
>d2000012
>001100c1
>88fe027e
>88fe007e
>d10a0000
>02010112
>be802400
>8980007e
>bf88020d
>061c0af0
>d0020002
>02021d02
>d2000000
>0009e480
>d2060000
>22010100
>7e021100
>06000af1
>d0020002
>02020500
>d2000005
>0009e480
>d2060005
>22010105
>7e0a1105
>36020305
>d1040002
>02018306
>d2000005
>00098280
>36020305
>d10a0002
>02010101
>d2000001
>000a050e
>d0020002
>02021d07
>d2000005
>0009e480
>d2060005
>22010105
>7e0a1105
>d0020002
>02020f00
>d200000e
>0009e480
>d206000e
>2201010e
>7e1c110e
>360a0b0e
>d1040002
>0201830d
>d200000e
>00098280
>360a0b0e
>d10a0002
>02010105
>d2000005
>000a0f00
>d00c0002
>02020305
>d2000000
>0009e480
>d2060000
>22010100
>7e001100
>061c18f0
>d00c0002
>02021d09
>d200000f
>0009e480
>d206000f
>2201010f
>7e1e110f
>d10a0002
>0201010f
>d2000009
>000a1d09
>061818f1
>d00c0002
>0202170c
>d200000e
>0009e480
>d206000e
>2201010e
>7e1c110e
>d10a0002
>0201010e
>d200000b
>000a190b
>d00c0002
>0202130b
>d200000c
>0009e480
>d206000c
>2201010c
>7e18110c
>3800010c
>d1040002
>02010100
>08181709
>7e000280
>be822402
>8982027e
>bf8801ac
>bf8c070f
>08000b01
>1000010c
>36180d0d
>d1040004
>0201830c
>d200000c
>00118280
>d1040004
>0201010c
>be842404
>8984047e
>bf88019e
>d10a0006
>0201830d
>be862406
>8986067e
>bf8800c9
>08181109
>7e1a550a
>d282000c
>041e1b0c
>081c110b
>d282000d
>041e1b0e
>d0020008
>02021b05
>d200000e
>0021e480
>d206000e
>2201010e
>7e1c110e
>d0020008
>0201010a
>d200000f
>0021e480
>d206000f
>2201010f
>7e1e110f
>361c1d0f
>d1040008
>0201010e
>be882408
>8988087e
>bf880060
>d002000a
>02021905
>d200000e
>0029e480
>d206000e
>2201010e
>7e1c110e
>d008000a
>0201010a
>d200000f
>0029e480
>d206000f
>2201010f
>7e1e110f
>361c1d0f
>d10a000a
>0201010e
>7e1c0300
>be8a240a
>898a0a7e
>bf88004a
>d002000c
>0202030d
>d200000e
>0031e480
>d206000e
>2201010e
>7e1c110e
>081e0f01
>d282000f
>04221f0a
>d002000c
>02021f0b
>d2000010
>0031e480
>d2060010
>22010110
>7e201110
>361c210e
>d10a000c
>0201010e
>7e1c0280
>be8c240c
>898c0c7e
>bf88002b
>081c170f
>08201b01
>102020f0
>101c1d10
>d002000e
>02020b0d
>d2000010
>0039e480
>d2060010
>22010110
>7e201110
>d10a000e
>02010110
>d2060010
>2201010d
>be8e240e
>898e0e7e
>08220f05
>d2820011
>0422230a
>08221711
>06202105
>102020f1
>d282000e
>043a2310
>88fe0e7e
>d002000e
>02021f09
>d2000010
>0039e480
>d2060010
>22010110
>7e201110
>d10a000e
>02010110
>be8e240e
>898e0e7e
>081e130f
>08201901
>102020f1
>d282000e
>043a1f10
>88fe0e7e
>88fe0c7e
>081e1709
>08200b01
>101e1f10
>7e1e550f
>101c1f0e
>101c1d00
>88fe0a7e
>be882508
>89fe087e
>bf880049
>d002000a
>02021b05
>d200000e
>0029e480
>d206000e
>2201010e
>7e1c110e
>081e0f05
>d282000f
>04221f0a
>d002000a
>02021f0b
>d2000010
>0029e480
>d2060010
>22010110
>7e201110
>361c210e
>d10a000a
>0201010e
>7e1c0280
>be8a240a
>898a0a7e
>bf880029
>081c170f
>08200b0d
>102020f0
>101c1d10
>d002000c
>02021b01
>d2000010
>0031e480
>d2060010
>22010110
>7e201110
>d10a000c
>02010110
>be8c240c
>898c0c7e
>080e0f01
>d2820007
>04220f0a
>080e1707
>0810030d
>101010f1
>d282000e
>043a0f08
>88fe0c7e
>d002000c
>02021f09
>d2000007
>0031e480
>d2060007
>22010107
>7e0e1107
>d10a000c
>02010107
>be8c240c
>898c0c7e
>080e130f
>08100b0c
>101010f1
>d282000e
>043a0f08
>88fe0c7e
>88fe0a7e
>080e1709
>08100b01
>100e0f08
>7e0e5507
>100e0f0e
>080e0ef2
>101c0f00
>88fe087e
>7e00030e
>88fe067e
>d10a0006
>02018306
>be862406
>8986067e
>bf8800c9
>080e070b
>7e0c5504
>d2820007
>040a0d07
>08100709
>d2820006
>040a0d08
>d0020008
>02020306
>d2000008
>0021e480
>d2060008
>22010108
>7e101108
>d0020008
>02010104
>d200000a
>0021e480
>d206000a
>2201010a
>7e14110a
>3610110a
>d1040008
>02010108
>be882408
>8988087e
>bf880061
>d002000a
>02020307
>d2000008
>0029e480
>d2060008
>22010108
>7e101108
>d008000a
>02010104
>d200000a
>0029e480
>d206000a
>2201010a
>7e14110a
>3610110a
>d10a000a
>02010108
>7e100300
>be8a240a
>898a0a7e
>bf88004b
>d002000c
>02020307
>d2000008
>0031e480
>d2060008
>22010108
>7e101108
>08140501
>d282000a
>040e1504
>d002000c
>0202150b
>d200000c
>0031e480
>d206000c
>2201010c
>7e18110c
>36101908
>d10a000c
>02010108
>7e100280
>be8c240c
>898c0c7e
>bf88002b
>0810170a
>08180f01
>101818f0
>1010110c
>d002000e
>02020b07
>d200000c
>0039e480
>d206000c
>2201010c
>7e18110c
>d10a000e
>0201010c
>d206000c
>22010107
>be8e240e
>898e0e7e
>081a0505
>d282000d
>040e1b04
>081a170d
>06181905
>101818f1
>d2820008
>04221b0c
>88fe0e7e
>d002000e
>02021509
>d200000c
>0039e480
>d206000c
>2201010c
>7e18110c
>d10a000e
>0201010c
>be8e240e
>898e0e7e
>0814130a
>08180d01
>101818f1
>d2820008
>0422150c
>88fe0e7e
>88fe0c7e
>08141709
>08180b01
>1014150c
>7e14550a
>10101508
>081010f2
>10101100
>88fe0a7e
>be882508
>89fe087e
>bf880048
>d002000a
>02020f05
>d2000008
>0029e480
>d2060008
>22010108
>7e101108
>08140505
>d282000a
>040e1504
>d002000a
>0202150b
>d200000c
>0029e480
>d206000c
>2201010c
>7e18110c
>36101908
>d10a000a
>02010108
>7e100280
>be8a240a
>898a0a7e
>bf880029
>0810170a
>08180b07
>101818f0
>1010110c
>d002000c
>02020f01
>d200000c
>0031e480
>d206000c
>2201010c
>7e18110c
>d10a000c
>0201010c
>be8c240c
>898c0c7e
>08040501
>d2820002
>040e0504
>08041702
>08060307
>100606f1
>d2820008
>04220503
>88fe0c7e
>d002000c
>02021509
>d2000002
>0031e480
>d2060002
>22010102
>7e041102
>d10a000c
>02010102
>be8c240c
>898c0c7e
>0804130a
>08060b06
>100606f1
>d2820008
>04220503
>88fe0c7e
>88fe0a7e
>08041709
>08020b01
>10020501
>7e025501
>10020308
>10100300
>88fe087e
>7e000308
>88fe067e
>88fe047e
>88fe027e
>88fe007e
>5e000080
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL OUT[2], GENERIC[20]
>DCL OUT[3], GENERIC[21]
>DCL TEMP[0..2], LOCAL
>  0: MOV TEMP[0].z, IN[4].wwww
>  1: MOV TEMP[0].w, IN[4].zzzz
>  2: MOV TEMP[1].x, IN[4].yyyy
>  3: MOV TEMP[1].y, IN[4].xxxx
>  4: MOV TEMP[1].z, IN[3].wwww
>  5: MOV TEMP[1].w, IN[3].zzzz
>  6: MOV TEMP[2].x, IN[3].yyyy
>  7: MOV TEMP[2].y, IN[3].xxxx
>  8: MOV TEMP[2].z, IN[2].yyyy
>  9: MOV TEMP[2].w, IN[2].xxxx
> 10: MOV TEMP[0].xy, IN[1].xyxx
> 11: MOV OUT[3], TEMP[2]
> 12: MOV OUT[2], TEMP[1]
> 13: MOV OUT[1], TEMP[0]
> 14: MOV OUT[0], IN[0]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
>  %23 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %22, i32 0, i32 %5)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %27, i32 0, i32 %5)
>  %29 = extractelement <4 x float> %28, i32 0
>  %30 = extractelement <4 x float> %28, i32 1
>  %31 = extractelement <4 x float> %28, i32 2
>  %32 = extractelement <4 x float> %28, i32 3
>  %33 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %34, i32 0, i32 %5)
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %39, float %38)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %37, float %36, float %32, float %31)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %30, float %29, float %25, float %24)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800710
>bf8c007f
>e00c2000
>80000100
>c0800704
>bf8c0070
>e00c2000
>80000500
>bf8c0770
>f800020f
>03040605
>c080070c
>bf8c000f
>e00c2000
>80000500
>bf8c0770
>f800021f
>07080102
>c0800708
>bf8c000f
>e00c2000
>80000100
>bf8c0770
>f800022f
>01020506
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL CONST[2..3]
>DCL TEMP[0..7], LOCAL
>IMM[0] INT32 {10, -10, 0, 1}
>IMM[1] UINT32 {4294967295, 0, 0, 0}
>IMM[2] INT32 {2, 3, 0, 0}
>IMM[3] FLT32 {    1.0000,     0.5000,     0.0000,     2.0000}
>IMM[4] FLT32 {    0.0010,     0.0000,     0.0000,     0.0000}
>  0: ISLT TEMP[0].x, CONST[3].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   MOV TEMP[0].xy, IN[0].xyyy
>  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  4:   MOV TEMP[0], TEMP[0]
>  5: ELSE :0
>  6:   MOV TEMP[1].x, IMM[1].xxxx
>  7:   UADD TEMP[2].x, CONST[3].xxxx, IMM[0].yyyy
>  8:   MUL TEMP[3].xy, IN[0].xyyy, CONST[0].xyyy
>  9:   MOV TEMP[4].xy, TEMP[3].xyxx
> 10:   USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].zzzz
> 11:   UIF TEMP[5].xxxx :0
> 12:     MOV TEMP[5].xy, TEMP[3].xyxx
> 13:   ELSE :0
> 14:     USEQ TEMP[6].x, TEMP[2].xxxx, IMM[0].wwww
> 15:     UIF TEMP[6].xxxx :0
> 16:       FRC TEMP[6].xy, TEMP[3].xyyy
> 17:       RCP TEMP[7].x, CONST[0].xxxx
> 18:       RCP TEMP[7].y, CONST[0].yyyy
> 19:       FLR TEMP[3].xy, TEMP[3].xyyy
> 20:       MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[3].xyyy
> 21:     ELSE :0
> 22:       USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].xxxx
> 23:       UIF TEMP[3].xxxx :0
> 24:         SGE TEMP[3].x, TEMP[4].xxxx, IMM[3].xxxx
> 25:         F2I TEMP[3].x, -TEMP[3]
> 26:         UIF TEMP[3].xxxx :0
> 27:           MUL TEMP[3].x, CONST[0].zzzz, CONST[0].xxxx
> 28:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 29:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[3].xxxx
> 30:         ELSE :0
> 31:           SLT TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz
> 32:           F2I TEMP[3].x, -TEMP[3]
> 33:           UIF TEMP[3].xxxx :0
> 34:             MOV TEMP[4].x, IMM[3].zzzz
> 35:           ENDIF
> 36:         ENDIF
> 37:         SGE TEMP[3].x, TEMP[4].yyyy, IMM[3].xxxx
> 38:         F2I TEMP[3].x, -TEMP[3]
> 39:         UIF TEMP[3].xxxx :0
> 40:           MUL TEMP[3].x, CONST[0].wwww, CONST[0].yyyy
> 41:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 42:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 43:           MOV TEMP[4].y, TEMP[3].xxxx
> 44:         ELSE :0
> 45:           SLT TEMP[3].x, TEMP[4].yyyy, IMM[3].zzzz
> 46:           F2I TEMP[3].x, -TEMP[3]
> 47:           UIF TEMP[3].xxxx :0
> 48:             MOV TEMP[4].y, IMM[3].zzzz
> 49:           ENDIF
> 50:         ENDIF
> 51:         RCP TEMP[3].x, CONST[0].xxxx
> 52:         RCP TEMP[3].y, CONST[0].yyyy
> 53:         MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[3].xyyy
> 54:       ELSE :0
> 55:         USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].yyyy
> 56:         UIF TEMP[3].xxxx :0
> 57:           FLR TEMP[3].x, TEMP[4].xxxx
> 58:           ABS TEMP[3].x, TEMP[3].xxxx
> 59:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 60:           FRC TEMP[3].x, TEMP[3].xxxx
> 61:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 62:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 63:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 64:           F2I TEMP[3].x, -TEMP[3]
> 65:           UIF TEMP[3].xxxx :0
> 66:             FRC TEMP[3].x, TEMP[4].xxxx
> 67:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 68:             RCP TEMP[6].x, CONST[0].xxxx
> 69:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 70:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[3].xxxx
> 71:           ELSE :0
> 72:             FRC TEMP[3].x, TEMP[4].xxxx
> 73:             RCP TEMP[6].x, CONST[0].xxxx
> 74:             MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx
> 75:           ENDIF
> 76:           FLR TEMP[3].x, TEMP[4].yyyy
> 77:           ABS TEMP[3].x, TEMP[3].xxxx
> 78:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 79:           FRC TEMP[3].x, TEMP[3].xxxx
> 80:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 81:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 82:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 83:           F2I TEMP[3].x, -TEMP[3]
> 84:           UIF TEMP[3].xxxx :0
> 85:             FRC TEMP[3].x, TEMP[4].yyyy
> 86:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 87:             RCP TEMP[6].x, CONST[0].yyyy
> 88:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 89:             ADD TEMP[3].x, IMM[3].wwww, -TEMP[3].xxxx
> 90:             MOV TEMP[4].y, TEMP[3].xxxx
> 91:           ELSE :0
> 92:             FRC TEMP[3].x, TEMP[4].yyyy
> 93:             RCP TEMP[6].x, CONST[0].yyyy
> 94:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 95:             MOV TEMP[4].y, TEMP[3].xxxx
> 96:           ENDIF
> 97:         ENDIF
> 98:       ENDIF
> 99:     ENDIF
>100:     MOV TEMP[5].xy, TEMP[4].xyxx
>101:   ENDIF
>102:   MOV TEMP[2].xy, TEMP[5].xyxx
>103:   USEQ TEMP[3].x, CONST[3].xxxx, IMM[0].xxxx
>104:   UIF TEMP[3].xxxx :0
>105:     SGE TEMP[3].x, TEMP[5].xxxx, IMM[3].zzzz
>106:     F2I TEMP[3].x, -TEMP[3]
>107:     SLT TEMP[4].x, TEMP[5].xxxx, IMM[3].xxxx
>108:     F2I TEMP[4].x, -TEMP[4]
>109:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>110:     SGE TEMP[4].x, TEMP[5].yyyy, IMM[3].zzzz
>111:     F2I TEMP[4].x, -TEMP[4]
>112:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>113:     SLT TEMP[4].x, TEMP[5].yyyy, IMM[3].xxxx
>114:     F2I TEMP[4].x, -TEMP[4]
>115:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>116:     NOT TEMP[3].x, TEMP[3].xxxx
>117:     UIF TEMP[3].xxxx :0
>118:       MOV TEMP[3].xyz, IMM[3].zzzz
>119:       MOV TEMP[3].w, IMM[3].zzzz
>120:       MOV TEMP[3], TEMP[3]
>121:       MOV TEMP[1].x, IMM[1].yyyy
>122:     ELSE :0
>123:       FRC TEMP[4].xy, TEMP[5].xyyy
>124:       RCP TEMP[5].x, CONST[0].xxxx
>125:       RCP TEMP[5].y, CONST[0].yyyy
>126:       MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy
>127:     ENDIF
>128:   ENDIF
>129:   UIF TEMP[1].xxxx :0
>130:     MOV TEMP[2].xy, TEMP[2].xyyy
>131:     TEX TEMP[2], TEMP[2], SAMP[0], 2D
>132:     MOV TEMP[3], TEMP[2]
>133:   ENDIF
>134:   MOV TEMP[0], TEMP[3]
>135: ENDIF
>136: MUL TEMP[0], CONST[2].wwww, TEMP[0]
>137: MOV OUT[0], TEMP[0]
>138: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %34 = bitcast float %27 to i32
>  %35 = icmp slt i32 %34, 10
>  %36 = sext i1 %35 to i32
>  %37 = bitcast i32 %36 to float
>  %38 = bitcast float %37 to i32
>  %39 = icmp ne i32 %38, 0
>  br i1 %39, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %40 = bitcast float %32 to i32
>  %41 = bitcast float %33 to i32
>  %42 = insertelement <2 x i32> undef, i32 %40, i32 0
>  %43 = insertelement <2 x i32> %42, i32 %41, i32 1
>  %44 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %43, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %49 = bitcast float %27 to i32
>  %50 = add i32 %49, -10
>  %51 = bitcast i32 %50 to float
>  %52 = fmul float %32, %22
>  %53 = fmul float %33, %23
>  %54 = bitcast float %51 to i32
>  %55 = icmp eq i32 %54, 0
>  %56 = sext i1 %55 to i32
>  %57 = bitcast i32 %56 to float
>  %58 = bitcast float %57 to i32
>  %59 = icmp ne i32 %58, 0
>  br i1 %59, label %ENDIF32, label %ELSE34
>
>ENDIF:                                            ; preds = %IF69, %ENDIF62, %IF
>  %temp3.0 = phi float [ %48, %IF ], [ %241, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp2.0 = phi float [ %47, %IF ], [ %240, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp1.0 = phi float [ %46, %IF ], [ %239, %IF69 ], [ %temp13.3, %ENDIF62 ]
>  %temp.0 = phi float [ %45, %IF ], [ %238, %IF69 ], [ %temp12.0, %ENDIF62 ]
>  %60 = fmul float %26, %temp.0
>  %61 = fmul float %26, %temp1.0
>  %62 = fmul float %26, %temp2.0
>  %63 = fmul float %26, %temp3.0
>  %64 = call i32 @llvm.SI.packf16(float %60, float %61)
>  %65 = bitcast i32 %64 to float
>  %66 = call i32 @llvm.SI.packf16(float %62, float %63)
>  %67 = bitcast i32 %66 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %65, float %67, float %65, float %67)
>  ret void
>
>ELSE34:                                           ; preds = %ELSE
>  %68 = bitcast float %51 to i32
>  %69 = icmp eq i32 %68, 1
>  %70 = sext i1 %69 to i32
>  %71 = bitcast i32 %70 to float
>  %72 = bitcast float %71 to i32
>  %73 = icmp ne i32 %72, 0
>  br i1 %73, label %IF36, label %ELSE37
>
>ENDIF32:                                          ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE
>  %temp13.0 = phi float [ %53, %ELSE ], [ %85, %IF36 ], [ %139, %ENDIF47 ], [ %53, %ELSE40 ], [ %53, %ELSE61 ], [ %53, %IF60 ]
>  %temp20.0 = phi float [ %52, %ELSE ], [ %87, %IF36 ], [ %140, %ENDIF47 ], [ %52, %ELSE40 ], [ %temp16.5, %ELSE61 ], [ %temp16.5, %IF60 ]
>  %temp21.0 = phi float [ %53, %ELSE ], [ %89, %IF36 ], [ %141, %ENDIF47 ], [ %53, %ELSE40 ], [ %185, %IF60 ], [ %187, %ELSE61 ]
>  %74 = bitcast float %27 to i32
>  %75 = icmp eq i32 %74, 10
>  %76 = sext i1 %75 to i32
>  %77 = bitcast i32 %76 to float
>  %78 = bitcast float %77 to i32
>  %79 = icmp ne i32 %78, 0
>  br i1 %79, label %IF63, label %ENDIF62
>
>IF36:                                             ; preds = %ELSE34
>  %80 = call float @llvm.AMDIL.fraction.(float %52)
>  %81 = call float @llvm.AMDIL.fraction.(float %53)
>  %82 = fdiv float 1.000000e+00, %22
>  %83 = fdiv float 1.000000e+00, %23
>  %84 = call float @floor(float %52)
>  %85 = call float @floor(float %53)
>  %86 = fmul float %80, %82
>  %87 = fadd float %86, %84
>  %88 = fmul float %81, %83
>  %89 = fadd float %88, %85
>  br label %ENDIF32
>
>ELSE37:                                           ; preds = %ELSE34
>  %90 = bitcast float %51 to i32
>  %91 = icmp eq i32 %90, 2
>  %92 = sext i1 %91 to i32
>  %93 = bitcast i32 %92 to float
>  %94 = bitcast float %93 to i32
>  %95 = icmp ne i32 %94, 0
>  br i1 %95, label %IF39, label %ELSE40
>
>IF39:                                             ; preds = %ELSE37
>  %96 = fcmp uge float %52, 1.000000e+00
>  %97 = select i1 %96, float 1.000000e+00, float 0.000000e+00
>  %98 = fsub float -0.000000e+00, %97
>  %99 = fptosi float %98 to i32
>  %100 = bitcast i32 %99 to float
>  %101 = bitcast float %100 to i32
>  %102 = icmp ne i32 %101, 0
>  br i1 %102, label %IF42, label %ELSE43
>
>ELSE40:                                           ; preds = %ELSE37
>  %103 = bitcast float %51 to i32
>  %104 = icmp eq i32 %103, 3
>  %105 = sext i1 %104 to i32
>  %106 = bitcast i32 %105 to float
>  %107 = bitcast float %106 to i32
>  %108 = icmp ne i32 %107, 0
>  br i1 %108, label %IF54, label %ENDIF32
>
>IF42:                                             ; preds = %IF39
>  %109 = fmul float %24, %22
>  %110 = fmul float %109, 5.000000e-01
>  %111 = fsub float -0.000000e+00, %110
>  %112 = fadd float 1.000000e+00, %111
>  br label %ENDIF41
>
>ELSE43:                                           ; preds = %IF39
>  %113 = fcmp ult float %52, 0.000000e+00
>  %114 = select i1 %113, float 1.000000e+00, float 0.000000e+00
>  %115 = fsub float -0.000000e+00, %114
>  %116 = fptosi float %115 to i32
>  %117 = bitcast i32 %116 to float
>  %118 = bitcast float %117 to i32
>  %119 = icmp ne i32 %118, 0
>  %. = select i1 %119, float 0.000000e+00, float %52
>  br label %ENDIF41
>
>ENDIF41:                                          ; preds = %ELSE43, %IF42
>  %temp16.2 = phi float [ %112, %IF42 ], [ %., %ELSE43 ]
>  %120 = fcmp uge float %53, 1.000000e+00
>  %121 = select i1 %120, float 1.000000e+00, float 0.000000e+00
>  %122 = fsub float -0.000000e+00, %121
>  %123 = fptosi float %122 to i32
>  %124 = bitcast i32 %123 to float
>  %125 = bitcast float %124 to i32
>  %126 = icmp ne i32 %125, 0
>  br i1 %126, label %IF48, label %ELSE49
>
>IF48:                                             ; preds = %ENDIF41
>  %127 = fmul float %25, %23
>  %128 = fmul float %127, 5.000000e-01
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fadd float 1.000000e+00, %129
>  br label %ENDIF47
>
>ELSE49:                                           ; preds = %ENDIF41
>  %131 = fcmp ult float %53, 0.000000e+00
>  %132 = select i1 %131, float 1.000000e+00, float 0.000000e+00
>  %133 = fsub float -0.000000e+00, %132
>  %134 = fptosi float %133 to i32
>  %135 = bitcast i32 %134 to float
>  %136 = bitcast float %135 to i32
>  %137 = icmp ne i32 %136, 0
>  %.71 = select i1 %137, float 0.000000e+00, float %53
>  br label %ENDIF47
>
>ENDIF47:                                          ; preds = %ELSE49, %IF48
>  %temp17.2 = phi float [ %130, %IF48 ], [ %.71, %ELSE49 ]
>  %138 = fdiv float 1.000000e+00, %22
>  %139 = fdiv float 1.000000e+00, %23
>  %140 = fmul float %temp16.2, %138
>  %141 = fmul float %temp17.2, %139
>  br label %ENDIF32
>
>IF54:                                             ; preds = %ELSE40
>  %142 = call float @floor(float %52)
>  %143 = call float @fabs(float %142)
>  %144 = fmul float %143, 5.000000e-01
>  %145 = call float @llvm.AMDIL.fraction.(float %144)
>  %146 = fmul float 2.000000e+00, %145
>  %147 = fsub float -0.000000e+00, %146
>  %148 = fadd float 1.000000e+00, %147
>  %149 = fcmp ult float %148, 0x3F50624DE0000000
>  %150 = select i1 %149, float 1.000000e+00, float 0.000000e+00
>  %151 = fsub float -0.000000e+00, %150
>  %152 = fptosi float %151 to i32
>  %153 = bitcast i32 %152 to float
>  %154 = bitcast float %153 to i32
>  %155 = icmp ne i32 %154, 0
>  %156 = call float @llvm.AMDIL.fraction.(float %52)
>  br i1 %155, label %IF57, label %ELSE58
>
>IF57:                                             ; preds = %IF54
>  %157 = fsub float -0.000000e+00, %156
>  %158 = fadd float 1.000000e+00, %157
>  %159 = fdiv float 1.000000e+00, %22
>  %160 = fmul float %158, %159
>  %161 = fsub float -0.000000e+00, %160
>  %162 = fadd float 2.000000e+00, %161
>  br label %ENDIF56
>
>ELSE58:                                           ; preds = %IF54
>  %163 = fdiv float 1.000000e+00, %22
>  %164 = fmul float %156, %163
>  br label %ENDIF56
>
>ENDIF56:                                          ; preds = %ELSE58, %IF57
>  %temp16.5 = phi float [ %162, %IF57 ], [ %164, %ELSE58 ]
>  %165 = call float @floor(float %53)
>  %166 = call float @fabs(float %165)
>  %167 = fmul float %166, 5.000000e-01
>  %168 = call float @llvm.AMDIL.fraction.(float %167)
>  %169 = fmul float 2.000000e+00, %168
>  %170 = fsub float -0.000000e+00, %169
>  %171 = fadd float 1.000000e+00, %170
>  %172 = fcmp ult float %171, 0x3F50624DE0000000
>  %173 = select i1 %172, float 1.000000e+00, float 0.000000e+00
>  %174 = fsub float -0.000000e+00, %173
>  %175 = fptosi float %174 to i32
>  %176 = bitcast i32 %175 to float
>  %177 = bitcast float %176 to i32
>  %178 = icmp ne i32 %177, 0
>  %179 = call float @llvm.AMDIL.fraction.(float %53)
>  br i1 %178, label %IF60, label %ELSE61
>
>IF60:                                             ; preds = %ENDIF56
>  %180 = fsub float -0.000000e+00, %179
>  %181 = fadd float 1.000000e+00, %180
>  %182 = fdiv float 1.000000e+00, %23
>  %183 = fmul float %181, %182
>  %184 = fsub float -0.000000e+00, %183
>  %185 = fadd float 2.000000e+00, %184
>  br label %ENDIF32
>
>ELSE61:                                           ; preds = %ENDIF56
>  %186 = fdiv float 1.000000e+00, %23
>  %187 = fmul float %179, %186
>  br label %ENDIF32
>
>IF63:                                             ; preds = %ENDIF32
>  %188 = fcmp uge float %temp20.0, 0.000000e+00
>  %189 = select i1 %188, float 1.000000e+00, float 0.000000e+00
>  %190 = fsub float -0.000000e+00, %189
>  %191 = fptosi float %190 to i32
>  %192 = bitcast i32 %191 to float
>  %193 = fcmp ult float %temp20.0, 1.000000e+00
>  %194 = select i1 %193, float 1.000000e+00, float 0.000000e+00
>  %195 = fsub float -0.000000e+00, %194
>  %196 = fptosi float %195 to i32
>  %197 = bitcast i32 %196 to float
>  %198 = bitcast float %192 to i32
>  %199 = bitcast float %197 to i32
>  %200 = and i32 %198, %199
>  %201 = bitcast i32 %200 to float
>  %202 = fcmp uge float %temp21.0, 0.000000e+00
>  %203 = select i1 %202, float 1.000000e+00, float 0.000000e+00
>  %204 = fsub float -0.000000e+00, %203
>  %205 = fptosi float %204 to i32
>  %206 = bitcast i32 %205 to float
>  %207 = bitcast float %201 to i32
>  %208 = bitcast float %206 to i32
>  %209 = and i32 %207, %208
>  %210 = bitcast i32 %209 to float
>  %211 = fcmp ult float %temp21.0, 1.000000e+00
>  %212 = select i1 %211, float 1.000000e+00, float 0.000000e+00
>  %213 = fsub float -0.000000e+00, %212
>  %214 = fptosi float %213 to i32
>  %215 = bitcast i32 %214 to float
>  %216 = bitcast float %210 to i32
>  %217 = bitcast float %215 to i32
>  %218 = and i32 %216, %217
>  %219 = bitcast i32 %218 to float
>  %220 = bitcast float %219 to i32
>  %221 = xor i32 %220, -1
>  %222 = bitcast i32 %221 to float
>  %223 = bitcast float %222 to i32
>  %224 = icmp ne i32 %223, 0
>  br i1 %224, label %ENDIF62, label %ELSE67
>
>ENDIF62:                                          ; preds = %ELSE67, %IF63, %ENDIF32
>  %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp8.0 = phi float [ %temp20.0, %ENDIF32 ], [ %231, %ELSE67 ], [ %temp20.0, %IF63 ]
>  %temp9.0 = phi float [ %temp21.0, %ENDIF32 ], [ %232, %ELSE67 ], [ %temp21.0, %IF63 ]
>  %temp12.0 = phi float [ %77, %ENDIF32 ], [ %222, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp13.3 = phi float [ %temp13.0, %ENDIF32 ], [ %temp13.0, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %225 = bitcast float %temp4.0 to i32
>  %226 = icmp ne i32 %225, 0
>  br i1 %226, label %IF69, label %ENDIF
>
>ELSE67:                                           ; preds = %IF63
>  %227 = call float @llvm.AMDIL.fraction.(float %temp20.0)
>  %228 = call float @llvm.AMDIL.fraction.(float %temp21.0)
>  %229 = fdiv float 1.000000e+00, %22
>  %230 = fdiv float 1.000000e+00, %23
>  %231 = fmul float %227, %229
>  %232 = fmul float %228, %230
>  br label %ENDIF62
>
>IF69:                                             ; preds = %ENDIF62
>  %233 = bitcast float %temp8.0 to i32
>  %234 = bitcast float %temp9.0 to i32
>  %235 = insertelement <2 x i32> undef, i32 %233, i32 0
>  %236 = insertelement <2 x i32> %235, i32 %234, i32 1
>  %237 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %236, <32 x i8> %29, <16 x i8> %31, i32 2)
>  %238 = extractelement <4 x float> %237, i32 0
>  %239 = extractelement <4 x float> %237, i32 1
>  %240 = extractelement <4 x float> %237, i32 2
>  %241 = extractelement <4 x float> %237, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c08c0100
>bf8c007f
>c201190b
>c2019903
>c20b1902
>c2021901
>c2029900
>c203190c
>bf8c007f
>d1020000
>02011406
>d2000000
>00018280
>d1040000
>02010100
>be802400
>8980007e
>bf880102
>7e140206
>7e120204
>7e100205
>100a1303
>10001102
>4a1a14ca
>d1040004
>0201010d
>d200000b
>00118280
>d1040004
>0201010b
>7e020305
>be842404
>8984047e
>bf8800a9
>d1040006
>0201030d
>d200000b
>00198280
>d1040006
>0201010b
>bf8c070f
>be862406
>8986067e
>bf880090
>d1040014
>0201050d
>d200000b
>00518280
>d1040014
>0201010b
>be942414
>8994147e
>bf880045
>d1040018
>0201070d
>7e020305
>7e160300
>be982418
>8998187e
>bf88003c
>7e164900
>d206010b
>0201010b
>101616f0
>7e16410b
>0616170b
>081616f2
>7e1802ff
>3a83126f
>d002001a
>0202190b
>d200000b
>0069e480
>d206000b
>2201010b
>7e16110b
>d104001a
>0201010b
>7e184100
>be9a241a
>899a1a7e
>7e165508
>1016170c
>be9a251a
>89fe1a7e
>7e165508
>081818f2
>1016170c
>081616f4
>88fe1a7e
>7e184905
>d206010c
>0201010c
>101818f0
>7e18410c
>0618190c
>081818f2
>7e1a02ff
>3a83126f
>d002001a
>02021b0c
>d200000c
>0069e480
>d206000c
>2201010c
>7e18110c
>d104001a
>0201010c
>7e184105
>be9a241a
>899a1a7e
>7e1a5509
>10021b0c
>be9a251a
>89fe1a7e
>7e1a5509
>081818f2
>10181b0c
>080218f4
>88fe1a7e
>88fe187e
>7e180305
>be942514
>89fe147e
>bf88003e
>d00c0018
>0201e500
>d200000b
>0061e480
>d206000b
>2201010b
>7e16110b
>d1040018
>0201010b
>be982418
>8998187e
>d002001a
>02010100
>d200000b
>0069e480
>d206000b
>2201010b
>7e16110b
>d10a001a
>0201010b
>d200000b
>00690100
>be982518
>89fe187e
>7e160216
>1016110b
>d282000b
>03c9e30b
>88fe187e
>d00c0016
>0201e505
>d200000c
>0059e480
>d206000c
>2201010c
>7e18110c
>d1040016
>0201010c
>be962416
>8996167e
>d0020018
>02010105
>d200000c
>0061e480
>d206000c
>2201010c
>7e18110c
>d10a0018
>0201010c
>d200000d
>00610105
>be962516
>89fe167e
>7e180203
>1018130c
>d282000d
>03c9e30c
>88fe167e
>7e185509
>1002190d
>7e1a5508
>10161b0b
>88fe147e
>be862506
>89fe067e
>7e184905
>7e165509
>7e084105
>d2820001
>04321704
>7e084900
>7e0a5508
>7e0c4100
>d282000b
>04120b06
>88fe067e
>7e0a030c
>7e00030b
>88fe047e
>d1040004
>0201150a
>d200000a
>00118280
>7e1c02c1
>be842404
>8984047e
>bf880032
>d0020006
>0201e500
>d200000a
>0019e480
>d206000a
>2201010a
>7e14110a
>d00c0006
>02010100
>d200000b
>0019e480
>d206000b
>2201010b
>7e16110b
>3614150b
>d00c0006
>02010101
>d200000b
>0019e480
>d206000b
>2201010b
>7e16110b
>3614170a
>d0020006
>0201e501
>d200000b
>0019e480
>d206000b
>2201010b
>7e16110b
>3614170a
>3a2014c1
>d1040006
>0201830a
>7e1e0280
>7e14030f
>7e1c030f
>be862406
>8986067e
>7e125509
>7e144101
>1002130a
>7e105508
>7e124100
>10001109
>7e1c02c1
>7e1e0305
>7e140310
>88fe067e
>7e0a030f
>88fe047e
>d10a0004
>0201010e
>7e0c0280
>7e0e0306
>be842404
>8984047e
>f0800f00
>00430a00
>bf8c0770
>7e0a030b
>7e0c030c
>7e0e030d
>88fe047e
>be802500
>7e000202
>89fe007e
>f0800f00
>00430402
>bf8c0770
>7e140304
>88fe007e
>10020f00
>10040d00
>5e020302
>10040b00
>10001500
>5e000500
>f8001c0f
>01000100
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL CONST[2..3]
>DCL TEMP[0..7], LOCAL
>IMM[0] INT32 {10, -10, 0, 1}
>IMM[1] UINT32 {4294967295, 0, 0, 0}
>IMM[2] INT32 {2, 3, 0, 0}
>IMM[3] FLT32 {    1.0000,     0.5000,     0.0000,     2.0000}
>IMM[4] FLT32 {    0.0010,     0.0000,     0.0000,     0.0000}
>  0: ISLT TEMP[0].x, CONST[3].xxxx, IMM[0].xxxx
>  1: UIF TEMP[0].xxxx :0
>  2:   MOV TEMP[0].xy, IN[0].xyyy
>  3:   TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  4:   MOV TEMP[0], TEMP[0]
>  5: ELSE :0
>  6:   MOV TEMP[1].x, IMM[1].xxxx
>  7:   UADD TEMP[2].x, CONST[3].xxxx, IMM[0].yyyy
>  8:   MUL TEMP[3].xy, IN[0].xyyy, CONST[0].xyyy
>  9:   MOV TEMP[4].xy, TEMP[3].xyxx
> 10:   USEQ TEMP[5].x, TEMP[2].xxxx, IMM[0].zzzz
> 11:   UIF TEMP[5].xxxx :0
> 12:     MOV TEMP[5].xy, TEMP[3].xyxx
> 13:   ELSE :0
> 14:     USEQ TEMP[6].x, TEMP[2].xxxx, IMM[0].wwww
> 15:     UIF TEMP[6].xxxx :0
> 16:       FRC TEMP[6].xy, TEMP[3].xyyy
> 17:       RCP TEMP[7].x, CONST[0].xxxx
> 18:       RCP TEMP[7].y, CONST[0].yyyy
> 19:       FLR TEMP[3].xy, TEMP[3].xyyy
> 20:       MAD TEMP[4].xy, TEMP[6].xyyy, TEMP[7].xyyy, TEMP[3].xyyy
> 21:     ELSE :0
> 22:       USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].xxxx
> 23:       UIF TEMP[3].xxxx :0
> 24:         SGE TEMP[3].x, TEMP[4].xxxx, IMM[3].xxxx
> 25:         F2I TEMP[3].x, -TEMP[3]
> 26:         UIF TEMP[3].xxxx :0
> 27:           MUL TEMP[3].x, CONST[0].zzzz, CONST[0].xxxx
> 28:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 29:           ADD TEMP[4].x, IMM[3].xxxx, -TEMP[3].xxxx
> 30:         ELSE :0
> 31:           SLT TEMP[3].x, TEMP[4].xxxx, IMM[3].zzzz
> 32:           F2I TEMP[3].x, -TEMP[3]
> 33:           UIF TEMP[3].xxxx :0
> 34:             MOV TEMP[4].x, IMM[3].zzzz
> 35:           ENDIF
> 36:         ENDIF
> 37:         SGE TEMP[3].x, TEMP[4].yyyy, IMM[3].xxxx
> 38:         F2I TEMP[3].x, -TEMP[3]
> 39:         UIF TEMP[3].xxxx :0
> 40:           MUL TEMP[3].x, CONST[0].wwww, CONST[0].yyyy
> 41:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 42:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 43:           MOV TEMP[4].y, TEMP[3].xxxx
> 44:         ELSE :0
> 45:           SLT TEMP[3].x, TEMP[4].yyyy, IMM[3].zzzz
> 46:           F2I TEMP[3].x, -TEMP[3]
> 47:           UIF TEMP[3].xxxx :0
> 48:             MOV TEMP[4].y, IMM[3].zzzz
> 49:           ENDIF
> 50:         ENDIF
> 51:         RCP TEMP[3].x, CONST[0].xxxx
> 52:         RCP TEMP[3].y, CONST[0].yyyy
> 53:         MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[3].xyyy
> 54:       ELSE :0
> 55:         USEQ TEMP[3].x, TEMP[2].xxxx, IMM[2].yyyy
> 56:         UIF TEMP[3].xxxx :0
> 57:           FLR TEMP[3].x, TEMP[4].xxxx
> 58:           ABS TEMP[3].x, TEMP[3].xxxx
> 59:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 60:           FRC TEMP[3].x, TEMP[3].xxxx
> 61:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 62:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 63:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 64:           F2I TEMP[3].x, -TEMP[3]
> 65:           UIF TEMP[3].xxxx :0
> 66:             FRC TEMP[3].x, TEMP[4].xxxx
> 67:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 68:             RCP TEMP[6].x, CONST[0].xxxx
> 69:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 70:             ADD TEMP[4].x, IMM[3].wwww, -TEMP[3].xxxx
> 71:           ELSE :0
> 72:             FRC TEMP[3].x, TEMP[4].xxxx
> 73:             RCP TEMP[6].x, CONST[0].xxxx
> 74:             MUL TEMP[4].x, TEMP[3].xxxx, TEMP[6].xxxx
> 75:           ENDIF
> 76:           FLR TEMP[3].x, TEMP[4].yyyy
> 77:           ABS TEMP[3].x, TEMP[3].xxxx
> 78:           MUL TEMP[3].x, TEMP[3].xxxx, IMM[3].yyyy
> 79:           FRC TEMP[3].x, TEMP[3].xxxx
> 80:           MUL TEMP[3].x, IMM[3].wwww, TEMP[3].xxxx
> 81:           ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 82:           SLT TEMP[3].x, TEMP[3].xxxx, IMM[4].xxxx
> 83:           F2I TEMP[3].x, -TEMP[3]
> 84:           UIF TEMP[3].xxxx :0
> 85:             FRC TEMP[3].x, TEMP[4].yyyy
> 86:             ADD TEMP[3].x, IMM[3].xxxx, -TEMP[3].xxxx
> 87:             RCP TEMP[6].x, CONST[0].yyyy
> 88:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 89:             ADD TEMP[3].x, IMM[3].wwww, -TEMP[3].xxxx
> 90:             MOV TEMP[4].y, TEMP[3].xxxx
> 91:           ELSE :0
> 92:             FRC TEMP[3].x, TEMP[4].yyyy
> 93:             RCP TEMP[6].x, CONST[0].yyyy
> 94:             MUL TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 95:             MOV TEMP[4].y, TEMP[3].xxxx
> 96:           ENDIF
> 97:         ENDIF
> 98:       ENDIF
> 99:     ENDIF
>100:     MOV TEMP[5].xy, TEMP[4].xyxx
>101:   ENDIF
>102:   MOV TEMP[2].xy, TEMP[5].xyxx
>103:   USEQ TEMP[3].x, CONST[3].xxxx, IMM[0].xxxx
>104:   UIF TEMP[3].xxxx :0
>105:     SGE TEMP[3].x, TEMP[5].xxxx, IMM[3].zzzz
>106:     F2I TEMP[3].x, -TEMP[3]
>107:     SLT TEMP[4].x, TEMP[5].xxxx, IMM[3].xxxx
>108:     F2I TEMP[4].x, -TEMP[4]
>109:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>110:     SGE TEMP[4].x, TEMP[5].yyyy, IMM[3].zzzz
>111:     F2I TEMP[4].x, -TEMP[4]
>112:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>113:     SLT TEMP[4].x, TEMP[5].yyyy, IMM[3].xxxx
>114:     F2I TEMP[4].x, -TEMP[4]
>115:     AND TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx
>116:     NOT TEMP[3].x, TEMP[3].xxxx
>117:     UIF TEMP[3].xxxx :0
>118:       MOV TEMP[3].xyz, IMM[3].zzzz
>119:       MOV TEMP[3].w, IMM[3].zzzz
>120:       MOV TEMP[3], TEMP[3]
>121:       MOV TEMP[1].x, IMM[1].yyyy
>122:     ELSE :0
>123:       FRC TEMP[4].xy, TEMP[5].xyyy
>124:       RCP TEMP[5].x, CONST[0].xxxx
>125:       RCP TEMP[5].y, CONST[0].yyyy
>126:       MUL TEMP[2].xy, TEMP[4].xyyy, TEMP[5].xyyy
>127:     ENDIF
>128:   ENDIF
>129:   UIF TEMP[1].xxxx :0
>130:     MOV TEMP[2].xy, TEMP[2].xyyy
>131:     TEX TEMP[2], TEMP[2], SAMP[0], 2D
>132:     MOV TEMP[3], TEMP[2]
>133:   ENDIF
>134:   MOV TEMP[0], TEMP[3]
>135: ENDIF
>136: MUL TEMP[0], CONST[2], TEMP[0]
>137: MOV OUT[0], TEMP[0]
>138: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %31 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
>  %33 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %37 = bitcast float %30 to i32
>  %38 = icmp slt i32 %37, 10
>  %39 = sext i1 %38 to i32
>  %40 = bitcast i32 %39 to float
>  %41 = bitcast float %40 to i32
>  %42 = icmp ne i32 %41, 0
>  br i1 %42, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %43 = bitcast float %35 to i32
>  %44 = bitcast float %36 to i32
>  %45 = insertelement <2 x i32> undef, i32 %43, i32 0
>  %46 = insertelement <2 x i32> %45, i32 %44, i32 1
>  %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = extractelement <4 x float> %47, i32 1
>  %50 = extractelement <4 x float> %47, i32 2
>  %51 = extractelement <4 x float> %47, i32 3
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %52 = bitcast float %30 to i32
>  %53 = add i32 %52, -10
>  %54 = bitcast i32 %53 to float
>  %55 = fmul float %35, %22
>  %56 = fmul float %36, %23
>  %57 = bitcast float %54 to i32
>  %58 = icmp eq i32 %57, 0
>  %59 = sext i1 %58 to i32
>  %60 = bitcast i32 %59 to float
>  %61 = bitcast float %60 to i32
>  %62 = icmp ne i32 %61, 0
>  br i1 %62, label %ENDIF32, label %ELSE34
>
>ENDIF:                                            ; preds = %IF69, %ENDIF62, %IF
>  %temp3.0 = phi float [ %51, %IF ], [ %244, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp2.0 = phi float [ %50, %IF ], [ %243, %IF69 ], [ 0.000000e+00, %ENDIF62 ]
>  %temp1.0 = phi float [ %49, %IF ], [ %242, %IF69 ], [ %temp13.3, %ENDIF62 ]
>  %temp.0 = phi float [ %48, %IF ], [ %241, %IF69 ], [ %temp12.0, %ENDIF62 ]
>  %63 = fmul float %26, %temp.0
>  %64 = fmul float %27, %temp1.0
>  %65 = fmul float %28, %temp2.0
>  %66 = fmul float %29, %temp3.0
>  %67 = call i32 @llvm.SI.packf16(float %63, float %64)
>  %68 = bitcast i32 %67 to float
>  %69 = call i32 @llvm.SI.packf16(float %65, float %66)
>  %70 = bitcast i32 %69 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %68, float %70, float %68, float %70)
>  ret void
>
>ELSE34:                                           ; preds = %ELSE
>  %71 = bitcast float %54 to i32
>  %72 = icmp eq i32 %71, 1
>  %73 = sext i1 %72 to i32
>  %74 = bitcast i32 %73 to float
>  %75 = bitcast float %74 to i32
>  %76 = icmp ne i32 %75, 0
>  br i1 %76, label %IF36, label %ELSE37
>
>ENDIF32:                                          ; preds = %IF60, %ELSE61, %ELSE40, %ENDIF47, %IF36, %ELSE
>  %temp13.0 = phi float [ %56, %ELSE ], [ %88, %IF36 ], [ %142, %ENDIF47 ], [ %56, %ELSE40 ], [ %56, %ELSE61 ], [ %56, %IF60 ]
>  %temp20.0 = phi float [ %55, %ELSE ], [ %90, %IF36 ], [ %143, %ENDIF47 ], [ %55, %ELSE40 ], [ %temp16.5, %ELSE61 ], [ %temp16.5, %IF60 ]
>  %temp21.0 = phi float [ %56, %ELSE ], [ %92, %IF36 ], [ %144, %ENDIF47 ], [ %56, %ELSE40 ], [ %188, %IF60 ], [ %190, %ELSE61 ]
>  %77 = bitcast float %30 to i32
>  %78 = icmp eq i32 %77, 10
>  %79 = sext i1 %78 to i32
>  %80 = bitcast i32 %79 to float
>  %81 = bitcast float %80 to i32
>  %82 = icmp ne i32 %81, 0
>  br i1 %82, label %IF63, label %ENDIF62
>
>IF36:                                             ; preds = %ELSE34
>  %83 = call float @llvm.AMDIL.fraction.(float %55)
>  %84 = call float @llvm.AMDIL.fraction.(float %56)
>  %85 = fdiv float 1.000000e+00, %22
>  %86 = fdiv float 1.000000e+00, %23
>  %87 = call float @floor(float %55)
>  %88 = call float @floor(float %56)
>  %89 = fmul float %83, %85
>  %90 = fadd float %89, %87
>  %91 = fmul float %84, %86
>  %92 = fadd float %91, %88
>  br label %ENDIF32
>
>ELSE37:                                           ; preds = %ELSE34
>  %93 = bitcast float %54 to i32
>  %94 = icmp eq i32 %93, 2
>  %95 = sext i1 %94 to i32
>  %96 = bitcast i32 %95 to float
>  %97 = bitcast float %96 to i32
>  %98 = icmp ne i32 %97, 0
>  br i1 %98, label %IF39, label %ELSE40
>
>IF39:                                             ; preds = %ELSE37
>  %99 = fcmp uge float %55, 1.000000e+00
>  %100 = select i1 %99, float 1.000000e+00, float 0.000000e+00
>  %101 = fsub float -0.000000e+00, %100
>  %102 = fptosi float %101 to i32
>  %103 = bitcast i32 %102 to float
>  %104 = bitcast float %103 to i32
>  %105 = icmp ne i32 %104, 0
>  br i1 %105, label %IF42, label %ELSE43
>
>ELSE40:                                           ; preds = %ELSE37
>  %106 = bitcast float %54 to i32
>  %107 = icmp eq i32 %106, 3
>  %108 = sext i1 %107 to i32
>  %109 = bitcast i32 %108 to float
>  %110 = bitcast float %109 to i32
>  %111 = icmp ne i32 %110, 0
>  br i1 %111, label %IF54, label %ENDIF32
>
>IF42:                                             ; preds = %IF39
>  %112 = fmul float %24, %22
>  %113 = fmul float %112, 5.000000e-01
>  %114 = fsub float -0.000000e+00, %113
>  %115 = fadd float 1.000000e+00, %114
>  br label %ENDIF41
>
>ELSE43:                                           ; preds = %IF39
>  %116 = fcmp ult float %55, 0.000000e+00
>  %117 = select i1 %116, float 1.000000e+00, float 0.000000e+00
>  %118 = fsub float -0.000000e+00, %117
>  %119 = fptosi float %118 to i32
>  %120 = bitcast i32 %119 to float
>  %121 = bitcast float %120 to i32
>  %122 = icmp ne i32 %121, 0
>  %. = select i1 %122, float 0.000000e+00, float %55
>  br label %ENDIF41
>
>ENDIF41:                                          ; preds = %ELSE43, %IF42
>  %temp16.2 = phi float [ %115, %IF42 ], [ %., %ELSE43 ]
>  %123 = fcmp uge float %56, 1.000000e+00
>  %124 = select i1 %123, float 1.000000e+00, float 0.000000e+00
>  %125 = fsub float -0.000000e+00, %124
>  %126 = fptosi float %125 to i32
>  %127 = bitcast i32 %126 to float
>  %128 = bitcast float %127 to i32
>  %129 = icmp ne i32 %128, 0
>  br i1 %129, label %IF48, label %ELSE49
>
>IF48:                                             ; preds = %ENDIF41
>  %130 = fmul float %25, %23
>  %131 = fmul float %130, 5.000000e-01
>  %132 = fsub float -0.000000e+00, %131
>  %133 = fadd float 1.000000e+00, %132
>  br label %ENDIF47
>
>ELSE49:                                           ; preds = %ENDIF41
>  %134 = fcmp ult float %56, 0.000000e+00
>  %135 = select i1 %134, float 1.000000e+00, float 0.000000e+00
>  %136 = fsub float -0.000000e+00, %135
>  %137 = fptosi float %136 to i32
>  %138 = bitcast i32 %137 to float
>  %139 = bitcast float %138 to i32
>  %140 = icmp ne i32 %139, 0
>  %.71 = select i1 %140, float 0.000000e+00, float %56
>  br label %ENDIF47
>
>ENDIF47:                                          ; preds = %ELSE49, %IF48
>  %temp17.2 = phi float [ %133, %IF48 ], [ %.71, %ELSE49 ]
>  %141 = fdiv float 1.000000e+00, %22
>  %142 = fdiv float 1.000000e+00, %23
>  %143 = fmul float %temp16.2, %141
>  %144 = fmul float %temp17.2, %142
>  br label %ENDIF32
>
>IF54:                                             ; preds = %ELSE40
>  %145 = call float @floor(float %55)
>  %146 = call float @fabs(float %145)
>  %147 = fmul float %146, 5.000000e-01
>  %148 = call float @llvm.AMDIL.fraction.(float %147)
>  %149 = fmul float 2.000000e+00, %148
>  %150 = fsub float -0.000000e+00, %149
>  %151 = fadd float 1.000000e+00, %150
>  %152 = fcmp ult float %151, 0x3F50624DE0000000
>  %153 = select i1 %152, float 1.000000e+00, float 0.000000e+00
>  %154 = fsub float -0.000000e+00, %153
>  %155 = fptosi float %154 to i32
>  %156 = bitcast i32 %155 to float
>  %157 = bitcast float %156 to i32
>  %158 = icmp ne i32 %157, 0
>  %159 = call float @llvm.AMDIL.fraction.(float %55)
>  br i1 %158, label %IF57, label %ELSE58
>
>IF57:                                             ; preds = %IF54
>  %160 = fsub float -0.000000e+00, %159
>  %161 = fadd float 1.000000e+00, %160
>  %162 = fdiv float 1.000000e+00, %22
>  %163 = fmul float %161, %162
>  %164 = fsub float -0.000000e+00, %163
>  %165 = fadd float 2.000000e+00, %164
>  br label %ENDIF56
>
>ELSE58:                                           ; preds = %IF54
>  %166 = fdiv float 1.000000e+00, %22
>  %167 = fmul float %159, %166
>  br label %ENDIF56
>
>ENDIF56:                                          ; preds = %ELSE58, %IF57
>  %temp16.5 = phi float [ %165, %IF57 ], [ %167, %ELSE58 ]
>  %168 = call float @floor(float %56)
>  %169 = call float @fabs(float %168)
>  %170 = fmul float %169, 5.000000e-01
>  %171 = call float @llvm.AMDIL.fraction.(float %170)
>  %172 = fmul float 2.000000e+00, %171
>  %173 = fsub float -0.000000e+00, %172
>  %174 = fadd float 1.000000e+00, %173
>  %175 = fcmp ult float %174, 0x3F50624DE0000000
>  %176 = select i1 %175, float 1.000000e+00, float 0.000000e+00
>  %177 = fsub float -0.000000e+00, %176
>  %178 = fptosi float %177 to i32
>  %179 = bitcast i32 %178 to float
>  %180 = bitcast float %179 to i32
>  %181 = icmp ne i32 %180, 0
>  %182 = call float @llvm.AMDIL.fraction.(float %56)
>  br i1 %181, label %IF60, label %ELSE61
>
>IF60:                                             ; preds = %ENDIF56
>  %183 = fsub float -0.000000e+00, %182
>  %184 = fadd float 1.000000e+00, %183
>  %185 = fdiv float 1.000000e+00, %23
>  %186 = fmul float %184, %185
>  %187 = fsub float -0.000000e+00, %186
>  %188 = fadd float 2.000000e+00, %187
>  br label %ENDIF32
>
>ELSE61:                                           ; preds = %ENDIF56
>  %189 = fdiv float 1.000000e+00, %23
>  %190 = fmul float %182, %189
>  br label %ENDIF32
>
>IF63:                                             ; preds = %ENDIF32
>  %191 = fcmp uge float %temp20.0, 0.000000e+00
>  %192 = select i1 %191, float 1.000000e+00, float 0.000000e+00
>  %193 = fsub float -0.000000e+00, %192
>  %194 = fptosi float %193 to i32
>  %195 = bitcast i32 %194 to float
>  %196 = fcmp ult float %temp20.0, 1.000000e+00
>  %197 = select i1 %196, float 1.000000e+00, float 0.000000e+00
>  %198 = fsub float -0.000000e+00, %197
>  %199 = fptosi float %198 to i32
>  %200 = bitcast i32 %199 to float
>  %201 = bitcast float %195 to i32
>  %202 = bitcast float %200 to i32
>  %203 = and i32 %201, %202
>  %204 = bitcast i32 %203 to float
>  %205 = fcmp uge float %temp21.0, 0.000000e+00
>  %206 = select i1 %205, float 1.000000e+00, float 0.000000e+00
>  %207 = fsub float -0.000000e+00, %206
>  %208 = fptosi float %207 to i32
>  %209 = bitcast i32 %208 to float
>  %210 = bitcast float %204 to i32
>  %211 = bitcast float %209 to i32
>  %212 = and i32 %210, %211
>  %213 = bitcast i32 %212 to float
>  %214 = fcmp ult float %temp21.0, 1.000000e+00
>  %215 = select i1 %214, float 1.000000e+00, float 0.000000e+00
>  %216 = fsub float -0.000000e+00, %215
>  %217 = fptosi float %216 to i32
>  %218 = bitcast i32 %217 to float
>  %219 = bitcast float %213 to i32
>  %220 = bitcast float %218 to i32
>  %221 = and i32 %219, %220
>  %222 = bitcast i32 %221 to float
>  %223 = bitcast float %222 to i32
>  %224 = xor i32 %223, -1
>  %225 = bitcast i32 %224 to float
>  %226 = bitcast float %225 to i32
>  %227 = icmp ne i32 %226, 0
>  br i1 %227, label %ENDIF62, label %ELSE67
>
>ENDIF62:                                          ; preds = %ELSE67, %IF63, %ENDIF32
>  %temp4.0 = phi float [ 0xFFFFFFFFE0000000, %ENDIF32 ], [ 0xFFFFFFFFE0000000, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp8.0 = phi float [ %temp20.0, %ENDIF32 ], [ %234, %ELSE67 ], [ %temp20.0, %IF63 ]
>  %temp9.0 = phi float [ %temp21.0, %ENDIF32 ], [ %235, %ELSE67 ], [ %temp21.0, %IF63 ]
>  %temp12.0 = phi float [ %80, %ENDIF32 ], [ %225, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %temp13.3 = phi float [ %temp13.0, %ENDIF32 ], [ %temp13.0, %ELSE67 ], [ 0.000000e+00, %IF63 ]
>  %228 = bitcast float %temp4.0 to i32
>  %229 = icmp ne i32 %228, 0
>  br i1 %229, label %IF69, label %ENDIF
>
>ELSE67:                                           ; preds = %IF63
>  %230 = call float @llvm.AMDIL.fraction.(float %temp20.0)
>  %231 = call float @llvm.AMDIL.fraction.(float %temp21.0)
>  %232 = fdiv float 1.000000e+00, %22
>  %233 = fdiv float 1.000000e+00, %23
>  %234 = fmul float %230, %232
>  %235 = fmul float %231, %233
>  br label %ENDIF62
>
>IF69:                                             ; preds = %ENDIF62
>  %236 = bitcast float %temp8.0 to i32
>  %237 = bitcast float %temp9.0 to i32
>  %238 = insertelement <2 x i32> undef, i32 %236, i32 0
>  %239 = insertelement <2 x i32> %238, i32 %237, i32 1
>  %240 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %239, <32 x i8> %32, <16 x i8> %34, i32 2)
>  %241 = extractelement <4 x float> %240, i32 0
>  %242 = extractelement <4 x float> %240, i32 1
>  %243 = extractelement <4 x float> %240, i32 2
>  %244 = extractelement <4 x float> %240, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: readonly
>declare float @floor(float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>c08c0100
>bf8c007f
>c201190b
>c201990a
>c2021909
>c2029908
>c20b1903
>c20b9902
>c2031901
>c2039900
>c20a190c
>bf8c007f
>d1020000
>02011414
>d2000000
>00018280
>d1040000
>02010100
>be802400
>8980007e
>bf880102
>7e140214
>7e120206
>7e100207
>100a1303
>10001102
>4a1a14ca
>d1040006
>0201010d
>d200000b
>00198280
>d1040006
>0201010b
>7e020305
>be862406
>8986067e
>bf8800a9
>d1040014
>0201030d
>d200000b
>00518280
>d1040014
>0201010b
>bf8c070f
>be942414
>8994147e
>bf880090
>d1040018
>0201050d
>d200000b
>00618280
>d1040018
>0201010b
>be982418
>8998187e
>bf880045
>d104001a
>0201070d
>7e020305
>7e160300
>be9a241a
>899a1a7e
>bf88003c
>7e164900
>d206010b
>0201010b
>101616f0
>7e16410b
>0616170b
>081616f2
>7e1802ff
>3a83126f
>d002001c
>0202190b
>d200000b
>0071e480
>d206000b
>2201010b
>7e16110b
>d104001c
>0201010b
>7e184100
>be9c241c
>899c1c7e
>7e165508
>1016170c
>be9c251c
>89fe1c7e
>7e165508
>081818f2
>1016170c
>081616f4
>88fe1c7e
>7e184905
>d206010c
>0201010c
>101818f0
>7e18410c
>0618190c
>081818f2
>7e1a02ff
>3a83126f
>d002001c
>02021b0c
>d200000c
>0071e480
>d206000c
>2201010c
>7e18110c
>d104001c
>0201010c
>7e184105
>be9c241c
>899c1c7e
>7e1a5509
>10021b0c
>be9c251c
>89fe1c7e
>7e1a5509
>081818f2
>10181b0c
>080218f4
>88fe1c7e
>88fe1a7e
>7e180305
>be982518
>89fe187e
>bf88003e
>d00c001a
>0201e500
>d200000b
>0069e480
>d206000b
>2201010b
>7e16110b
>d104001a
>0201010b
>be9a241a
>899a1a7e
>d002001c
>02010100
>d200000b
>0071e480
>d206000b
>2201010b
>7e16110b
>d10a001c
>0201010b
>d200000b
>00710100
>be9a251a
>89fe1a7e
>7e160217
>1016110b
>d282000b
>03c9e30b
>88fe1a7e
>d00c001a
>0201e505
>d200000c
>0069e480
>d206000c
>2201010c
>7e18110c
>d104001a
>0201010c
>be9a241a
>899a1a7e
>d002001c
>02010105
>d200000c
>0071e480
>d206000c
>2201010c
>7e18110c
>d10a001c
>0201010c
>d200000d
>00710105
>be9a251a
>89fe1a7e
>7e180216
>1018130c
>d282000d
>03c9e30c
>88fe1a7e
>7e185509
>1002190d
>7e1a5508
>10161b0b
>88fe187e
>be942514
>89fe147e
>7e184905
>7e165509
>7e084105
>d2820001
>04321704
>7e084900
>7e0a5508
>7e0c4100
>d282000b
>04120b06
>88fe147e
>7e0a030c
>7e00030b
>88fe067e
>d1040006
>0201150a
>d200000a
>00198280
>7e1c02c1
>be862406
>8986067e
>bf880032
>d0020014
>0201e500
>d200000a
>0051e480
>d206000a
>2201010a
>7e14110a
>d00c0014
>02010100
>d200000b
>0051e480
>d206000b
>2201010b
>7e16110b
>3614150b
>d00c0014
>02010101
>d200000b
>0051e480
>d206000b
>2201010b
>7e16110b
>3614170a
>d0020014
>0201e501
>d200000b
>0051e480
>d206000b
>2201010b
>7e16110b
>3614170a
>3a2014c1
>d1040014
>0201830a
>7e1e0280
>7e14030f
>7e1c030f
>be942414
>8994147e
>7e125509
>7e144101
>1002130a
>7e105508
>7e124100
>10001109
>7e1c02c1
>7e1e0305
>7e140310
>88fe147e
>7e0a030f
>88fe067e
>d10a0006
>0201010e
>7e0c0280
>7e0e0306
>be862406
>8986067e
>f0800f00
>00430a00
>bf8c0770
>7e0a030b
>7e0c030c
>7e0e030d
>88fe067e
>be802500
>7e120202
>7e100203
>7e020204
>7e000205
>89fe007e
>f0800f00
>00430402
>bf8c0770
>7e140304
>88fe007e
>10040f09
>10060d08
>5e040503
>10020b01
>10001500
>5e000300
>f8001c0f
>02000200
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..25]
>DCL TEMP[0..6], LOCAL
>IMM[0] INT32 {0, 1, 3, 2}
>IMM[1] FLT32 {    0.0000,     2.0000,     0.0000,     1.0000}
>IMM[2] INT32 {4, 5, 6, 7}
>IMM[3] INT32 {8, 0, 0, 0}
>  0: MOV TEMP[0].x, IMM[0].xxxx
>  1: MUL TEMP[1].xyz, CONST[23].xyzz, IN[0].xxxx
>  2: MAD TEMP[1].xyz, CONST[24].xyzz, IN[0].yyyy, TEMP[1].xyzz
>  3: ADD TEMP[1].xyz, TEMP[1].xyzz, CONST[25].xyzz
>  4: USEQ TEMP[2].x, CONST[21].xxxx, IMM[0].xxxx
>  5: UIF TEMP[2].xxxx :0
>  6:   MUL TEMP[2].x, TEMP[1].xxxx, CONST[20].xxxx
>  7:   ADD TEMP[2].x, TEMP[1].yyyy, -TEMP[2].xxxx
>  8:   MUL TEMP[2].x, TEMP[2].xxxx, CONST[19].xxxx
>  9:   MUL TEMP[3].x, CONST[18].xxxx, TEMP[1].zzzz
> 10:   MUL TEMP[4].x, CONST[17].xxxx, TEMP[1].zzzz
> 11: ELSE :0
> 12:   USEQ TEMP[5].x, CONST[21].xxxx, IMM[0].yyyy
> 13:   UIF TEMP[5].xxxx :0
> 14:     MOV TEMP[2].x, TEMP[1].xxxx
> 15:     MUL TEMP[3].x, CONST[18].xxxx, TEMP[1].zzzz
> 16:     MUL TEMP[4].x, CONST[17].xxxx, TEMP[1].zzzz
> 17:   ENDIF
> 18: ENDIF
> 19: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[3].xxxx
> 20: USEQ TEMP[1].x, CONST[22].xxxx, IMM[0].yyyy
> 21: UIF TEMP[1].xxxx :0
> 22:   BGNLOOP :0
> 23:     SGE TEMP[1].x, TEMP[4].xxxx, TEMP[2].xxxx
> 24:     F2I TEMP[1].x, -TEMP[1]
> 25:     UIF TEMP[1].xxxx :0
> 26:       BRK
> 27:     ENDIF
> 28:     ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
> 29:   ENDLOOP :0
> 30:   BGNLOOP :0
> 31:     SGE TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx
> 32:     F2I TEMP[1].x, -TEMP[1]
> 33:     UIF TEMP[1].xxxx :0
> 34:       BRK
> 35:     ENDIF
> 36:     ADD TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
> 37:   ENDLOOP :0
> 38: ENDIF
> 39: USEQ TEMP[1].x, CONST[22].xxxx, IMM[0].zzzz
> 40: UIF TEMP[1].xxxx :0
> 41:   BGNLOOP :0
> 42:     SGE TEMP[1].x, TEMP[4].xxxx, TEMP[2].xxxx
> 43:     F2I TEMP[1].x, -TEMP[1]
> 44:     UIF TEMP[1].xxxx :0
> 45:       BRK
> 46:     ENDIF
> 47:     ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[4].xxxx
> 48:     USEQ TEMP[3].x, TEMP[0].xxxx, IMM[0].xxxx
> 49:     UIF TEMP[3].xxxx :0
> 50:       MOV TEMP[0].x, IMM[0].yyyy
> 51:     ELSE :0
> 52:       MOV TEMP[0].x, IMM[0].xxxx
> 53:     ENDIF
> 54:   ENDLOOP :0
> 55:   BGNLOOP :0
> 56:     SGE TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx
> 57:     F2I TEMP[1].x, -TEMP[1]
> 58:     UIF TEMP[1].xxxx :0
> 59:       BRK
> 60:     ENDIF
> 61:     ADD TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
> 62:     USEQ TEMP[3].x, TEMP[0].xxxx, IMM[0].xxxx
> 63:     UIF TEMP[3].xxxx :0
> 64:       MOV TEMP[0].x, IMM[0].yyyy
> 65:     ELSE :0
> 66:       MOV TEMP[0].x, IMM[0].xxxx
> 67:     ENDIF
> 68:   ENDLOOP :0
> 69:   USEQ TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy
> 70:   UIF TEMP[0].xxxx :0
> 71:     ADD TEMP[2].x, TEMP[4].xxxx, -TEMP[2].xxxx
> 72:   ENDIF
> 73: ENDIF
> 74: RCP TEMP[0].x, TEMP[4].xxxx
> 75: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[0].xxxx
> 76: SLT TEMP[1].x, TEMP[0].xxxx, CONST[16].xxxx
> 77: F2I TEMP[1].x, -TEMP[1]
> 78: ISGE TEMP[2].x, CONST[15].xxxx, IMM[0].yyyy
> 79: AND TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
> 80: UIF TEMP[1].xxxx :0
> 81:   MOV TEMP[1], CONST[14]
> 82:   MOV TEMP[2], CONST[14]
> 83:   MOV TEMP[3].x, CONST[16].xxxx
> 84:   MOV TEMP[4].x, CONST[16].xxxx
> 85: ELSE :0
> 86:   SLT TEMP[5].x, TEMP[0].xxxx, CONST[13].xxxx
> 87:   F2I TEMP[5].x, -TEMP[5]
> 88:   ISGE TEMP[6].x, CONST[15].xxxx, IMM[0].wwww
> 89:   AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
> 90:   UIF TEMP[5].xxxx :0
> 91:     MOV TEMP[1], CONST[14]
> 92:     MOV TEMP[2], CONST[12]
> 93:     MOV TEMP[3].x, CONST[13].xxxx
> 94:     MOV TEMP[4].x, CONST[16].xxxx
> 95:   ELSE :0
> 96:     SLT TEMP[5].x, TEMP[0].xxxx, CONST[11].xxxx
> 97:     F2I TEMP[5].x, -TEMP[5]
> 98:     ISGE TEMP[6].x, CONST[15].xxxx, IMM[0].zzzz
> 99:     AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>100:     UIF TEMP[5].xxxx :0
>101:       MOV TEMP[1], CONST[12]
>102:       MOV TEMP[2], CONST[10]
>103:       MOV TEMP[3].x, CONST[11].xxxx
>104:       MOV TEMP[4].x, CONST[13].xxxx
>105:     ELSE :0
>106:       SLT TEMP[5].x, TEMP[0].xxxx, CONST[9].xxxx
>107:       F2I TEMP[5].x, -TEMP[5]
>108:       ISGE TEMP[6].x, CONST[15].xxxx, IMM[2].xxxx
>109:       AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>110:       UIF TEMP[5].xxxx :0
>111:         MOV TEMP[1], CONST[10]
>112:         MOV TEMP[2], CONST[8]
>113:         MOV TEMP[3].x, CONST[9].xxxx
>114:         MOV TEMP[4].x, CONST[11].xxxx
>115:       ELSE :0
>116:         SLT TEMP[5].x, TEMP[0].xxxx, CONST[7].xxxx
>117:         F2I TEMP[5].x, -TEMP[5]
>118:         ISGE TEMP[6].x, CONST[15].xxxx, IMM[2].yyyy
>119:         AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>120:         UIF TEMP[5].xxxx :0
>121:           MOV TEMP[1], CONST[8]
>122:           MOV TEMP[2], CONST[6]
>123:           MOV TEMP[3].x, CONST[7].xxxx
>124:           MOV TEMP[4].x, CONST[9].xxxx
>125:         ELSE :0
>126:           SLT TEMP[5].x, TEMP[0].xxxx, CONST[5].xxxx
>127:           F2I TEMP[5].x, -TEMP[5]
>128:           ISGE TEMP[6].x, CONST[15].xxxx, IMM[2].zzzz
>129:           AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>130:           UIF TEMP[5].xxxx :0
>131:             MOV TEMP[1], CONST[6]
>132:             MOV TEMP[2], CONST[4]
>133:             MOV TEMP[3].x, CONST[5].xxxx
>134:             MOV TEMP[4].x, CONST[7].xxxx
>135:           ELSE :0
>136:             SLT TEMP[5].x, TEMP[0].xxxx, CONST[3].xxxx
>137:             F2I TEMP[5].x, -TEMP[5]
>138:             ISGE TEMP[6].x, CONST[15].xxxx, IMM[2].wwww
>139:             AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>140:             UIF TEMP[5].xxxx :0
>141:               MOV TEMP[1], CONST[4]
>142:               MOV TEMP[2], CONST[2]
>143:               MOV TEMP[3].x, CONST[3].xxxx
>144:               MOV TEMP[4].x, CONST[5].xxxx
>145:             ELSE :0
>146:               SLT TEMP[5].x, TEMP[0].xxxx, CONST[1].xxxx
>147:               F2I TEMP[5].x, -TEMP[5]
>148:               ISGE TEMP[6].x, CONST[15].xxxx, IMM[3].xxxx
>149:               AND TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
>150:               UIF TEMP[5].xxxx :0
>151:                 MOV TEMP[1], CONST[2]
>152:                 MOV TEMP[2], CONST[0]
>153:                 MOV TEMP[3].x, CONST[1].xxxx
>154:                 MOV TEMP[4].x, CONST[3].xxxx
>155:               ELSE :0
>156:                 MOV TEMP[1], CONST[0]
>157:                 MOV TEMP[2], CONST[0]
>158:                 MOV TEMP[3].x, CONST[1].xxxx
>159:                 MOV TEMP[4].x, CONST[1].xxxx
>160:               ENDIF
>161:             ENDIF
>162:           ENDIF
>163:         ENDIF
>164:       ENDIF
>165:     ENDIF
>166:   ENDIF
>167: ENDIF
>168: ADD TEMP[5].x, TEMP[3].xxxx, -TEMP[4].xxxx
>169: SLT TEMP[5].x, IMM[1].yyyy, TEMP[5].xxxx
>170: F2I TEMP[5].x, -TEMP[5]
>171: UIF TEMP[5].xxxx :0
>172:   MOV TEMP[5].x, IMM[1].xxxx
>173: ELSE :0
>174:   ADD TEMP[6].x, TEMP[3].xxxx, -TEMP[4].xxxx
>175:   SLT TEMP[6].x, TEMP[6].xxxx, IMM[1].zzzz
>176:   F2I TEMP[6].x, -TEMP[6]
>177:   UIF TEMP[6].xxxx :0
>178:     MOV TEMP[5].x, IMM[1].xxxx
>179:   ELSE :0
>180:     ADD TEMP[0].x, TEMP[0].xxxx, -TEMP[4].xxxx
>181:     ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[4].xxxx
>182:     RCP TEMP[3].x, TEMP[3].xxxx
>183:     MUL TEMP[5].x, TEMP[0].xxxx, TEMP[3].xxxx
>184:   ENDIF
>185: ENDIF
>186: ADD TEMP[0].x, IMM[1].wwww, -TEMP[5].xxxx
>187: MUL TEMP[3].x, TEMP[5].xxxx, TEMP[2].wwww
>188: MAD TEMP[0].x, TEMP[0].xxxx, TEMP[1].wwww, TEMP[3].xxxx
>189: ADD TEMP[3].x, IMM[1].wwww, -TEMP[5].xxxx
>190: MUL TEMP[2].xyz, TEMP[5].xxxx, TEMP[2].xyzz
>191: MAD TEMP[1].xyz, TEMP[3].xxxx, TEMP[1].xyzz, TEMP[2].xyzz
>192: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
>193: MOV TEMP[1].w, TEMP[0].xxxx
>194: MOV OUT[0], TEMP[1]
>195: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 108)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 140)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 236)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 240)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 304)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 384)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 388)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 392)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 400)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 404)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 408)
>  %78 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %79 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %80 = fmul float %69, %78
>  %81 = fmul float %70, %78
>  %82 = fmul float %71, %78
>  %83 = fmul float %72, %79
>  %84 = fadd float %83, %80
>  %85 = fmul float %73, %79
>  %86 = fadd float %85, %81
>  %87 = fmul float %74, %79
>  %88 = fadd float %87, %82
>  %89 = fadd float %84, %75
>  %90 = fadd float %86, %76
>  %91 = fadd float %88, %77
>  %92 = bitcast float %67 to i32
>  %93 = icmp eq i32 %92, 0
>  %94 = sext i1 %93 to i32
>  %95 = bitcast i32 %94 to float
>  %96 = bitcast float %95 to i32
>  %97 = icmp ne i32 %96, 0
>  br i1 %97, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %98 = fmul float %89, %66
>  %99 = fsub float -0.000000e+00, %98
>  %100 = fadd float %90, %99
>  %101 = fmul float %100, %65
>  %102 = fmul float %64, %91
>  %103 = fmul float %63, %91
>  br label %ENDIF
>
>ELSE:                                             ; preds = %main_body
>  %104 = bitcast float %67 to i32
>  %105 = icmp eq i32 %104, 1
>  %106 = sext i1 %105 to i32
>  %107 = bitcast i32 %106 to float
>  %108 = bitcast float %107 to i32
>  %109 = icmp ne i32 %108, 0
>  br i1 %109, label %IF29, label %ENDIF
>
>ENDIF:                                            ; preds = %IF29, %ELSE, %IF
>  %temp12.0 = phi float [ %102, %IF ], [ %118, %IF29 ], [ 0.000000e+00, %ELSE ]
>  %temp8.0 = phi float [ %101, %IF ], [ %89, %IF29 ], [ %95, %ELSE ]
>  %temp16.0 = phi float [ %103, %IF ], [ %119, %IF29 ], [ 0.000000e+00, %ELSE ]
>  %110 = fsub float -0.000000e+00, %temp12.0
>  %111 = fadd float %temp8.0, %110
>  %112 = bitcast float %68 to i32
>  %113 = icmp eq i32 %112, 1
>  %114 = sext i1 %113 to i32
>  %115 = bitcast i32 %114 to float
>  %116 = bitcast float %115 to i32
>  %117 = icmp ne i32 %116, 0
>  br i1 %117, label %IF32, label %ENDIF31
>
>IF29:                                             ; preds = %ELSE
>  %118 = fmul float %64, %91
>  %119 = fmul float %63, %91
>  br label %ENDIF
>
>IF32:                                             ; preds = %ENDIF
>  %120 = fsub float -0.000000e+00, %temp16.0
>  br label %LOOP
>
>ENDIF31:                                          ; preds = %LOOP38, %ENDIF
>  %temp8.2 = phi float [ %111, %ENDIF ], [ %temp8.4, %LOOP38 ]
>  %121 = bitcast float %68 to i32
>  %122 = icmp eq i32 %121, 3
>  %123 = sext i1 %122 to i32
>  %124 = bitcast i32 %123 to float
>  %125 = bitcast float %124 to i32
>  %126 = icmp ne i32 %125, 0
>  br i1 %126, label %IF43, label %ENDIF42
>
>LOOP:                                             ; preds = %ENDIF34, %IF32
>  %temp8.3 = phi float [ %111, %IF32 ], [ %134, %ENDIF34 ]
>  %127 = fcmp uge float %temp16.0, %temp8.3
>  %128 = select i1 %127, float 1.000000e+00, float 0.000000e+00
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fptosi float %129 to i32
>  %131 = bitcast i32 %130 to float
>  %132 = bitcast float %131 to i32
>  %133 = icmp ne i32 %132, 0
>  br i1 %133, label %LOOP38, label %ENDIF34
>
>ENDIF34:                                          ; preds = %LOOP
>  %134 = fadd float %temp8.3, %120
>  br label %LOOP
>
>LOOP38:                                           ; preds = %LOOP, %ENDIF39
>  %temp8.4 = phi float [ %142, %ENDIF39 ], [ %temp8.3, %LOOP ]
>  %135 = fcmp uge float %temp8.4, 0.000000e+00
>  %136 = select i1 %135, float 1.000000e+00, float 0.000000e+00
>  %137 = fsub float -0.000000e+00, %136
>  %138 = fptosi float %137 to i32
>  %139 = bitcast i32 %138 to float
>  %140 = bitcast float %139 to i32
>  %141 = icmp ne i32 %140, 0
>  br i1 %141, label %ENDIF31, label %ENDIF39
>
>ENDIF39:                                          ; preds = %LOOP38
>  %142 = fadd float %temp8.4, %temp16.0
>  br label %LOOP38
>
>IF43:                                             ; preds = %ENDIF31
>  %143 = fsub float -0.000000e+00, %temp16.0
>  br label %LOOP46
>
>ENDIF42:                                          ; preds = %IF62, %IF56, %ENDIF31
>  %temp8.5 = phi float [ %temp8.2, %ENDIF31 ], [ %196, %IF62 ], [ %temp8.7, %IF56 ]
>  %144 = fdiv float 1.000000e+00, %temp16.0
>  %145 = fmul float %temp8.5, %144
>  %146 = fcmp ult float %145, %62
>  %147 = select i1 %146, float 1.000000e+00, float 0.000000e+00
>  %148 = fsub float -0.000000e+00, %147
>  %149 = fptosi float %148 to i32
>  %150 = bitcast i32 %149 to float
>  %151 = bitcast float %61 to i32
>  %152 = icmp sge i32 %151, 1
>  %153 = sext i1 %152 to i32
>  %154 = bitcast i32 %153 to float
>  %155 = bitcast float %150 to i32
>  %156 = bitcast float %154 to i32
>  %157 = and i32 %155, %156
>  %158 = bitcast i32 %157 to float
>  %159 = bitcast float %158 to i32
>  %160 = icmp ne i32 %159, 0
>  br i1 %160, label %ENDIF64, label %ELSE66
>
>LOOP46:                                           ; preds = %ENDIF47, %IF43
>  %temp8.6 = phi float [ %temp8.2, %IF43 ], [ %168, %ENDIF47 ]
>  %temp.0 = phi float [ 0.000000e+00, %IF43 ], [ %., %ENDIF47 ]
>  %161 = fcmp uge float %temp16.0, %temp8.6
>  %162 = select i1 %161, float 1.000000e+00, float 0.000000e+00
>  %163 = fsub float -0.000000e+00, %162
>  %164 = fptosi float %163 to i32
>  %165 = bitcast i32 %164 to float
>  %166 = bitcast float %165 to i32
>  %167 = icmp ne i32 %166, 0
>  br i1 %167, label %LOOP54, label %ENDIF47
>
>ENDIF47:                                          ; preds = %LOOP46
>  %168 = fadd float %temp8.6, %143
>  %169 = bitcast float %temp.0 to i32
>  %170 = icmp eq i32 %169, 0
>  %171 = sext i1 %170 to i32
>  %172 = bitcast i32 %171 to float
>  %173 = bitcast float %172 to i32
>  %174 = icmp ne i32 %173, 0
>  %. = select i1 %174, float 0x36A0000000000000, float 0.000000e+00
>  br label %LOOP46
>
>LOOP54:                                           ; preds = %LOOP46, %ENDIF55
>  %temp8.7 = phi float [ %188, %ENDIF55 ], [ %temp8.6, %LOOP46 ]
>  %temp.2 = phi float [ %.94, %ENDIF55 ], [ %temp.0, %LOOP46 ]
>  %175 = fcmp uge float %temp8.7, 0.000000e+00
>  %176 = select i1 %175, float 1.000000e+00, float 0.000000e+00
>  %177 = fsub float -0.000000e+00, %176
>  %178 = fptosi float %177 to i32
>  %179 = bitcast i32 %178 to float
>  %180 = bitcast float %179 to i32
>  %181 = icmp ne i32 %180, 0
>  br i1 %181, label %IF56, label %ENDIF55
>
>IF56:                                             ; preds = %LOOP54
>  %182 = bitcast float %temp.2 to i32
>  %183 = icmp eq i32 %182, 1
>  %184 = sext i1 %183 to i32
>  %185 = bitcast i32 %184 to float
>  %186 = bitcast float %185 to i32
>  %187 = icmp ne i32 %186, 0
>  br i1 %187, label %IF62, label %ENDIF42
>
>ENDIF55:                                          ; preds = %LOOP54
>  %188 = fadd float %temp8.7, %temp16.0
>  %189 = bitcast float %temp.2 to i32
>  %190 = icmp eq i32 %189, 0
>  %191 = sext i1 %190 to i32
>  %192 = bitcast i32 %191 to float
>  %193 = bitcast float %192 to i32
>  %194 = icmp ne i32 %193, 0
>  %.94 = select i1 %194, float 0x36A0000000000000, float 0.000000e+00
>  br label %LOOP54
>
>IF62:                                             ; preds = %IF56
>  %195 = fsub float -0.000000e+00, %temp8.7
>  %196 = fadd float %temp16.0, %195
>  br label %ENDIF42
>
>ELSE66:                                           ; preds = %ENDIF42
>  %197 = fcmp ult float %145, %56
>  %198 = select i1 %197, float 1.000000e+00, float 0.000000e+00
>  %199 = fsub float -0.000000e+00, %198
>  %200 = fptosi float %199 to i32
>  %201 = bitcast i32 %200 to float
>  %202 = bitcast float %61 to i32
>  %203 = icmp sge i32 %202, 2
>  %204 = sext i1 %203 to i32
>  %205 = bitcast i32 %204 to float
>  %206 = bitcast float %201 to i32
>  %207 = bitcast float %205 to i32
>  %208 = and i32 %206, %207
>  %209 = bitcast i32 %208 to float
>  %210 = bitcast float %209 to i32
>  %211 = icmp ne i32 %210, 0
>  br i1 %211, label %ENDIF64, label %ELSE69
>
>ENDIF64:                                          ; preds = %ELSE84, %ELSE81, %ELSE78, %ELSE75, %ELSE72, %ELSE69, %ELSE66, %ENDIF42
>  %temp11.0 = phi float [ %60, %ENDIF42 ], [ %55, %ELSE66 ], [ %50, %ELSE69 ], [ %45, %ELSE72 ], [ %40, %ELSE75 ], [ %35, %ELSE78 ], [ %25, %ELSE84 ], [ %30, %ELSE81 ]
>  %temp12.2 = phi float [ %62, %ENDIF42 ], [ %56, %ELSE66 ], [ %51, %ELSE69 ], [ %46, %ELSE72 ], [ %41, %ELSE75 ], [ %36, %ELSE78 ], [ %26, %ELSE84 ], [ %31, %ELSE81 ]
>  %temp10.0 = phi float [ %59, %ENDIF42 ], [ %54, %ELSE66 ], [ %49, %ELSE69 ], [ %44, %ELSE72 ], [ %39, %ELSE75 ], [ %34, %ELSE78 ], [ %24, %ELSE84 ], [ %29, %ELSE81 ]
>  %temp9.0 = phi float [ %58, %ENDIF42 ], [ %53, %ELSE66 ], [ %48, %ELSE69 ], [ %43, %ELSE72 ], [ %38, %ELSE75 ], [ %33, %ELSE78 ], [ %23, %ELSE84 ], [ %28, %ELSE81 ]
>  %temp8.9 = phi float [ %57, %ENDIF42 ], [ %52, %ELSE66 ], [ %47, %ELSE69 ], [ %42, %ELSE72 ], [ %37, %ELSE75 ], [ %32, %ELSE78 ], [ %22, %ELSE84 ], [ %27, %ELSE81 ]
>  %temp16.2 = phi float [ %62, %ENDIF42 ], [ %62, %ELSE66 ], [ %56, %ELSE69 ], [ %51, %ELSE72 ], [ %46, %ELSE75 ], [ %41, %ELSE78 ], [ %.95, %ELSE84 ], [ %36, %ELSE81 ]
>  %temp7.0 = phi float [ %60, %ENDIF42 ], [ %60, %ELSE66 ], [ %55, %ELSE69 ], [ %50, %ELSE72 ], [ %45, %ELSE75 ], [ %40, %ELSE78 ], [ %.96, %ELSE84 ], [ %35, %ELSE81 ]
>  %temp6.0 = phi float [ %59, %ENDIF42 ], [ %59, %ELSE66 ], [ %54, %ELSE69 ], [ %49, %ELSE72 ], [ %44, %ELSE75 ], [ %39, %ELSE78 ], [ %.97, %ELSE84 ], [ %34, %ELSE81 ]
>  %temp5.0 = phi float [ %58, %ENDIF42 ], [ %58, %ELSE66 ], [ %53, %ELSE69 ], [ %48, %ELSE72 ], [ %43, %ELSE75 ], [ %38, %ELSE78 ], [ %.98, %ELSE84 ], [ %33, %ELSE81 ]
>  %temp4.0 = phi float [ %57, %ENDIF42 ], [ %57, %ELSE66 ], [ %52, %ELSE69 ], [ %47, %ELSE72 ], [ %42, %ELSE75 ], [ %37, %ELSE78 ], [ %.99, %ELSE84 ], [ %32, %ELSE81 ]
>  %212 = fsub float -0.000000e+00, %temp16.2
>  %213 = fadd float %temp12.2, %212
>  %214 = fcmp ult float 2.000000e+00, %213
>  %215 = select i1 %214, float 1.000000e+00, float 0.000000e+00
>  %216 = fsub float -0.000000e+00, %215
>  %217 = fptosi float %216 to i32
>  %218 = bitcast i32 %217 to float
>  %219 = bitcast float %218 to i32
>  %220 = icmp ne i32 %219, 0
>  br i1 %220, label %ENDIF88, label %ELSE90
>
>ELSE69:                                           ; preds = %ELSE66
>  %221 = fcmp ult float %145, %51
>  %222 = select i1 %221, float 1.000000e+00, float 0.000000e+00
>  %223 = fsub float -0.000000e+00, %222
>  %224 = fptosi float %223 to i32
>  %225 = bitcast i32 %224 to float
>  %226 = bitcast float %61 to i32
>  %227 = icmp sge i32 %226, 3
>  %228 = sext i1 %227 to i32
>  %229 = bitcast i32 %228 to float
>  %230 = bitcast float %225 to i32
>  %231 = bitcast float %229 to i32
>  %232 = and i32 %230, %231
>  %233 = bitcast i32 %232 to float
>  %234 = bitcast float %233 to i32
>  %235 = icmp ne i32 %234, 0
>  br i1 %235, label %ENDIF64, label %ELSE72
>
>ELSE72:                                           ; preds = %ELSE69
>  %236 = fcmp ult float %145, %46
>  %237 = select i1 %236, float 1.000000e+00, float 0.000000e+00
>  %238 = fsub float -0.000000e+00, %237
>  %239 = fptosi float %238 to i32
>  %240 = bitcast i32 %239 to float
>  %241 = bitcast float %61 to i32
>  %242 = icmp sge i32 %241, 4
>  %243 = sext i1 %242 to i32
>  %244 = bitcast i32 %243 to float
>  %245 = bitcast float %240 to i32
>  %246 = bitcast float %244 to i32
>  %247 = and i32 %245, %246
>  %248 = bitcast i32 %247 to float
>  %249 = bitcast float %248 to i32
>  %250 = icmp ne i32 %249, 0
>  br i1 %250, label %ENDIF64, label %ELSE75
>
>ELSE75:                                           ; preds = %ELSE72
>  %251 = fcmp ult float %145, %41
>  %252 = select i1 %251, float 1.000000e+00, float 0.000000e+00
>  %253 = fsub float -0.000000e+00, %252
>  %254 = fptosi float %253 to i32
>  %255 = bitcast i32 %254 to float
>  %256 = bitcast float %61 to i32
>  %257 = icmp sge i32 %256, 5
>  %258 = sext i1 %257 to i32
>  %259 = bitcast i32 %258 to float
>  %260 = bitcast float %255 to i32
>  %261 = bitcast float %259 to i32
>  %262 = and i32 %260, %261
>  %263 = bitcast i32 %262 to float
>  %264 = bitcast float %263 to i32
>  %265 = icmp ne i32 %264, 0
>  br i1 %265, label %ENDIF64, label %ELSE78
>
>ELSE78:                                           ; preds = %ELSE75
>  %266 = fcmp ult float %145, %36
>  %267 = select i1 %266, float 1.000000e+00, float 0.000000e+00
>  %268 = fsub float -0.000000e+00, %267
>  %269 = fptosi float %268 to i32
>  %270 = bitcast i32 %269 to float
>  %271 = bitcast float %61 to i32
>  %272 = icmp sge i32 %271, 6
>  %273 = sext i1 %272 to i32
>  %274 = bitcast i32 %273 to float
>  %275 = bitcast float %270 to i32
>  %276 = bitcast float %274 to i32
>  %277 = and i32 %275, %276
>  %278 = bitcast i32 %277 to float
>  %279 = bitcast float %278 to i32
>  %280 = icmp ne i32 %279, 0
>  br i1 %280, label %ENDIF64, label %ELSE81
>
>ELSE81:                                           ; preds = %ELSE78
>  %281 = fcmp ult float %145, %31
>  %282 = select i1 %281, float 1.000000e+00, float 0.000000e+00
>  %283 = fsub float -0.000000e+00, %282
>  %284 = fptosi float %283 to i32
>  %285 = bitcast i32 %284 to float
>  %286 = bitcast float %61 to i32
>  %287 = icmp sge i32 %286, 7
>  %288 = sext i1 %287 to i32
>  %289 = bitcast i32 %288 to float
>  %290 = bitcast float %285 to i32
>  %291 = bitcast float %289 to i32
>  %292 = and i32 %290, %291
>  %293 = bitcast i32 %292 to float
>  %294 = bitcast float %293 to i32
>  %295 = icmp ne i32 %294, 0
>  br i1 %295, label %ENDIF64, label %ELSE84
>
>ELSE84:                                           ; preds = %ELSE81
>  %296 = fcmp ult float %145, %26
>  %297 = select i1 %296, float 1.000000e+00, float 0.000000e+00
>  %298 = fsub float -0.000000e+00, %297
>  %299 = fptosi float %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = bitcast float %61 to i32
>  %302 = icmp sge i32 %301, 8
>  %303 = sext i1 %302 to i32
>  %304 = bitcast i32 %303 to float
>  %305 = bitcast float %300 to i32
>  %306 = bitcast float %304 to i32
>  %307 = and i32 %305, %306
>  %308 = bitcast i32 %307 to float
>  %309 = bitcast float %308 to i32
>  %310 = icmp ne i32 %309, 0
>  %.95 = select i1 %310, float %31, float %26
>  %.96 = select i1 %310, float %30, float %25
>  %.97 = select i1 %310, float %29, float %24
>  %.98 = select i1 %310, float %28, float %23
>  %.99 = select i1 %310, float %27, float %22
>  br label %ENDIF64
>
>ELSE90:                                           ; preds = %ENDIF64
>  %311 = fsub float -0.000000e+00, %temp16.2
>  %312 = fadd float %temp12.2, %311
>  %313 = fcmp ult float %312, 0x3EB0C6F7A0000000
>  %314 = select i1 %313, float 1.000000e+00, float 0.000000e+00
>  %315 = fsub float -0.000000e+00, %314
>  %316 = fptosi float %315 to i32
>  %317 = bitcast i32 %316 to float
>  %318 = bitcast float %317 to i32
>  %319 = icmp ne i32 %318, 0
>  br i1 %319, label %ENDIF88, label %ELSE93
>
>ENDIF88:                                          ; preds = %ELSE93, %ELSE90, %ENDIF64
>  %temp20.0 = phi float [ 0.000000e+00, %ENDIF64 ], [ %347, %ELSE93 ], [ 0.000000e+00, %ELSE90 ]
>  %320 = fsub float -0.000000e+00, %temp20.0
>  %321 = fadd float 1.000000e+00, %320
>  %322 = fmul float %temp20.0, %temp11.0
>  %323 = fmul float %321, %temp7.0
>  %324 = fadd float %323, %322
>  %325 = fsub float -0.000000e+00, %temp20.0
>  %326 = fadd float 1.000000e+00, %325
>  %327 = fmul float %temp20.0, %temp8.9
>  %328 = fmul float %temp20.0, %temp9.0
>  %329 = fmul float %temp20.0, %temp10.0
>  %330 = fmul float %326, %temp4.0
>  %331 = fadd float %330, %327
>  %332 = fmul float %326, %temp5.0
>  %333 = fadd float %332, %328
>  %334 = fmul float %326, %temp6.0
>  %335 = fadd float %334, %329
>  %336 = fmul float %331, %324
>  %337 = fmul float %333, %324
>  %338 = fmul float %335, %324
>  %339 = call i32 @llvm.SI.packf16(float %336, float %337)
>  %340 = bitcast i32 %339 to float
>  %341 = call i32 @llvm.SI.packf16(float %338, float %324)
>  %342 = bitcast i32 %341 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %340, float %342, float %340, float %342)
>  ret void
>
>ELSE93:                                           ; preds = %ELSE90
>  %343 = fadd float %145, %311
>  %344 = fsub float -0.000000e+00, %temp16.2
>  %345 = fadd float %temp12.2, %344
>  %346 = fdiv float 1.000000e+00, %345
>  %347 = fmul float %343, %346
>  br label %ENDIF88
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0000
>c80d0001
>c0960100
>bf8c007f
>c2002d5e
>bf8c007f
>10000600
>c2002d62
>bf8c007f
>d2820000
>04020400
>c2002d66
>bf8c007f
>06000000
>c2002d5d
>bf8c007f
>10020600
>c2002d61
>bf8c007f
>d2820001
>04060400
>c2002d65
>bf8c007f
>06020200
>c2002d5c
>bf8c007f
>10060600
>c2002d60
>bf8c007f
>d2820002
>040e0400
>c2002d64
>bf8c007f
>06040400
>c215ad58
>c214ad50
>c2152d4c
>c2182d48
>c218ad44
>c2002d40
>c200ad3c
>c2012d3b
>c201ad3a
>c2022d39
>c202ad38
>c2032d34
>c203ad33
>c2042d32
>c204ad31
>c2052d30
>c205ad2c
>c2062d2b
>c206ad2a
>c2072d29
>c207ad28
>c2082d24
>c208ad23
>c2092d22
>c209ad21
>c20a2d20
>c20aad1c
>c20b2d1b
>c20bad1a
>c20c2d19
>c20cad18
>c20d2d14
>c20dad13
>c20e2d12
>c20ead11
>c20f2d10
>c20fad0c
>c2102d0b
>c210ad0a
>c2112d09
>c211ad08
>c2122d04
>c212ad03
>c2132d02
>c213ad01
>c2142d00
>c2172d54
>bf8c007f
>d104002c
>0201002e
>d2000003
>00b18280
>d104002c
>02010103
>7e080230
>7e0a0231
>beac242c
>89ac2c7e
>bf88000b
>7e0c022e
>d104002e
>02010306
>7e0e0280
>7e0c0307
>beae242e
>89ae2e7e
>100e0105
>100c0104
>7e060302
>88fe2e7e
>beac252c
>7e56022b
>89fe2c7e
>7e100229
>7e06022a
>100e0105
>100c0104
>10001102
>08000101
>10060700
>88fe2c7e
>08540d03
>d104002a
>0201032b
>beaa242a
>89aa2a7e
>bf880028
>d2060001
>22010107
>beac0480
>beae042c
>7e00032a
>d00c0030
>02020107
>d2000002
>00c1e480
>d2060002
>22010102
>7e041102
>d1040030
>02010102
>beb02430
>89b0307e
>06540300
>88fe307e
>88ae2e30
>8afe2e7e
>bf89ffef
>88fe2e7e
>7e540300
>d00c0030
>0201012a
>d2000000
>00c1e480
>d2060000
>22010100
>7e001100
>d1040030
>02010100
>beb02430
>89b0307e
>06000f2a
>88fe307e
>88ac2c30
>8afe2c7e
>bf89ffee
>88fe2c7e
>88fe2a7e
>7e080200
>7e160201
>7e060202
>7e020203
>7e040204
>7e000205
>7e120206
>7e140207
>7e100208
>7e0c0209
>7e0a020a
>7e4a020b
>7e4c020c
>7e4e020d
>7e50020e
>7e52020f
>7e400210
>7e420211
>7e440212
>7e460213
>7e480214
>7e360215
>7e380216
>7e3a0217
>7e3c0218
>7e3e0219
>7e2c021a
>7e2e021b
>7e30021c
>7e32021d
>7e34021e
>7e1e021f
>7e220220
>7e260221
>7e280222
>7e2a0223
>7e1a0224
>7e180225
>7e1c0226
>7e200227
>7e240228
>d1040000
>0201072b
>be802400
>8980007e
>bf880039
>d206002d
>22010107
>7e5c0280
>be820480
>be840402
>7e56032a
>7e58032e
>d00c0006
>02025707
>d200002a
>0019e480
>d206002a
>2201012a
>7e54112a
>d1040006
>0201012a
>be862406
>8986067e
>06545b2b
>d1040008
>0201012c
>d200002e
>00210280
>88fe067e
>88840406
>8afe047e
>bf89ffea
>88fe047e
>7e54032b
>7e5a032c
>d00c0006
>0201012a
>d200002b
>0019e480
>d206002b
>2201012b
>7e56112b
>d1040006
>0201012b
>be862406
>8986067e
>06560f2a
>d1040008
>0201012d
>d200002c
>00210280
>88fe067e
>88820206
>8afe027e
>bf89ffe9
>88fe027e
>d1040002
>0201032d
>be822402
>8982027e
>08545507
>88fe027e
>88fe007e
>7e0e5507
>100e0f2a
>d0020000
>02020907
>d200002a
>0001e480
>d206002a
>2201012a
>7e54112a
>d1080000
>0201010b
>d200002b
>00018280
>3654572a
>d1040000
>0201012a
>7e5c0304
>7e5a0303
>7e540301
>7e580302
>7e560300
>be802400
>8980007e
>bf8800c5
>d0020002
>02021307
>d200002a
>0009e480
>d206002a
>2201012a
>7e54112a
>d1080002
>0201030b
>d200002b
>00098280
>3654572a
>d1040002
>0201012a
>be822402
>8982027e
>bf8800a9
>d0020004
>02024b07
>d2000000
>0011e480
>d2060000
>22010100
>7e001100
>d1080004
>0201050b
>d2000001
>00118280
>36000300
>d1040004
>02010100
>7e000305
>7e040306
>7e020308
>7e06030a
>7e080309
>7e0a0329
>7e0c0328
>7e100327
>7e120325
>7e140326
>be842404
>8984047e
>bf88008d
>d0020006
>02024107
>d2000000
>0019e480
>d2060000
>22010100
>7e001100
>d1080006
>0201070b
>d2000001
>00198280
>36000300
>d1040006
>02010100
>7e000329
>7e040328
>7e020327
>7e060326
>7e080325
>7e0a0324
>7e0c0323
>7e100322
>7e120320
>7e140321
>be862406
>8986067e
>bf880071
>d0020008
>02023707
>d2000000
>0021e480
>d2060000
>22010100
>7e001100
>d1080008
>0201090b
>d2000001
>00218280
>36000300
>d1040008
>02010100
>7e000324
>7e040323
>7e020322
>7e060321
>7e080320
>7e0a031f
>7e0c031e
>7e10031d
>7e12031b
>7e14031c
>be882408
>8988087e
>bf880055
>d002000a
>02022d07
>d2000000
>0029e480
>d2060000
>22010100
>7e001100
>d108000a
>02010b0b
>d2000001
>00298280
>36000300
>d104000a
>02010100
>7e00031f
>7e04031e
>7e02031d
>7e06031c
>7e08031b
>7e0a031a
>7e0c0319
>7e100318
>7e120316
>7e140317
>be8a240a
>898a0a7e
>bf880039
>d002000c
>02021f07
>d2000000
>0031e480
>d2060000
>22010100
>7e001100
>d108000c
>02010d0b
>d2000001
>00318280
>36000300
>d104000c
>02010100
>7e00031a
>7e040319
>7e020318
>7e060317
>7e080316
>7e0a0315
>7e0c0314
>7e100313
>7e12030f
>7e140311
>be8c240c
>898c0c7e
>bf88001d
>d002000e
>02021b07
>d2000000
>0039e480
>d2060000
>22010100
>7e001100
>d108000e
>02010f0b
>d2000001
>00398280
>36000300
>d10a000e
>02010100
>d2000000
>003a2b12
>d2000002
>003a2910
>d2000001
>003a270e
>d2000003
>003a230c
>d2000004
>003a1f0d
>7e0a0312
>7e0c0310
>7e10030e
>7e12030d
>7e14030c
>88fe0c7e
>88fe0a7e
>88fe087e
>88fe067e
>88fe047e
>88fe027e
>7e560300
>7e580302
>7e540301
>7e5a0303
>7e5c0304
>7e06030a
>7e080309
>7e020308
>7e040306
>7e000305
>88fe007e
>080a5d04
>d0080000
>0201e905
>d2000005
>0001e480
>d2060005
>22010105
>7e0a1105
>d1040000
>02010105
>7e0a0280
>be802400
>8980007e
>bf880017
>080a5d04
>7e0c02ff
>358637bd
>d0020002
>02020d05
>d2000005
>0009e480
>d2060005
>22010105
>7e0a1105
>d1040002
>02010105
>d2060006
>2201012e
>7e0a0280
>be822402
>8982027e
>060a0d07
>08085d04
>7e085504
>100a0905
>bf8c070f
>88fe027e
>88fe007e
>10060705
>08080af2
>d2820003
>040e5b04
>10040505
>d2820002
>040a5904
>10040702
>10000105
>d2820000
>04025704
>10000700
>5e000500
>10020305
>d2820001
>04065504
>10020701
>5e020701
>f8001c0f
>01000100
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyxx
>  1: MOV OUT[1], TEMP[0]
>  2: MOV OUT[0], IN[0]
>  3: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>7e0a0280
>bf8c0770
>f800020f
>05050201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..25]
>DCL TEMP[0..9], LOCAL
>IMM[0] UINT32 {4294967295, 0, 0, 0}
>IMM[1] FLT32 {    0.0000,     0.0000,     0.5000,     1.0000}
>IMM[2] INT32 {0, 1, 3, 2}
>IMM[3] FLT32 {   -1.0000,     2.0000,     0.0000,     0.0000}
>IMM[4] INT32 {4, 5, 6, 7}
>IMM[5] INT32 {8, 0, 0, 0}
>  0: MOV TEMP[0].x, IMM[0].xxxx
>  1: MOV TEMP[1].x, IMM[1].xxxx
>  2: MOV TEMP[2].x, IMM[2].xxxx
>  3: MOV TEMP[3].x, IMM[2].xxxx
>  4: MUL TEMP[4].xyz, CONST[23].xyzz, IN[0].xxxx
>  5: MAD TEMP[4].xyz, CONST[24].xyzz, IN[0].yyyy, TEMP[4].xyzz
>  6: ADD TEMP[4].xyz, TEMP[4].xyzz, CONST[25].xyzz
>  7: MOV TEMP[5].z, TEMP[4].zzzz
>  8: RCP TEMP[6].x, TEMP[4].zzzz
>  9: MUL TEMP[5].xy, TEMP[4].xyyy, TEMP[6].xxxx
> 10: ADD TEMP[4].x, CONST[17].xxxx, -CONST[19].xxxx
> 11: ADD TEMP[6].x, TEMP[5].yyyy, -CONST[20].yyyy
> 12: ADD TEMP[7].x, CONST[18].yyyy, -CONST[20].yyyy
> 13: ADD TEMP[8].x, TEMP[5].xxxx, -CONST[20].xxxx
> 14: ADD TEMP[9].x, CONST[18].xxxx, -CONST[20].xxxx
> 15: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx
> 16: MAD TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx, TEMP[8].xxxx
> 17: MAD TEMP[4].x, CONST[19].xxxx, TEMP[4].xxxx, TEMP[6].xxxx
> 18: ADD TEMP[6].x, TEMP[5].yyyy, -CONST[20].yyyy
> 19: ADD TEMP[7].x, TEMP[5].yyyy, -CONST[20].yyyy
> 20: ADD TEMP[8].x, TEMP[5].xxxx, -CONST[20].xxxx
> 21: ADD TEMP[5].x, TEMP[5].xxxx, -CONST[20].xxxx
> 22: MUL TEMP[5].x, TEMP[8].xxxx, TEMP[5].xxxx
> 23: MAD TEMP[5].x, TEMP[6].xxxx, TEMP[7].xxxx, TEMP[5].xxxx
> 24: MUL TEMP[6].x, CONST[19].xxxx, CONST[19].xxxx
> 25: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[6].xxxx
> 26: ABS TEMP[6].x, CONST[21].xxxx
> 27: SLT TEMP[6].x, TEMP[6].xxxx, IMM[1].yyyy
> 28: F2I TEMP[6].x, -TEMP[6]
> 29: UIF TEMP[6].xxxx :0
> 30:   SEQ TEMP[6].x, TEMP[4].xxxx, IMM[1].xxxx
> 31:   F2I TEMP[6].x, -TEMP[6]
> 32:   UIF TEMP[6].xxxx :0
> 33:     MOV TEMP[3].x, IMM[2].yyyy
> 34:     MOV TEMP[6].x, IMM[1].xxxx
> 35:     MOV TEMP[0].x, IMM[0].yyyy
> 36:   ELSE :0
> 37:     MUL TEMP[7].x, IMM[1].zzzz, TEMP[5].xxxx
> 38:     RCP TEMP[8].x, TEMP[4].xxxx
> 39:     MUL TEMP[1].x, TEMP[7].xxxx, TEMP[8].xxxx
> 40:   ENDIF
> 41: ELSE :0
> 42:   MUL TEMP[5].x, CONST[21].xxxx, TEMP[5].xxxx
> 43:   MAD TEMP[5].x, TEMP[4].xxxx, TEMP[4].xxxx, -TEMP[5].xxxx
> 44:   MOV TEMP[7].x, TEMP[5].xxxx
> 45:   SLT TEMP[8].x, TEMP[5].xxxx, IMM[1].xxxx
> 46:   F2I TEMP[8].x, -TEMP[8]
> 47:   UIF TEMP[8].xxxx :0
> 48:     MOV TEMP[3].x, IMM[2].yyyy
> 49:     MOV TEMP[6].x, TEMP[1].xxxx
> 50:     MOV TEMP[0].x, IMM[0].yyyy
> 51:   ELSE :0
> 52:     RSQ TEMP[8].x, TEMP[5].xxxx
> 53:     MUL TEMP[8].x, TEMP[8].xxxx, TEMP[5].xxxx
> 54:     CMP TEMP[5].x, -TEMP[5].xxxx, TEMP[8].xxxx, IMM[1].xxxx
> 55:     MOV TEMP[7].x, TEMP[5].xxxx
> 56:     ADD TEMP[5].x, TEMP[4].xxxx, TEMP[5].xxxx
> 57:     RCP TEMP[8].x, CONST[21].xxxx
> 58:     MUL TEMP[1].x, TEMP[5].xxxx, TEMP[8].xxxx
> 59:   ENDIF
> 60: ENDIF
> 61: UIF TEMP[0].xxxx :0
> 62:   USEQ TEMP[5].x, CONST[22].xxxx, IMM[2].xxxx
> 63:   UIF TEMP[5].xxxx :0
> 64:     SGE TEMP[5].x, IMM[1].xxxx, TEMP[1].xxxx
> 65:     F2I TEMP[5].x, -TEMP[5]
> 66:     SLT TEMP[8].x, IMM[1].wwww, TEMP[1].xxxx
> 67:     F2I TEMP[8].x, -TEMP[8]
> 68:     OR TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx
> 69:     UIF TEMP[5].xxxx :0
> 70:       ADD TEMP[5].x, TEMP[4].xxxx, -TEMP[7].xxxx
> 71:       RCP TEMP[8].x, CONST[21].xxxx
> 72:       MUL TEMP[1].x, TEMP[5].xxxx, TEMP[8].xxxx
> 73:     ENDIF
> 74:     SGE TEMP[5].x, IMM[1].xxxx, TEMP[1].xxxx
> 75:     F2I TEMP[5].x, -TEMP[5]
> 76:     SLT TEMP[8].x, IMM[1].wwww, TEMP[1].xxxx
> 77:     F2I TEMP[8].x, -TEMP[8]
> 78:     OR TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx
> 79:     UIF TEMP[5].xxxx :0
> 80:       MOV TEMP[3].x, IMM[2].yyyy
> 81:       MOV TEMP[6].x, TEMP[1].xxxx
> 82:       MOV TEMP[0].x, IMM[0].yyyy
> 83:     ENDIF
> 84:   ELSE :0
> 85:     ADD TEMP[5].x, CONST[17].xxxx, -CONST[19].xxxx
> 86:     MUL TEMP[5].x, TEMP[1].xxxx, TEMP[5].xxxx
> 87:     MUL TEMP[8].x, IMM[3].xxxx, CONST[19].xxxx
> 88:     SGE TEMP[5].x, TEMP[8].xxxx, TEMP[5].xxxx
> 89:     F2I TEMP[5].x, -TEMP[5]
> 90:     UIF TEMP[5].xxxx :0
> 91:       ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx
> 92:       RCP TEMP[5].x, CONST[21].xxxx
> 93:       MUL TEMP[1].x, TEMP[4].xxxx, TEMP[5].xxxx
> 94:     ENDIF
> 95:     ADD TEMP[4].x, CONST[17].xxxx, -CONST[19].xxxx
> 96:     MUL TEMP[4].x, TEMP[1].xxxx, TEMP[4].xxxx
> 97:     MUL TEMP[5].x, IMM[3].xxxx, CONST[19].xxxx
> 98:     SGE TEMP[4].x, TEMP[5].xxxx, TEMP[4].xxxx
> 99:     F2I TEMP[4].x, -TEMP[4]
>100:     UIF TEMP[4].xxxx :0
>101:       MOV TEMP[3].x, IMM[2].yyyy
>102:       MOV TEMP[6].x, TEMP[1].xxxx
>103:       MOV TEMP[0].x, IMM[0].yyyy
>104:     ENDIF
>105:   ENDIF
>106:   UIF TEMP[0].xxxx :0
>107:     USEQ TEMP[0].x, CONST[22].xxxx, IMM[2].yyyy
>108:     UIF TEMP[0].xxxx :0
>109:       BGNLOOP :0
>110:         SGE TEMP[0].x, IMM[1].wwww, TEMP[1].xxxx
>111:         F2I TEMP[0].x, -TEMP[0]
>112:         UIF TEMP[0].xxxx :0
>113:           BRK
>114:         ENDIF
>115:         ADD TEMP[1].x, TEMP[1].xxxx, IMM[3].xxxx
>116:       ENDLOOP :0
>117:       BGNLOOP :0
>118:         SGE TEMP[0].x, TEMP[1].xxxx, IMM[1].xxxx
>119:         F2I TEMP[0].x, -TEMP[0]
>120:         UIF TEMP[0].xxxx :0
>121:           BRK
>122:         ENDIF
>123:         ADD TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>124:       ENDLOOP :0
>125:     ENDIF
>126:     USEQ TEMP[0].x, CONST[22].xxxx, IMM[2].zzzz
>127:     UIF TEMP[0].xxxx :0
>128:       BGNLOOP :0
>129:         SGE TEMP[0].x, IMM[1].wwww, TEMP[1].xxxx
>130:         F2I TEMP[0].x, -TEMP[0]
>131:         UIF TEMP[0].xxxx :0
>132:           BRK
>133:         ENDIF
>134:         ADD TEMP[1].x, TEMP[1].xxxx, IMM[3].xxxx
>135:         USEQ TEMP[4].x, TEMP[2].xxxx, IMM[2].xxxx
>136:         UIF TEMP[4].xxxx :0
>137:           MOV TEMP[2].x, IMM[2].yyyy
>138:         ELSE :0
>139:           MOV TEMP[2].x, IMM[2].xxxx
>140:         ENDIF
>141:       ENDLOOP :0
>142:       BGNLOOP :0
>143:         SGE TEMP[0].x, TEMP[1].xxxx, IMM[1].xxxx
>144:         F2I TEMP[0].x, -TEMP[0]
>145:         UIF TEMP[0].xxxx :0
>146:           BRK
>147:         ENDIF
>148:         ADD TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>149:         USEQ TEMP[4].x, TEMP[2].xxxx, IMM[2].xxxx
>150:         UIF TEMP[4].xxxx :0
>151:           MOV TEMP[2].x, IMM[2].yyyy
>152:         ELSE :0
>153:           MOV TEMP[2].x, IMM[2].xxxx
>154:         ENDIF
>155:       ENDLOOP :0
>156:       USEQ TEMP[0].x, TEMP[2].xxxx, IMM[2].yyyy
>157:       UIF TEMP[0].xxxx :0
>158:         ADD TEMP[1].x, IMM[1].wwww, -TEMP[1].xxxx
>159:       ENDIF
>160:     ENDIF
>161:     MOV TEMP[6].x, TEMP[1].xxxx
>162:   ENDIF
>163: ENDIF
>164: USEQ TEMP[0].x, TEMP[3].xxxx, IMM[2].yyyy
>165: UIF TEMP[0].xxxx :0
>166:   MOV TEMP[0], IMM[1].xxxx
>167: ELSE :0
>168:   SLT TEMP[1].x, TEMP[6].xxxx, CONST[16].xxxx
>169:   F2I TEMP[1].x, -TEMP[1]
>170:   ISGE TEMP[2].x, CONST[15].xxxx, IMM[2].yyyy
>171:   AND TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
>172:   UIF TEMP[1].xxxx :0
>173:     MOV TEMP[1], CONST[14]
>174:     MOV TEMP[2], CONST[14]
>175:     MOV TEMP[3].x, CONST[16].xxxx
>176:     MOV TEMP[4].x, CONST[16].xxxx
>177:   ELSE :0
>178:     SLT TEMP[5].x, TEMP[6].xxxx, CONST[13].xxxx
>179:     F2I TEMP[5].x, -TEMP[5]
>180:     ISGE TEMP[7].x, CONST[15].xxxx, IMM[2].wwww
>181:     AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>182:     UIF TEMP[5].xxxx :0
>183:       MOV TEMP[1], CONST[14]
>184:       MOV TEMP[2], CONST[12]
>185:       MOV TEMP[3].x, CONST[13].xxxx
>186:       MOV TEMP[4].x, CONST[16].xxxx
>187:     ELSE :0
>188:       SLT TEMP[5].x, TEMP[6].xxxx, CONST[11].xxxx
>189:       F2I TEMP[5].x, -TEMP[5]
>190:       ISGE TEMP[7].x, CONST[15].xxxx, IMM[2].zzzz
>191:       AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>192:       UIF TEMP[5].xxxx :0
>193:         MOV TEMP[1], CONST[12]
>194:         MOV TEMP[2], CONST[10]
>195:         MOV TEMP[3].x, CONST[11].xxxx
>196:         MOV TEMP[4].x, CONST[13].xxxx
>197:       ELSE :0
>198:         SLT TEMP[5].x, TEMP[6].xxxx, CONST[9].xxxx
>199:         F2I TEMP[5].x, -TEMP[5]
>200:         ISGE TEMP[7].x, CONST[15].xxxx, IMM[4].xxxx
>201:         AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>202:         UIF TEMP[5].xxxx :0
>203:           MOV TEMP[1], CONST[10]
>204:           MOV TEMP[2], CONST[8]
>205:           MOV TEMP[3].x, CONST[9].xxxx
>206:           MOV TEMP[4].x, CONST[11].xxxx
>207:         ELSE :0
>208:           SLT TEMP[5].x, TEMP[6].xxxx, CONST[7].xxxx
>209:           F2I TEMP[5].x, -TEMP[5]
>210:           ISGE TEMP[7].x, CONST[15].xxxx, IMM[4].yyyy
>211:           AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>212:           UIF TEMP[5].xxxx :0
>213:             MOV TEMP[1], CONST[8]
>214:             MOV TEMP[2], CONST[6]
>215:             MOV TEMP[3].x, CONST[7].xxxx
>216:             MOV TEMP[4].x, CONST[9].xxxx
>217:           ELSE :0
>218:             SLT TEMP[5].x, TEMP[6].xxxx, CONST[5].xxxx
>219:             F2I TEMP[5].x, -TEMP[5]
>220:             ISGE TEMP[7].x, CONST[15].xxxx, IMM[4].zzzz
>221:             AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>222:             UIF TEMP[5].xxxx :0
>223:               MOV TEMP[1], CONST[6]
>224:               MOV TEMP[2], CONST[4]
>225:               MOV TEMP[3].x, CONST[5].xxxx
>226:               MOV TEMP[4].x, CONST[7].xxxx
>227:             ELSE :0
>228:               SLT TEMP[5].x, TEMP[6].xxxx, CONST[3].xxxx
>229:               F2I TEMP[5].x, -TEMP[5]
>230:               ISGE TEMP[7].x, CONST[15].xxxx, IMM[4].wwww
>231:               AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>232:               UIF TEMP[5].xxxx :0
>233:                 MOV TEMP[1], CONST[4]
>234:                 MOV TEMP[2], CONST[2]
>235:                 MOV TEMP[3].x, CONST[3].xxxx
>236:                 MOV TEMP[4].x, CONST[5].xxxx
>237:               ELSE :0
>238:                 SLT TEMP[5].x, TEMP[6].xxxx, CONST[1].xxxx
>239:                 F2I TEMP[5].x, -TEMP[5]
>240:                 ISGE TEMP[7].x, CONST[15].xxxx, IMM[5].xxxx
>241:                 AND TEMP[5].x, TEMP[5].xxxx, TEMP[7].xxxx
>242:                 UIF TEMP[5].xxxx :0
>243:                   MOV TEMP[1], CONST[2]
>244:                   MOV TEMP[2], CONST[0]
>245:                   MOV TEMP[3].x, CONST[1].xxxx
>246:                   MOV TEMP[4].x, CONST[3].xxxx
>247:                 ELSE :0
>248:                   MOV TEMP[1], CONST[0]
>249:                   MOV TEMP[2], CONST[0]
>250:                   MOV TEMP[3].x, CONST[1].xxxx
>251:                   MOV TEMP[4].x, CONST[1].xxxx
>252:                 ENDIF
>253:               ENDIF
>254:             ENDIF
>255:           ENDIF
>256:         ENDIF
>257:       ENDIF
>258:     ENDIF
>259:   ENDIF
>260:   ADD TEMP[5].x, TEMP[3].xxxx, -TEMP[4].xxxx
>261:   SLT TEMP[5].x, IMM[3].yyyy, TEMP[5].xxxx
>262:   F2I TEMP[5].x, -TEMP[5]
>263:   UIF TEMP[5].xxxx :0
>264:     MOV TEMP[5].x, IMM[1].xxxx
>265:   ELSE :0
>266:     ADD TEMP[7].x, TEMP[3].xxxx, -TEMP[4].xxxx
>267:     SLT TEMP[7].x, TEMP[7].xxxx, IMM[3].zzzz
>268:     F2I TEMP[7].x, -TEMP[7]
>269:     UIF TEMP[7].xxxx :0
>270:       MOV TEMP[5].x, IMM[1].xxxx
>271:     ELSE :0
>272:       ADD TEMP[6].x, TEMP[6].xxxx, -TEMP[4].xxxx
>273:       ADD TEMP[3].x, TEMP[3].xxxx, -TEMP[4].xxxx
>274:       RCP TEMP[3].x, TEMP[3].xxxx
>275:       MUL TEMP[5].x, TEMP[6].xxxx, TEMP[3].xxxx
>276:     ENDIF
>277:   ENDIF
>278:   ADD TEMP[3].x, IMM[1].wwww, -TEMP[5].xxxx
>279:   MUL TEMP[4].x, TEMP[5].xxxx, TEMP[2].wwww
>280:   MAD TEMP[3].x, TEMP[3].xxxx, TEMP[1].wwww, TEMP[4].xxxx
>281:   ADD TEMP[4].x, IMM[1].wwww, -TEMP[5].xxxx
>282:   MUL TEMP[2].xyz, TEMP[5].xxxx, TEMP[2].xyzz
>283:   MAD TEMP[1].xyz, TEMP[4].xxxx, TEMP[1].xyzz, TEMP[2].xyzz
>284:   MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
>285:   MOV TEMP[1].w, TEMP[3].xxxx
>286:   MOV TEMP[0], TEMP[1]
>287: ENDIF
>288: MOV OUT[0], TEMP[0]
>289: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 108)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 140)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 204)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 236)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 240)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 304)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 368)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 372)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 376)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 384)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 388)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 392)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 400)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 404)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 408)
>  %80 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %81 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %82 = fmul float %71, %80
>  %83 = fmul float %72, %80
>  %84 = fmul float %73, %80
>  %85 = fmul float %74, %81
>  %86 = fadd float %85, %82
>  %87 = fmul float %75, %81
>  %88 = fadd float %87, %83
>  %89 = fmul float %76, %81
>  %90 = fadd float %89, %84
>  %91 = fadd float %86, %77
>  %92 = fadd float %88, %78
>  %93 = fadd float %90, %79
>  %94 = fdiv float 1.000000e+00, %93
>  %95 = fmul float %91, %94
>  %96 = fmul float %92, %94
>  %97 = fsub float -0.000000e+00, %66
>  %98 = fadd float %63, %97
>  %99 = fsub float -0.000000e+00, %68
>  %100 = fadd float %96, %99
>  %101 = fsub float -0.000000e+00, %68
>  %102 = fadd float %65, %101
>  %103 = fsub float -0.000000e+00, %67
>  %104 = fadd float %95, %103
>  %105 = fsub float -0.000000e+00, %67
>  %106 = fadd float %64, %105
>  %107 = fmul float %104, %106
>  %108 = fmul float %100, %102
>  %109 = fadd float %108, %107
>  %110 = fmul float %66, %98
>  %111 = fadd float %110, %109
>  %112 = fsub float -0.000000e+00, %68
>  %113 = fadd float %96, %112
>  %114 = fsub float -0.000000e+00, %68
>  %115 = fadd float %96, %114
>  %116 = fsub float -0.000000e+00, %67
>  %117 = fadd float %95, %116
>  %118 = fsub float -0.000000e+00, %67
>  %119 = fadd float %95, %118
>  %120 = fmul float %117, %119
>  %121 = fmul float %113, %115
>  %122 = fadd float %121, %120
>  %123 = fmul float %66, %66
>  %124 = fsub float -0.000000e+00, %123
>  %125 = fadd float %122, %124
>  %126 = call float @fabs(float %69)
>  %127 = fcmp ult float %126, 0x3EE4F8B580000000
>  %128 = select i1 %127, float 1.000000e+00, float 0.000000e+00
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fptosi float %129 to i32
>  %131 = bitcast i32 %130 to float
>  %132 = bitcast float %131 to i32
>  %133 = icmp ne i32 %132, 0
>  br i1 %133, label %IF, label %ELSE
>
>IF:                                               ; preds = %main_body
>  %134 = fcmp ueq float %111, 0.000000e+00
>  %135 = select i1 %134, float 1.000000e+00, float 0.000000e+00
>  %136 = fsub float -0.000000e+00, %135
>  %137 = fptosi float %136 to i32
>  %138 = bitcast i32 %137 to float
>  %139 = bitcast float %138 to i32
>  %140 = icmp ne i32 %139, 0
>  br i1 %140, label %ENDIF, label %ELSE42
>
>ELSE:                                             ; preds = %main_body
>  %141 = fmul float %69, %125
>  %142 = fsub float -0.000000e+00, %141
>  %143 = fmul float %111, %111
>  %144 = fadd float %143, %142
>  %145 = fcmp ult float %144, 0.000000e+00
>  %146 = select i1 %145, float 1.000000e+00, float 0.000000e+00
>  %147 = fsub float -0.000000e+00, %146
>  %148 = fptosi float %147 to i32
>  %149 = bitcast i32 %148 to float
>  %150 = bitcast float %149 to i32
>  %151 = icmp ne i32 %150, 0
>  br i1 %151, label %ENDIF, label %ELSE45
>
>ENDIF:                                            ; preds = %ELSE45, %ELSE, %ELSE42, %IF
>  %temp12.0 = phi float [ 0.000000e+00, %ELSE42 ], [ 0x36A0000000000000, %IF ], [ 0.000000e+00, %ELSE45 ], [ 0x36A0000000000000, %ELSE ]
>  %temp24.0 = phi float [ %138, %ELSE42 ], [ 0.000000e+00, %IF ], [ %131, %ELSE45 ], [ 0.000000e+00, %ELSE ]
>  %temp28.0 = phi float [ %154, %ELSE42 ], [ %115, %IF ], [ %161, %ELSE45 ], [ %144, %ELSE ]
>  %temp4.0 = phi float [ %156, %ELSE42 ], [ 0.000000e+00, %IF ], [ %164, %ELSE45 ], [ 0.000000e+00, %ELSE ]
>  %temp.0 = phi float [ 0xFFFFFFFFE0000000, %ELSE42 ], [ 0.000000e+00, %IF ], [ 0xFFFFFFFFE0000000, %ELSE45 ], [ 0.000000e+00, %ELSE ]
>  %152 = bitcast float %temp.0 to i32
>  %153 = icmp ne i32 %152, 0
>  br i1 %153, label %IF47, label %ENDIF46
>
>ELSE42:                                           ; preds = %IF
>  %154 = fmul float 5.000000e-01, %125
>  %155 = fdiv float 1.000000e+00, %111
>  %156 = fmul float %154, %155
>  br label %ENDIF
>
>ELSE45:                                           ; preds = %ELSE
>  %157 = call float @fabs(float %144)
>  %158 = call float @llvm.AMDGPU.rsq(float %157)
>  %159 = fmul float %158, %144
>  %160 = fsub float -0.000000e+00, %144
>  %161 = call float @llvm.AMDGPU.cndlt(float %160, float %159, float 0.000000e+00)
>  %162 = fadd float %111, %161
>  %163 = fdiv float 1.000000e+00, %69
>  %164 = fmul float %162, %163
>  br label %ENDIF
>
>IF47:                                             ; preds = %ENDIF
>  %165 = bitcast float %70 to i32
>  %166 = icmp eq i32 %165, 0
>  %167 = sext i1 %166 to i32
>  %168 = bitcast i32 %167 to float
>  %169 = bitcast float %168 to i32
>  %170 = icmp ne i32 %169, 0
>  br i1 %170, label %IF50, label %ELSE51
>
>ENDIF46:                                          ; preds = %IF98, %IF92, %ENDIF67, %ENDIF49, %ENDIF
>  %temp12.3 = phi float [ %temp12.0, %ENDIF ], [ %temp12.4, %ENDIF49 ], [ %temp12.4, %ENDIF67 ], [ %temp12.4, %IF92 ], [ %temp12.4, %IF98 ]
>  %temp24.3 = phi float [ %temp24.0, %ENDIF ], [ %temp24.4, %ENDIF49 ], [ %temp4.6, %ENDIF67 ], [ %304, %IF98 ], [ %temp4.11, %IF92 ]
>  %171 = bitcast float %temp12.3 to i32
>  %172 = icmp eq i32 %171, 1
>  %173 = sext i1 %172 to i32
>  %174 = bitcast i32 %173 to float
>  %175 = bitcast float %174 to i32
>  %176 = icmp ne i32 %175, 0
>  br i1 %176, label %ENDIF100, label %ELSE102
>
>IF50:                                             ; preds = %IF47
>  %177 = fcmp uge float 0.000000e+00, %temp4.0
>  %178 = select i1 %177, float 1.000000e+00, float 0.000000e+00
>  %179 = fsub float -0.000000e+00, %178
>  %180 = fptosi float %179 to i32
>  %181 = bitcast i32 %180 to float
>  %182 = fcmp ult float 1.000000e+00, %temp4.0
>  %183 = select i1 %182, float 1.000000e+00, float 0.000000e+00
>  %184 = fsub float -0.000000e+00, %183
>  %185 = fptosi float %184 to i32
>  %186 = bitcast i32 %185 to float
>  %187 = bitcast float %181 to i32
>  %188 = bitcast float %186 to i32
>  %189 = or i32 %187, %188
>  %190 = bitcast i32 %189 to float
>  %191 = bitcast float %190 to i32
>  %192 = icmp ne i32 %191, 0
>  br i1 %192, label %IF53, label %ENDIF52
>
>ELSE51:                                           ; preds = %IF47
>  %193 = fsub float -0.000000e+00, %66
>  %194 = fadd float %63, %193
>  %195 = fmul float %temp4.0, %194
>  %196 = fmul float -1.000000e+00, %66
>  %197 = fcmp uge float %196, %195
>  %198 = select i1 %197, float 1.000000e+00, float 0.000000e+00
>  %199 = fsub float -0.000000e+00, %198
>  %200 = fptosi float %199 to i32
>  %201 = bitcast i32 %200 to float
>  %202 = bitcast float %201 to i32
>  %203 = icmp ne i32 %202, 0
>  br i1 %203, label %IF59, label %ENDIF58
>
>ENDIF49:                                          ; preds = %ENDIF58, %ENDIF52
>  %.sink = phi i1 [ %225, %ENDIF52 ], [ %240, %ENDIF58 ]
>  %temp12.4 = phi float [ %.temp12.0, %ENDIF52 ], [ %.temp12.0133, %ENDIF58 ]
>  %temp24.4 = phi float [ %temp4.4.temp24.0, %ENDIF52 ], [ %temp4.5.temp24.0, %ENDIF58 ]
>  %temp4.3 = phi float [ %temp4.4, %ENDIF52 ], [ %temp4.5, %ENDIF58 ]
>  %.temp.0 = select i1 %.sink, float 0.000000e+00, float %temp.0
>  %204 = bitcast float %.temp.0 to i32
>  %205 = icmp ne i32 %204, 0
>  br i1 %205, label %IF65, label %ENDIF46
>
>IF53:                                             ; preds = %IF50
>  %206 = fsub float -0.000000e+00, %temp28.0
>  %207 = fadd float %111, %206
>  %208 = fdiv float 1.000000e+00, %69
>  %209 = fmul float %207, %208
>  br label %ENDIF52
>
>ENDIF52:                                          ; preds = %IF50, %IF53
>  %temp4.4 = phi float [ %209, %IF53 ], [ %temp4.0, %IF50 ]
>  %210 = fcmp uge float 0.000000e+00, %temp4.4
>  %211 = select i1 %210, float 1.000000e+00, float 0.000000e+00
>  %212 = fsub float -0.000000e+00, %211
>  %213 = fptosi float %212 to i32
>  %214 = bitcast i32 %213 to float
>  %215 = fcmp ult float 1.000000e+00, %temp4.4
>  %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00
>  %217 = fsub float -0.000000e+00, %216
>  %218 = fptosi float %217 to i32
>  %219 = bitcast i32 %218 to float
>  %220 = bitcast float %214 to i32
>  %221 = bitcast float %219 to i32
>  %222 = or i32 %220, %221
>  %223 = bitcast i32 %222 to float
>  %224 = bitcast float %223 to i32
>  %225 = icmp ne i32 %224, 0
>  %.temp12.0 = select i1 %225, float 0x36A0000000000000, float %temp12.0
>  %temp4.4.temp24.0 = select i1 %225, float %temp4.4, float %temp24.0
>  br label %ENDIF49
>
>IF59:                                             ; preds = %ELSE51
>  %226 = fsub float -0.000000e+00, %temp28.0
>  %227 = fadd float %111, %226
>  %228 = fdiv float 1.000000e+00, %69
>  %229 = fmul float %227, %228
>  br label %ENDIF58
>
>ENDIF58:                                          ; preds = %ELSE51, %IF59
>  %temp4.5 = phi float [ %229, %IF59 ], [ %temp4.0, %ELSE51 ]
>  %230 = fsub float -0.000000e+00, %66
>  %231 = fadd float %63, %230
>  %232 = fmul float %temp4.5, %231
>  %233 = fmul float -1.000000e+00, %66
>  %234 = fcmp uge float %233, %232
>  %235 = select i1 %234, float 1.000000e+00, float 0.000000e+00
>  %236 = fsub float -0.000000e+00, %235
>  %237 = fptosi float %236 to i32
>  %238 = bitcast i32 %237 to float
>  %239 = bitcast float %238 to i32
>  %240 = icmp ne i32 %239, 0
>  %.temp12.0133 = select i1 %240, float 0x36A0000000000000, float %temp12.0
>  %temp4.5.temp24.0 = select i1 %240, float %temp4.5, float %temp24.0
>  br label %ENDIF49
>
>IF65:                                             ; preds = %ENDIF49
>  %241 = bitcast float %70 to i32
>  %242 = icmp eq i32 %241, 1
>  %243 = sext i1 %242 to i32
>  %244 = bitcast i32 %243 to float
>  %245 = bitcast float %244 to i32
>  %246 = icmp ne i32 %245, 0
>  br i1 %246, label %LOOP, label %ENDIF67
>
>ENDIF67:                                          ; preds = %LOOP74, %IF65
>  %temp4.6 = phi float [ %temp4.3, %IF65 ], [ %temp4.8, %LOOP74 ]
>  %247 = bitcast float %70 to i32
>  %248 = icmp eq i32 %247, 3
>  %249 = sext i1 %248 to i32
>  %250 = bitcast i32 %249 to float
>  %251 = bitcast float %250 to i32
>  %252 = icmp ne i32 %251, 0
>  br i1 %252, label %LOOP82, label %ENDIF46
>
>LOOP:                                             ; preds = %IF65, %ENDIF70
>  %temp4.7 = phi float [ %260, %ENDIF70 ], [ %temp4.3, %IF65 ]
>  %253 = fcmp uge float 1.000000e+00, %temp4.7
>  %254 = select i1 %253, float 1.000000e+00, float 0.000000e+00
>  %255 = fsub float -0.000000e+00, %254
>  %256 = fptosi float %255 to i32
>  %257 = bitcast i32 %256 to float
>  %258 = bitcast float %257 to i32
>  %259 = icmp ne i32 %258, 0
>  br i1 %259, label %LOOP74, label %ENDIF70
>
>ENDIF70:                                          ; preds = %LOOP
>  %260 = fadd float %temp4.7, -1.000000e+00
>  br label %LOOP
>
>LOOP74:                                           ; preds = %LOOP, %ENDIF75
>  %temp4.8 = phi float [ %268, %ENDIF75 ], [ %temp4.7, %LOOP ]
>  %261 = fcmp uge float %temp4.8, 0.000000e+00
>  %262 = select i1 %261, float 1.000000e+00, float 0.000000e+00
>  %263 = fsub float -0.000000e+00, %262
>  %264 = fptosi float %263 to i32
>  %265 = bitcast i32 %264 to float
>  %266 = bitcast float %265 to i32
>  %267 = icmp ne i32 %266, 0
>  br i1 %267, label %ENDIF67, label %ENDIF75
>
>ENDIF75:                                          ; preds = %LOOP74
>  %268 = fadd float %temp4.8, 1.000000e+00
>  br label %LOOP74
>
>LOOP82:                                           ; preds = %ENDIF67, %ENDIF83
>  %temp8.0 = phi float [ %., %ENDIF83 ], [ 0.000000e+00, %ENDIF67 ]
>  %temp4.10 = phi float [ %276, %ENDIF83 ], [ %temp4.6, %ENDIF67 ]
>  %269 = fcmp uge float 1.000000e+00, %temp4.10
>  %270 = select i1 %269, float 1.000000e+00, float 0.000000e+00
>  %271 = fsub float -0.000000e+00, %270
>  %272 = fptosi float %271 to i32
>  %273 = bitcast i32 %272 to float
>  %274 = bitcast float %273 to i32
>  %275 = icmp ne i32 %274, 0
>  br i1 %275, label %LOOP90, label %ENDIF83
>
>ENDIF83:                                          ; preds = %LOOP82
>  %276 = fadd float %temp4.10, -1.000000e+00
>  %277 = bitcast float %temp8.0 to i32
>  %278 = icmp eq i32 %277, 0
>  %279 = sext i1 %278 to i32
>  %280 = bitcast i32 %279 to float
>  %281 = bitcast float %280 to i32
>  %282 = icmp ne i32 %281, 0
>  %. = select i1 %282, float 0x36A0000000000000, float 0.000000e+00
>  br label %LOOP82
>
>LOOP90:                                           ; preds = %LOOP82, %ENDIF91
>  %temp8.2 = phi float [ %.135, %ENDIF91 ], [ %temp8.0, %LOOP82 ]
>  %temp4.11 = phi float [ %296, %ENDIF91 ], [ %temp4.10, %LOOP82 ]
>  %283 = fcmp uge float %temp4.11, 0.000000e+00
>  %284 = select i1 %283, float 1.000000e+00, float 0.000000e+00
>  %285 = fsub float -0.000000e+00, %284
>  %286 = fptosi float %285 to i32
>  %287 = bitcast i32 %286 to float
>  %288 = bitcast float %287 to i32
>  %289 = icmp ne i32 %288, 0
>  br i1 %289, label %IF92, label %ENDIF91
>
>IF92:                                             ; preds = %LOOP90
>  %290 = bitcast float %temp8.2 to i32
>  %291 = icmp eq i32 %290, 1
>  %292 = sext i1 %291 to i32
>  %293 = bitcast i32 %292 to float
>  %294 = bitcast float %293 to i32
>  %295 = icmp ne i32 %294, 0
>  br i1 %295, label %IF98, label %ENDIF46
>
>ENDIF91:                                          ; preds = %LOOP90
>  %296 = fadd float %temp4.11, 1.000000e+00
>  %297 = bitcast float %temp8.2 to i32
>  %298 = icmp eq i32 %297, 0
>  %299 = sext i1 %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = bitcast float %300 to i32
>  %302 = icmp ne i32 %301, 0
>  %.135 = select i1 %302, float 0x36A0000000000000, float 0.000000e+00
>  br label %LOOP90
>
>IF98:                                             ; preds = %IF92
>  %303 = fsub float -0.000000e+00, %temp4.11
>  %304 = fadd float 1.000000e+00, %303
>  br label %ENDIF46
>
>ELSE102:                                          ; preds = %ENDIF46
>  %305 = fcmp ult float %temp24.3, %62
>  %306 = select i1 %305, float 1.000000e+00, float 0.000000e+00
>  %307 = fsub float -0.000000e+00, %306
>  %308 = fptosi float %307 to i32
>  %309 = bitcast i32 %308 to float
>  %310 = bitcast float %61 to i32
>  %311 = icmp sge i32 %310, 1
>  %312 = sext i1 %311 to i32
>  %313 = bitcast i32 %312 to float
>  %314 = bitcast float %309 to i32
>  %315 = bitcast float %313 to i32
>  %316 = and i32 %314, %315
>  %317 = bitcast i32 %316 to float
>  %318 = bitcast float %317 to i32
>  %319 = icmp ne i32 %318, 0
>  br i1 %319, label %ENDIF103, label %ELSE105
>
>ENDIF100:                                         ; preds = %ENDIF46, %ENDIF127
>  %temp3.0 = phi float [ %451, %ENDIF127 ], [ 0.000000e+00, %ENDIF46 ]
>  %temp2.0 = phi float [ %465, %ENDIF127 ], [ 0.000000e+00, %ENDIF46 ]
>  %temp1.0 = phi float [ %464, %ENDIF127 ], [ 0.000000e+00, %ENDIF46 ]
>  %temp.6 = phi float [ %463, %ENDIF127 ], [ 0.000000e+00, %ENDIF46 ]
>  %320 = call i32 @llvm.SI.packf16(float %temp.6, float %temp1.0)
>  %321 = bitcast i32 %320 to float
>  %322 = call i32 @llvm.SI.packf16(float %temp2.0, float %temp3.0)
>  %323 = bitcast i32 %322 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %321, float %323, float %321, float %323)
>  ret void
>
>ELSE105:                                          ; preds = %ELSE102
>  %324 = fcmp ult float %temp24.3, %56
>  %325 = select i1 %324, float 1.000000e+00, float 0.000000e+00
>  %326 = fsub float -0.000000e+00, %325
>  %327 = fptosi float %326 to i32
>  %328 = bitcast i32 %327 to float
>  %329 = bitcast float %61 to i32
>  %330 = icmp sge i32 %329, 2
>  %331 = sext i1 %330 to i32
>  %332 = bitcast i32 %331 to float
>  %333 = bitcast float %328 to i32
>  %334 = bitcast float %332 to i32
>  %335 = and i32 %333, %334
>  %336 = bitcast i32 %335 to float
>  %337 = bitcast float %336 to i32
>  %338 = icmp ne i32 %337, 0
>  br i1 %338, label %ENDIF103, label %ELSE108
>
>ENDIF103:                                         ; preds = %ELSE123, %ELSE120, %ELSE117, %ELSE114, %ELSE111, %ELSE108, %ELSE105, %ELSE102
>  %temp16.0 = phi float [ %62, %ELSE102 ], [ %62, %ELSE105 ], [ %56, %ELSE108 ], [ %51, %ELSE111 ], [ %46, %ELSE114 ], [ %41, %ELSE117 ], [ %.136, %ELSE123 ], [ %36, %ELSE120 ]
>  %temp12.7 = phi float [ %62, %ELSE102 ], [ %56, %ELSE105 ], [ %51, %ELSE108 ], [ %46, %ELSE111 ], [ %41, %ELSE114 ], [ %36, %ELSE117 ], [ %26, %ELSE123 ], [ %31, %ELSE120 ]
>  %temp11.0 = phi float [ %60, %ELSE102 ], [ %55, %ELSE105 ], [ %50, %ELSE108 ], [ %45, %ELSE111 ], [ %40, %ELSE114 ], [ %35, %ELSE117 ], [ %25, %ELSE123 ], [ %30, %ELSE120 ]
>  %temp10.0 = phi float [ %59, %ELSE102 ], [ %54, %ELSE105 ], [ %49, %ELSE108 ], [ %44, %ELSE111 ], [ %39, %ELSE114 ], [ %34, %ELSE117 ], [ %24, %ELSE123 ], [ %29, %ELSE120 ]
>  %temp9.0 = phi float [ %58, %ELSE102 ], [ %53, %ELSE105 ], [ %48, %ELSE108 ], [ %43, %ELSE111 ], [ %38, %ELSE114 ], [ %33, %ELSE117 ], [ %23, %ELSE123 ], [ %28, %ELSE120 ]
>  %temp8.4 = phi float [ %57, %ELSE102 ], [ %52, %ELSE105 ], [ %47, %ELSE108 ], [ %42, %ELSE111 ], [ %37, %ELSE114 ], [ %32, %ELSE117 ], [ %22, %ELSE123 ], [ %27, %ELSE120 ]
>  %temp7.0 = phi float [ %60, %ELSE102 ], [ %60, %ELSE105 ], [ %55, %ELSE108 ], [ %50, %ELSE111 ], [ %45, %ELSE114 ], [ %40, %ELSE117 ], [ %.137, %ELSE123 ], [ %35, %ELSE120 ]
>  %temp6.0 = phi float [ %59, %ELSE102 ], [ %59, %ELSE105 ], [ %54, %ELSE108 ], [ %49, %ELSE111 ], [ %44, %ELSE114 ], [ %39, %ELSE117 ], [ %.138, %ELSE123 ], [ %34, %ELSE120 ]
>  %temp5.0 = phi float [ %58, %ELSE102 ], [ %58, %ELSE105 ], [ %53, %ELSE108 ], [ %48, %ELSE111 ], [ %43, %ELSE114 ], [ %38, %ELSE117 ], [ %.139, %ELSE123 ], [ %33, %ELSE120 ]
>  %temp4.13 = phi float [ %57, %ELSE102 ], [ %57, %ELSE105 ], [ %52, %ELSE108 ], [ %47, %ELSE111 ], [ %42, %ELSE114 ], [ %37, %ELSE117 ], [ %.140, %ELSE123 ], [ %32, %ELSE120 ]
>  %339 = fsub float -0.000000e+00, %temp16.0
>  %340 = fadd float %temp12.7, %339
>  %341 = fcmp ult float 2.000000e+00, %340
>  %342 = select i1 %341, float 1.000000e+00, float 0.000000e+00
>  %343 = fsub float -0.000000e+00, %342
>  %344 = fptosi float %343 to i32
>  %345 = bitcast i32 %344 to float
>  %346 = bitcast float %345 to i32
>  %347 = icmp ne i32 %346, 0
>  br i1 %347, label %ENDIF127, label %ELSE129
>
>ELSE108:                                          ; preds = %ELSE105
>  %348 = fcmp ult float %temp24.3, %51
>  %349 = select i1 %348, float 1.000000e+00, float 0.000000e+00
>  %350 = fsub float -0.000000e+00, %349
>  %351 = fptosi float %350 to i32
>  %352 = bitcast i32 %351 to float
>  %353 = bitcast float %61 to i32
>  %354 = icmp sge i32 %353, 3
>  %355 = sext i1 %354 to i32
>  %356 = bitcast i32 %355 to float
>  %357 = bitcast float %352 to i32
>  %358 = bitcast float %356 to i32
>  %359 = and i32 %357, %358
>  %360 = bitcast i32 %359 to float
>  %361 = bitcast float %360 to i32
>  %362 = icmp ne i32 %361, 0
>  br i1 %362, label %ENDIF103, label %ELSE111
>
>ELSE111:                                          ; preds = %ELSE108
>  %363 = fcmp ult float %temp24.3, %46
>  %364 = select i1 %363, float 1.000000e+00, float 0.000000e+00
>  %365 = fsub float -0.000000e+00, %364
>  %366 = fptosi float %365 to i32
>  %367 = bitcast i32 %366 to float
>  %368 = bitcast float %61 to i32
>  %369 = icmp sge i32 %368, 4
>  %370 = sext i1 %369 to i32
>  %371 = bitcast i32 %370 to float
>  %372 = bitcast float %367 to i32
>  %373 = bitcast float %371 to i32
>  %374 = and i32 %372, %373
>  %375 = bitcast i32 %374 to float
>  %376 = bitcast float %375 to i32
>  %377 = icmp ne i32 %376, 0
>  br i1 %377, label %ENDIF103, label %ELSE114
>
>ELSE114:                                          ; preds = %ELSE111
>  %378 = fcmp ult float %temp24.3, %41
>  %379 = select i1 %378, float 1.000000e+00, float 0.000000e+00
>  %380 = fsub float -0.000000e+00, %379
>  %381 = fptosi float %380 to i32
>  %382 = bitcast i32 %381 to float
>  %383 = bitcast float %61 to i32
>  %384 = icmp sge i32 %383, 5
>  %385 = sext i1 %384 to i32
>  %386 = bitcast i32 %385 to float
>  %387 = bitcast float %382 to i32
>  %388 = bitcast float %386 to i32
>  %389 = and i32 %387, %388
>  %390 = bitcast i32 %389 to float
>  %391 = bitcast float %390 to i32
>  %392 = icmp ne i32 %391, 0
>  br i1 %392, label %ENDIF103, label %ELSE117
>
>ELSE117:                                          ; preds = %ELSE114
>  %393 = fcmp ult float %temp24.3, %36
>  %394 = select i1 %393, float 1.000000e+00, float 0.000000e+00
>  %395 = fsub float -0.000000e+00, %394
>  %396 = fptosi float %395 to i32
>  %397 = bitcast i32 %396 to float
>  %398 = bitcast float %61 to i32
>  %399 = icmp sge i32 %398, 6
>  %400 = sext i1 %399 to i32
>  %401 = bitcast i32 %400 to float
>  %402 = bitcast float %397 to i32
>  %403 = bitcast float %401 to i32
>  %404 = and i32 %402, %403
>  %405 = bitcast i32 %404 to float
>  %406 = bitcast float %405 to i32
>  %407 = icmp ne i32 %406, 0
>  br i1 %407, label %ENDIF103, label %ELSE120
>
>ELSE120:                                          ; preds = %ELSE117
>  %408 = fcmp ult float %temp24.3, %31
>  %409 = select i1 %408, float 1.000000e+00, float 0.000000e+00
>  %410 = fsub float -0.000000e+00, %409
>  %411 = fptosi float %410 to i32
>  %412 = bitcast i32 %411 to float
>  %413 = bitcast float %61 to i32
>  %414 = icmp sge i32 %413, 7
>  %415 = sext i1 %414 to i32
>  %416 = bitcast i32 %415 to float
>  %417 = bitcast float %412 to i32
>  %418 = bitcast float %416 to i32
>  %419 = and i32 %417, %418
>  %420 = bitcast i32 %419 to float
>  %421 = bitcast float %420 to i32
>  %422 = icmp ne i32 %421, 0
>  br i1 %422, label %ENDIF103, label %ELSE123
>
>ELSE123:                                          ; preds = %ELSE120
>  %423 = fcmp ult float %temp24.3, %26
>  %424 = select i1 %423, float 1.000000e+00, float 0.000000e+00
>  %425 = fsub float -0.000000e+00, %424
>  %426 = fptosi float %425 to i32
>  %427 = bitcast i32 %426 to float
>  %428 = bitcast float %61 to i32
>  %429 = icmp sge i32 %428, 8
>  %430 = sext i1 %429 to i32
>  %431 = bitcast i32 %430 to float
>  %432 = bitcast float %427 to i32
>  %433 = bitcast float %431 to i32
>  %434 = and i32 %432, %433
>  %435 = bitcast i32 %434 to float
>  %436 = bitcast float %435 to i32
>  %437 = icmp ne i32 %436, 0
>  %.136 = select i1 %437, float %31, float %26
>  %.137 = select i1 %437, float %30, float %25
>  %.138 = select i1 %437, float %29, float %24
>  %.139 = select i1 %437, float %28, float %23
>  %.140 = select i1 %437, float %27, float %22
>  br label %ENDIF103
>
>ELSE129:                                          ; preds = %ENDIF103
>  %438 = fsub float -0.000000e+00, %temp16.0
>  %439 = fadd float %temp12.7, %438
>  %440 = fcmp ult float %439, 0x3EB0C6F7A0000000
>  %441 = select i1 %440, float 1.000000e+00, float 0.000000e+00
>  %442 = fsub float -0.000000e+00, %441
>  %443 = fptosi float %442 to i32
>  %444 = bitcast i32 %443 to float
>  %445 = bitcast float %444 to i32
>  %446 = icmp ne i32 %445, 0
>  br i1 %446, label %ENDIF127, label %ELSE132
>
>ENDIF127:                                         ; preds = %ELSE132, %ELSE129, %ENDIF103
>  %temp20.0 = phi float [ 0.000000e+00, %ENDIF103 ], [ %470, %ELSE132 ], [ 0.000000e+00, %ELSE129 ]
>  %447 = fsub float -0.000000e+00, %temp20.0
>  %448 = fadd float 1.000000e+00, %447
>  %449 = fmul float %temp20.0, %temp11.0
>  %450 = fmul float %448, %temp7.0
>  %451 = fadd float %450, %449
>  %452 = fsub float -0.000000e+00, %temp20.0
>  %453 = fadd float 1.000000e+00, %452
>  %454 = fmul float %temp20.0, %temp8.4
>  %455 = fmul float %temp20.0, %temp9.0
>  %456 = fmul float %temp20.0, %temp10.0
>  %457 = fmul float %453, %temp4.13
>  %458 = fadd float %457, %454
>  %459 = fmul float %453, %temp5.0
>  %460 = fadd float %459, %455
>  %461 = fmul float %453, %temp6.0
>  %462 = fadd float %461, %456
>  %463 = fmul float %458, %451
>  %464 = fmul float %460, %451
>  %465 = fmul float %462, %451
>  br label %ENDIF100
>
>ELSE132:                                          ; preds = %ELSE129
>  %466 = fadd float %temp24.3, %438
>  %467 = fsub float -0.000000e+00, %temp16.0
>  %468 = fadd float %temp12.7, %467
>  %469 = fdiv float 1.000000e+00, %468
>  %470 = fmul float %466, %469
>  br label %ENDIF127
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>Stack dump:
>0.	Running pass 'Function Pass Manager' on module 'tgsi'.
>1.	Running pass 'AMDGPU DAG->DAG Pattern Instruction Selection' on function '@main'
>(EE) 
>(EE) Backtrace:
>(EE) 0: /usr/bin/X (xorg_backtrace+0x36) [0x585cd6]
>(EE) 1: /usr/bin/X (0x400000+0x189769) [0x589769]
>(EE) 2: /lib64/libpthread.so.0 (0x7fe3e16db000+0xf670) [0x7fe3e16ea670]
>(EE) 3: /usr/lib64/../lib64/libLLVM-3.4svn.so (0x7fe3da342000+0x6c8397) [0x7fe3daa0a397]
>(EE) 4: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm16SelectionDAGISel22DoInstructionSelectionEv+0x217) [0x7fe3da7dd927]
>(EE) 5: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm16SelectionDAGISel17CodeGenAndEmitDAGEv+0x1c6) [0x7fe3da7e38a6]
>(EE) 6: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm16SelectionDAGISel20SelectAllBasicBlocksERKNS_8FunctionE+0x74a) [0x7fe3da7e532a]
>(EE) 7: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm16SelectionDAGISel20runOnMachineFunctionERNS_15MachineFunctionE+0x361) [0x7fe3da7e65e1]
>(EE) 8: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm13FPPassManager13runOnFunctionERNS_8FunctionE+0x1d7) [0x7fe3dab865a7]
>(EE) 9: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm13FPPassManager11runOnModuleERNS_6ModuleE+0x2b) [0x7fe3dab8663b]
>(EE) 10: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm13MPPassManager11runOnModuleERNS_6ModuleE+0x20b) [0x7fe3dab8686b]
>(EE) 11: /usr/lib64/../lib64/libLLVM-3.4svn.so (_ZN4llvm15PassManagerImpl3runERNS_6ModuleE+0xac) [0x7fe3dab8899c]
>(EE) 12: /usr/lib64/../lib64/libLLVM-3.4svn.so (0x7fe3da342000+0xc3505e) [0x7fe3daf7705e]
>(EE) 13: /usr/lib64/../lib64/libLLVM-3.4svn.so (LLVMTargetMachineEmitToMemoryBuffer+0x160) [0x7fe3daf773b0]
>(EE) 14: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (radeon_llvm_compile+0x172) [0x7fe3dbc7acf2]
>(EE) 15: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (si_compile_llvm+0x6f) [0x7fe3dbc709ff]
>(EE) 16: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (si_pipe_shader_create+0x4b7) [0x7fe3dbc71107]
>(EE) 17: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (si_shader_select+0x28e) [0x7fe3dbc76fee]
>(EE) 18: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x31a24a) [0x7fe3dbc7724a]
>(EE) 19: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x18ce77) [0x7fe3dbae9e77]
>(EE) 20: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x18e08e) [0x7fe3dbaeb08e]
>(EE) 21: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x15ba67) [0x7fe3dbab8a67]
>(EE) 22: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x1588c7) [0x7fe3dbab58c7]
>(EE) 23: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x16bda4) [0x7fe3dbac8da4]
>(EE) 24: /usr/lib64/xorg/modules/dri/radeonsi_dri.so (0x7fe3db95d000+0x145654) [0x7fe3dbaa2654]
>(EE) 25: /usr/lib64/libglamor.so.0 (0x7fe3de1a0000+0x162a5) [0x7fe3de1b62a5]
>(EE) 26: /usr/lib64/libglamor.so.0 (0x7fe3de1a0000+0x12890) [0x7fe3de1b2890]
>(EE) 27: /usr/lib64/libglamor.so.0 (0x7fe3de1a0000+0x129aa) [0x7fe3de1b29aa]
>(EE) 28: /usr/lib64/libglamor.so.0 (0x7fe3de1a0000+0x13c6a) [0x7fe3de1b3c6a]
>(EE) 29: /usr/lib64/libglamor.so.0 (0x7fe3de1a0000+0x14322) [0x7fe3de1b4322]
>(EE) 30: /usr/bin/X (0x400000+0x10fd19) [0x50fd19]
>(EE) 31: /usr/bin/X (0x400000+0x1092f4) [0x5092f4]
>(EE) 32: /usr/bin/X (0x400000+0x36836) [0x436836]
>(EE) 33: /usr/bin/X (0x400000+0x2530a) [0x42530a]
>(EE) 34: /lib64/libc.so.6 (__libc_start_main+0xf5) [0x7fe3df874d85]
>(EE) 35: /usr/bin/X (0x400000+0x2564d) [0x42564d]
>(EE) 
>(EE) Segmentation fault at address 0x7febdb4e91d8
>
>Fatal server error:
>Caught signal 11 (Segmentation fault). Server aborting
>
>(EE) 
>Please consult the The X.Org Foundation support 
>	 at http://wiki.x.org
> for help. 
>(EE) Please also check the log file at "/var/log/Xorg.0.log" for additional information.
>(EE) 
>Server terminated with error (1). Closing log file.
>xfce4-panel: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>wrapper: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>xfce4-mixer-plugin: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>xfce4-orageclock-plugin: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>xinit: connection to X server lost
>xfsettingsd: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>xfwm4: Fatal IO error 11 (Die Ressource ist zur Zeit nicht verfÃ¼gbar) on X server :0.0.
>xfdesktop: Fatal IO error 104 (Die Verbindung wurde vom Kommunikationspartner zurÃ¼ckgesetzt) on X server :0.0.

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Attachments on bug 65438: 80375 | 80567 | 80630

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