Attachment 81152 Details for Bug 66000 – dmesg

dmesg

dmesg_ivb60621.txt (text/plain), 127.29 KB, created by lu hua on 2013-06-21 08:19:03 UTC

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Creator: lu hua

Created: 2013-06-21 08:19:03 UTC

Size: 127.29 KB

patch

obsolete

>[ 3323.107161] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3323.107162] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3323.107163] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3323.107165] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 31500KHz
>[ 3323.107168] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3323.107169] [drm:intel_dp_compute_config], DP link bw required 75600 available 129600
>[ 3323.107170] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3323.107171] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3323.107173] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3323.107174] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3323.107174] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3323.107175] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1468006, gmch_n: 4194304, link_m: 61166, link_n: 524288, tu: 64
>[ 3323.107177] [drm:intel_dump_pipe_config], requested mode:
>[ 3323.107178] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 3323.107180] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3323.107181] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 3323.107183] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3323.107184] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3323.107185] [drm:intel_dump_pipe_config], ips: 0
>[ 3323.107193] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3323.107194] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3323.107195] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3323.107519] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3323.108319] [drm:ironlake_update_plane], Writing base 09981000 00000000 0 0 2560
>[ 3323.108322] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3323.108327] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3323.108328] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3323.108329] [drm:ironlake_write_eld], ELD on pipe B
>[ 3323.108330] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3323.108331] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3323.108343] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 52, cursor: 6
>[ 3323.108344] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3323.108346] [drm:ironlake_check_srwm], watermark 2: display plane 18, fbc lines 3, cursor 6
>[ 3323.108347] [drm:ironlake_check_srwm], watermark 3: display plane 34, fbc lines 3, cursor 6
>[ 3323.108349] [drm:ironlake_check_srwm], watermark 3: display plane 65, fbc lines 4, cursor 10
>[ 3323.160597] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3323.212546] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3323.212709] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3323.213367] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3323.213369] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3323.214027] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3323.214028] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3323.214029] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3323.214030] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3323.214032] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3323.215646] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3323.216231] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3323.216232] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3323.217130] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3323.231538] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3323.231545] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3323.231557] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3323.231562] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3323.231564] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3323.231567] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3323.231569] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3323.231573] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3323.231576] [drm:check_crtc_state], [CRTC:3]
>[ 3323.231577] [drm:check_crtc_state], [CRTC:5]
>[ 3323.231585] [drm:check_crtc_state], [CRTC:7]
>[ 3323.231586] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3323.231590] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3330.237828] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3330.237840] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3330.237841] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3330.237843] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3330.237844] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3330.238021] [drm:intel_dp_link_down], 
>[ 3330.290645] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3330.290651] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3330.291085] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3330.291092] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3330.291095] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3330.291097] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3330.291100] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3330.291102] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3330.291105] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3330.291107] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3330.291110] [drm:check_crtc_state], [CRTC:3]
>[ 3330.291111] [drm:check_crtc_state], [CRTC:5]
>[ 3330.291112] [drm:check_crtc_state], [CRTC:7]
>[ 3330.291113] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3330.291117] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3330.291129] [drm:drm_mode_addfb2], [FB:29]
>[ 3330.291131] [drm:drm_mode_addfb2], [FB:30]
>[ 3330.291132] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3330.291134] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3330.291135] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3330.291137] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3330.291138] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 3330.291139] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 3330.291141] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3330.291142] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3330.291144] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3330.291145] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3330.291146] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3330.291148] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3330.291149] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
>[ 3330.291150] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[ 3330.291151] [drm:intel_dp_compute_config], DP link bw required 45360 available 129600
>[ 3330.291153] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3330.291154] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[ 3330.291155] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3330.291156] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3330.291157] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[ 3330.291158] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 880803, gmch_n: 4194304, link_m: 48933, link_n: 524288, tu: 64
>[ 3330.291160] [drm:intel_dump_pipe_config], requested mode:
>[ 3330.291160] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3330.291162] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3330.291163] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3330.291165] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3330.291166] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3330.291167] [drm:intel_dump_pipe_config], ips: 0
>[ 3330.291175] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3330.291176] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3330.291177] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3330.291502] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3330.291896] [drm:ironlake_update_plane], Writing base 09AAD000 00000000 0 0 1280
>[ 3330.291899] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3330.291903] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3330.291904] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3330.291906] [drm:ironlake_write_eld], ELD on pipe B
>[ 3330.291908] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3330.291909] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3330.291919] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 4
>[ 3330.291920] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 4
>[ 3330.291921] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 4
>[ 3330.291923] [drm:ironlake_check_srwm], watermark 3: display plane 15, fbc lines 3, cursor 4
>[ 3330.291924] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 4, cursor 6
>[ 3330.343584] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3330.395534] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3330.395697] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3330.396355] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3330.396357] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3330.397015] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3330.397017] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3330.397018] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3330.397019] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3330.397020] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3330.398637] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3330.399219] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3330.399220] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3330.400118] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3330.418521] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3330.418527] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3330.418540] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3330.418545] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3330.418547] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3330.418550] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3330.418552] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3330.418556] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3330.418558] [drm:check_crtc_state], [CRTC:3]
>[ 3330.418560] [drm:check_crtc_state], [CRTC:5]
>[ 3330.418568] [drm:check_crtc_state], [CRTC:7]
>[ 3330.418568] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3330.418573] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3337.440914] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3337.440926] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3337.440927] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3337.440928] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3337.440930] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3337.441108] [drm:intel_dp_link_down], 
>[ 3337.493613] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3337.493619] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3337.494051] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3337.494057] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3337.494060] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3337.494063] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3337.494065] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3337.494068] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3337.494071] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3337.494073] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3337.494075] [drm:check_crtc_state], [CRTC:3]
>[ 3337.494076] [drm:check_crtc_state], [CRTC:5]
>[ 3337.494077] [drm:check_crtc_state], [CRTC:7]
>[ 3337.494078] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3337.494082] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3337.494093] [drm:drm_mode_addfb2], could not create framebuffer
>[ 3337.494111] [drm:drm_mode_addfb2], [FB:29]
>[ 3337.494113] [drm:drm_mode_addfb2], [FB:30]
>[ 3337.494114] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3337.494116] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3337.494117] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3337.494119] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3337.494120] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3337.494121] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3337.494122] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3337.494124] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3337.494125] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3337.494126] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
>[ 3337.494128] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3337.494129] [drm:intel_dp_compute_config], DP link bw required 60480 available 129600
>[ 3337.494131] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3337.494132] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3337.494133] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3337.494134] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3337.494135] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3337.494136] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1174405, gmch_n: 4194304, link_m: 48933, link_n: 524288, tu: 64
>[ 3337.494137] [drm:intel_dump_pipe_config], requested mode:
>[ 3337.494138] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3337.494140] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3337.494141] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3337.494143] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3337.494144] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3337.494145] [drm:intel_dump_pipe_config], ips: 0
>[ 3337.494153] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3337.494154] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3337.494155] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3337.494474] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3337.495226] [drm:ironlake_update_plane], Writing base 09B43000 00000000 0 0 2560
>[ 3337.495229] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3337.495234] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3337.495236] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3337.495237] [drm:ironlake_write_eld], ELD on pipe B
>[ 3337.495239] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3337.495240] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3337.495251] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3337.495253] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3337.495255] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3337.495256] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3337.495257] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3337.547551] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3337.599500] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3337.599662] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3337.600319] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3337.600321] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3337.600978] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3337.600981] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3337.600982] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3337.600982] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3337.600984] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3337.602600] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3337.603184] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3337.603185] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3337.604085] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3337.622486] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3337.622493] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3337.622496] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3337.622510] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3337.622513] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3337.622515] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3337.622517] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3337.622521] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3337.622523] [drm:check_crtc_state], [CRTC:3]
>[ 3337.622525] [drm:check_crtc_state], [CRTC:5]
>[ 3337.622533] [drm:check_crtc_state], [CRTC:7]
>[ 3337.622534] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3337.622537] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3344.628865] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3344.628877] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3344.628878] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3344.628880] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3344.628881] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3344.629058] [drm:intel_dp_link_down], 
>[ 3344.681597] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3344.681617] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3344.682039] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3344.682048] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3344.682050] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3344.682053] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3344.682056] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3344.682058] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3344.682060] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3344.682063] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3344.682065] [drm:check_crtc_state], [CRTC:3]
>[ 3344.682066] [drm:check_crtc_state], [CRTC:5]
>[ 3344.682067] [drm:check_crtc_state], [CRTC:7]
>[ 3344.682068] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3344.682073] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3344.682084] [drm:drm_mode_addfb2], [FB:29]
>[ 3344.682087] [drm:drm_mode_addfb2], [FB:30]
>[ 3344.682088] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3344.682090] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3344.682091] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3344.682093] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3344.682094] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3344.682095] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3344.682096] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3344.682097] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3344.682099] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3344.682100] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
>[ 3344.682102] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 30
>[ 3344.682103] [drm:intel_dp_compute_config], DP link bw required 75600 available 129600
>[ 3344.682104] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3344.682105] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 30, dithering: 0
>[ 3344.682106] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3344.682107] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3344.682108] [drm:intel_dump_pipe_config], pipe bpp: 30, dithering: 0
>[ 3344.682109] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1468006, gmch_n: 4194304, link_m: 48933, link_n: 524288, tu: 64
>[ 3344.682111] [drm:intel_dump_pipe_config], requested mode:
>[ 3344.682112] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3344.682114] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3344.682114] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3344.682116] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3344.682117] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3344.682118] [drm:intel_dump_pipe_config], ips: 0
>[ 3344.682126] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3344.682127] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3344.682128] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3344.682454] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3344.683229] [drm:ironlake_update_plane], Writing base 09C6F000 00000000 0 0 2560
>[ 3344.683231] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3344.683236] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3344.683238] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3344.683239] [drm:ironlake_write_eld], ELD on pipe B
>[ 3344.683240] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3344.683241] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3344.683252] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3344.683254] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3344.683255] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3344.683257] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3344.683258] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3344.735532] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3344.787482] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3344.787642] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3344.788300] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3344.788302] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3344.788960] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3344.788962] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3344.788963] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3344.788964] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3344.788965] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3344.790579] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3344.791160] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3344.791161] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3344.792058] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3344.810470] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3344.810476] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3344.810480] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3344.810492] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3344.810495] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3344.810497] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3344.810500] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3344.810504] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3344.810506] [drm:check_crtc_state], [CRTC:3]
>[ 3344.810507] [drm:check_crtc_state], [CRTC:5]
>[ 3344.810515] [drm:check_crtc_state], [CRTC:7]
>[ 3344.810515] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3344.810519] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3351.864509] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3351.864522] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3351.864523] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3351.864524] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3351.864525] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3351.864703] [drm:intel_dp_link_down], 
>[ 3351.902037] [drm:ivb_err_int_handler], Pipe B FIFO underrun
>[ 3351.919527] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3351.919534] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3351.919963] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3351.919973] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3351.919976] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3351.919978] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3351.919981] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3351.919983] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3351.919985] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3351.919988] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3351.919990] [drm:check_crtc_state], [CRTC:3]
>[ 3351.919991] [drm:check_crtc_state], [CRTC:5]
>[ 3351.919992] [drm:check_crtc_state], [CRTC:7]
>[ 3351.919993] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3351.919998] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3351.920009] [drm:drm_mode_addfb2], [FB:29]
>[ 3351.920011] [drm:drm_mode_addfb2], [FB:30]
>[ 3351.920013] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3351.920014] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3351.920015] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3351.920017] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3351.920018] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3351.920019] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3351.920020] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3351.920021] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3351.920023] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3351.920025] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25200KHz
>[ 3351.920026] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3351.920027] [drm:intel_dp_compute_config], DP link bw required 60480 available 129600
>[ 3351.920029] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3351.920030] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3351.920031] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3351.920032] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3351.920033] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3351.920034] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1174405, gmch_n: 4194304, link_m: 48933, link_n: 524288, tu: 64
>[ 3351.920035] [drm:intel_dump_pipe_config], requested mode:
>[ 3351.920036] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3351.920038] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3351.920039] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3351.920041] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3351.920042] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3351.920043] [drm:intel_dump_pipe_config], ips: 0
>[ 3351.920051] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3351.920052] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3351.920053] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3351.920377] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3351.921151] [drm:ironlake_update_plane], Writing base 09D9B000 00000000 0 0 2560
>[ 3351.921154] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3351.921159] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3351.921160] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3351.921162] [drm:ironlake_write_eld], ELD on pipe B
>[ 3351.921164] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3351.921165] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3351.921177] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3351.921178] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3351.921179] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3351.921182] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3351.921183] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3351.973466] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3352.025416] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3352.025579] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3352.026237] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3352.026239] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3352.026897] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3352.026898] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3352.026899] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3352.026900] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3352.026901] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3352.028515] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3352.029099] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3352.029100] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3352.029998] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3352.048403] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3352.048410] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3352.048422] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3352.048425] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3352.048427] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3352.048430] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3352.048432] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3352.048436] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3352.048439] [drm:check_crtc_state], [CRTC:3]
>[ 3352.048440] [drm:check_crtc_state], [CRTC:5]
>[ 3352.048448] [drm:check_crtc_state], [CRTC:7]
>[ 3352.048449] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3352.048453] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3359.054774] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3359.054786] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3359.054787] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3359.054788] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3359.054789] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3359.054965] [drm:intel_dp_link_down], 
>[ 3359.090027] [drm:ivb_err_int_handler], Pipe B FIFO underrun
>[ 3359.107511] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3359.107517] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3359.107949] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3359.107956] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3359.107959] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3359.107962] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3359.107964] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3359.107967] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3359.107969] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3359.107971] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3359.107974] [drm:check_crtc_state], [CRTC:3]
>[ 3359.107975] [drm:check_crtc_state], [CRTC:5]
>[ 3359.107976] [drm:check_crtc_state], [CRTC:7]
>[ 3359.107977] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3359.107981] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3359.107992] [drm:drm_mode_addfb2], [FB:29]
>[ 3359.107995] [drm:drm_mode_addfb2], [FB:30]
>[ 3359.107996] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3359.107997] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3359.107998] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3359.108000] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3359.108001] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 3359.108002] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3359.108004] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3359.108006] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3359.108007] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3359.108008] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3359.108009] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3359.108011] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3359.108012] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
>[ 3359.108013] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[ 3359.108015] [drm:intel_dp_compute_config], DP link bw required 45315 available 129600
>[ 3359.108016] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3359.108017] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[ 3359.108018] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3359.108019] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3359.108020] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[ 3359.108021] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 879930, gmch_n: 4194304, link_m: 48885, link_n: 524288, tu: 64
>[ 3359.108023] [drm:intel_dump_pipe_config], requested mode:
>[ 3359.108024] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3359.108025] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3359.108026] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3359.108028] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3359.108029] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3359.108030] [drm:intel_dump_pipe_config], ips: 0
>[ 3359.108038] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3359.108039] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3359.108040] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3359.108363] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3359.108749] [drm:ironlake_update_plane], Writing base 09EC7000 00000000 0 0 1280
>[ 3359.108751] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3359.108757] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3359.108758] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3359.108759] [drm:ironlake_write_eld], ELD on pipe B
>[ 3359.108762] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3359.108763] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3359.108773] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 4
>[ 3359.108775] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 4
>[ 3359.108776] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 4
>[ 3359.108778] [drm:ironlake_check_srwm], watermark 3: display plane 15, fbc lines 3, cursor 4
>[ 3359.108780] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 4, cursor 6
>[ 3359.160448] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3359.212397] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3359.212559] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3359.213217] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3359.213220] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3359.213877] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3359.213879] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3359.213880] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3359.213881] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3359.213882] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3359.215496] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3359.216078] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3359.216080] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3359.216979] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3359.235386] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3359.235392] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3359.235405] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3359.235409] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3359.235412] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3359.235414] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3359.235417] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3359.235421] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3359.235424] [drm:check_crtc_state], [CRTC:3]
>[ 3359.235425] [drm:check_crtc_state], [CRTC:5]
>[ 3359.235432] [drm:check_crtc_state], [CRTC:7]
>[ 3359.235433] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3359.235437] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3366.257810] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3366.257815] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3366.257816] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3366.257817] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3366.257819] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3366.258005] [drm:intel_dp_link_down], 
>[ 3366.318471] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3366.318478] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3366.318915] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3366.318923] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3366.318926] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3366.318929] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3366.318931] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3366.318934] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3366.318936] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3366.318939] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3366.318941] [drm:check_crtc_state], [CRTC:3]
>[ 3366.318942] [drm:check_crtc_state], [CRTC:5]
>[ 3366.318943] [drm:check_crtc_state], [CRTC:7]
>[ 3366.318944] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3366.318949] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3366.318964] [drm:drm_mode_addfb2], could not create framebuffer
>[ 3366.318979] [drm:drm_mode_addfb2], [FB:29]
>[ 3366.318986] [drm:drm_mode_addfb2], [FB:30]
>[ 3366.318987] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3366.318989] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3366.318990] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3366.318992] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3366.318993] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3366.318994] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3366.318996] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3366.318997] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3366.318998] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3366.319000] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
>[ 3366.319002] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3366.319003] [drm:intel_dp_compute_config], DP link bw required 60420 available 129600
>[ 3366.319004] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3366.319006] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3366.319007] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3366.319008] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3366.319009] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3366.319010] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1173240, gmch_n: 4194304, link_m: 48885, link_n: 524288, tu: 64
>[ 3366.319011] [drm:intel_dump_pipe_config], requested mode:
>[ 3366.319012] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3366.319014] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3366.319015] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3366.319017] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3366.319018] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3366.319019] [drm:intel_dump_pipe_config], ips: 0
>[ 3366.319028] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3366.319029] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3366.319030] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3366.319352] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3366.320081] [drm:ironlake_update_plane], Writing base 09F5D000 00000000 0 0 2560
>[ 3366.320084] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3366.320089] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3366.320091] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3366.320093] [drm:ironlake_write_eld], ELD on pipe B
>[ 3366.320095] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3366.320096] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3366.320108] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3366.320109] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3366.320111] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3366.320112] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3366.320114] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3366.372407] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3366.424356] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3366.424518] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3366.425177] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3366.425179] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3366.425836] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3366.425838] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3366.425839] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3366.425840] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3366.425841] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3366.427458] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3366.428037] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3366.428039] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3366.428936] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3366.447344] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3366.447350] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3366.447363] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3366.447368] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3366.447370] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3366.447373] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3366.447375] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3366.447379] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3366.447382] [drm:check_crtc_state], [CRTC:3]
>[ 3366.447383] [drm:check_crtc_state], [CRTC:5]
>[ 3366.447392] [drm:check_crtc_state], [CRTC:7]
>[ 3366.447393] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3366.447396] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3373.453810] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3373.453822] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3373.453823] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3373.453824] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3373.453826] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3373.454003] [drm:intel_dp_link_down], 
>[ 3373.514442] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3373.514448] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3373.514871] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3373.514880] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3373.514882] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3373.514885] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3373.514887] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3373.514890] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3373.514892] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3373.514895] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3373.514897] [drm:check_crtc_state], [CRTC:3]
>[ 3373.514898] [drm:check_crtc_state], [CRTC:5]
>[ 3373.514899] [drm:check_crtc_state], [CRTC:7]
>[ 3373.514900] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3373.514904] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3373.514916] [drm:drm_mode_addfb2], [FB:29]
>[ 3373.514918] [drm:drm_mode_addfb2], [FB:30]
>[ 3373.514919] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3373.514921] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3373.514922] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3373.514924] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3373.514925] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3373.514926] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3373.514927] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3373.514928] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3373.514930] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3373.514931] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
>[ 3373.514933] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 30
>[ 3373.514934] [drm:intel_dp_compute_config], DP link bw required 75525 available 129600
>[ 3373.514936] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3373.514937] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 30, dithering: 0
>[ 3373.514938] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3373.514939] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3373.514940] [drm:intel_dump_pipe_config], pipe bpp: 30, dithering: 0
>[ 3373.514941] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1466550, gmch_n: 4194304, link_m: 48885, link_n: 524288, tu: 64
>[ 3373.514942] [drm:intel_dump_pipe_config], requested mode:
>[ 3373.514943] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3373.514945] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3373.514946] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3373.514947] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3373.514949] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3373.514950] [drm:intel_dump_pipe_config], ips: 0
>[ 3373.514958] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3373.514959] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3373.514960] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3373.515283] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3373.515970] [drm:ironlake_update_plane], Writing base 0A089000 00000000 0 0 2560
>[ 3373.515972] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3373.515977] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3373.515979] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3373.515980] [drm:ironlake_write_eld], ELD on pipe B
>[ 3373.515982] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3373.515983] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3373.515994] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3373.515996] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3373.515997] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3373.515999] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3373.516001] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3373.568382] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3373.620331] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3373.620491] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3373.621148] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3373.621150] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3373.621807] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3373.621810] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3373.621811] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3373.621812] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3373.621813] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3373.623428] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3373.624012] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3373.624013] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3373.624911] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3373.643316] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3373.643323] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3373.643327] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3373.643339] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3373.643344] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3373.643347] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3373.643349] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3373.643353] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3373.643355] [drm:check_crtc_state], [CRTC:3]
>[ 3373.643356] [drm:check_crtc_state], [CRTC:5]
>[ 3373.643364] [drm:check_crtc_state], [CRTC:7]
>[ 3373.643365] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3373.643369] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3380.697973] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3380.697985] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3380.697986] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3380.697988] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3380.697989] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3380.698167] [drm:intel_dp_link_down], 
>[ 3380.760371] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3380.760377] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3380.760811] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3380.760819] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3380.760821] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3380.760824] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3380.760826] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3380.760829] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3380.760831] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3380.760833] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3380.760836] [drm:check_crtc_state], [CRTC:3]
>[ 3380.760837] [drm:check_crtc_state], [CRTC:5]
>[ 3380.760838] [drm:check_crtc_state], [CRTC:7]
>[ 3380.760839] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3380.760843] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3380.760855] [drm:drm_mode_addfb2], [FB:29]
>[ 3380.760858] [drm:drm_mode_addfb2], [FB:30]
>[ 3380.760860] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3380.760861] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3380.760862] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3380.760864] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3380.760865] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3380.760866] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3380.760868] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3380.760869] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3380.760871] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3380.760872] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 25175KHz
>[ 3380.760873] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3380.760875] [drm:intel_dp_compute_config], DP link bw required 60420 available 129600
>[ 3380.760876] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3380.760877] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3380.760878] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3380.760879] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3380.760880] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3380.760881] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1173240, gmch_n: 4194304, link_m: 48885, link_n: 524288, tu: 64
>[ 3380.760883] [drm:intel_dump_pipe_config], requested mode:
>[ 3380.760884] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3380.760886] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3380.760886] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3380.760888] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3380.760889] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3380.760890] [drm:intel_dump_pipe_config], ips: 0
>[ 3380.760898] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3380.760899] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3380.760900] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3380.761224] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3380.761936] [drm:ironlake_update_plane], Writing base 0A1B5000 00000000 0 0 2560
>[ 3380.761938] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:640x480]
>[ 3380.761944] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3380.761945] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3380.761946] [drm:ironlake_write_eld], ELD on pipe B
>[ 3380.761949] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3380.761950] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3380.761961] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 51, cursor: 6
>[ 3380.761962] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3380.761964] [drm:ironlake_check_srwm], watermark 2: display plane 15, fbc lines 3, cursor 6
>[ 3380.761966] [drm:ironlake_check_srwm], watermark 3: display plane 27, fbc lines 3, cursor 6
>[ 3380.761968] [drm:ironlake_check_srwm], watermark 3: display plane 52, fbc lines 4, cursor 10
>[ 3380.814307] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3380.866256] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3380.866419] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3380.867077] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3380.867080] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3380.867737] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3380.867740] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3380.867740] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3380.867741] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3380.867743] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3380.869354] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3380.869934] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3380.869936] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3380.870831] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3380.889244] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3380.889251] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3380.889263] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3380.889268] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3380.889271] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3380.889273] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3380.889276] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3380.889280] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3380.889283] [drm:check_crtc_state], [CRTC:3]
>[ 3380.889284] [drm:check_crtc_state], [CRTC:5]
>[ 3380.889292] [drm:check_crtc_state], [CRTC:7]
>[ 3380.889293] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3380.889297] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3387.895633] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3387.895646] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3387.895648] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3387.895649] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3387.895650] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3387.895829] [drm:intel_dp_link_down], 
>[ 3387.956342] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3387.956348] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3387.956779] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3387.956787] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3387.956790] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3387.956793] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3387.956795] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3387.956798] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3387.956800] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3387.956803] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3387.956805] [drm:check_crtc_state], [CRTC:3]
>[ 3387.956807] [drm:check_crtc_state], [CRTC:5]
>[ 3387.956808] [drm:check_crtc_state], [CRTC:7]
>[ 3387.956808] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3387.956812] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3387.956824] [drm:drm_mode_addfb2], [FB:29]
>[ 3387.956826] [drm:drm_mode_addfb2], [FB:30]
>[ 3387.956828] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3387.956829] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3387.956830] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3387.956832] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3387.956833] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 3387.956834] [drm:drm_mode_debug_printmodeline], Modeline 48:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3387.956836] [drm:drm_mode_debug_printmodeline], Modeline 48:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3387.956837] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3387.956839] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3387.956840] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3387.956841] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3387.956842] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3387.956844] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
>[ 3387.956845] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[ 3387.956846] [drm:intel_dp_compute_config], DP link bw required 50976 available 129600
>[ 3387.956848] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3387.956849] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[ 3387.956850] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3387.956851] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3387.956852] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[ 3387.956853] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 989855, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3387.956854] [drm:intel_dump_pipe_config], requested mode:
>[ 3387.956855] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3387.956857] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3387.956858] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3387.956859] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3387.956861] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3387.956862] [drm:intel_dump_pipe_config], ips: 0
>[ 3387.956870] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3387.956871] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3387.956872] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3387.957195] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3387.957551] [drm:ironlake_update_plane], Writing base 0A2E1000 00000000 0 0 1472
>[ 3387.957553] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:720x400]
>[ 3387.957558] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3387.957560] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3387.957561] [drm:ironlake_write_eld], ELD on pipe B
>[ 3387.957563] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3387.957564] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3387.957575] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 41, cursor: 4
>[ 3387.957577] [drm:ironlake_check_srwm], watermark 1: display plane 4, fbc lines 3, cursor 4
>[ 3387.957578] [drm:ironlake_check_srwm], watermark 2: display plane 9, fbc lines 3, cursor 4
>[ 3387.957580] [drm:ironlake_check_srwm], watermark 3: display plane 16, fbc lines 3, cursor 4
>[ 3387.957581] [drm:ironlake_check_srwm], watermark 3: display plane 30, fbc lines 4, cursor 6
>[ 3388.009282] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3388.061231] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3388.061393] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3388.062051] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3388.062053] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3388.062711] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3388.062714] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3388.062714] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3388.062715] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3388.062716] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3388.064331] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3388.064933] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3388.064934] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3388.065835] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3388.080221] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3388.080227] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3388.080232] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3388.080246] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3388.080248] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3388.080251] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3388.080253] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3388.080257] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3388.080259] [drm:check_crtc_state], [CRTC:3]
>[ 3388.080260] [drm:check_crtc_state], [CRTC:5]
>[ 3388.080269] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 4, found 0)
>[ 3388.080271] ------------[ cut here ]------------
>[ 3388.080281] WARNING: at drivers/gpu/drm/i915/intel_display.c:8281 check_crtc_state+0x604/0x64b [i915]()
>[ 3388.080282] pipe state doesn't match!
>[ 3388.080283] Modules linked in: dm_mod acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi snd_hda_codec_realtek iTCO_wdt microcode iTCO_vendor_support pcspkr i2c_i801 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc lpc_ich mfd_core snd_timer snd soundcore ppdev parport_pc parport wmi i915 video button drm_kms_helper drm mperf freq_table
>[ 3388.080295] CPU: 2 PID: 10899 Comm: kms_render Tainted: G        W    3.10.0-rc2_drm-intel-next-queued_854c94_20130619_+ #4227
>[ 3388.080296] Hardware name:                  /DH77EB, BIOS EBH7710H.86A.0062.2012.0329.1914 03/29/2012
>[ 3388.080298]  ffffffff816de142 0000000000000000 ffffffff8102c67d ffff8802104af8a0
>[ 3388.080299]  ffff8802104af8a8 0000000000000001 ffff88021598e000 ffff8802112aa000
>[ 3388.080301]  ffff8802104af918 ffff88021598e6c8 ffffffff8102c72d ffffffffa00c1e75
>[ 3388.080303] Call Trace:
>[ 3388.080307]  [<ffffffff816de142>] ? dump_stack+0xd/0x17
>[ 3388.080310]  [<ffffffff8102c67d>] ? warn_slowpath_common+0x5f/0x77
>[ 3388.080312]  [<ffffffff8102c72d>] ? warn_slowpath_fmt+0x45/0x4a
>[ 3388.080318]  [<ffffffffa00807b3>] ? check_crtc_state+0x604/0x64b [i915]
>[ 3388.080325]  [<ffffffffa0089776>] ? intel_modeset_check_state+0x36f/0x5e8 [i915]
>[ 3388.080330]  [<ffffffffa0089a5f>] ? intel_set_mode+0x1d/0x27 [i915]
>[ 3388.080334]  [<ffffffffa0089fec>] ? intel_crtc_set_config+0x583/0x73b [i915]
>[ 3388.080340]  [<ffffffffa0013cc1>] ? drm_mode_set_config_internal+0x19/0x40 [drm]
>[ 3388.080344]  [<ffffffffa0015925>] ? drm_mode_setcrtc+0x437/0x4e8 [drm]
>[ 3388.080349]  [<ffffffffa008a580>] ? intel_framebuffer_create+0x7e/0xcc [i915]
>[ 3388.080351]  [<ffffffff816e0d38>] ? mutex_lock+0xd/0x2d
>[ 3388.080355]  [<ffffffffa000946c>] ? drm_ioctl+0x290/0x3b5 [drm]
>[ 3388.080359]  [<ffffffffa00154ee>] ? drm_mode_setplane+0x30f/0x30f [drm]
>[ 3388.080361]  [<ffffffff810c97a9>] ? kmem_cache_free+0xe2/0xe6
>[ 3388.080363]  [<ffffffff810dc342>] ? vfs_ioctl+0x1e/0x31
>[ 3388.080365]  [<ffffffff810dcb71>] ? do_vfs_ioctl+0x3e9/0x42b
>[ 3388.080366]  [<ffffffff810d02ce>] ? __fput+0x1af/0x1d6
>[ 3388.080368]  [<ffffffff810e56a3>] ? mnt_get_count+0x35/0x45
>[ 3388.080370]  [<ffffffff810e5712>] ? mntput_no_expire+0x5f/0x12b
>[ 3388.080372]  [<ffffffff8104a5e6>] ? lg_global_unlock+0x30/0x3a
>[ 3388.080374]  [<ffffffff810dcc01>] ? SyS_ioctl+0x4e/0x7d
>[ 3388.080375]  [<ffffffff816e7e12>] ? system_call_fastpath+0x16/0x1b
>[ 3388.080377] ---[ end trace 7d7c1054f0a165e7 ]---
>[ 3388.080377] [drm:intel_dump_pipe_config], [CRTC:5][hw state] config for pipe B
>[ 3388.080379] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3388.080380] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0
>[ 3388.080380] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 989855, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3388.080382] [drm:intel_dump_pipe_config], requested mode:
>[ 3388.080383] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 720 0 0 0 400 0 0 0 0x0 0x0
>[ 3388.080385] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3388.080386] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
>[ 3388.080387] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3388.080388] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3388.080389] [drm:intel_dump_pipe_config], ips: 0
>[ 3388.080390] [drm:intel_dump_pipe_config], [CRTC:5][sw state] config for pipe B
>[ 3388.080391] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3388.080392] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[ 3388.080393] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 989855, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3388.080395] [drm:intel_dump_pipe_config], requested mode:
>[ 3388.080395] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3388.080397] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3388.080398] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3388.080400] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3388.080401] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3388.080402] [drm:intel_dump_pipe_config], ips: 0
>[ 3388.080403] [drm:check_crtc_state], [CRTC:7]
>[ 3388.080404] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3388.080410] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3395.101712] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3395.101717] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3395.101719] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3395.101720] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3395.101721] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3395.101903] [drm:intel_dp_link_down], 
>[ 3395.152318] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3395.152327] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3395.152761] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3395.152769] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3395.152772] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3395.152775] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3395.152778] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3395.152780] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3395.152782] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3395.152783] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3395.152786] [drm:check_crtc_state], [CRTC:3]
>[ 3395.152787] [drm:check_crtc_state], [CRTC:5]
>[ 3395.152788] [drm:check_crtc_state], [CRTC:7]
>[ 3395.152789] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3395.152793] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3395.152807] [drm:drm_mode_addfb2], could not create framebuffer
>[ 3395.152827] [drm:drm_mode_addfb2], [FB:29]
>[ 3395.152829] [drm:drm_mode_addfb2], [FB:30]
>[ 3395.152831] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3395.152833] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3395.152834] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3395.152836] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3395.152837] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3395.152838] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3395.152840] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3395.152841] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3395.152842] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3395.152844] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
>[ 3395.152848] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3395.152849] [drm:intel_dp_compute_config], DP link bw required 67968 available 129600
>[ 3395.152850] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3395.152852] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3395.152853] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3395.152854] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3395.152855] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3395.152856] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3395.152857] [drm:intel_dump_pipe_config], requested mode:
>[ 3395.152858] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3395.152860] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3395.152861] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3395.152863] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3395.152864] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3395.152865] [drm:intel_dump_pipe_config], ips: 0
>[ 3395.152874] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3395.152875] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3395.152876] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3395.153198] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3395.153920] [drm:ironlake_update_plane], Writing base 0A371000 00000000 0 0 2880
>[ 3395.153923] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:720x400]
>[ 3395.153929] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3395.153930] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3395.153931] [drm:ironlake_write_eld], ELD on pipe B
>[ 3395.153933] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3395.153934] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3395.153946] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
>[ 3395.153948] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3395.153949] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
>[ 3395.153951] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
>[ 3395.153952] [drm:ironlake_check_srwm], watermark 3: display plane 59, fbc lines 4, cursor 10
>[ 3395.206255] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3395.258205] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3395.258368] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3395.259025] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3395.259028] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3395.259682] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3395.259685] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3395.259686] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3395.259687] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3395.259688] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3395.261301] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3395.261885] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3395.261887] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3395.262783] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3395.277189] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3395.277194] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3395.277197] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3395.277199] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3395.277202] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3395.277204] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3395.277207] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3395.277211] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3395.277213] [drm:check_crtc_state], [CRTC:3]
>[ 3395.277214] [drm:check_crtc_state], [CRTC:5]
>[ 3395.277223] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 4, found 0)
>[ 3395.277224] ------------[ cut here ]------------
>[ 3395.277235] WARNING: at drivers/gpu/drm/i915/intel_display.c:8281 check_crtc_state+0x604/0x64b [i915]()
>[ 3395.277236] pipe state doesn't match!
>[ 3395.277236] Modules linked in: dm_mod acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi snd_hda_codec_realtek iTCO_wdt microcode iTCO_vendor_support pcspkr i2c_i801 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc lpc_ich mfd_core snd_timer snd soundcore ppdev parport_pc parport wmi i915 video button drm_kms_helper drm mperf freq_table
>[ 3395.277249] CPU: 1 PID: 10899 Comm: kms_render Tainted: G        W    3.10.0-rc2_drm-intel-next-queued_854c94_20130619_+ #4227
>[ 3395.277250] Hardware name:                  /DH77EB, BIOS EBH7710H.86A.0062.2012.0329.1914 03/29/2012
>[ 3395.277252]  ffffffff816de142 0000000000000000 ffffffff8102c67d ffff8802104af8a0
>[ 3395.277253]  ffff8802104af8a8 0000000000000001 ffff88021598e000 ffff8802112aa000
>[ 3395.277255]  ffff8802104af918 ffff88021598e6c8 ffffffff8102c72d ffffffffa00c1e75
>[ 3395.277257] Call Trace:
>[ 3395.277261]  [<ffffffff816de142>] ? dump_stack+0xd/0x17
>[ 3395.277264]  [<ffffffff8102c67d>] ? warn_slowpath_common+0x5f/0x77
>[ 3395.277266]  [<ffffffff8102c72d>] ? warn_slowpath_fmt+0x45/0x4a
>[ 3395.277272]  [<ffffffffa00807b3>] ? check_crtc_state+0x604/0x64b [i915]
>[ 3395.277278]  [<ffffffffa0089776>] ? intel_modeset_check_state+0x36f/0x5e8 [i915]
>[ 3395.277283]  [<ffffffffa0089a5f>] ? intel_set_mode+0x1d/0x27 [i915]
>[ 3395.277288]  [<ffffffffa0089fec>] ? intel_crtc_set_config+0x583/0x73b [i915]
>[ 3395.277293]  [<ffffffffa0013cc1>] ? drm_mode_set_config_internal+0x19/0x40 [drm]
>[ 3395.277297]  [<ffffffffa0015925>] ? drm_mode_setcrtc+0x437/0x4e8 [drm]
>[ 3395.277302]  [<ffffffffa008a580>] ? intel_framebuffer_create+0x7e/0xcc [i915]
>[ 3395.277304]  [<ffffffff816e0d38>] ? mutex_lock+0xd/0x2d
>[ 3395.277308]  [<ffffffffa000946c>] ? drm_ioctl+0x290/0x3b5 [drm]
>[ 3395.277311]  [<ffffffffa00154ee>] ? drm_mode_setplane+0x30f/0x30f [drm]
>[ 3395.277313]  [<ffffffff816e1b31>] ? __schedule+0x60a/0x751
>[ 3395.277316]  [<ffffffff8104b125>] ? __wake_up+0x35/0x46
>[ 3395.277318]  [<ffffffff810dc342>] ? vfs_ioctl+0x1e/0x31
>[ 3395.277320]  [<ffffffff810dcb71>] ? do_vfs_ioctl+0x3e9/0x42b
>[ 3395.277321]  [<ffffffff810dcc01>] ? SyS_ioctl+0x4e/0x7d
>[ 3395.277323]  [<ffffffff816e7e12>] ? system_call_fastpath+0x16/0x1b
>[ 3395.277325] ---[ end trace 7d7c1054f0a165e8 ]---
>[ 3395.277325] [drm:intel_dump_pipe_config], [CRTC:5][hw state] config for pipe B
>[ 3395.277327] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3395.277327] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0
>[ 3395.277328] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3395.277330] [drm:intel_dump_pipe_config], requested mode:
>[ 3395.277331] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 720 0 0 0 400 0 0 0 0x0 0x0
>[ 3395.277333] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3395.277334] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
>[ 3395.277335] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3395.277336] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3395.277337] [drm:intel_dump_pipe_config], ips: 0
>[ 3395.277338] [drm:intel_dump_pipe_config], [CRTC:5][sw state] config for pipe B
>[ 3395.277339] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3395.277340] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3395.277341] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3395.277343] [drm:intel_dump_pipe_config], requested mode:
>[ 3395.277343] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3395.277345] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3395.277346] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3395.277348] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3395.277349] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3395.277350] [drm:intel_dump_pipe_config], ips: 0
>[ 3395.277351] [drm:check_crtc_state], [CRTC:7]
>[ 3395.277352] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3395.277358] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3402.283479] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3402.283483] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3402.283485] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3402.283486] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3402.283487] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3402.283667] [drm:intel_dp_link_down], 
>[ 3402.334304] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3402.334313] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3402.334746] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3402.334753] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3402.334756] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3402.334759] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3402.334761] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3402.334763] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3402.334766] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3402.334768] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3402.334770] [drm:check_crtc_state], [CRTC:3]
>[ 3402.334772] [drm:check_crtc_state], [CRTC:5]
>[ 3402.334773] [drm:check_crtc_state], [CRTC:7]
>[ 3402.334774] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3402.334778] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3402.334792] [drm:drm_mode_addfb2], [FB:29]
>[ 3402.334795] [drm:drm_mode_addfb2], [FB:30]
>[ 3402.334796] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3402.334798] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3402.334799] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3402.334801] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3402.334802] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3402.334803] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3402.334805] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3402.334806] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3402.334808] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3402.334809] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
>[ 3402.334813] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 30
>[ 3402.334814] [drm:intel_dp_compute_config], DP link bw required 84960 available 129600
>[ 3402.334816] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3402.334817] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 30, dithering: 0
>[ 3402.334818] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3402.334819] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3402.334820] [drm:intel_dump_pipe_config], pipe bpp: 30, dithering: 0
>[ 3402.334821] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1649759, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3402.334823] [drm:intel_dump_pipe_config], requested mode:
>[ 3402.334824] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3402.334826] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3402.334826] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3402.334828] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3402.334829] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3402.334831] [drm:intel_dump_pipe_config], ips: 0
>[ 3402.334840] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3402.334841] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3402.334842] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3402.335165] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3402.335909] [drm:ironlake_update_plane], Writing base 0A48B000 00000000 0 0 2880
>[ 3402.335913] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:720x400]
>[ 3402.335918] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3402.335919] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3402.335920] [drm:ironlake_write_eld], ELD on pipe B
>[ 3402.335923] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3402.335924] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3402.335936] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
>[ 3402.335938] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3402.335940] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
>[ 3402.335941] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
>[ 3402.335943] [drm:ironlake_check_srwm], watermark 3: display plane 59, fbc lines 4, cursor 10
>[ 3402.388244] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3402.440196] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3402.440360] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3402.441018] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3402.441021] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3402.441679] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3402.441681] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3402.441682] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3402.441683] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3402.441684] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3402.443303] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3402.443887] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3402.443889] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3402.444789] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3402.459183] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3402.459189] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3402.459203] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3402.459206] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3402.459208] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3402.459211] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3402.459213] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3402.459218] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3402.459220] [drm:check_crtc_state], [CRTC:3]
>[ 3402.459221] [drm:check_crtc_state], [CRTC:5]
>[ 3402.459231] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 4, found 0)
>[ 3402.459232] ------------[ cut here ]------------
>[ 3402.459242] WARNING: at drivers/gpu/drm/i915/intel_display.c:8281 check_crtc_state+0x604/0x64b [i915]()
>[ 3402.459243] pipe state doesn't match!
>[ 3402.459244] Modules linked in: dm_mod acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi snd_hda_codec_realtek iTCO_wdt microcode iTCO_vendor_support pcspkr i2c_i801 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc lpc_ich mfd_core snd_timer snd soundcore ppdev parport_pc parport wmi i915 video button drm_kms_helper drm mperf freq_table
>[ 3402.459257] CPU: 1 PID: 10899 Comm: kms_render Tainted: G        W    3.10.0-rc2_drm-intel-next-queued_854c94_20130619_+ #4227
>[ 3402.459258] Hardware name:                  /DH77EB, BIOS EBH7710H.86A.0062.2012.0329.1914 03/29/2012
>[ 3402.459259]  ffffffff816de142 0000000000000000 ffffffff8102c67d ffff8802104af8a0
>[ 3402.459261]  ffff8802104af8a8 0000000000000001 ffff88021598e000 ffff8802112aa000
>[ 3402.459262]  ffff8802104af918 ffff88021598e6c8 ffffffff8102c72d ffffffffa00c1e75
>[ 3402.459264] Call Trace:
>[ 3402.459269]  [<ffffffff816de142>] ? dump_stack+0xd/0x17
>[ 3402.459272]  [<ffffffff8102c67d>] ? warn_slowpath_common+0x5f/0x77
>[ 3402.459274]  [<ffffffff8102c72d>] ? warn_slowpath_fmt+0x45/0x4a
>[ 3402.459279]  [<ffffffffa00807b3>] ? check_crtc_state+0x604/0x64b [i915]
>[ 3402.459286]  [<ffffffffa0089776>] ? intel_modeset_check_state+0x36f/0x5e8 [i915]
>[ 3402.459291]  [<ffffffffa0089a5f>] ? intel_set_mode+0x1d/0x27 [i915]
>[ 3402.459296]  [<ffffffffa0089fec>] ? intel_crtc_set_config+0x583/0x73b [i915]
>[ 3402.459301]  [<ffffffffa0013cc1>] ? drm_mode_set_config_internal+0x19/0x40 [drm]
>[ 3402.459305]  [<ffffffffa0015925>] ? drm_mode_setcrtc+0x437/0x4e8 [drm]
>[ 3402.459310]  [<ffffffffa008a580>] ? intel_framebuffer_create+0x7e/0xcc [i915]
>[ 3402.459312]  [<ffffffff816e0d38>] ? mutex_lock+0xd/0x2d
>[ 3402.459316]  [<ffffffffa000946c>] ? drm_ioctl+0x290/0x3b5 [drm]
>[ 3402.459319]  [<ffffffffa00154ee>] ? drm_mode_setplane+0x30f/0x30f [drm]
>[ 3402.459322]  [<ffffffff810c97a9>] ? kmem_cache_free+0xe2/0xe6
>[ 3402.459324]  [<ffffffff810dc342>] ? vfs_ioctl+0x1e/0x31
>[ 3402.459325]  [<ffffffff810dcb71>] ? do_vfs_ioctl+0x3e9/0x42b
>[ 3402.459327]  [<ffffffff810d02ce>] ? __fput+0x1af/0x1d6
>[ 3402.459329]  [<ffffffff810e56a3>] ? mnt_get_count+0x35/0x45
>[ 3402.459331]  [<ffffffff810e5712>] ? mntput_no_expire+0x5f/0x12b
>[ 3402.459333]  [<ffffffff8104a5e6>] ? lg_global_unlock+0x30/0x3a
>[ 3402.459335]  [<ffffffff810dcc01>] ? SyS_ioctl+0x4e/0x7d
>[ 3402.459336]  [<ffffffff816e7e12>] ? system_call_fastpath+0x16/0x1b
>[ 3402.459338] ---[ end trace 7d7c1054f0a165e9 ]---
>[ 3402.459338] [drm:intel_dump_pipe_config], [CRTC:5][hw state] config for pipe B
>[ 3402.459340] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3402.459340] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0
>[ 3402.459342] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1649759, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3402.459343] [drm:intel_dump_pipe_config], requested mode:
>[ 3402.459344] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 720 0 0 0 400 0 0 0 0x0 0x0
>[ 3402.459346] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3402.459347] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
>[ 3402.459348] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3402.459349] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3402.459350] [drm:intel_dump_pipe_config], ips: 0
>[ 3402.459351] [drm:intel_dump_pipe_config], [CRTC:5][sw state] config for pipe B
>[ 3402.459352] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3402.459353] [drm:intel_dump_pipe_config], pipe bpp: 30, dithering: 0
>[ 3402.459354] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1649759, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3402.459355] [drm:intel_dump_pipe_config], requested mode:
>[ 3402.459356] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3402.459358] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3402.459359] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3402.459361] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3402.459362] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3402.459363] [drm:intel_dump_pipe_config], ips: 0
>[ 3402.459364] [drm:check_crtc_state], [CRTC:7]
>[ 3402.459365] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3402.459371] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3409.511289] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3409.511293] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3409.511295] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3409.511296] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3409.511297] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3409.511476] [drm:intel_dp_link_down], 
>[ 3409.560251] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3409.560260] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3409.560691] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3409.560699] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3409.560701] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3409.560704] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3409.560706] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3409.560709] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3409.560711] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3409.560714] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3409.560716] [drm:check_crtc_state], [CRTC:3]
>[ 3409.560717] [drm:check_crtc_state], [CRTC:5]
>[ 3409.560718] [drm:check_crtc_state], [CRTC:7]
>[ 3409.560719] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3409.560723] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3409.560738] [drm:drm_mode_addfb2], [FB:29]
>[ 3409.560740] [drm:drm_mode_addfb2], [FB:30]
>[ 3409.560742] [drm:drm_mode_setcrtc], [CRTC:5]
>[ 3409.560744] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3409.560745] [drm:intel_crtc_set_config], [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[ 3409.560747] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3409.560748] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3409.560750] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:5]
>[ 3409.560751] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3409.560752] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 3409.560754] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3409.560755] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 28320KHz
>[ 3409.560759] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 24
>[ 3409.560760] [drm:intel_dp_compute_config], DP link bw required 67968 available 129600
>[ 3409.560762] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe B, lanes 1
>[ 3409.560763] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3409.560764] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[ 3409.560765] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3409.560766] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3409.560767] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3409.560769] [drm:intel_dump_pipe_config], requested mode:
>[ 3409.560769] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3409.560772] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3409.560772] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3409.560774] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3409.560775] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3409.560776] [drm:intel_dump_pipe_config], ips: 0
>[ 3409.560785] [drm:intel_get_shared_dpll], CRTC:5 allocated PCH DPLL A
>[ 3409.560786] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe B
>[ 3409.560787] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3409.561109] [drm:cpt_enable_fdi_bc_bifurcation], enabling fdi C rx
>[ 3409.561844] [drm:ironlake_update_plane], Writing base 0A5A5000 00000000 0 0 2880
>[ 3409.561846] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:720x400]
>[ 3409.561851] [drm:intel_dp_mode_set], Enabling DP audio on pipe B
>[ 3409.561853] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3409.561854] [drm:ironlake_write_eld], ELD on pipe B
>[ 3409.561856] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3409.561857] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3409.561870] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 42, cursor: 6
>[ 3409.561871] [drm:ironlake_check_srwm], watermark 1: display plane 6, fbc lines 3, cursor 6
>[ 3409.561873] [drm:ironlake_check_srwm], watermark 2: display plane 17, fbc lines 3, cursor 6
>[ 3409.561875] [drm:ironlake_check_srwm], watermark 3: display plane 31, fbc lines 3, cursor 6
>[ 3409.561876] [drm:ironlake_check_srwm], watermark 3: display plane 59, fbc lines 4, cursor 10
>[ 3409.614187] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3409.666140] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3409.666302] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3409.666961] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3409.666963] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3409.667621] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3409.667624] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3409.667624] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3409.667625] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 5
>[ 3409.667627] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3409.669240] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3409.669825] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3409.669827] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3409.670723] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3409.685127] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3409.685133] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3409.685135] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3409.685138] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3409.685141] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3409.685143] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3409.685146] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3409.685150] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3409.685152] [drm:check_crtc_state], [CRTC:3]
>[ 3409.685153] [drm:check_crtc_state], [CRTC:5]
>[ 3409.685162] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 4, found 0)
>[ 3409.685163] ------------[ cut here ]------------
>[ 3409.685174] WARNING: at drivers/gpu/drm/i915/intel_display.c:8281 check_crtc_state+0x604/0x64b [i915]()
>[ 3409.685175] pipe state doesn't match!
>[ 3409.685175] Modules linked in: dm_mod acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi snd_hda_codec_realtek iTCO_wdt microcode iTCO_vendor_support pcspkr i2c_i801 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc lpc_ich mfd_core snd_timer snd soundcore ppdev parport_pc parport wmi i915 video button drm_kms_helper drm mperf freq_table
>[ 3409.685188] CPU: 1 PID: 10899 Comm: kms_render Tainted: G        W    3.10.0-rc2_drm-intel-next-queued_854c94_20130619_+ #4227
>[ 3409.685189] Hardware name:                  /DH77EB, BIOS EBH7710H.86A.0062.2012.0329.1914 03/29/2012
>[ 3409.685190]  ffffffff816de142 0000000000000000 ffffffff8102c67d ffff8802104af8a0
>[ 3409.685192]  ffff8802104af8a8 0000000000000001 ffff88021598e000 ffff8802112aa000
>[ 3409.685194]  ffff8802104af918 ffff88021598e6c8 ffffffff8102c72d ffffffffa00c1e75
>[ 3409.685195] Call Trace:
>[ 3409.685200]  [<ffffffff816de142>] ? dump_stack+0xd/0x17
>[ 3409.685203]  [<ffffffff8102c67d>] ? warn_slowpath_common+0x5f/0x77
>[ 3409.685205]  [<ffffffff8102c72d>] ? warn_slowpath_fmt+0x45/0x4a
>[ 3409.685210]  [<ffffffffa00807b3>] ? check_crtc_state+0x604/0x64b [i915]
>[ 3409.685217]  [<ffffffffa0089776>] ? intel_modeset_check_state+0x36f/0x5e8 [i915]
>[ 3409.685222]  [<ffffffffa0089a5f>] ? intel_set_mode+0x1d/0x27 [i915]
>[ 3409.685227]  [<ffffffffa0089fec>] ? intel_crtc_set_config+0x583/0x73b [i915]
>[ 3409.685232]  [<ffffffffa0013cc1>] ? drm_mode_set_config_internal+0x19/0x40 [drm]
>[ 3409.685236]  [<ffffffffa0015925>] ? drm_mode_setcrtc+0x437/0x4e8 [drm]
>[ 3409.685241]  [<ffffffffa008a580>] ? intel_framebuffer_create+0x7e/0xcc [i915]
>[ 3409.685243]  [<ffffffff816e0d38>] ? mutex_lock+0xd/0x2d
>[ 3409.685246]  [<ffffffffa000946c>] ? drm_ioctl+0x290/0x3b5 [drm]
>[ 3409.685249]  [<ffffffff810b00bc>] ? handle_pte_fault+0x231/0x6b0
>[ 3409.685253]  [<ffffffffa00154ee>] ? drm_mode_setplane+0x30f/0x30f [drm]
>[ 3409.685255]  [<ffffffff810c97a9>] ? kmem_cache_free+0xe2/0xe6
>[ 3409.685258]  [<ffffffff810dc342>] ? vfs_ioctl+0x1e/0x31
>[ 3409.685259]  [<ffffffff810dcb71>] ? do_vfs_ioctl+0x3e9/0x42b
>[ 3409.685261]  [<ffffffff810d02ce>] ? __fput+0x1af/0x1d6
>[ 3409.685263]  [<ffffffff810e56a3>] ? mnt_get_count+0x35/0x45
>[ 3409.685265]  [<ffffffff810e5712>] ? mntput_no_expire+0x5f/0x12b
>[ 3409.685267]  [<ffffffff8104a5e6>] ? lg_global_unlock+0x30/0x3a
>[ 3409.685269]  [<ffffffff810dcc01>] ? SyS_ioctl+0x4e/0x7d
>[ 3409.685271]  [<ffffffff816e7e12>] ? system_call_fastpath+0x16/0x1b
>[ 3409.685272] ---[ end trace 7d7c1054f0a165ea ]---
>[ 3409.685273] [drm:intel_dump_pipe_config], [CRTC:5][hw state] config for pipe B
>[ 3409.685274] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3409.685275] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0
>[ 3409.685276] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3409.685277] [drm:intel_dump_pipe_config], requested mode:
>[ 3409.685278] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 720 0 0 0 400 0 0 0 0x0 0x0
>[ 3409.685280] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3409.685281] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
>[ 3409.685282] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3409.685284] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3409.685285] [drm:intel_dump_pipe_config], ips: 0
>[ 3409.685286] [drm:intel_dump_pipe_config], [CRTC:5][sw state] config for pipe B
>[ 3409.685287] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[ 3409.685287] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3409.685288] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 1, gmch_m: 1319807, gmch_n: 4194304, link_m: 54991, link_n: 524288, tu: 64
>[ 3409.685290] [drm:intel_dump_pipe_config], requested mode:
>[ 3409.685291] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3409.685292] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3409.685293] [drm:drm_mode_debug_printmodeline], Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3409.685295] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3409.685296] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3409.685297] [drm:intel_dump_pipe_config], ips: 0
>[ 3409.685298] [drm:check_crtc_state], [CRTC:7]
>[ 3409.685299] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3409.685305] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3416.691423] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3416.691428] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [NOCRTC]
>[ 3416.691429] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3416.691431] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3416.691432] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[ 3416.691613] [drm:intel_dp_link_down], 
>[ 3416.742240] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 5
>[ 3416.742258] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 3416.742679] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3416.742686] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3416.742689] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3416.742692] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3416.742694] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3416.742697] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3416.742700] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3416.742702] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3416.742705] [drm:check_crtc_state], [CRTC:3]
>[ 3416.742706] [drm:check_crtc_state], [CRTC:5]
>[ 3416.742707] [drm:check_crtc_state], [CRTC:7]
>[ 3416.742708] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3416.742712] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3416.742720] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[7] ENCODERS[7]
>[ 3416.742723] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[7] ENCODERS[7]
>[ 3416.742726] [drm:drm_mode_getconnector], [CONNECTOR:22:?]
>[ 3416.742727] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:22:DP-2]
>[ 3416.743023] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[ 3416.743715] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.762965] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.782179] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.782180] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[ 3416.782865] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.802087] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.821308] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 3416.821323] [drm:drm_edid_to_eld], ELD monitor DELL U3011
>[ 3416.821324] [drm:drm_edid_to_eld], ELD size 9, SAD count 1
>[ 3416.821338] [drm:drm_mode_debug_printmodeline], Modeline 83:"1440x576i" 0 27000 1440 1464 1590 1728 576 580 586 625 0x40 0x101a
>[ 3416.821340] [drm:drm_mode_prune_invalid], Not using 1440x576i mode 3
>[ 3416.821341] [drm:drm_mode_debug_printmodeline], Modeline 80:"1440x480i" 0 27000 1440 1478 1602 1716 480 488 494 525 0x40 0x101a
>[ 3416.821343] [drm:drm_mode_prune_invalid], Not using 1440x480i mode 3
>[ 3416.821346] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:22:DP-2] probed modes :
>[ 3416.821347] [drm:drm_mode_debug_printmodeline], Modeline 26:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.821349] [drm:drm_mode_debug_printmodeline], Modeline 36:"1920x1440" 60 234000 1920 2048 2256 2600 1440 1441 1444 1500 0x40 0x6
>[ 3416.821351] [drm:drm_mode_debug_printmodeline], Modeline 35:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[ 3416.821352] [drm:drm_mode_debug_printmodeline], Modeline 59:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 3416.821354] [drm:drm_mode_debug_printmodeline], Modeline 45:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 3416.821356] [drm:drm_mode_debug_printmodeline], Modeline 60:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 3416.821357] [drm:drm_mode_debug_printmodeline], Modeline 58:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 3416.821359] [drm:drm_mode_debug_printmodeline], Modeline 46:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 3416.821361] [drm:drm_mode_debug_printmodeline], Modeline 34:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 3416.821363] [drm:drm_mode_debug_printmodeline], Modeline 41:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 3416.821364] [drm:drm_mode_debug_printmodeline], Modeline 33:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 3416.821366] [drm:drm_mode_debug_printmodeline], Modeline 32:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[ 3416.821368] [drm:drm_mode_debug_printmodeline], Modeline 31:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 3416.821370] [drm:drm_mode_debug_printmodeline], Modeline 57:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 3416.821371] [drm:drm_mode_debug_printmodeline], Modeline 47:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 3416.821373] [drm:drm_mode_debug_printmodeline], Modeline 42:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 3416.821375] [drm:drm_mode_debug_printmodeline], Modeline 43:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 3416.821376] [drm:drm_mode_debug_printmodeline], Modeline 44:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 3416.821378] [drm:drm_mode_debug_printmodeline], Modeline 37:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 3416.821380] [drm:drm_mode_debug_printmodeline], Modeline 55:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 3416.821381] [drm:drm_mode_debug_printmodeline], Modeline 49:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 3416.821383] [drm:drm_mode_debug_printmodeline], Modeline 38:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 3416.821384] [drm:drm_mode_debug_printmodeline], Modeline 39:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3416.821386] [drm:drm_mode_debug_printmodeline], Modeline 52:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3416.821388] [drm:drm_mode_debug_printmodeline], Modeline 40:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3416.821392] [drm:drm_mode_getconnector], [CONNECTOR:22:?]
>[ 3416.821399] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[7] ENCODERS[7]
>[ 3416.821401] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[7] ENCODERS[7]
>[ 3416.821411] [drm:drm_mode_addfb2], [FB:29]
>[ 3416.821414] [drm:drm_mode_addfb2], [FB:30]
>[ 3416.821415] [drm:drm_mode_setcrtc], [CRTC:7]
>[ 3416.821417] [drm:drm_mode_setcrtc], [CONNECTOR:22:DP-2]
>[ 3416.821418] [drm:intel_crtc_set_config], [CRTC:7] [FB:29] #connectors=1 (x y) (0 0)
>[ 3416.821420] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3416.821421] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 3416.821422] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 3416.821423] [drm:drm_mode_debug_printmodeline], Modeline 48:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.821425] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3416.821427] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:7]
>[ 3416.821428] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3416.821429] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 3416.821431] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3416.821432] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[ 3416.821433] [drm:intel_dp_compute_config], DP link bw 06 lane count 4 clock 162000 bpp 18
>[ 3416.821435] [drm:intel_dp_compute_config], DP link bw required 483300 available 518400
>[ 3416.821436] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe C, lanes 3
>[ 3416.821437] [drm:ironlake_check_fdi_lanes], invalid shared fdi lane config on pipe C: 3 lanes
>[ 3416.821438] [drm:intel_modeset_pipe_config], CRTC fixup failed
>[ 3416.821440] [drm:intel_crtc_set_config] *ERROR* failed to set mode on [CRTC:7], err = -22
>[ 3416.821441] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[ 3416.821448] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3416.821455] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3416.821458] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3416.821460] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3416.821463] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3416.821465] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3416.821468] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3416.821470] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3416.821473] [drm:check_crtc_state], [CRTC:3]
>[ 3416.821474] [drm:check_crtc_state], [CRTC:5]
>[ 3416.821475] [drm:check_crtc_state], [CRTC:7]
>[ 3416.821476] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3416.821480] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3416.821529] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[ 3416.821530] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[ 3416.821530] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[ 3416.821532] [drm:drm_mode_debug_printmodeline], Modeline 48:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 3416.821533] [drm:drm_mode_debug_printmodeline], Modeline 27:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.821534] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[ 3416.821535] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3416.821535] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[ 3416.821536] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 3416.821538] [drm:connected_sink_compute_bpp], [CONNECTOR:22:DP-2] checking for sink bpp constrains
>[ 3416.821539] [drm:intel_dp_compute_config], DP link computation with max lane count 4 max bw 0a pixel clock 268500KHz
>[ 3416.821542] [drm:intel_dp_compute_config], DP link bw 0a lane count 4 clock 270000 bpp 24
>[ 3416.821542] [drm:intel_dp_compute_config], DP link bw required 644400 available 864000
>[ 3416.821543] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe A, lanes 4
>[ 3416.821544] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 3416.821545] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[ 3416.821545] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[ 3416.821546] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3416.821547] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 4, gmch_m: 6256503, gmch_n: 8388608, link_m: 521375, link_n: 524288, tu: 64
>[ 3416.821548] [drm:intel_dump_pipe_config], requested mode:
>[ 3416.821549] [drm:drm_mode_debug_printmodeline], Modeline 0:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.821550] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3416.821551] [drm:drm_mode_debug_printmodeline], Modeline 0:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.821552] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3416.821553] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3416.821553] [drm:intel_dump_pipe_config], ips: 0
>[ 3416.821560] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[ 3416.821575] [drm:intel_get_shared_dpll], CRTC:3 allocated PCH DPLL A
>[ 3416.821576] [drm:intel_get_shared_dpll], using PCH DPLL A for pipe A
>[ 3416.821576] [drm:intel_get_shared_dpll], setting up PCH DPLL A
>[ 3416.821898] [drm:ironlake_update_plane], Writing base 00073000 00000000 0 0 10240
>[ 3416.821900] [drm:intel_crtc_mode_set], [ENCODER:21:TMDS-21] set [MODE:0:2560x1600]
>[ 3416.821904] [drm:intel_dp_mode_set], Enabling DP audio on pipe A
>[ 3416.821905] [drm:intel_write_eld], ELD on [CONNECTOR:22:DP-2], [ENCODER:21:TMDS-21]
>[ 3416.821905] [drm:ironlake_write_eld], ELD on pipe A
>[ 3416.821907] [drm:ironlake_write_eld], Audio directed to unknown port
>[ 3416.821908] [drm:ironlake_write_eld], ELD: DisplayPort detected
>[ 3416.821920] [drm:ivybridge_update_wm], FIFO watermarks For pipe A - plane 13, cursor: 6
>[ 3416.821921] [drm:ironlake_check_srwm], watermark 1: display plane 36, fbc lines 3, cursor 6
>[ 3416.821922] [drm:ironlake_check_srwm], watermark 2: display plane 137, fbc lines 3, cursor 6
>[ 3416.821923] [drm:ironlake_check_srwm], watermark 3: display plane 271, fbc lines 4, cursor 10
>[ 3416.821924] [drm:ironlake_check_srwm], watermark 3: display plane 539, fbc lines 6, cursor 18
>[ 3416.821925] [drm:ironlake_check_srwm], display watermark(539) is too large(511), disabling wm3+
>[ 3416.874100] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3416.926050] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[ 3416.926211] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[ 3416.926869] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[ 3416.926871] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[ 3416.927528] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[ 3416.927529] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[ 3416.927530] [drm:ivb_manual_fdi_link_train], FDI train done.
>[ 3416.927531] [drm:ironlake_enable_shared_dpll], enable PCH DPLL A (active 0, on? 0)for crtc 3
>[ 3416.927531] [drm:ironlake_enable_shared_dpll], enabling PCH DPLL A
>[ 3416.929144] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3416.929752] [drm:intel_dp_start_link_train], clock recovery OK
>[ 3416.929753] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[ 3416.930654] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[ 3416.949030] [drm:intel_connector_check_state], [CONNECTOR:22:DP-2]
>[ 3416.949034] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 3416.949036] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 3416.949038] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 3416.949040] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 3416.949041] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 3416.949042] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 3416.949046] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 3416.949048] [drm:check_crtc_state], [CRTC:3]
>[ 3416.949056] [drm:intel_pipe_config_compare] *ERROR* mismatch in adjusted_mode.flags (expected 1, found 0)
>[ 3416.949056] ------------[ cut here ]------------
>[ 3416.949067] WARNING: at drivers/gpu/drm/i915/intel_display.c:8281 check_crtc_state+0x604/0x64b [i915]()
>[ 3416.949067] pipe state doesn't match!
>[ 3416.949075] Modules linked in: dm_mod acpi_cpufreq coretemp kvm_intel kvm snd_hda_codec_hdmi snd_hda_codec_realtek iTCO_wdt microcode iTCO_vendor_support pcspkr i2c_i801 snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_page_alloc lpc_ich mfd_core snd_timer snd soundcore ppdev parport_pc parport wmi i915 video button drm_kms_helper drm mperf freq_table
>[ 3416.949077] CPU: 1 PID: 10899 Comm: kms_render Tainted: G        W    3.10.0-rc2_drm-intel-next-queued_854c94_20130619_+ #4227
>[ 3416.949077] Hardware name:                  /DH77EB, BIOS EBH7710H.86A.0062.2012.0329.1914 03/29/2012
>[ 3416.949079]  ffffffff816de142 0000000000000000 ffffffff8102c67d ffff8802104af6d0
>[ 3416.949080]  ffff8802104af6d8 0000000000000001 ffff88021598c000 ffff8802112aa000
>[ 3416.949080]  ffff8802104af748 ffff88021598c6c8 ffffffff8102c72d ffffffffa00c1e75
>[ 3416.949081] Call Trace:
>[ 3416.949085]  [<ffffffff816de142>] ? dump_stack+0xd/0x17
>[ 3416.949088]  [<ffffffff8102c67d>] ? warn_slowpath_common+0x5f/0x77
>[ 3416.949089]  [<ffffffff8102c72d>] ? warn_slowpath_fmt+0x45/0x4a
>[ 3416.949094]  [<ffffffffa00807b3>] ? check_crtc_state+0x604/0x64b [i915]
>[ 3416.949100]  [<ffffffffa0089776>] ? intel_modeset_check_state+0x36f/0x5e8 [i915]
>[ 3416.949105]  [<ffffffffa0089a5f>] ? intel_set_mode+0x1d/0x27 [i915]
>[ 3416.949109]  [<ffffffffa0089fec>] ? intel_crtc_set_config+0x583/0x73b [i915]
>[ 3416.949114]  [<ffffffffa0013cc1>] ? drm_mode_set_config_internal+0x19/0x40 [drm]
>[ 3416.949116]  [<ffffffffa004ab8a>] ? drm_fb_helper_set_par+0x54/0x9a [drm_kms_helper]
>[ 3416.949118]  [<ffffffffa004ab36>] ? drm_fb_helper_initial_config+0x459/0x459 [drm_kms_helper]
>[ 3416.949120]  [<ffffffff812dc38e>] ? fb_set_var+0x246/0x32c
>[ 3416.949122]  [<ffffffff811857ff>] ? __ext4_journal_stop+0x61/0x79
>[ 3416.949124]  [<ffffffff8116f4e6>] ? ext4_da_write_end+0x1ad/0x1c9
>[ 3416.949126]  [<ffffffff812e6315>] ? fbcon_blank+0x71/0x230
>[ 3416.949128]  [<ffffffff810d28b5>] ? chrdev_open+0x11c/0x143
>[ 3416.949130]  [<ffffffff81333a8a>] ? do_unblank_screen+0xed/0x166
>[ 3416.949131]  [<ffffffff8132bcf3>] ? vt_ioctl+0x4be/0x1027
>[ 3416.949133]  [<ffffffff813244c2>] ? tty_ioctl+0x910/0x97f
>[ 3416.949135]  [<ffffffff81002362>] ? do_signal+0x3b4/0x46e
>[ 3416.949136]  [<ffffffff810dc342>] ? vfs_ioctl+0x1e/0x31
>[ 3416.949137]  [<ffffffff810dcb71>] ? do_vfs_ioctl+0x3e9/0x42b
>[ 3416.949138]  [<ffffffff810dcc01>] ? SyS_ioctl+0x4e/0x7d
>[ 3416.949140]  [<ffffffff816e7e12>] ? system_call_fastpath+0x16/0x1b
>[ 3416.949141] ---[ end trace 7d7c1054f0a165eb ]---
>[ 3416.949141] [drm:intel_dump_pipe_config], [CRTC:3][hw state] config for pipe A
>[ 3416.949142] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[ 3416.949143] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0
>[ 3416.949144] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 4, gmch_m: 6256503, gmch_n: 8388608, link_m: 521375, link_n: 524288, tu: 64
>[ 3416.949145] [drm:intel_dump_pipe_config], requested mode:
>[ 3416.949146] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 2560 0 0 0 1600 0 0 0 0x0 0x0
>[ 3416.949147] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3416.949148] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa
>[ 3416.949149] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3416.949150] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3416.949151] [drm:intel_dump_pipe_config], ips: 0
>[ 3416.949151] [drm:intel_dump_pipe_config], [CRTC:3][sw state] config for pipe A
>[ 3416.949152] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[ 3416.949153] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
>[ 3416.949154] [drm:intel_dump_pipe_config], fdi/pch: 1, lanes: 4, gmch_m: 6256503, gmch_n: 8388608, link_m: 521375, link_n: 524288, tu: 64
>[ 3416.949154] [drm:intel_dump_pipe_config], requested mode:
>[ 3416.949156] [drm:drm_mode_debug_printmodeline], Modeline 0:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.949156] [drm:intel_dump_pipe_config], adjusted mode:
>[ 3416.949158] [drm:drm_mode_debug_printmodeline], Modeline 0:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x48 0x9
>[ 3416.949158] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 3416.949159] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[ 3416.949160] [drm:intel_dump_pipe_config], ips: 0
>[ 3416.949160] [drm:check_crtc_state], [CRTC:5]
>[ 3416.949161] [drm:check_crtc_state], [CRTC:7]
>[ 3416.949162] [drm:check_shared_dpll_state], PCH DPLL A
>[ 3416.949167] [drm:check_shared_dpll_state], PCH DPLL B
>[ 3416.949171] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3416.949173] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3416.949174] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 3416.949175] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3416.949176] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[ 3416.949177] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3416.949185] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[ 3416.949186] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3416.960469] [drm:i915_driver_open], 
>[ 3416.960475] [drm:i915_driver_open], 
>[ 3417.135339] [drm:intel_crtc_set_config], [CRTC:3] [FB:28] #connectors=1 (x y) (0 0)
>[ 3417.135345] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3417.135347] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 3417.135349] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 3417.135350] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 3417.135351] [drm:intel_modeset_stage_output_state], [CONNECTOR:22:DP-2] to [CRTC:3]
>[ 4017.300079] [drm:intel_dp_link_down], 
>[ 4017.362821] [drm:intel_disable_shared_dpll], disable PCH DPLL A (active 1, on? 1) for crtc 3
>[ 4017.362825] [drm:intel_disable_shared_dpll], disabling PCH DPLL A
>[ 4017.363251] [drm:check_encoder_state], [ENCODER:10:DAC-10]
>[ 4017.363254] [drm:check_encoder_state], [ENCODER:11:TMDS-11]
>[ 4017.363256] [drm:check_encoder_state], [ENCODER:15:TMDS-15]
>[ 4017.363258] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
>[ 4017.363260] [drm:check_encoder_state], [ENCODER:19:TMDS-19]
>[ 4017.363262] [drm:check_encoder_state], [ENCODER:21:TMDS-21]
>[ 4017.363263] [drm:check_encoder_state], [ENCODER:23:TMDS-23]
>[ 4017.363265] [drm:check_crtc_state], [CRTC:3]
>[ 4017.363268] [drm:check_crtc_state], [CRTC:5]
>[ 4017.363269] [drm:check_crtc_state], [CRTC:7]
>[ 4017.363270] [drm:check_shared_dpll_state], PCH DPLL A
>[ 4017.363274] [drm:check_shared_dpll_state], PCH DPLL B
>[ 4018.825096] [drm:i915_hotplug_work_func], running encoder hotplug functions
>[ 4018.825100] [drm:i915_hotplug_work_func], Connector HDMI-A-2 (pin 5) received hotplug event.
>[ 4018.825103] [drm:i915_hotplug_work_func], Connector DP-2 (pin 5) received hotplug event.
>[ 4018.825318] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[ 4018.825322] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[ 4018.825333] [drm:intel_hpd_irq_event], [CONNECTOR:18:HDMI-A-2] status updated from 2 to 2
>[ 4018.825628] [drm:intel_dp_get_dpcd], DPCD: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00
>[ 4018.826311] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 4018.845502] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 4018.864691] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return 2
>[ 4018.864692] [drm:drm_detect_monitor_audio], Monitor has basic audio support
>[ 4018.864694] [drm:intel_hpd_irq_event], [CONNECTOR:22:DP-2] status updated from 1 to 1

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Attachments on bug 66000: 81152 | 81153

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