Attachment 81305 Details for Bug 66111 – dmesg

dmesg

dmesg_ivb4_0624.txt (text/plain), 30.09 KB, created by lu hua on 2013-06-24 07:40:53 UTC

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Creator: lu hua

Created: 2013-06-24 07:40:53 UTC

Size: 30.09 KB

patch

obsolete

>[  198.913508] [drm:i915_driver_open], 
>[  198.913523] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
>[  198.913527] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  198.913529] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  198.913531] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  198.913533] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  198.913535] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  198.913541] [drm:i915_driver_open], 
>[  198.913575] [drm:i915_getparam], Unknown parameter 22
>[  198.913954] [drm:i915_getparam], Unknown parameter 22
>[  198.913982] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.913989] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.913999] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.914001] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.914005] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  198.914007] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
>[  198.914011] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x83f40018, result 1
>[  198.914013] [drm:intel_crt_detect], CRT detected via hotplug
>[  198.926764] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  198.926779] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
>[  198.926781] [drm:drm_mode_debug_printmodeline], Modeline 24:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  198.926784] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  198.926787] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6
>[  198.926789] [drm:drm_mode_debug_printmodeline], Modeline 28:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  198.926792] [drm:drm_mode_debug_printmodeline], Modeline 27:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  198.926795] [drm:drm_mode_debug_printmodeline], Modeline 29:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  198.926797] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  198.926800] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  198.926802] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  198.926805] [drm:drm_mode_debug_printmodeline], Modeline 59:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  198.926808] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  198.926810] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  198.926813] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  198.926815] [drm:drm_mode_debug_printmodeline], Modeline 42:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  198.926818] [drm:drm_mode_debug_printmodeline], Modeline 44:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  198.926820] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  198.926823] [drm:drm_mode_debug_printmodeline], Modeline 31:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  198.926826] [drm:drm_mode_debug_printmodeline], Modeline 32:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  198.926828] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  198.926831] [drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  198.926833] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  198.926836] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  198.926838] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  198.926845] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  198.926859] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.926862] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  198.926885] [drm:drm_mode_addfb], [FB:45]
>[  198.926888] [drm:drm_mode_addfb], [FB:46]
>[  198.926893] [drm:drm_mode_addfb], [FB:47]
>[  199.980574] [drm:drm_mode_setcrtc], [CRTC:3]
>[  199.980582] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
>[  199.980585] [drm:intel_crtc_set_config], [CRTC:3] [FB:45] #connectors=1 (x y) (0 0)
>[  199.980589] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  199.980590] [drm:drm_mode_debug_printmodeline], Modeline 23:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  199.980594] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  199.980598] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  199.980600] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  199.980601] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  199.980605] [drm:intel_modeset_pipe_config], [CRTC:3]
>[  199.980607] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[  199.980609] [drm:__intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  200.018499] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  200.018503] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  200.018921] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[  200.018953] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  200.018955] [drm:drm_mode_debug_printmodeline], Modeline 0:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  200.018958] [drm:intel_get_pch_pll], CRTC:3 reusing existing PCH PLL c6014
>[  200.018959] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  200.019271] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 3
>[  200.070551] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.073811] [drm:ironlake_update_plane], Writing base 00374000 00000000 0 0 8192
>[  200.125595] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.125612] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:0:2048x1152]
>[  200.125617] [drm:ivybridge_update_wm], FIFO watermarks For pipe A - plane 10, cursor: 6
>[  200.125619] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  200.125622] [drm:ironlake_check_srwm], watermark 2: display plane 89, fbc lines 3, cursor 6
>[  200.125623] [drm:ironlake_check_srwm], watermark 3: display plane 187, fbc lines 4, cursor 10
>[  200.125625] [drm:ironlake_check_srwm], watermark 3: display plane 372, fbc lines 5, cursor 14
>[  200.177650] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.229718] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  200.229878] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[  200.230536] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  200.230539] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[  200.231196] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  200.231199] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[  200.231201] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  200.231202] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  200.231206] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  200.250740] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
>[  200.250749] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  200.250753] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  200.250756] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  200.250759] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  200.250762] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  200.250765] [drm:intel_modeset_check_state], [CRTC:3]
>[  200.250769] [drm:intel_modeset_check_state], [CRTC:5]
>[  200.250770] [drm:intel_modeset_check_state], [CRTC:7]
>[  205.284375] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  205.284380] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [NOCRTC]
>[  205.284382] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  205.284383] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  205.284385] [drm:__intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  205.336055] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 3
>[  205.336059] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  205.336477] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[  205.336485] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  205.336489] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  205.336492] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  205.336495] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  205.336498] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  205.336501] [drm:intel_modeset_check_state], [CRTC:3]
>[  205.336503] [drm:intel_modeset_check_state], [CRTC:5]
>[  205.336504] [drm:intel_modeset_check_state], [CRTC:7]
>[  205.336519] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  205.336523] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  205.336527] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  205.336529] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
>[  205.336534] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x3f40010, result 1
>[  205.336536] [drm:intel_crt_detect], CRT detected via hotplug
>[  205.349398] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  205.349415] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
>[  205.349417] [drm:drm_mode_debug_printmodeline], Modeline 24:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  205.349420] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  205.349423] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6
>[  205.349425] [drm:drm_mode_debug_printmodeline], Modeline 28:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  205.349428] [drm:drm_mode_debug_printmodeline], Modeline 27:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  205.349431] [drm:drm_mode_debug_printmodeline], Modeline 29:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  205.349434] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  205.349436] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  205.349439] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  205.349441] [drm:drm_mode_debug_printmodeline], Modeline 59:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  205.349444] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  205.349447] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  205.349449] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  205.349452] [drm:drm_mode_debug_printmodeline], Modeline 42:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  205.349454] [drm:drm_mode_debug_printmodeline], Modeline 44:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  205.349457] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  205.349459] [drm:drm_mode_debug_printmodeline], Modeline 31:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  205.349462] [drm:drm_mode_debug_printmodeline], Modeline 32:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  205.349464] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  205.349467] [drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  205.349469] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  205.349472] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  205.349474] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  205.349482] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  205.349492] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  205.349495] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  205.349522] [drm:drm_mode_addfb], [FB:45]
>[  205.349526] [drm:drm_mode_addfb], [FB:46]
>[  205.349529] [drm:drm_mode_addfb], [FB:47]
>[  205.395421] [drm:drm_mode_setcrtc], [CRTC:5]
>[  205.395428] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
>[  205.395430] [drm:intel_crtc_set_config], [CRTC:5] [FB:45] #connectors=1 (x y) (0 0)
>[  205.395434] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  205.395435] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  205.395437] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  205.395440] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  205.395443] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  205.395445] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:5]
>[  205.395447] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  205.395448] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  205.395450] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  205.395454] [drm:intel_modeset_pipe_config], [CRTC:5]
>[  205.395455] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[  205.395457] [drm:__intel_set_mode], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  205.395491] [drm:ironlake_crtc_mode_set], Mode for pipe 1:
>[  205.395492] [drm:drm_mode_debug_printmodeline], Modeline 0:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  205.395495] [drm:intel_get_pch_pll], CRTC:5 allocated PCH PLL c6014
>[  205.395497] [drm:intel_get_pch_pll], using pll 0 for pipe 1
>[  205.395498] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  205.395810] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 1, lanes 3
>[  205.447170] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  205.450571] [drm:ironlake_update_plane], Writing base 02574000 00000000 0 0 8192
>[  205.450577] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:0:2048x1152]
>[  205.450582] [drm:ivybridge_update_wm], FIFO watermarks For pipe B - plane 10, cursor: 6
>[  205.450584] [drm:ironlake_check_srwm], watermark 1: display plane 15, fbc lines 3, cursor 6
>[  205.450586] [drm:ironlake_check_srwm], watermark 2: display plane 89, fbc lines 3, cursor 6
>[  205.450588] [drm:ironlake_check_srwm], watermark 3: display plane 187, fbc lines 4, cursor 10
>[  205.450590] [drm:ironlake_check_srwm], watermark 3: display plane 372, fbc lines 5, cursor 14
>[  205.502214] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  205.554268] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  205.554439] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[  205.555097] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  205.555100] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[  205.555759] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  205.555762] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[  205.555764] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  205.555765] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 5
>[  205.555769] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  205.575308] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
>[  205.575316] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  205.575320] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  205.575323] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  205.575326] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  205.575329] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  205.575332] [drm:intel_modeset_check_state], [CRTC:3]
>[  205.575334] [drm:intel_modeset_check_state], [CRTC:5]
>[  205.575337] [drm:intel_modeset_check_state], [CRTC:7]
>[  210.642401] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  210.642406] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [NOCRTC]
>[  210.642408] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  210.642410] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  210.642411] [drm:__intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  210.693658] [drm:intel_disable_pch_pll], disable PCH PLL c6014 (active 1, on? 1) for crtc 5
>[  210.693662] [drm:intel_disable_pch_pll], disabling PCH PLL c6014
>[  210.694078] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[  210.694087] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  210.694091] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  210.694094] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  210.694097] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  210.694100] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  210.694103] [drm:intel_modeset_check_state], [CRTC:3]
>[  210.694104] [drm:intel_modeset_check_state], [CRTC:5]
>[  210.694106] [drm:intel_modeset_check_state], [CRTC:7]
>[  210.694120] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  210.694124] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  210.694127] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  210.694129] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
>[  210.694134] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x23f40010, result 1
>[  210.694136] [drm:intel_crt_detect], CRT detected via hotplug
>[  210.706994] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  210.707010] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
>[  210.707012] [drm:drm_mode_debug_printmodeline], Modeline 24:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  210.707016] [drm:drm_mode_debug_printmodeline], Modeline 25:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  210.707019] [drm:drm_mode_debug_printmodeline], Modeline 26:"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x0 0x6
>[  210.707021] [drm:drm_mode_debug_printmodeline], Modeline 28:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  210.707024] [drm:drm_mode_debug_printmodeline], Modeline 27:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  210.707026] [drm:drm_mode_debug_printmodeline], Modeline 29:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  210.707029] [drm:drm_mode_debug_printmodeline], Modeline 52:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  210.707032] [drm:drm_mode_debug_printmodeline], Modeline 38:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  210.707035] [drm:drm_mode_debug_printmodeline], Modeline 30:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  210.707037] [drm:drm_mode_debug_printmodeline], Modeline 59:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  210.707040] [drm:drm_mode_debug_printmodeline], Modeline 39:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  210.707042] [drm:drm_mode_debug_printmodeline], Modeline 40:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  210.707045] [drm:drm_mode_debug_printmodeline], Modeline 41:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  210.707048] [drm:drm_mode_debug_printmodeline], Modeline 42:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  210.707050] [drm:drm_mode_debug_printmodeline], Modeline 44:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  210.707053] [drm:drm_mode_debug_printmodeline], Modeline 43:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  210.707055] [drm:drm_mode_debug_printmodeline], Modeline 31:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  210.707058] [drm:drm_mode_debug_printmodeline], Modeline 32:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  210.707060] [drm:drm_mode_debug_printmodeline], Modeline 34:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  210.707063] [drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  210.707065] [drm:drm_mode_debug_printmodeline], Modeline 35:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  210.707068] [drm:drm_mode_debug_printmodeline], Modeline 36:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  210.707070] [drm:drm_mode_debug_printmodeline], Modeline 37:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  210.707078] [drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[  210.707088] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  210.707091] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  210.707118] [drm:drm_mode_addfb], [FB:45]
>[  210.707128] [drm:drm_mode_addfb], [FB:46]
>[  210.707132] [drm:drm_mode_addfb], [FB:47]
>[  210.752992] [drm:drm_mode_setcrtc], [CRTC:7]
>[  210.753000] [drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
>[  210.753002] [drm:intel_crtc_set_config], [CRTC:7] [FB:45] #connectors=1 (x y) (0 0)
>[  210.753005] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  210.753007] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  210.753008] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  210.753011] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  210.753014] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  210.753016] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:7]
>[  210.753018] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  210.753020] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  210.753021] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  210.753025] [drm:intel_modeset_pipe_config], [CRTC:7]
>[  210.753027] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[  210.753028] [drm:__intel_set_mode], set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  210.753062] [drm:ironlake_crtc_mode_set], Mode for pipe 2:
>[  210.753064] [drm:drm_mode_debug_printmodeline], Modeline 0:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  210.753067] [drm:intel_get_pch_pll], CRTC:7 allocated PCH PLL c6014
>[  210.753068] [drm:intel_get_pch_pll], using pll 0 for pipe 2
>[  210.753070] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  210.753382] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 2, lanes 3
>[  210.753383] [drm:ironlake_check_fdi_lanes], invalid shared fdi lane config on pipe 2: 3 lanes
>[  210.804754] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  210.808167] [drm:ironlake_update_plane], Writing base 04774000 00000000 0 0 8192
>[  210.808174] [drm:intel_crtc_set_config] *ERROR* failed to set mode on [CRTC:7], err = -22
>[  210.808177] [drm:__intel_set_mode], set mode pipe masks: modeset: 0, prepare: 0, disable: 4
>[  210.808184] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[  210.808193] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  210.808196] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  210.808199] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  210.808202] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  210.808205] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  210.808208] [drm:intel_modeset_check_state], [CRTC:3]
>[  210.808209] [drm:intel_modeset_check_state], [CRTC:5]
>[  210.808211] [drm:intel_modeset_check_state], [CRTC:7]
>[  210.808281] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
>[  210.808282] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  210.808283] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  210.808286] [drm:drm_mode_debug_printmodeline], Modeline 48:"2048x1152" 60 197000 2048 2184 2400 2752 1152 1155 1160 1195 0x48 0x6
>[  210.808288] [drm:drm_mode_debug_printmodeline], Modeline 23:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  210.808289] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  210.808291] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.808292] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  210.808292] [drm:intel_crtc_set_config], attempting to set mode from userspace
>[  210.808295] [drm:drm_mode_debug_printmodeline], Modeline 23:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  210.808296] [drm:intel_modeset_pipe_config], [CRTC:3]
>[  210.808297] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
>[  210.808299] [drm:__intel_set_mode], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  210.808303] [drm:ivb_modeset_global_resources], disabling fdi C rx
>[  210.808315] [drm:ironlake_crtc_mode_set], Mode for pipe 0:
>[  210.808317] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  210.808319] [drm:intel_get_pch_pll], CRTC:3 allocated PCH PLL c6014
>[  210.808319] [drm:intel_get_pch_pll], using pll 0 for pipe 0
>[  210.808320] [drm:intel_get_pch_pll], switching PLL c6014 off
>[  210.808632] [drm:ironlake_check_fdi_lanes], checking fdi config on pipe 0, lanes 1
>[  210.859826] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  210.859830] [drm:ironlake_update_plane], Writing base 00073000 00000000 0 0 4096
>[  210.859833] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:0:1024x768]
>[  210.859837] [drm:ivybridge_update_wm], FIFO watermarks For pipe A - plane 5, cursor: 6
>[  210.859838] [drm:ironlake_check_srwm], watermark 1: display plane 7, fbc lines 3, cursor 6
>[  210.859840] [drm:ironlake_check_srwm], watermark 2: display plane 37, fbc lines 3, cursor 6
>[  210.859841] [drm:ironlake_check_srwm], watermark 3: display plane 66, fbc lines 4, cursor 6
>[  210.859843] [drm:ironlake_check_srwm], watermark 3: display plane 130, fbc lines 5, cursor 10
>[  210.911881] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  210.963935] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  210.964093] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR before link train 0x0
>[  210.964749] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x100
>[  210.964752] [drm:ivb_manual_fdi_link_train], FDI train 1 done, level 0.
>[  210.965410] [drm:ivb_manual_fdi_link_train], FDI_RX_IIR 0x600
>[  210.965412] [drm:ivb_manual_fdi_link_train], FDI train 2 done, level 0.
>[  210.965413] [drm:ivb_manual_fdi_link_train], FDI train done.
>[  210.965414] [drm:ironlake_enable_pch_pll], enable PCH PLL c6014 (active 0, on? 0)for crtc 3
>[  210.965417] [drm:ironlake_enable_pch_pll], enabling PCH PLL c6014
>[  210.980953] [drm:intel_connector_check_state], [CONNECTOR:9:VGA-1]
>[  210.980959] [drm:intel_modeset_check_state], [ENCODER:10:DAC-10]
>[  210.980962] [drm:intel_modeset_check_state], [ENCODER:11:TMDS-11]
>[  210.980965] [drm:intel_modeset_check_state], [ENCODER:15:TMDS-15]
>[  210.980967] [drm:intel_modeset_check_state], [ENCODER:17:TMDS-17]
>[  210.980970] [drm:intel_modeset_check_state], [ENCODER:19:TMDS-19]
>[  210.980972] [drm:intel_modeset_check_state], [CRTC:3]
>[  210.980975] [drm:intel_modeset_check_state], [CRTC:5]
>[  210.980976] [drm:intel_modeset_check_state], [CRTC:7]
>[  210.980978] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  210.980980] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.980981] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  210.980983] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.980985] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
>[  210.980987] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.980997] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
>[  210.980998] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.984079] [drm:i915_driver_open], 
>[  210.984089] [drm:i915_driver_open], 
>[  210.984119] [drm:i915_getparam], Unknown parameter 22
>[  210.995096] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
>[  210.995103] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.995106] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  210.995108] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[  210.995110] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[  210.995112] [drm:intel_modeset_stage_output_state], [CONNECTOR:9:VGA-1] to [CRTC:3]

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Attachments on bug 66111: 81305 | 81381 | 81436

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