Attachment 81945 Details for Bug 66519 – Debugging patch

[patch] Debugging patch

cp_int_debug.patch (text/plain), 2.16 KB, created by Christian König on 2013-07-03 08:29:55 UTC

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Creator: Christian König

Created: 2013-07-03 08:29:55 UTC

Size: 2.16 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
>index 0de5b74..276ee55 100644
>--- a/drivers/gpu/drm/radeon/evergreen.c
>+++ b/drivers/gpu/drm/radeon/evergreen.c
>@@ -4885,11 +4885,11 @@ restart_ih:
> 		case 176: /* CP_INT in ring buffer */
> 		case 177: /* CP_INT in IB1 */
> 		case 178: /* CP_INT in IB2 */
>-			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
>+			DRM_ERROR("IH: CP int: 0x%08x\n", src_data);
> 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
> 			break;
> 		case 181: /* CP EOP event */
>-			DRM_DEBUG("IH: CP EOP\n");
>+			DRM_ERROR("IH: CP EOP\n");
> 			if (rdev->family >= CHIP_CAYMAN) {
> 				switch (src_data) {
> 				case 0:
>diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
>index 2d3655f..0aeaefc 100644
>--- a/drivers/gpu/drm/radeon/r600.c
>+++ b/drivers/gpu/drm/radeon/r600.c
>@@ -4525,11 +4525,11 @@ restart_ih:
> 		case 176: /* CP_INT in ring buffer */
> 		case 177: /* CP_INT in IB1 */
> 		case 178: /* CP_INT in IB2 */
>-			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
>+			DRM_ERROR("IH: CP int: 0x%08x\n", src_data);
> 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
> 			break;
> 		case 181: /* CP EOP event */
>-			DRM_DEBUG("IH: CP EOP\n");
>+			DRM_ERROR("IH: CP EOP\n");
> 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
> 			break;
> 		case 224: /* DMA trap event */
>diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
>index 2349067..5b1e722 100644
>--- a/drivers/gpu/drm/radeon/si.c
>+++ b/drivers/gpu/drm/radeon/si.c
>@@ -6010,16 +6010,19 @@ restart_ih:
> 			WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
> 			break;
> 		case 176: /* RINGID0 CP_INT */
>+			DRM_ERROR("IH: CP 0\n");
> 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
> 			break;
> 		case 177: /* RINGID1 CP_INT */
>+			DRM_ERROR("IH: CP 1\n");
> 			radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
> 			break;
> 		case 178: /* RINGID2 CP_INT */
>+			DRM_ERROR("IH: CP 2\n");
> 			radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
> 			break;
> 		case 181: /* CP EOP event */
>-			DRM_DEBUG("IH: CP EOP\n");
>+			DRM_ERROR("IH: CP EOP\n");
> 			switch (ring_id) {
> 			case 0:
> 				radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);

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Attachments on bug 66519: 81905 | 81907 | 81908 | 81945 | 81952

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