Attachment 82095 Details for Bug 66516 – i8xx dvo pll fixes

[patch] i8xx dvo pll fixes

0001-i8xx-dvo-dpll-fixes.patch (text/plain), 4.76 KB, created by Daniel Vetter on 2013-07-05 21:23:21 UTC

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Creator: Daniel Vetter

Created: 2013-07-05 21:23:21 UTC

Size: 4.76 KB

patch

obsolete

>From 0810a680581dd56f3e08167e9acfe245081c1f7a Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Fri, 5 Jul 2013 23:20:05 +0200
>Subject: [PATCH] i8xx dvo dpll fixes
>
>- For oddball reasons the dvo_mode_set function frobbed bit 30 for us,
>  and I've missed this. Fix it up. Also bikeshed the #defines a bit,
>  on gen2 is DVO_2X mode on gen3+ it's serial dvo high speed mode.
>
>- Apparently for DVO we _must_ have a p2 divisor of 4. Add new limits
>  for that case.
>---
> drivers/gpu/drm/i915/i915_reg.h      |    3 ++-
> drivers/gpu/drm/i915/intel_display.c |   30 ++++++++++++++++++++++++------
> drivers/gpu/drm/i915/intel_dvo.c     |    3 ---
> 3 files changed, 26 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 9b51be8..a8bcd36 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -1126,7 +1126,8 @@
> #define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
> #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
> #define   DPLL_VCO_ENABLE		(1 << 31)
>-#define   DPLL_DVO_HIGH_SPEED		(1 << 30)
>+#define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
>+#define   DPLL_DVO_2X			(1 << 30)
> #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
> #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
> #define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 8776312..ce6b9b1 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -89,7 +89,7 @@ intel_fdi_link_freq(struct drm_device *dev)
> 		return 27;
> }
> 
>-static const intel_limit_t intel_limits_i8xx_dvo = {
>+static const intel_limit_t intel_limits_i8xx_dac = {
> 	.dot = { .min = 25000, .max = 350000 },
> 	.vco = { .min = 930000, .max = 1400000 },
> 	.n = { .min = 3, .max = 16 },
>@@ -102,6 +102,19 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
> 		.p2_slow = 4, .p2_fast = 2 },
> };
> 
>+static const intel_limit_t intel_limits_i8xx_dvo = {
>+	.dot = { .min = 25000, .max = 350000 },
>+	.vco = { .min = 930000, .max = 1400000 },
>+	.n = { .min = 3, .max = 16 },
>+	.m = { .min = 96, .max = 140 },
>+	.m1 = { .min = 18, .max = 26 },
>+	.m2 = { .min = 6, .max = 16 },
>+	.p = { .min = 4, .max = 128 },
>+	.p1 = { .min = 2, .max = 33 },
>+	.p2 = { .dot_limit = 165000,
>+		.p2_slow = 4, .p2_fast = 4 },
>+};
>+
> static const intel_limit_t intel_limits_i8xx_lvds = {
> 	.dot = { .min = 25000, .max = 350000 },
> 	.vco = { .min = 930000, .max = 1400000 },
>@@ -410,8 +423,10 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
> 	} else {
> 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> 			limit = &intel_limits_i8xx_lvds;
>-		else
>+		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
> 			limit = &intel_limits_i8xx_dvo;
>+		else
>+			limit = &intel_limits_i8xx_dac;
> 	}
> 	return limit;
> }
>@@ -4551,10 +4566,10 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
> 	}
> 
> 	if (is_sdvo)
>-		dpll |= DPLL_DVO_HIGH_SPEED;
>+		dpll |= DPLL_SDVO_HIGH_SPEED;
> 
> 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
>-		dpll |= DPLL_DVO_HIGH_SPEED;
>+		dpll |= DPLL_SDVO_HIGH_SPEED;
> 
> 	/* compute bitmask from p1 value */
> 	if (IS_PINEVIEW(dev))
>@@ -4626,6 +4641,9 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
> 			dpll |= PLL_P2_DIVIDE_BY_4;
> 	}
> 
>+	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
>+		dpll |= DPLL_DVO_2X;
>+
> 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
> 		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
>@@ -5657,9 +5675,9 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> 		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
> 
> 	if (is_sdvo)
>-		dpll |= DPLL_DVO_HIGH_SPEED;
>+		dpll |= DPLL_SDVO_HIGH_SPEED;
> 	if (intel_crtc->config.has_dp_encoder)
>-		dpll |= DPLL_DVO_HIGH_SPEED;
>+		dpll |= DPLL_SDVO_HIGH_SPEED;
> 
> 	/* compute bitmask from p1 value */
> 	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
>diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
>index eb2020e..cbbc49d 100644
>--- a/drivers/gpu/drm/i915/intel_dvo.c
>+++ b/drivers/gpu/drm/i915/intel_dvo.c
>@@ -283,7 +283,6 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
> 	int pipe = intel_crtc->pipe;
> 	u32 dvo_val;
> 	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
>-	int dpll_reg = DPLL(pipe);
> 
> 	switch (dvo_reg) {
> 	case DVOA:
>@@ -314,8 +313,6 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
> 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
> 
>-	I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED);
>-
> 	/*I915_WRITE(DVOB_SRCDIM,
> 	  (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
> 	  (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
>-- 
>1.7.10.4
>

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