Attachment 82722 Details for Bug 67111 – shader dump from SS3 with RADEON_DUMP_SHADERS=1

shader dump from SS3 with RADEON_DUMP_SHADERS=1

stdout.log (text/plain), 912.19 KB, created by Vladimir Usikov on 2013-07-20 09:09:33 UTC

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Filename:

MIME Type:

Creator: Vladimir Usikov

Created: 2013-07-20 09:09:33 UTC

Size: 912.19 KB

patch

obsolete

>Running Steam on arch rolling 32-bit
>STEAM_RUNTIME is enabled automatically
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>[2013-07-20 12:55:46] Startup - updater built Jul 19 2013 10:21:47
>[2013-07-20 12:55:46] Opted in to client beta 'publicbeta' via beta file
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>unlinked 0 orphaned pipes
>
>(steam:2026): Gtk-WARNING **: ÐÐ°Ð³ÑÑÐ¶Ð°ÐµÐ¼ÑÐ¹ Ð¼Ð¾Ð´ÑÐ»Ñ ÑÐµÐ¼ Ð½Ðµ Ð½Ð°Ð¹Ð´ÐµÐ½ Ð² module_path: Â«qtcurveÂ»,
>/home/behem0th/.gtkrc-2.0:12: error: scanner: unterminated string constant
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
>Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
>Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number
>[0720/125555:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
>Looks like steam didn't shutdown cleanly, scheduling immediate update check
>[2013-07-20 12:55:46] Checking for update on startup
>[2013-07-20 12:55:46] ÐÑÐ¾Ð²ÐµÑÐºÐ° Ð½Ð° Ð½Ð°Ð»Ð¸ÑÐ¸Ðµ Ð¾Ð±Ð½Ð¾Ð²Ð»ÐµÐ½Ð¸Ð¹...
>[2013-07-20 12:55:47] Download skipped: /client/steam_client_publicbeta_ubuntu12 version 1374261093, installed version 1374261093
>[2013-07-20 12:55:47] Nothing to do
>[2013-07-20 12:55:47] ÐÑÐ¾Ð²ÐµÑÐºÐ° ÑÑÑÐ°Ð½Ð¾Ð²ÐºÐ¸...
>[2013-07-20 12:55:47] Performing checksum verification of executable files
>[2013-07-20 12:55:52] Verification complete
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>PulseAudio connect failed (used only for Mic Volume Control) with error: Access denied
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Process 2026 created /behem0th-ValveIPCSharedObjects5
>Errors in resource/styles/steam.styles:
>Unknown key 'visible' set in style 'html-findbar' in file 'resource/styles/steam.styles'
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  %69 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
>  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
>  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
>  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %69, float %70, float %71, float %72)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %43, %25
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
>  %51 = bitcast i32 %50 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>10080604
>c2020112
>bf8c007f
>100a0404
>5e080905
>c2020111
>bf8c007f
>100a0204
>c2000110
>bf8c007f
>10000000
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Generating new string page texture 6: 48x256, total string texture memory is 49,15 KB
>Generating new string page texture 7: 48x256, total string texture memory is 49,15 KB
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV_SAT OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %5)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %30, %11
>  %49 = fmul float %30, %12
>  %50 = fmul float %30, %13
>  %51 = fmul float %30, %14
>  %52 = fmul float %31, %15
>  %53 = fadd float %52, %48
>  %54 = fmul float %31, %16
>  %55 = fadd float %54, %49
>  %56 = fmul float %31, %17
>  %57 = fadd float %56, %50
>  %58 = fmul float %31, %18
>  %59 = fadd float %58, %51
>  %60 = fmul float %32, %19
>  %61 = fadd float %60, %53
>  %62 = fmul float %32, %20
>  %63 = fadd float %62, %55
>  %64 = fmul float %32, %21
>  %65 = fadd float %64, %57
>  %66 = fmul float %32, %22
>  %67 = fadd float %66, %59
>  %68 = fmul float %33, %23
>  %69 = fadd float %68, %61
>  %70 = fmul float %33, %24
>  %71 = fadd float %70, %63
>  %72 = fmul float %33, %25
>  %73 = fadd float %72, %65
>  %74 = fmul float %33, %26
>  %75 = fadd float %74, %67
>  %76 = call float @llvm.AMDIL.clamp.(float %37, float 0,000000e+00, float 0x3FF0000000000000)
>  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0,000000e+00, float 0x3FF0000000000000)
>  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0,000000e+00, float 0x3FF0000000000000)
>  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0,000000e+00, float 0x3FF0000000000000)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %76, float %77, float %78, float %79)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %44, float %45, float %46, float %47)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %69, float %71, float %73, float %75)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>d2060805
>02010104
>d2060806
>02010103
>d2060807
>02010102
>d2060801
>02010101
>f800020f
>05060701
>c0840708
>bf8c000f
>e00c2000
>80020100
>bf8c0770
>f800021f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>Generating new string page texture 8: 384x256, total string texture memory is 442,37 KB
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>
>** (steam:2026): WARNING **: replace_settings: error updating connection /org/freedesktop/NetworkManager/Settings/0 settings: (1) type
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>roaming config store loaded successfully - 8533 bytes.
>migrating temporary roaming config store
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Adding license for package 0
>Adding license for package 34
>Adding license for package 783
>Adding license for package 995
>Adding license for package 1259
>Adding license for package 1290
>Adding license for package 1333
>Adding license for package 1507
>Adding license for package 1774
>Adding license for package 2008
>Adding license for package 2075
>Adding license for package 2377
>Adding license for package 2481
>Adding license for package 2832
>Adding license for package 3052
>Adding license for package 4066
>Adding license for package 4097
>Adding license for package 4912
>Adding license for package 6098
>Adding license for package 6146
>Adding license for package 6232
>Adding license for package 6428
>Adding license for package 6443
>Adding license for package 6660
>Adding license for package 6749
>Adding license for package 7150
>Adding license for package 7166
>Adding license for package 7350
>Adding license for package 7431
>Adding license for package 7802
>Adding license for package 7877
>Adding license for package 8009
>Adding license for package 8372
>Adding license for package 8386
>Adding license for package 8535
>Adding license for package 8731
>Adding license for package 11010
>Adding license for package 11072
>Adding license for package 11274
>Adding license for package 11542
>Adding license for package 11591
>Adding license for package 11732
>Adding license for package 11793
>Adding license for package 11850
>Adding license for package 11984
>Adding license for package 12225
>Adding license for package 12288
>Adding license for package 12361
>Adding license for package 12456
>Adding license for package 12544
>Adding license for package 12897
>Adding license for package 12985
>Adding license for package 13054
>Adding license for package 13086
>Adding license for package 13314
>Adding license for package 14188
>Adding license for package 14712
>Adding license for package 15123
>Adding license for package 15349
>Adding license for package 15371
>Adding license for package 15376
>Adding license for package 15479
>Adding license for package 16547
>Adding license for package 16549
>Adding license for package 16699
>Adding license for package 17496
>Adding license for package 17638
>Adding license for package 17919
>Adding license for package 17922
>Adding license for package 17968
>Adding license for package 18207
>Adding license for package 18265
>Adding license for package 18613
>Adding license for package 18777
>Adding license for package 25835
>Adding license for package 26331
>Adding license for package 26375
>Adding license for package 27195
>Adding license for package 27235
>Adding license for package 27531
>Adding license for package 27644
>Adding license for package 28596
>ExecCommandLine: "/home/behem0th/Steam/ubuntu12_32/steam"
>System startup time: 17,34 seconds
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>Running Steam on arch rolling 32-bit
>STEAM_RUNTIME has been set by the user to: /home/behem0th/Steam/ubuntu12_32/steam-runtime
>Generating new string page texture 91: 1024x256, total string texture memory is 1,49 MB
>Generating new string page texture 92: 128x256, total string texture memory is 1,62 MB
>Generating new string page texture 93: 256x256, total string texture memory is 311,30 KB
>Generating new string page texture 94: 256x256, total string texture memory is 1,88 MB
>Generating new string page texture 95: 128x256, total string texture memory is 442,37 KB
>Generating new string page texture 96: 24x256, total string texture memory is 1,91 MB
>Generating new string page texture 97: 32x256, total string texture memory is 1,94 MB
>Generating new string page texture 98: 64x256, total string texture memory is 507,90 KB
>Generating new string page texture 99: 64x256, total string texture memory is 2,01 MB
>Generating new string page texture 100: 8x256, total string texture memory is 516,10 KB
>Generating new string page texture 101: 8x256, total string texture memory is 2,02 MB
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>ExecCommandLine: "/home/behem0th/.steam/root/ubuntu12_32/steam steam://open/driverhelperready"
>ExecSteamURL: "steam://open/driverhelperready"
>Generating new string page texture 105: 16x256, total string texture memory is 2,03 MB
>Generating new string page texture 106: 128x256, total string texture memory is 2,16 MB
>Generating new string page texture 134: 128x256, total string texture memory is 2,29 MB
>Generating new string page texture 135: 256x256, total string texture memory is 2,56 MB
>Installing breakpad exception handler for appid(steam)/version(1374261093_client)
>Game update: AppID 41070 "Serious Sam 3: BFE", ProcID 2241, IP 0.0.0.0:0
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>
>(steam:2026): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
>cat: /etc/debian_version: ÐÐµÑ ÑÐ°ÐºÐ¾Ð³Ð¾ ÑÐ°Ð¹Ð»Ð° Ð¸Ð»Ð¸ ÐºÐ°ÑÐ°Ð»Ð¾Ð³Ð°
>Setting breakpad minidump AppID = 41070
>Steam_SetMinidumpSteamID:  Caching Steam ID:  76561198026030947 [API loaded no]
>WRN:  CPU Power saving is enabled and performance governor is not used.
>INF:  GameEnv API: Steam
>INF:  Encoded user ID = d60a20be:bf98cdef
>INF:  
>INF:  * Desktop settings...
>INF:  Color depth: 32-bit
>INF:  Desktop resolution: 1280 x 1024
>INF:  Fullscreen on primary display
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>WRN:  [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed.
>WRN:  [OpenGL] Unable to determine VRAM size... assuming 512 MB.
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>INF:  
>INF:  Gfx API: OpenGL
>INF:  Resolution: 1280 x 1024
>INF:  Vendor: ATI (0x1002)
>INF:  Driver: X.Org (0x679A)
>INF:  Renderer: Gallium 0.4 on AMD TAHITI
>INF:  Version: 2.1 Mesa 9.2.0-devel (git-719000b)
>INF:  Video memory size: 512 MB
>INF:  Available for textures: 512 MB
>INF:  Active GPU(s): 1
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>WRN:  Display driver is too old, please update it ASAP!
>INF:  SysMessage: Display driver is too old or version cannot be determined.
>INF:  Press OK to update driver, or Cancel to continue.
>INF:  Fullscreen on primary display
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>7e000280
>f8001800
>00000000
>bf810000
>WRN:  [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed.
>WRN:  [OpenGL] Unable to determine VRAM size... assuming 512 MB.
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>INF:  
>INF:  Gfx API: OpenGL
>INF:  Resolution: 1280 x 1024
>INF:  Vendor: ATI (0x1002)
>INF:  Driver: X.Org (0x679A)
>INF:  Renderer: Gallium 0.4 on AMD TAHITI
>INF:  Version: 2.1 Mesa 9.2.0-devel (git-719000b)
>INF:  Video memory size: 512 MB
>INF:  Available for textures: 512 MB
>INF:  Active GPU(s): 1
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>ALSA lib pcm.c:2217:(snd_pcm_open_noupdate) Unknown PCM cards.pcm.rear
>ALSA lib pcm.c:2217:(snd_pcm_open_noupdate) Unknown PCM cards.pcm.center_lfe
>ALSA lib pcm.c:2217:(snd_pcm_open_noupdate) Unknown PCM cards.pcm.side
>ALSA lib setup.c:519:(add_elem) Unknown field skip_rest
>ALSA lib setup.c:519:(add_elem) Unknown field skip_rest
>ALSA lib pcm_dmix.c:957:(snd_pcm_dmix_open) The dmix plugin supports only playback stream
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>INF:  
>INF:  Sfx API: OpenAL
>INF:  Device: ALSA Default
>INF:  Mixer frequency: 44100 Hz
>INF:  Mixer voices: 64
>INF:  Max sound sources: 25
>INF:  Max total volume: 3
>INF:  Speaker config: (unknown)
>INF:  Environment FX: not supported
>INF:  
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %32, float %33, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>f800180f
>03020100
>bf810000
>AL lib: pulseaudio.c:612: Context did not connect: Access denied
>INF:  Using cheats will invalidate your score for this level and achievements won't be awarded for the remainder of the game.
>INF:  Value of gfx_ulVideoMemoryMB changed from '3072' to '512'
>INF:  AutoDetect: Hardware values changed, adjusting settings automatically.
>INF:  CPU efficiency: 1980 MHz * 4 cores = 4752 Mhz
>INF:  ID: 0x679a; card: Radeon HD 7900 series; quality: 5
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  %24 = call i32 @llvm.SI.packf16(float %20, float %21)
>  %25 = bitcast i32 %24 to float
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %25, float %27, float %25, float %27)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>5e000101
>c8060102
>c80a0002
>5e020302
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>Installing breakpad exception handler for appid(gameoverlayui)/version(20130719102159_client)
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
>Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
>Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
>Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number
>
>(gameoverlayui:2327): Gtk-WARNING **: ÐÐ°Ð³ÑÑÐ¶Ð°ÐµÐ¼ÑÐ¹ Ð¼Ð¾Ð´ÑÐ»Ñ ÑÐµÐ¼ Ð½Ðµ Ð½Ð°Ð¹Ð´ÐµÐ½ Ð² module_path: Â«qtcurveÂ»,
>/home/behem0th/.gtkrc-2.0:12: error: scanner: unterminated string constant
>[0720/125638:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %33 = fdiv float %30, %32
>  %34 = fdiv float %31, %32
>  %35 = bitcast float %33 to i32
>  %36 = bitcast float %34 to i32
>  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
>  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
>  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fmul float %40, %22
>  %45 = fmul float %41, %23
>  %46 = fmul float %42, %24
>  %47 = fmul float %43, %25
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  %50 = call i32 @llvm.SI.packf16(float %46, float %47)
>  %51 = bitcast i32 %50 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %49, float %51, float %49, float %51)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0300
>c80d0301
>7e085503
>10060902
>c8140000
>c8150001
>10040905
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>10080604
>c2020112
>bf8c007f
>100a0404
>5e080905
>c2020111
>bf8c007f
>100a0204
>c2000110
>bf8c007f
>10000000
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
>  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
>  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
>  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %46, %11
>  %58 = fmul float %46, %12
>  %59 = fmul float %46, %13
>  %60 = fmul float %46, %14
>  %61 = fmul float %47, %15
>  %62 = fadd float %61, %57
>  %63 = fmul float %47, %16
>  %64 = fadd float %63, %58
>  %65 = fmul float %47, %17
>  %66 = fadd float %65, %59
>  %67 = fmul float %47, %18
>  %68 = fadd float %67, %60
>  %69 = fmul float %48, %19
>  %70 = fadd float %69, %62
>  %71 = fmul float %48, %20
>  %72 = fadd float %71, %64
>  %73 = fmul float %48, %21
>  %74 = fadd float %73, %66
>  %75 = fmul float %48, %22
>  %76 = fadd float %75, %68
>  %77 = fmul float %49, %23
>  %78 = fadd float %77, %70
>  %79 = fmul float %49, %24
>  %80 = fadd float %79, %72
>  %81 = fmul float %49, %25
>  %82 = fadd float %81, %74
>  %83 = fmul float %49, %26
>  %84 = fadd float %83, %76
>  %85 = fmul float %53, %27
>  %86 = fmul float %53, %28
>  %87 = fmul float %53, %29
>  %88 = fmul float %53, %30
>  %89 = fmul float %54, %31
>  %90 = fadd float %89, %85
>  %91 = fmul float %54, %32
>  %92 = fadd float %91, %86
>  %93 = fmul float %54, %33
>  %94 = fadd float %93, %87
>  %95 = fmul float %54, %34
>  %96 = fadd float %95, %88
>  %97 = fmul float %55, %35
>  %98 = fadd float %97, %90
>  %99 = fmul float %55, %36
>  %100 = fadd float %99, %92
>  %101 = fmul float %55, %37
>  %102 = fadd float %101, %94
>  %103 = fmul float %55, %38
>  %104 = fadd float %103, %96
>  %105 = fmul float %56, %39
>  %106 = fadd float %105, %98
>  %107 = fmul float %56, %40
>  %108 = fadd float %107, %100
>  %109 = fmul float %56, %41
>  %110 = fadd float %109, %102
>  %111 = fmul float %56, %42
>  %112 = fadd float %111, %104
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %106, float %108, float %110, float %112)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %78, float %80, float %82, float %84)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800020f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], IN[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %27 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %31 = fdiv float %28, %30
>  %32 = fdiv float %29, %30
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, %24
>  %43 = fmul float %39, %25
>  %44 = fmul float %40, %26
>  %45 = fmul float %41, %27
>  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
>  %47 = bitcast i32 %46 to float
>  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
>  %49 = bitcast i32 %48 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080500
>c8090501
>c80c0700
>c80d0701
>7e085503
>10060902
>c8140400
>c8150401
>10040905
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020202
>c8180300
>c8190301
>bf8c0770
>100c0d05
>c81c0200
>c81d0201
>100e0f04
>5e0c0d07
>c81c0100
>c81d0101
>100e0f03
>c8200000
>c8210001
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..7]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
>  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
>  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
>  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
>  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %5)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = extractelement <4 x float> %45, i32 1
>  %48 = extractelement <4 x float> %45, i32 2
>  %49 = extractelement <4 x float> %45, i32 3
>  %50 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %51, i32 0, i32 %5)
>  %53 = extractelement <4 x float> %52, i32 0
>  %54 = extractelement <4 x float> %52, i32 1
>  %55 = extractelement <4 x float> %52, i32 2
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %58, i32 0, i32 %5)
>  %60 = extractelement <4 x float> %59, i32 0
>  %61 = extractelement <4 x float> %59, i32 1
>  %62 = extractelement <4 x float> %59, i32 2
>  %63 = extractelement <4 x float> %59, i32 3
>  %64 = fmul float %46, %11
>  %65 = fmul float %46, %12
>  %66 = fmul float %46, %13
>  %67 = fmul float %46, %14
>  %68 = fmul float %47, %15
>  %69 = fadd float %68, %64
>  %70 = fmul float %47, %16
>  %71 = fadd float %70, %65
>  %72 = fmul float %47, %17
>  %73 = fadd float %72, %66
>  %74 = fmul float %47, %18
>  %75 = fadd float %74, %67
>  %76 = fmul float %48, %19
>  %77 = fadd float %76, %69
>  %78 = fmul float %48, %20
>  %79 = fadd float %78, %71
>  %80 = fmul float %48, %21
>  %81 = fadd float %80, %73
>  %82 = fmul float %48, %22
>  %83 = fadd float %82, %75
>  %84 = fmul float %49, %23
>  %85 = fadd float %84, %77
>  %86 = fmul float %49, %24
>  %87 = fadd float %86, %79
>  %88 = fmul float %49, %25
>  %89 = fadd float %88, %81
>  %90 = fmul float %49, %26
>  %91 = fadd float %90, %83
>  %92 = fmul float %60, %27
>  %93 = fmul float %60, %28
>  %94 = fmul float %60, %29
>  %95 = fmul float %60, %30
>  %96 = fmul float %61, %31
>  %97 = fadd float %96, %92
>  %98 = fmul float %61, %32
>  %99 = fadd float %98, %93
>  %100 = fmul float %61, %33
>  %101 = fadd float %100, %94
>  %102 = fmul float %61, %34
>  %103 = fadd float %102, %95
>  %104 = fmul float %62, %35
>  %105 = fadd float %104, %97
>  %106 = fmul float %62, %36
>  %107 = fadd float %106, %99
>  %108 = fmul float %62, %37
>  %109 = fadd float %108, %101
>  %110 = fmul float %62, %38
>  %111 = fadd float %110, %103
>  %112 = fmul float %63, %39
>  %113 = fadd float %112, %105
>  %114 = fmul float %63, %40
>  %115 = fadd float %114, %107
>  %116 = fmul float %63, %41
>  %117 = fadd float %116, %109
>  %118 = fmul float %63, %42
>  %119 = fadd float %118, %111
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %53, float %54, float %55, float %56)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %113, float %115, float %117, float %119)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %85, float %87, float %89, float %91)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0840708
>bf8c000f
>e00c2000
>80020100
>c0800100
>bf8c0070
>c2020113
>bf8c007f
>100a0204
>c2020117
>bf8c007f
>d2820005
>04140902
>c202011b
>bf8c007f
>d2820005
>04140903
>c202011f
>bf8c007f
>d2820005
>04140904
>c2020112
>bf8c007f
>100c0204
>c2020116
>bf8c007f
>d2820006
>04180902
>c202011a
>bf8c007f
>d2820006
>04180903
>c202011e
>bf8c007f
>d2820006
>04180904
>c2020111
>bf8c007f
>100e0204
>c2020115
>bf8c007f
>d2820007
>041c0902
>c2020119
>bf8c007f
>d2820007
>041c0903
>c202011d
>bf8c007f
>d2820007
>041c0904
>c2020110
>bf8c007f
>10100204
>c2020114
>bf8c007f
>d2820008
>04200902
>c2020118
>bf8c007f
>d2820008
>04200903
>c202011c
>bf8c007f
>d2820001
>04200904
>f800021f
>05060701
>c0820700
>bf8c000f
>e00c2000
>80010000
>c2020103
>bf8c0070
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
>  %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = extractelement <4 x float> %29, i32 1
>  %32 = extractelement <4 x float> %29, i32 2
>  %33 = extractelement <4 x float> %29, i32 3
>  %34 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %5)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %30, %11
>  %42 = fmul float %30, %12
>  %43 = fmul float %30, %13
>  %44 = fmul float %30, %14
>  %45 = fmul float %31, %15
>  %46 = fadd float %45, %41
>  %47 = fmul float %31, %16
>  %48 = fadd float %47, %42
>  %49 = fmul float %31, %17
>  %50 = fadd float %49, %43
>  %51 = fmul float %31, %18
>  %52 = fadd float %51, %44
>  %53 = fmul float %32, %19
>  %54 = fadd float %53, %46
>  %55 = fmul float %32, %20
>  %56 = fadd float %55, %48
>  %57 = fmul float %32, %21
>  %58 = fadd float %57, %50
>  %59 = fmul float %32, %22
>  %60 = fadd float %59, %52
>  %61 = fmul float %33, %23
>  %62 = fadd float %61, %54
>  %63 = fmul float %33, %24
>  %64 = fadd float %63, %56
>  %65 = fmul float %33, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %33, %26
>  %68 = fadd float %67, %60
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %37, float %38, float %39, float %40)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %62, float %64, float %66, float %68)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80020100
>bf8c0770
>f800020f
>04030201
>c0820700
>bf8c000f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080004
>c2020107
>bf8c007f
>d2820004
>04100901
>c202010b
>bf8c007f
>d2820004
>04100902
>c202010f
>bf8c007f
>d2820004
>04100903
>c2020102
>bf8c007f
>100a0004
>c2020106
>bf8c007f
>d2820005
>04140901
>c202010a
>bf8c007f
>d2820005
>04140902
>c202010e
>bf8c007f
>d2820005
>04140903
>c2020101
>bf8c007f
>100c0004
>c2020105
>bf8c007f
>d2820006
>04180901
>c2020109
>bf8c007f
>d2820006
>04180902
>c202010d
>bf8c007f
>d2820006
>04180903
>c2020100
>bf8c007f
>100e0004
>c2020104
>bf8c007f
>d2820007
>041c0901
>c2020108
>bf8c007f
>d2820007
>041c0902
>c200010c
>bf8c007f
>d2820000
>041c0103
>f80008cf
>04050600
>bf810000
>INF:  AutoDetect: storing new settings: gfx_iPixelProgramVersion=30,gfx_ctConcurrentGPUs=1,sys_iGPUVendorID=4098,sys_iCPUFamily=15,sys_iCPUMHz=2200,sys_iGPUDeviceID=26522,sys_strCPUVendor=AuthenticAMD,gfx_ulVideoMemoryMB=512,
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
>  3: EX2 TEMP[1].x, TEMP[1].xxxx
>  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
>  5: MOV TEMP[1].w, IMM[0].zzzz
>  6: SGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
>  7: F2I TEMP[2].x, -TEMP[2]
>  8: UIF TEMP[2].xxxx :0
>  9:   MOV TEMP[1], TEMP[1]
> 10: ELSE :0
> 11:   MOV TEMP[1], TEMP[0]
> 12: ENDIF
> 13: MUL TEMP[0], TEMP[1], IN[0]
> 14: MOV OUT[0], TEMP[0]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %24 = load <32 x i8> addrspace(2)* %23, !tbaa !0
>  %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0
>  %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %30 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %33 = bitcast float %31 to i32
>  %34 = bitcast float %32 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %24, <16 x i8> %26, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %41, 3.200000e+01
>  %43 = fadd float %42, -1.600000e+01
>  %44 = call float @llvm.AMDIL.exp.(float %43)
>  %45 = fmul float %38, %44
>  %46 = fmul float %39, %44
>  %47 = fmul float %40, %44
>  %48 = fcmp uge float %22, 0.000000e+00
>  %49 = select i1 %48, float 1.000000e+00, float 0.000000e+00
>  %50 = fsub float -0.000000e+00, %49
>  %51 = fptosi float %50 to i32
>  %52 = bitcast i32 %51 to float
>  %53 = bitcast float %52 to i32
>  %54 = icmp ne i32 %53, 0
>  %. = select i1 %54, float %45, float %38
>  %.12 = select i1 %54, float %46, float %39
>  %.13 = select i1 %54, float %47, float %40
>  %.14 = select i1 %54, float 1.000000e+00, float %41
>  %55 = fmul float %., %27
>  %56 = fmul float %.12, %28
>  %57 = fmul float %.13, %29
>  %58 = fmul float %.14, %30
>  %59 = call i32 @llvm.SI.packf16(float %55, float %56)
>  %60 = bitcast i32 %59 to float
>  %61 = call i32 @llvm.SI.packf16(float %57, float %58)
>  %62 = bitcast i32 %61 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0500
>c80d0501
>c8080400
>c8090401
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430202
>7e0c02ff
>c1800000
>7e0e02ff
>42000000
>bf8c0770
>d2820006
>041a0f05
>7e0c4b06
>100e0d03
>c0800100
>bf8c007f
>c2000100
>bf8c007f
>d00c0000
>02010000
>d2000008
>0001e480
>d2060008
>22010108
>7e101108
>d10a0000
>02010108
>d2000007
>00020f03
>c8200100
>c8210101
>100e1107
>10100d02
>d2000008
>00021102
>c8240000
>c8250001
>10101308
>5e0e0f08
>100c0d04
>d2000006
>00020d04
>c8200200
>c8210201
>100c1106
>d2000002
>0001e505
>c80c0300
>c80d0301
>10000702
>5e000106
>f8001c0f
>00070007
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL CONST[0..5]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: DP4 TEMP[1].x, IN[0], CONST[3]
>  6: MOV TEMP[0].w, TEMP[1].xxxx
>  7: SGE TEMP[1].x, CONST[4].zzzz, IMM[0].xxxx
>  8: F2I TEMP[1].x, -TEMP[1]
>  9: UIF TEMP[1].xxxx :0
> 10:   MOV TEMP[1], IN[2].zyxw
> 11: ELSE :0
> 12:   MOV TEMP[1], CONST[5]
> 13: ENDIF
> 14: MOV TEMP[2].w, TEMP[1].wwww
> 15: POW TEMP[3].x, TEMP[1].xxxx, CONST[4].xxxx
> 16: POW TEMP[3].y, TEMP[1].yyyy, CONST[4].xxxx
> 17: POW TEMP[3].z, TEMP[1].zzzz, CONST[4].xxxx
> 18: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[4].yyyy
> 19: MUL TEMP[0], TEMP[0], CONST[4].wwww
> 20: MOV TEMP[1].xy, IN[1].xyxx
> 21: MOV OUT[3], TEMP[1]
> 22: MOV OUT[2], TEMP[2]
> 23: MOV OUT[0], TEMP[0]
> 24: MOV OUT[1], TEMP[0]
> 25: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %5)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %5)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = fmul float %38, %11
>  %55 = fmul float %39, %12
>  %56 = fadd float %54, %55
>  %57 = fmul float %40, %13
>  %58 = fadd float %56, %57
>  %59 = fmul float %41, %14
>  %60 = fadd float %58, %59
>  %61 = fmul float %38, %15
>  %62 = fmul float %39, %16
>  %63 = fadd float %61, %62
>  %64 = fmul float %40, %17
>  %65 = fadd float %63, %64
>  %66 = fmul float %41, %18
>  %67 = fadd float %65, %66
>  %68 = fmul float %38, %19
>  %69 = fmul float %39, %20
>  %70 = fadd float %68, %69
>  %71 = fmul float %40, %21
>  %72 = fadd float %70, %71
>  %73 = fmul float %41, %22
>  %74 = fadd float %72, %73
>  %75 = fmul float %38, %23
>  %76 = fmul float %39, %24
>  %77 = fadd float %75, %76
>  %78 = fmul float %40, %25
>  %79 = fadd float %77, %78
>  %80 = fmul float %41, %26
>  %81 = fadd float %79, %80
>  %82 = fcmp uge float %29, 0.000000e+00
>  %83 = select i1 %82, float 1.000000e+00, float 0.000000e+00
>  %84 = fsub float -0.000000e+00, %83
>  %85 = fptosi float %84 to i32
>  %86 = bitcast i32 %85 to float
>  %87 = bitcast float %86 to i32
>  %88 = icmp ne i32 %87, 0
>  %. = select i1 %88, float %52, float %31
>  %.16 = select i1 %88, float %51, float %32
>  %.17 = select i1 %88, float %50, float %33
>  %.18 = select i1 %88, float %53, float %34
>  %89 = call float @llvm.pow.f32(float %., float %27)
>  %90 = call float @llvm.pow.f32(float %.16, float %27)
>  %91 = call float @llvm.pow.f32(float %.17, float %27)
>  %92 = fmul float %89, %28
>  %93 = fmul float %90, %28
>  %94 = fmul float %91, %28
>  %95 = fmul float %60, %30
>  %96 = fmul float %67, %30
>  %97 = fmul float %74, %30
>  %98 = fmul float %81, %30
>  %99 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call float @llvm.SI.load.const(<16 x i8> %100, i32 0)
>  %102 = fmul float %101, %95
>  %103 = call float @llvm.SI.load.const(<16 x i8> %100, i32 4)
>  %104 = fmul float %103, %96
>  %105 = fadd float %102, %104
>  %106 = call float @llvm.SI.load.const(<16 x i8> %100, i32 8)
>  %107 = fmul float %106, %97
>  %108 = fadd float %105, %107
>  %109 = call float @llvm.SI.load.const(<16 x i8> %100, i32 12)
>  %110 = fmul float %109, %98
>  %111 = fadd float %108, %110
>  %112 = call float @llvm.SI.load.const(<16 x i8> %100, i32 16)
>  %113 = fmul float %112, %95
>  %114 = call float @llvm.SI.load.const(<16 x i8> %100, i32 20)
>  %115 = fmul float %114, %96
>  %116 = fadd float %113, %115
>  %117 = call float @llvm.SI.load.const(<16 x i8> %100, i32 24)
>  %118 = fmul float %117, %97
>  %119 = fadd float %116, %118
>  %120 = call float @llvm.SI.load.const(<16 x i8> %100, i32 28)
>  %121 = fmul float %120, %98
>  %122 = fadd float %119, %121
>  %123 = call float @llvm.SI.load.const(<16 x i8> %100, i32 32)
>  %124 = fmul float %123, %95
>  %125 = call float @llvm.SI.load.const(<16 x i8> %100, i32 36)
>  %126 = fmul float %125, %96
>  %127 = fadd float %124, %126
>  %128 = call float @llvm.SI.load.const(<16 x i8> %100, i32 40)
>  %129 = fmul float %128, %97
>  %130 = fadd float %127, %129
>  %131 = call float @llvm.SI.load.const(<16 x i8> %100, i32 44)
>  %132 = fmul float %131, %98
>  %133 = fadd float %130, %132
>  %134 = call float @llvm.SI.load.const(<16 x i8> %100, i32 48)
>  %135 = fmul float %134, %95
>  %136 = call float @llvm.SI.load.const(<16 x i8> %100, i32 52)
>  %137 = fmul float %136, %96
>  %138 = fadd float %135, %137
>  %139 = call float @llvm.SI.load.const(<16 x i8> %100, i32 56)
>  %140 = fmul float %139, %97
>  %141 = fadd float %138, %140
>  %142 = call float @llvm.SI.load.const(<16 x i8> %100, i32 60)
>  %143 = fmul float %142, %98
>  %144 = fadd float %141, %143
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %111, float %122, float %133, float %144)
>  %145 = call float @llvm.SI.load.const(<16 x i8> %100, i32 64)
>  %146 = fmul float %145, %95
>  %147 = call float @llvm.SI.load.const(<16 x i8> %100, i32 68)
>  %148 = fmul float %147, %96
>  %149 = fadd float %146, %148
>  %150 = call float @llvm.SI.load.const(<16 x i8> %100, i32 72)
>  %151 = fmul float %150, %97
>  %152 = fadd float %149, %151
>  %153 = call float @llvm.SI.load.const(<16 x i8> %100, i32 76)
>  %154 = fmul float %153, %98
>  %155 = fadd float %152, %154
>  %156 = call float @llvm.SI.load.const(<16 x i8> %100, i32 80)
>  %157 = fmul float %156, %95
>  %158 = call float @llvm.SI.load.const(<16 x i8> %100, i32 84)
>  %159 = fmul float %158, %96
>  %160 = fadd float %157, %159
>  %161 = call float @llvm.SI.load.const(<16 x i8> %100, i32 88)
>  %162 = fmul float %161, %97
>  %163 = fadd float %160, %162
>  %164 = call float @llvm.SI.load.const(<16 x i8> %100, i32 92)
>  %165 = fmul float %164, %98
>  %166 = fadd float %163, %165
>  %167 = call float @llvm.SI.load.const(<16 x i8> %100, i32 96)
>  %168 = fmul float %167, %95
>  %169 = call float @llvm.SI.load.const(<16 x i8> %100, i32 100)
>  %170 = fmul float %169, %96
>  %171 = fadd float %168, %170
>  %172 = call float @llvm.SI.load.const(<16 x i8> %100, i32 104)
>  %173 = fmul float %172, %97
>  %174 = fadd float %171, %173
>  %175 = call float @llvm.SI.load.const(<16 x i8> %100, i32 108)
>  %176 = fmul float %175, %98
>  %177 = fadd float %174, %176
>  %178 = call float @llvm.SI.load.const(<16 x i8> %100, i32 112)
>  %179 = fmul float %178, %95
>  %180 = call float @llvm.SI.load.const(<16 x i8> %100, i32 116)
>  %181 = fmul float %180, %96
>  %182 = fadd float %179, %181
>  %183 = call float @llvm.SI.load.const(<16 x i8> %100, i32 120)
>  %184 = fmul float %183, %97
>  %185 = fadd float %182, %184
>  %186 = call float @llvm.SI.load.const(<16 x i8> %100, i32 124)
>  %187 = fmul float %186, %98
>  %188 = fadd float %185, %187
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %155, float %166, float %177, float %188)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %92, float %93, float %94, float %.18)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %.17, float %.18)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %95, float %96, float %97, float %98)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840700
>bf8c007f
>e00c2000
>80020400
>c0840100
>bf8c0070
>c2010901
>bf8c007f
>10020a02
>c2010900
>bf8c007f
>d2820001
>04040504
>c2010902
>bf8c007f
>d2820001
>04040506
>c2010903
>bf8c007f
>d2820001
>04040507
>c2020913
>bf8c007f
>10020204
>c2010905
>bf8c007f
>10040a02
>c2010904
>bf8c007f
>d2820002
>04080504
>c2010906
>bf8c007f
>d2820002
>04080506
>c2010907
>bf8c007f
>d2820002
>04080507
>10040404
>c0800104
>bf8c007f
>c202810d
>bf8c007f
>10060405
>c202810c
>bf8c007f
>d2820008
>040e0205
>c2028909
>bf8c007f
>10060a05
>c2028908
>bf8c007f
>d2820003
>040c0b04
>c202890a
>bf8c007f
>d2820003
>040c0b06
>c202890b
>bf8c007f
>d2820003
>040c0b07
>10060604
>c202810e
>bf8c007f
>d2820008
>04220605
>c202890d
>bf8c007f
>10120a05
>c202890c
>bf8c007f
>d2820009
>04240b04
>c202890e
>bf8c007f
>d2820009
>04240b06
>c202890f
>bf8c007f
>d2820004
>04240b07
>10080804
>c202010f
>bf8c007f
>d2820005
>04220804
>c2020109
>bf8c007f
>100c0404
>c2020108
>bf8c007f
>d2820006
>041a0204
>c202010a
>bf8c007f
>d2820006
>041a0604
>c202010b
>bf8c007f
>d2820006
>041a0804
>c2020105
>bf8c007f
>100e0404
>c2020104
>bf8c007f
>d2820007
>041e0204
>c2020106
>bf8c007f
>d2820007
>041e0604
>c2020107
>bf8c007f
>d2820007
>041e0804
>c2020101
>bf8c007f
>10100404
>c2020100
>bf8c007f
>d2820008
>04220204
>c2020102
>bf8c007f
>d2820008
>04220604
>c2020103
>bf8c007f
>d2820008
>04220804
>f80000ef
>05060708
>c202011d
>bf8c000f
>100a0404
>c202011c
>bf8c007f
>d2820005
>04160204
>c202011e
>bf8c007f
>d2820005
>04160604
>c202011f
>bf8c007f
>d2820005
>04160804
>c2020119
>bf8c007f
>100c0404
>c2020118
>bf8c007f
>d2820006
>041a0204
>c202011a
>bf8c007f
>d2820006
>041a0604
>c202011b
>bf8c007f
>d2820006
>041a0804
>c2020115
>bf8c007f
>100e0404
>c2020114
>bf8c007f
>d2820007
>041e0204
>c2020116
>bf8c007f
>d2820007
>041e0604
>c2020117
>bf8c007f
>d2820007
>041e0804
>c2020111
>bf8c007f
>10100404
>c2020110
>bf8c007f
>d2820008
>04220204
>c2020112
>bf8c007f
>d2820008
>04220604
>c2000113
>bf8c007f
>d2820008
>04220800
>f80000ff
>05060708
>c0800708
>bf8c000f
>e00c2000
>80000500
>c2000917
>bf8c0070
>7e120200
>c2000912
>bf8c007f
>d00c0000
>02010000
>d200000a
>0001e480
>d206000a
>2201010a
>7e14110a
>d10a0000
>0201010a
>d2000009
>00021109
>c2010916
>bf8c007f
>7e140202
>d200000a
>00020b0a
>7e164f0a
>c2010910
>bf8c007f
>0e161602
>7e164b0b
>c2018911
>bf8c007f
>10161603
>c2020915
>bf8c007f
>7e180204
>d200000c
>00020d0c
>7e184f0c
>0e181802
>7e184b0c
>10181803
>c2020914
>bf8c007f
>7e1a0204
>d2000005
>00020f0d
>7e0a4f05
>0e0a0a02
>7e0a4b05
>100a0a03
>f800020f
>090b0c05
>c0800704
>bf8c000f
>e00c2000
>80000500
>bf8c0770
>f800021f
>090a0605
>f80008cf
>04030201
>bf810000
>INF:  Started simulation on 'Content/SeriousSam3/Levels/Menu/Intro.wld' in 0.56 seconds.
>WRN:  Couldn't utilize anti-aliasing for HDR buffer.
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %9)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %9)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = extractelement <4 x float> %30, i32 3
>  %35 = call i32 @llvm.SI.packf16(float %31, float %32)
>  %36 = bitcast i32 %35 to float
>  %37 = call i32 @llvm.SI.packf16(float %33, float %34)
>  %38 = bitcast i32 %37 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %36, float %38, float %36, float %38)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800f00
>00010002
>bf8c0770
>5e080702
>5e000300
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %10, i32 0, i32 %5)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = extractelement <4 x float> %11, i32 1
>  %14 = extractelement <4 x float> %11, i32 2
>  %15 = extractelement <4 x float> %11, i32 3
>  %16 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %17 = load <16 x i8> addrspace(2)* %16, !tbaa !0
>  %18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %17, i32 0, i32 %5)
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = extractelement <4 x float> %18, i32 3
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %19, float %20, float %21, float %22)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %12, float %13, float %14, float %15)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0800704
>bf8c007f
>e00c2000
>80000100
>bf8c0770
>f800020f
>04030201
>c0800700
>bf8c000f
>e00c2000
>80000000
>bf8c0770
>f80008cf
>03020100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.2500,     0.0000,     0.0000,     0.0000}
>  0: MIN TEMP[0], IN[0], CONST[0].zwzw
>  1: MAX TEMP[0], TEMP[0], CONST[0].xyxy
>  2: MOV TEMP[1].xy, TEMP[0].xyyy
>  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
>  4: MUL TEMP[1], TEMP[1], IMM[0].xxxx
>  5: MOV TEMP[0].xy, TEMP[0].zwww
>  6: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  7: MAD TEMP[1], TEMP[0], IMM[0].xxxx, TEMP[1]
>  8: MIN TEMP[0], IN[1], CONST[0].zwzw
>  9: MAX TEMP[0], TEMP[0], CONST[0].xyxy
> 10: MOV TEMP[2].xy, TEMP[0].xyyy
> 11: TEX TEMP[2], TEMP[2], SAMP[0], 2D
> 12: MAD TEMP[1], TEMP[2], IMM[0].xxxx, TEMP[1]
> 13: MOV TEMP[0].xy, TEMP[0].zwww
> 14: TEX TEMP[0], TEMP[0], SAMP[0], 2D
> 15: MAD TEMP[0], TEMP[0], IMM[0].xxxx, TEMP[1]
> 16: MOV OUT[0], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %36 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %37 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %38 = fcmp uge float %30, %24
>  %39 = select i1 %38, float %24, float %30
>  %40 = fcmp uge float %31, %25
>  %41 = select i1 %40, float %25, float %31
>  %42 = fcmp uge float %32, %24
>  %43 = select i1 %42, float %24, float %32
>  %44 = fcmp uge float %33, %25
>  %45 = select i1 %44, float %25, float %33
>  %46 = fcmp uge float %39, %22
>  %47 = select i1 %46, float %39, float %22
>  %48 = fcmp uge float %41, %23
>  %49 = select i1 %48, float %41, float %23
>  %50 = fcmp uge float %43, %22
>  %51 = select i1 %50, float %43, float %22
>  %52 = fcmp uge float %45, %23
>  %53 = select i1 %52, float %45, float %23
>  %54 = bitcast float %47 to i32
>  %55 = bitcast float %49 to i32
>  %56 = insertelement <2 x i32> undef, i32 %54, i32 0
>  %57 = insertelement <2 x i32> %56, i32 %55, i32 1
>  %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %57, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = extractelement <4 x float> %58, i32 3
>  %63 = fmul float %59, 2.500000e-01
>  %64 = fmul float %60, 2.500000e-01
>  %65 = fmul float %61, 2.500000e-01
>  %66 = fmul float %62, 2.500000e-01
>  %67 = bitcast float %51 to i32
>  %68 = bitcast float %53 to i32
>  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
>  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
>  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  %75 = extractelement <4 x float> %71, i32 3
>  %76 = fmul float %72, 2.500000e-01
>  %77 = fadd float %76, %63
>  %78 = fmul float %73, 2.500000e-01
>  %79 = fadd float %78, %64
>  %80 = fmul float %74, 2.500000e-01
>  %81 = fadd float %80, %65
>  %82 = fmul float %75, 2.500000e-01
>  %83 = fadd float %82, %66
>  %84 = fcmp uge float %34, %24
>  %85 = select i1 %84, float %24, float %34
>  %86 = fcmp uge float %35, %25
>  %87 = select i1 %86, float %25, float %35
>  %88 = fcmp uge float %36, %24
>  %89 = select i1 %88, float %24, float %36
>  %90 = fcmp uge float %37, %25
>  %91 = select i1 %90, float %25, float %37
>  %92 = fcmp uge float %85, %22
>  %93 = select i1 %92, float %85, float %22
>  %94 = fcmp uge float %87, %23
>  %95 = select i1 %94, float %87, float %23
>  %96 = fcmp uge float %89, %22
>  %97 = select i1 %96, float %89, float %22
>  %98 = fcmp uge float %91, %23
>  %99 = select i1 %98, float %91, float %23
>  %100 = bitcast float %93 to i32
>  %101 = bitcast float %95 to i32
>  %102 = insertelement <2 x i32> undef, i32 %100, i32 0
>  %103 = insertelement <2 x i32> %102, i32 %101, i32 1
>  %104 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %103, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %105 = extractelement <4 x float> %104, i32 0
>  %106 = extractelement <4 x float> %104, i32 1
>  %107 = extractelement <4 x float> %104, i32 2
>  %108 = extractelement <4 x float> %104, i32 3
>  %109 = fmul float %105, 2.500000e-01
>  %110 = fadd float %109, %77
>  %111 = fmul float %106, 2.500000e-01
>  %112 = fadd float %111, %79
>  %113 = fmul float %107, 2.500000e-01
>  %114 = fadd float %113, %81
>  %115 = fmul float %108, 2.500000e-01
>  %116 = fadd float %115, %83
>  %117 = bitcast float %97 to i32
>  %118 = bitcast float %99 to i32
>  %119 = insertelement <2 x i32> undef, i32 %117, i32 0
>  %120 = insertelement <2 x i32> %119, i32 %118, i32 1
>  %121 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %120, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = extractelement <4 x float> %121, i32 1
>  %124 = extractelement <4 x float> %121, i32 2
>  %125 = extractelement <4 x float> %121, i32 3
>  %126 = fmul float %122, 2.500000e-01
>  %127 = fadd float %126, %110
>  %128 = fmul float %123, 2.500000e-01
>  %129 = fadd float %128, %112
>  %130 = fmul float %124, 2.500000e-01
>  %131 = fadd float %130, %114
>  %132 = fmul float %125, 2.500000e-01
>  %133 = fadd float %132, %116
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %127, float %129, float %131, float %133)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080300
>c8090301
>c0840100
>bf8c007f
>c2000903
>bf8c007f
>d00c000c
>02000102
>7e0c0200
>d2000002
>00320d02
>c2008901
>bf8c007f
>d00c000c
>02000302
>7e0e0201
>d2000003
>00320507
>c8100200
>c8110201
>c2038902
>bf8c007f
>d00c000c
>02000f04
>7e100207
>d2000004
>00321104
>c2040900
>bf8c007f
>d00c000a
>02001104
>7e120208
>d2000002
>002a0909
>c0860300
>c0c80500
>bf8c007f
>f0800f00
>00640202
>c8280100
>c8290101
>d00c0002
>0200010a
>d200000a
>000a0d0a
>d00c0002
>0200030a
>d200000b
>000a1507
>c8300000
>c8310001
>d00c0002
>02000f0c
>d200000c
>000a110c
>d00c0002
>0200110c
>d200000a
>000a1909
>f0800f00
>00640b0a
>bf8c0770
>101e1cff
>3e800000
>7e1402ff
>3e800000
>d2820013
>043e1505
>c83c0500
>c83d0501
>d00c0002
>0200010f
>d200000f
>000a0d0f
>d00c0002
>0200030f
>d2000010
>000a1f07
>c8440400
>c8450401
>d00c0002
>02000f11
>d2000011
>000a1111
>d00c0002
>02001111
>d200000f
>000a2309
>f0800f00
>00640f0f
>bf8c0770
>d2820013
>044e1512
>c8500700
>c8510701
>d00c0002
>02000114
>d2000006
>000a0d14
>d00c0000
>02000306
>d2000007
>00020d07
>c8500600
>c8510601
>d00c0000
>02000f14
>d2000000
>00021114
>d00c0000
>02001100
>d2000006
>00020109
>f0800f00
>00640606
>bf8c0770
>d2820000
>044e1509
>10021aff
>3e800000
>d2820001
>04061504
>d2820001
>04061511
>d2820001
>04061508
>102618ff
>3e800000
>d2820013
>044e1503
>d2820013
>044e1510
>d2820013
>044e1507
>101616ff
>3e800000
>d2820002
>042e1502
>d2820002
>040a150f
>d2820002
>040a1506
>f800180f
>00011302
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL CONST[0..1]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.5000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MUL TEMP[2].xy, CONST[1].xyyy, IMM[0].zzzz
>  4: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
>  5: MOV TEMP[2].xy, TEMP[1].xyxx
>  6: ADD TEMP[1].x, TEMP[1].xxxx, CONST[1].xxxx
>  7: MOV TEMP[2].zw, TEMP[1].yyxy
>  8: ADD TEMP[3].x, TEMP[1].yyyy, CONST[1].yyyy
>  9: MOV TEMP[1].y, TEMP[3].xxxx
> 10: MOV TEMP[3].zw, TEMP[1].yyxy
> 11: ADD TEMP[1].x, TEMP[1].xxxx, -CONST[1].xxxx
> 12: MOV TEMP[3].xy, TEMP[1].xyxx
> 13: MOV OUT[2], TEMP[2]
> 14: MOV OUT[3], TEMP[3]
> 15: MOV OUT[0], TEMP[0]
> 16: MOV OUT[1], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
>  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %5)
>  %20 = extractelement <4 x float> %19, i32 0
>  %21 = extractelement <4 x float> %19, i32 1
>  %22 = extractelement <4 x float> %19, i32 2
>  %23 = extractelement <4 x float> %19, i32 3
>  %24 = fmul float %22, %11
>  %25 = fadd float %24, %13
>  %26 = fmul float %23, %12
>  %27 = fadd float %26, %14
>  %28 = fmul float %15, 5.000000e-01
>  %29 = fmul float %16, 5.000000e-01
>  %30 = fsub float -0.000000e+00, %28
>  %31 = fadd float %25, %30
>  %32 = fsub float -0.000000e+00, %29
>  %33 = fadd float %27, %32
>  %34 = fadd float %31, %15
>  %35 = fadd float %33, %16
>  %36 = fsub float -0.000000e+00, %15
>  %37 = fadd float %34, %36
>  %38 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
>  %40 = call float @llvm.SI.load.const(<16 x i8> %39, i32 0)
>  %41 = fmul float %40, %20
>  %42 = call float @llvm.SI.load.const(<16 x i8> %39, i32 4)
>  %43 = fmul float %42, %21
>  %44 = fadd float %41, %43
>  %45 = call float @llvm.SI.load.const(<16 x i8> %39, i32 8)
>  %46 = fmul float %45, 0.000000e+00
>  %47 = fadd float %44, %46
>  %48 = call float @llvm.SI.load.const(<16 x i8> %39, i32 12)
>  %49 = fmul float %48, 1.000000e+00
>  %50 = fadd float %47, %49
>  %51 = call float @llvm.SI.load.const(<16 x i8> %39, i32 16)
>  %52 = fmul float %51, %20
>  %53 = call float @llvm.SI.load.const(<16 x i8> %39, i32 20)
>  %54 = fmul float %53, %21
>  %55 = fadd float %52, %54
>  %56 = call float @llvm.SI.load.const(<16 x i8> %39, i32 24)
>  %57 = fmul float %56, 0.000000e+00
>  %58 = fadd float %55, %57
>  %59 = call float @llvm.SI.load.const(<16 x i8> %39, i32 28)
>  %60 = fmul float %59, 1.000000e+00
>  %61 = fadd float %58, %60
>  %62 = call float @llvm.SI.load.const(<16 x i8> %39, i32 32)
>  %63 = fmul float %62, %20
>  %64 = call float @llvm.SI.load.const(<16 x i8> %39, i32 36)
>  %65 = fmul float %64, %21
>  %66 = fadd float %63, %65
>  %67 = call float @llvm.SI.load.const(<16 x i8> %39, i32 40)
>  %68 = fmul float %67, 0.000000e+00
>  %69 = fadd float %66, %68
>  %70 = call float @llvm.SI.load.const(<16 x i8> %39, i32 44)
>  %71 = fmul float %70, 1.000000e+00
>  %72 = fadd float %69, %71
>  %73 = call float @llvm.SI.load.const(<16 x i8> %39, i32 48)
>  %74 = fmul float %73, %20
>  %75 = call float @llvm.SI.load.const(<16 x i8> %39, i32 52)
>  %76 = fmul float %75, %21
>  %77 = fadd float %74, %76
>  %78 = call float @llvm.SI.load.const(<16 x i8> %39, i32 56)
>  %79 = fmul float %78, 0.000000e+00
>  %80 = fadd float %77, %79
>  %81 = call float @llvm.SI.load.const(<16 x i8> %39, i32 60)
>  %82 = fmul float %81, 1.000000e+00
>  %83 = fadd float %80, %82
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %50, float %61, float %72, float %83)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %39, i32 64)
>  %85 = fmul float %84, %20
>  %86 = call float @llvm.SI.load.const(<16 x i8> %39, i32 68)
>  %87 = fmul float %86, %21
>  %88 = fadd float %85, %87
>  %89 = call float @llvm.SI.load.const(<16 x i8> %39, i32 72)
>  %90 = fmul float %89, 0.000000e+00
>  %91 = fadd float %88, %90
>  %92 = call float @llvm.SI.load.const(<16 x i8> %39, i32 76)
>  %93 = fmul float %92, 1.000000e+00
>  %94 = fadd float %91, %93
>  %95 = call float @llvm.SI.load.const(<16 x i8> %39, i32 80)
>  %96 = fmul float %95, %20
>  %97 = call float @llvm.SI.load.const(<16 x i8> %39, i32 84)
>  %98 = fmul float %97, %21
>  %99 = fadd float %96, %98
>  %100 = call float @llvm.SI.load.const(<16 x i8> %39, i32 88)
>  %101 = fmul float %100, 0.000000e+00
>  %102 = fadd float %99, %101
>  %103 = call float @llvm.SI.load.const(<16 x i8> %39, i32 92)
>  %104 = fmul float %103, 1.000000e+00
>  %105 = fadd float %102, %104
>  %106 = call float @llvm.SI.load.const(<16 x i8> %39, i32 96)
>  %107 = fmul float %106, %20
>  %108 = call float @llvm.SI.load.const(<16 x i8> %39, i32 100)
>  %109 = fmul float %108, %21
>  %110 = fadd float %107, %109
>  %111 = call float @llvm.SI.load.const(<16 x i8> %39, i32 104)
>  %112 = fmul float %111, 0.000000e+00
>  %113 = fadd float %110, %112
>  %114 = call float @llvm.SI.load.const(<16 x i8> %39, i32 108)
>  %115 = fmul float %114, 1.000000e+00
>  %116 = fadd float %113, %115
>  %117 = call float @llvm.SI.load.const(<16 x i8> %39, i32 112)
>  %118 = fmul float %117, %20
>  %119 = call float @llvm.SI.load.const(<16 x i8> %39, i32 116)
>  %120 = fmul float %119, %21
>  %121 = fadd float %118, %120
>  %122 = call float @llvm.SI.load.const(<16 x i8> %39, i32 120)
>  %123 = fmul float %122, 0.000000e+00
>  %124 = fadd float %121, %123
>  %125 = call float @llvm.SI.load.const(<16 x i8> %39, i32 124)
>  %126 = fmul float %125, 1.000000e+00
>  %127 = fadd float %124, %126
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %94, float %105, float %116, float %127)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %31, float %33, float %34, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %37, float %35, float %34, float %35)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %20, float %21, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0820104
>bf8c0070
>c201050d
>bf8c007f
>10080202
>c201050c
>bf8c007f
>d2820004
>04120002
>c201050e
>bf8c007f
>d2820004
>04110002
>c201050f
>bf8c007f
>06080802
>c2010509
>bf8c007f
>100a0202
>c2010508
>bf8c007f
>d2820005
>04160002
>c201050a
>bf8c007f
>d2820005
>04150002
>c201050b
>bf8c007f
>060a0a02
>c2010505
>bf8c007f
>100c0202
>c2010504
>bf8c007f
>d2820006
>041a0002
>c2010506
>bf8c007f
>d2820006
>04190002
>c2010507
>bf8c007f
>060c0c02
>c2010501
>bf8c007f
>100e0202
>c2010500
>bf8c007f
>d2820007
>041e0002
>c2010502
>bf8c007f
>d2820007
>041d0002
>c2010503
>bf8c007f
>060e0e02
>f80000ef
>04050607
>c201051d
>bf8c000f
>10080202
>c201051c
>bf8c007f
>d2820004
>04120002
>c201051e
>bf8c007f
>d2820004
>04110002
>c201051f
>bf8c007f
>06080802
>c2010519
>bf8c007f
>100a0202
>c2010518
>bf8c007f
>d2820005
>04160002
>c201051a
>bf8c007f
>d2820005
>04150002
>c201051b
>bf8c007f
>060a0a02
>c2010515
>bf8c007f
>100c0202
>c2010514
>bf8c007f
>d2820006
>041a0002
>c2010516
>bf8c007f
>d2820006
>04190002
>c2010517
>bf8c007f
>060c0c02
>c2010511
>bf8c007f
>100e0202
>c2010510
>bf8c007f
>d2820007
>041e0002
>c2010512
>bf8c007f
>d2820007
>041d0002
>c2010513
>bf8c007f
>060e0e02
>f80000ff
>04050607
>c0800100
>bf8c000f
>c2020101
>c2028103
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020105
>bf8c007f
>d2100005
>0201e004
>08080b04
>c2028100
>c2030102
>bf8c007f
>7e0a0206
>d2820005
>04140b02
>c2000104
>bf8c007f
>d2100006
>0201e000
>080c0d05
>060a0c00
>f800020f
>04050406
>bf8c070f
>06080804
>0a0c0a00
>f800021f
>04050406
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
>  %21 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %3)
>  %22 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %3)
>  %23 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %3)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %20, float %21, float %22, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>befe0a7e
>befc0306
>c8020302
>c8060202
>c80a0102
>c80e0002
>f800180f
>00010203
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], POSITION, LINEAR
>DCL IN[1], GENERIC[19], PERSPECTIVE
>DCL IN[2], GENERIC[20], PERSPECTIVE
>DCL IN[3], GENERIC[21], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL CONST[8]
>DCL CONST[0..3]
>DCL TEMP[0]
>DCL TEMP[1..5], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     2.0000,    -1.0000}
>  0: MOV TEMP[0], IN[0]
>  1: MAD TEMP[0].y, IN[0], CONST[8].xxxx, CONST[8].yyyy
>  2: MOV TEMP[1].xy, IN[1].zwww
>  3: TEX TEMP[1].w, TEMP[1], SAMP[2], 2D
>  4: MUL TEMP[1].x, TEMP[1].wwww, IN[3].wwww
>  5: MUL TEMP[2].x, CONST[0].xxxx, TEMP[1].xxxx
>  6: MUL TEMP[1].x, CONST[0].yyyy, TEMP[1].xxxx
>  7: DP3 TEMP[3].x, IN[2].xyzz, IN[2].xyzz
>  8: RSQ TEMP[3].x, TEMP[3].xxxx
>  9: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[3].xxxx
> 10: ABS TEMP[4].x, TEMP[3].zzzz
> 11: ADD_SAT TEMP[4].x, TEMP[4].xxxx, -CONST[2].zzzz
> 12: MAD TEMP[4].x, TEMP[4].xxxx, CONST[2].yyyy, IMM[0].xxxx
> 13: POW TEMP[4].x, TEMP[4].xxxx, CONST[2].xxxx
> 14: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx
> 15: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
> 16: MOV TEMP[4].xy, IN[1].xyyy
> 17: TEX TEMP[4], TEMP[4], SAMP[1], 2D
> 18: SLT TEMP[5].x, IMM[0].yyyy, TEMP[4].zzzz
> 19: F2I TEMP[5].x, -TEMP[5]
> 20: UIF TEMP[5].xxxx :2
> 21:   MOV TEMP[5].xy, TEMP[4].ywyy
> 22: ELSE :2
> 23:   MOV TEMP[5].xy, TEMP[4].xyxx
> 24: ENDIF
> 25: MAD TEMP[4].xy, TEMP[5].xyyy, IMM[0].zzzz, IMM[0].wwww
> 26: MUL TEMP[2].xy, TEMP[2].xxxx, TEMP[3].xyyy
> 27: MAD TEMP[1].xy, TEMP[1].xxxx, -TEMP[4].xyyy, TEMP[2].xyyy
> 28: MUL TEMP[2].xy, TEMP[0].xyyy, CONST[3].xyyy
> 29: MOV TEMP[3].xy, TEMP[2].xyyy
> 30: TEX TEMP[3].x, TEMP[3], SAMP[3], 2D
> 31: ABS TEMP[3].x, TEMP[3].xxxx
> 32: MAD TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww, -CONST[3].zzzz
> 33: ADD TEMP[3].x, TEMP[3].xxxx, -IN[2].wwww
> 34: MUL_SAT TEMP[3].x, TEMP[3].xxxx, CONST[2].wwww
> 35: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[3].xxxx
> 36: ADD_SAT TEMP[2].xy, TEMP[2].xyyy, TEMP[1].xyyy
> 37: MOV TEMP[2].xy, TEMP[2].xyyy
> 38: TEX TEMP[2].x, TEMP[2], SAMP[3], 2D
> 39: ABS TEMP[2].x, TEMP[2].xxxx
> 40: MAD TEMP[2].x, TEMP[2].xxxx, CONST[3].wwww, -CONST[3].zzzz
> 41: ADD TEMP[2].x, TEMP[2].xxxx, -IN[2].wwww
> 42: MUL_SAT TEMP[2].x, TEMP[2].xxxx, CONST[2].wwww
> 43: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
> 44: MAD TEMP[1].xy, TEMP[0].xyyy, CONST[0].zwww, TEMP[1].xyyy
> 45: MIN TEMP[1].xy, TEMP[1].xyyy, CONST[1].zwww
> 46: MAX TEMP[1].xy, TEMP[1].xyyy, CONST[1].xyyy
> 47: MOV TEMP[1].xy, TEMP[1].xyyy
> 48: TEX TEMP[1], TEMP[1], SAMP[0], 2D
> 49: MOV TEMP[2].w, TEMP[1].wwww
> 50: MUL TEMP[2].xyz, TEMP[1].xyzz, IN[3].xyzz
> 51: MOV OUT[0], TEMP[2]
> 52: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %40 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
>  %44 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %45 = load <32 x i8> addrspace(2)* %44, !tbaa !0
>  %46 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0
>  %48 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %49 = load <32 x i8> addrspace(2)* %48, !tbaa !0
>  %50 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %51 = load <16 x i8> addrspace(2)* %50, !tbaa !0
>  %52 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %53 = load <32 x i8> addrspace(2)* %52, !tbaa !0
>  %54 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %57 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %58 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %59 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %60 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %61 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %62 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %63 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %64 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %65 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %66 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %67 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %68 = fmul float %13, %38
>  %69 = fadd float %68, %39
>  %70 = bitcast float %58 to i32
>  %71 = bitcast float %59 to i32
>  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
>  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
>  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %49, <16 x i8> %51, i32 2)
>  %75 = extractelement <4 x float> %74, i32 3
>  %76 = fmul float %75, %67
>  %77 = fmul float %22, %76
>  %78 = fmul float %23, %76
>  %79 = fmul float %60, %60
>  %80 = fmul float %61, %61
>  %81 = fadd float %80, %79
>  %82 = fmul float %62, %62
>  %83 = fadd float %81, %82
>  %84 = call float @llvm.AMDGPU.rsq(float %83)
>  %85 = fmul float %60, %84
>  %86 = fmul float %61, %84
>  %87 = fmul float %62, %84
>  %88 = call float @fabs(float %87)
>  %89 = fsub float -0.000000e+00, %32
>  %90 = fadd float %88, %89
>  %91 = call float @llvm.AMDIL.clamp.(float %90, float 0.000000e+00, float 1.000000e+00)
>  %92 = fmul float %91, %31
>  %93 = fadd float %92, 0x3EE4F8B580000000
>  %94 = call float @llvm.pow.f32(float %93, float %30)
>  %95 = fmul float %78, %94
>  %96 = fmul float %77, %94
>  %97 = bitcast float %56 to i32
>  %98 = bitcast float %57 to i32
>  %99 = insertelement <2 x i32> undef, i32 %97, i32 0
>  %100 = insertelement <2 x i32> %99, i32 %98, i32 1
>  %101 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %100, <32 x i8> %45, <16 x i8> %47, i32 2)
>  %102 = extractelement <4 x float> %101, i32 0
>  %103 = extractelement <4 x float> %101, i32 1
>  %104 = extractelement <4 x float> %101, i32 2
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = fcmp ult float 0.000000e+00, %104
>  %107 = select i1 %106, float 1.000000e+00, float 0.000000e+00
>  %108 = fsub float -0.000000e+00, %107
>  %109 = fptosi float %108 to i32
>  %110 = bitcast i32 %109 to float
>  %111 = bitcast float %110 to i32
>  %112 = icmp ne i32 %111, 0
>  %. = select i1 %112, float %103, float %102
>  %.24 = select i1 %112, float %105, float %103
>  %113 = fmul float %., 2.000000e+00
>  %114 = fadd float %113, -1.000000e+00
>  %115 = fmul float %.24, 2.000000e+00
>  %116 = fadd float %115, -1.000000e+00
>  %117 = fmul float %96, %85
>  %118 = fmul float %96, %86
>  %119 = fsub float -0.000000e+00, %114
>  %120 = fmul float %95, %119
>  %121 = fadd float %120, %117
>  %122 = fsub float -0.000000e+00, %116
>  %123 = fmul float %95, %122
>  %124 = fadd float %123, %118
>  %125 = fmul float %12, %34
>  %126 = fmul float %69, %35
>  %127 = bitcast float %125 to i32
>  %128 = bitcast float %126 to i32
>  %129 = insertelement <2 x i32> undef, i32 %127, i32 0
>  %130 = insertelement <2 x i32> %129, i32 %128, i32 1
>  %131 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %130, <32 x i8> %53, <16 x i8> %55, i32 2)
>  %132 = extractelement <4 x float> %131, i32 0
>  %133 = call float @fabs(float %132)
>  %134 = fsub float -0.000000e+00, %36
>  %135 = fmul float %133, %37
>  %136 = fadd float %135, %134
>  %137 = fsub float -0.000000e+00, %63
>  %138 = fadd float %136, %137
>  %139 = fmul float %138, %33
>  %140 = call float @llvm.AMDIL.clamp.(float %139, float 0.000000e+00, float 1.000000e+00)
>  %141 = fmul float %121, %140
>  %142 = fmul float %124, %140
>  %143 = fadd float %125, %141
>  %144 = fadd float %126, %142
>  %145 = call float @llvm.AMDIL.clamp.(float %143, float 0.000000e+00, float 1.000000e+00)
>  %146 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00)
>  %147 = bitcast float %145 to i32
>  %148 = bitcast float %146 to i32
>  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
>  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
>  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %53, <16 x i8> %55, i32 2)
>  %152 = extractelement <4 x float> %151, i32 0
>  %153 = call float @fabs(float %152)
>  %154 = fsub float -0.000000e+00, %36
>  %155 = fmul float %153, %37
>  %156 = fadd float %155, %154
>  %157 = fsub float -0.000000e+00, %63
>  %158 = fadd float %156, %157
>  %159 = fmul float %158, %33
>  %160 = call float @llvm.AMDIL.clamp.(float %159, float 0.000000e+00, float 1.000000e+00)
>  %161 = fmul float %141, %160
>  %162 = fmul float %142, %160
>  %163 = fmul float %12, %24
>  %164 = fadd float %163, %161
>  %165 = fmul float %69, %25
>  %166 = fadd float %165, %162
>  %167 = fcmp uge float %164, %28
>  %168 = select i1 %167, float %28, float %164
>  %169 = fcmp uge float %166, %29
>  %170 = select i1 %169, float %29, float %166
>  %171 = fcmp uge float %168, %26
>  %172 = select i1 %171, float %168, float %26
>  %173 = fcmp uge float %170, %27
>  %174 = select i1 %173, float %170, float %27
>  %175 = bitcast float %172 to i32
>  %176 = bitcast float %174 to i32
>  %177 = insertelement <2 x i32> undef, i32 %175, i32 0
>  %178 = insertelement <2 x i32> %177, i32 %176, i32 1
>  %179 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %178, <32 x i8> %41, <16 x i8> %43, i32 2)
>  %180 = extractelement <4 x float> %179, i32 0
>  %181 = extractelement <4 x float> %179, i32 1
>  %182 = extractelement <4 x float> %179, i32 2
>  %183 = extractelement <4 x float> %179, i32 3
>  %184 = fmul float %180, %64
>  %185 = fmul float %181, %65
>  %186 = fmul float %182, %66
>  %187 = call i32 @llvm.SI.packf16(float %184, float %185)
>  %188 = bitcast i32 %187 to float
>  %189 = call i32 @llvm.SI.packf16(float %186, float %183)
>  %190 = bitcast i32 %189 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %188, float %190, float %188, float %190)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #4
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>attributes #4 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8140100
>c8150101
>c8100000
>c8110001
>c0840304
>c0c60508
>bf8c007f
>f0800f00
>00430404
>bf8c0770
>d0080008
>02010106
>d2000008
>0021e480
>d2060008
>22010108
>7e101108
>d10a000c
>02010108
>d2000008
>00320b04
>06101108
>061210f3
>c82c0300
>c82d0301
>c8280200
>c8290201
>c0840308
>c0c80510
>bf8c007f
>f0800800
>0044080a
>c8280b00
>c8290b01
>bf8c0770
>10181508
>c0840100
>bf8c007f
>c2000901
>bf8c007f
>10161800
>c8200500
>c8210501
>c8340400
>c8350401
>10141b0d
>d282000a
>042a1108
>c8380600
>c8390601
>d282000a
>042a1d0e
>7e145b0a
>101c150e
>d206010e
>0201010e
>c200090a
>bf8c007f
>0a1c1c00
>d206080e
>0201010e
>c2000909
>7e1e02ff
>3727c5ac
>bf8c007f
>d282000e
>043c010e
>7e1c4f0e
>c2000908
>bf8c007f
>0e1c1c00
>7e1c4b0e
>10161d0b
>1012130b
>c2000900
>bf8c007f
>10181800
>10181d0c
>101a150d
>101a1b0c
>081a130d
>c8240700
>c8250701
>c2000920
>c2008921
>bf8c007f
>7e1c0201
>d2820003
>04380103
>c200090d
>bf8c007f
>101e0600
>c207890c
>bf8c007f
>101c040f
>c088030c
>c0ca0518
>bf8c007f
>f0800100
>00850e0e
>bf8c0770
>d206010e
>0201010e
>c200890f
>bf8c007f
>101c1c01
>c203890e
>bf8c007f
>0a1c1c07
>081c130e
>c207090b
>bf8c007f
>101c1c0e
>d2060810
>0201010e
>101a210d
>d282000e
>04341f02
>d206080e
>0201010e
>d2000004
>00320f05
>06080904
>060808f3
>1008090b
>100a1508
>100a0b0c
>08080905
>10082104
>d2820005
>04100103
>d206080f
>02010105
>f0800100
>0085050e
>bf8c0770
>d2060105
>02010105
>100a0a01
>0a0a0a07
>080a1305
>100a0a0e
>d2060805
>02010105
>10080b04
>c2000903
>bf8c007f
>d2820003
>04100103
>c2000907
>bf8c007f
>d00c000c
>02000103
>7e080200
>d2000003
>00320903
>c2000905
>bf8c007f
>d00c000c
>02000103
>7e080200
>d2000004
>00320704
>100a0b0d
>c2000902
>bf8c007f
>d2820002
>04140102
>c2000906
>bf8c007f
>d00c000c
>02000102
>7e0a0200
>d2000002
>00320b02
>c2000904
>bf8c007f
>d00c0008
>02000102
>7e0a0200
>d2000003
>00220505
>c0800300
>c0c40500
>bf8c007f
>f0800f00
>00020203
>c8180a00
>c8190a01
>bf8c0770
>100c0d04
>5e0c0b06
>c81c0900
>c81d0901
>100e0f03
>c8200800
>c8210801
>10001102
>5e000f00
>f8001c0f
>06000600
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL OUT[4], GENERIC[21]
>DCL CONST[0..240]
>DCL TEMP[0..9], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,    -0.1000}
>IMM[1] INT32 {3, 41, 42, 43}
>  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[10].zzzz, CONST[10].wwww
>  1: MOV TEMP[1].xz, TEMP[0].xxzx
>  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
>  3: MOV TEMP[1].y, TEMP[0].xxxx
>  4: MOV TEMP[0], IN[0]
>  5: MOV TEMP[2].xyz, TEMP[1].xyzx
>  6: UIF CONST[240].xxxx :0
>  7:   DP3 TEMP[3].x, IN[4].xyzz, IMM[0].yyyy
>  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
>  9:   MUL TEMP[4], IN[3], IMM[0].zzzz
> 10:   F2I TEMP[4], TEMP[4]
> 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
> 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
> 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
> 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
> 15:   UARL ADDR[0].x, TEMP[8].xxxx
> 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[4].xxxx
> 17:   UARL ADDR[0].x, TEMP[7].xxxx
> 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].yyyy, TEMP[8]
> 19:   UARL ADDR[0].x, TEMP[6].xxxx
> 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[4].zzzz, TEMP[7]
> 21:   UARL ADDR[0].x, TEMP[5].xxxx
> 22:   UARL ADDR[0].x, TEMP[5].xxxx
> 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
> 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
> 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
> 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
> 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
> 28:   UARL ADDR[0].x, TEMP[9].xxxx
> 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[4].xxxx
> 30:   UARL ADDR[0].x, TEMP[8].xxxx
> 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[4].yyyy, TEMP[9]
> 32:   UARL ADDR[0].x, TEMP[7].xxxx
> 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].zzzz, TEMP[8]
> 34:   UARL ADDR[0].x, TEMP[6].xxxx
> 35:   UARL ADDR[0].x, TEMP[6].xxxx
> 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
> 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
> 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
> 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
> 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
> 41:   UARL ADDR[0].x, TEMP[4].xxxx
> 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[4].xxxx
> 43:   UARL ADDR[0].x, TEMP[9].xxxx
> 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].yyyy, TEMP[4]
> 45:   UARL ADDR[0].x, TEMP[8].xxxx
> 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].zzzz, TEMP[4]
> 47:   UARL ADDR[0].x, TEMP[7].xxxx
> 48:   UARL ADDR[0].x, TEMP[7].xxxx
> 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
> 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
> 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
> 52:   MOV TEMP[4].y, TEMP[7].xxxx
> 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
> 54:   MOV TEMP[4].z, TEMP[7].xxxx
> 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
> 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
> 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
> 58:   MOV TEMP[4].y, TEMP[5].xxxx
> 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
> 60:   MOV TEMP[4].z, TEMP[1].xxxx
> 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
> 62: ENDIF
> 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
> 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
> 65: MOV TEMP[1].y, TEMP[3].xxxx
> 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
> 67: MOV TEMP[1].z, TEMP[3].xxxx
> 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
> 69: MOV TEMP[1].w, TEMP[3].xxxx
> 70: DP3 TEMP[3].x, TEMP[2].xyzz, CONST[4].xyzz
> 71: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[5].xyzz
> 72: DP3 TEMP[2].x, TEMP[2].xyzz, CONST[6].xyzz
> 73: MOV TEMP[3].z, TEMP[2].xxxx
> 74: MOV TEMP[2].xz, TEMP[3].xxzx
> 75: MOV TEMP[2].y, -TEMP[4].xxxx
> 76: DP4 TEMP[0].x, TEMP[0], CONST[9]
> 77: ADD TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww
> 78: MOV TEMP[2].w, TEMP[0].xxxx
> 79: DP4 TEMP[0].x, IN[2], CONST[7]
> 80: DP4 TEMP[3].x, IN[2], CONST[8]
> 81: MOV TEMP[0].y, TEMP[3].xxxx
> 82: MOV TEMP[0].xy, TEMP[0].xyxx
> 83: MOV TEMP[0].zw, IN[5].yyxy
> 84: MAD TEMP[3], IN[6].zyxw, CONST[10].xxxx, CONST[10].yyyy
> 85: MOV TEMP[4].w, TEMP[3].wwww
> 86: MUL TEMP[4].xyz, TEMP[3].xyzz, TEMP[3].xyzz
> 87: LRP TEMP[4].xyz, TEMP[3].wwww, TEMP[4].xyzz, IMM[0].yyyy
> 88: MOV OUT[2], TEMP[0]
> 89: MOV OUT[3], TEMP[2]
> 90: MOV OUT[0], TEMP[1]
> 91: MOV OUT[4], TEMP[4]
> 92: MOV OUT[1], TEMP[1]
> 93: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 168)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 172)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3840)
>  %53 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %54 = load <16 x i8> addrspace(2)* %53, !tbaa !0
>  %55 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %54, i32 0, i32 %5)
>  %56 = extractelement <4 x float> %55, i32 0
>  %57 = extractelement <4 x float> %55, i32 1
>  %58 = extractelement <4 x float> %55, i32 2
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
>  %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %5)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = extractelement <4 x float> %62, i32 1
>  %65 = extractelement <4 x float> %62, i32 2
>  %66 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0
>  %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %5)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = extractelement <4 x float> %68, i32 1
>  %71 = extractelement <4 x float> %68, i32 2
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %74, i32 0, i32 %5)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = extractelement <4 x float> %75, i32 3
>  %80 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %81 = load <16 x i8> addrspace(2)* %80, !tbaa !0
>  %82 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %81, i32 0, i32 %5)
>  %83 = extractelement <4 x float> %82, i32 0
>  %84 = extractelement <4 x float> %82, i32 1
>  %85 = extractelement <4 x float> %82, i32 2
>  %86 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %87 = load <16 x i8> addrspace(2)* %86, !tbaa !0
>  %88 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %87, i32 0, i32 %5)
>  %89 = extractelement <4 x float> %88, i32 0
>  %90 = extractelement <4 x float> %88, i32 1
>  %91 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0
>  %93 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %92, i32 0, i32 %5)
>  %94 = extractelement <4 x float> %93, i32 0
>  %95 = extractelement <4 x float> %93, i32 1
>  %96 = extractelement <4 x float> %93, i32 2
>  %97 = extractelement <4 x float> %93, i32 3
>  %98 = fmul float %63, %50
>  %99 = fadd float %98, %51
>  %100 = fmul float %64, %50
>  %101 = fadd float %100, %51
>  %102 = fmul float %65, %50
>  %103 = fadd float %102, %51
>  %104 = fadd float %101, 0x3F50624DE0000000
>  %105 = bitcast float %52 to i32
>  %106 = icmp ne i32 %105, 0
>  br i1 %106, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %107 = fmul float %83, 1.000000e+00
>  %108 = fmul float %84, 1.000000e+00
>  %109 = fadd float %108, %107
>  %110 = fmul float %85, 1.000000e+00
>  %111 = fadd float %109, %110
>  %112 = fsub float -0.000000e+00, %111
>  %113 = fadd float 1.000000e+00, %112
>  %114 = fmul float %76, 0x406FE051E0000000
>  %115 = fmul float %77, 0x406FE051E0000000
>  %116 = fmul float %78, 0x406FE051E0000000
>  %117 = fmul float %79, 0x406FE051E0000000
>  %118 = fptosi float %114 to i32
>  %119 = fptosi float %115 to i32
>  %120 = fptosi float %116 to i32
>  %121 = fptosi float %117 to i32
>  %122 = bitcast i32 %118 to float
>  %123 = bitcast i32 %119 to float
>  %124 = bitcast i32 %120 to float
>  %125 = bitcast i32 %121 to float
>  %126 = bitcast float %125 to i32
>  %127 = mul i32 %126, 3
>  %128 = add i32 %127, 41
>  %129 = bitcast i32 %128 to float
>  %130 = bitcast float %124 to i32
>  %131 = mul i32 %130, 3
>  %132 = add i32 %131, 41
>  %133 = bitcast i32 %132 to float
>  %134 = bitcast float %123 to i32
>  %135 = mul i32 %134, 3
>  %136 = add i32 %135, 41
>  %137 = bitcast i32 %136 to float
>  %138 = bitcast float %122 to i32
>  %139 = mul i32 %138, 3
>  %140 = add i32 %139, 41
>  %141 = bitcast i32 %140 to float
>  %142 = bitcast float %141 to i32
>  %143 = shl i32 %142, 4
>  %144 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %143)
>  %145 = fmul float %144, %83
>  %146 = shl i32 %142, 4
>  %147 = add i32 %146, 4
>  %148 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %147)
>  %149 = fmul float %148, %83
>  %150 = shl i32 %142, 4
>  %151 = add i32 %150, 8
>  %152 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %151)
>  %153 = fmul float %152, %83
>  %154 = shl i32 %142, 4
>  %155 = add i32 %154, 12
>  %156 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %155)
>  %157 = fmul float %156, %83
>  %158 = bitcast float %137 to i32
>  %159 = shl i32 %158, 4
>  %160 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %159)
>  %161 = fmul float %160, %84
>  %162 = fadd float %161, %145
>  %163 = shl i32 %158, 4
>  %164 = add i32 %163, 4
>  %165 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %164)
>  %166 = fmul float %165, %84
>  %167 = fadd float %166, %149
>  %168 = shl i32 %158, 4
>  %169 = add i32 %168, 8
>  %170 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %169)
>  %171 = fmul float %170, %84
>  %172 = fadd float %171, %153
>  %173 = shl i32 %158, 4
>  %174 = add i32 %173, 12
>  %175 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %174)
>  %176 = fmul float %175, %84
>  %177 = fadd float %176, %157
>  %178 = bitcast float %133 to i32
>  %179 = shl i32 %178, 4
>  %180 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %179)
>  %181 = fmul float %180, %85
>  %182 = fadd float %181, %162
>  %183 = shl i32 %178, 4
>  %184 = add i32 %183, 4
>  %185 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %184)
>  %186 = fmul float %185, %85
>  %187 = fadd float %186, %167
>  %188 = shl i32 %178, 4
>  %189 = add i32 %188, 8
>  %190 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %189)
>  %191 = fmul float %190, %85
>  %192 = fadd float %191, %172
>  %193 = shl i32 %178, 4
>  %194 = add i32 %193, 12
>  %195 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %194)
>  %196 = fmul float %195, %85
>  %197 = fadd float %196, %177
>  %198 = bitcast float %129 to i32
>  %199 = shl i32 %198, 4
>  %200 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %199)
>  %201 = fmul float %200, %113
>  %202 = fadd float %201, %182
>  %203 = shl i32 %198, 4
>  %204 = add i32 %203, 4
>  %205 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %204)
>  %206 = fmul float %205, %113
>  %207 = fadd float %206, %187
>  %208 = shl i32 %198, 4
>  %209 = add i32 %208, 8
>  %210 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %209)
>  %211 = fmul float %210, %113
>  %212 = fadd float %211, %192
>  %213 = shl i32 %198, 4
>  %214 = add i32 %213, 12
>  %215 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %214)
>  %216 = fmul float %215, %113
>  %217 = fadd float %216, %197
>  %218 = bitcast float %125 to i32
>  %219 = mul i32 %218, 3
>  %220 = add i32 %219, 42
>  %221 = bitcast i32 %220 to float
>  %222 = bitcast float %124 to i32
>  %223 = mul i32 %222, 3
>  %224 = add i32 %223, 42
>  %225 = bitcast i32 %224 to float
>  %226 = bitcast float %123 to i32
>  %227 = mul i32 %226, 3
>  %228 = add i32 %227, 42
>  %229 = bitcast i32 %228 to float
>  %230 = bitcast float %122 to i32
>  %231 = mul i32 %230, 3
>  %232 = add i32 %231, 42
>  %233 = bitcast i32 %232 to float
>  %234 = bitcast float %233 to i32
>  %235 = shl i32 %234, 4
>  %236 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %235)
>  %237 = fmul float %236, %83
>  %238 = shl i32 %234, 4
>  %239 = add i32 %238, 4
>  %240 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %239)
>  %241 = fmul float %240, %83
>  %242 = shl i32 %234, 4
>  %243 = add i32 %242, 8
>  %244 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %243)
>  %245 = fmul float %244, %83
>  %246 = shl i32 %234, 4
>  %247 = add i32 %246, 12
>  %248 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %247)
>  %249 = fmul float %248, %83
>  %250 = bitcast float %229 to i32
>  %251 = shl i32 %250, 4
>  %252 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %251)
>  %253 = fmul float %252, %84
>  %254 = fadd float %253, %237
>  %255 = shl i32 %250, 4
>  %256 = add i32 %255, 4
>  %257 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %256)
>  %258 = fmul float %257, %84
>  %259 = fadd float %258, %241
>  %260 = shl i32 %250, 4
>  %261 = add i32 %260, 8
>  %262 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %261)
>  %263 = fmul float %262, %84
>  %264 = fadd float %263, %245
>  %265 = shl i32 %250, 4
>  %266 = add i32 %265, 12
>  %267 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %266)
>  %268 = fmul float %267, %84
>  %269 = fadd float %268, %249
>  %270 = bitcast float %225 to i32
>  %271 = shl i32 %270, 4
>  %272 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %271)
>  %273 = fmul float %272, %85
>  %274 = fadd float %273, %254
>  %275 = shl i32 %270, 4
>  %276 = add i32 %275, 4
>  %277 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %276)
>  %278 = fmul float %277, %85
>  %279 = fadd float %278, %259
>  %280 = shl i32 %270, 4
>  %281 = add i32 %280, 8
>  %282 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %281)
>  %283 = fmul float %282, %85
>  %284 = fadd float %283, %264
>  %285 = shl i32 %270, 4
>  %286 = add i32 %285, 12
>  %287 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %286)
>  %288 = fmul float %287, %85
>  %289 = fadd float %288, %269
>  %290 = bitcast float %221 to i32
>  %291 = shl i32 %290, 4
>  %292 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %291)
>  %293 = fmul float %292, %113
>  %294 = fadd float %293, %274
>  %295 = shl i32 %290, 4
>  %296 = add i32 %295, 4
>  %297 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %296)
>  %298 = fmul float %297, %113
>  %299 = fadd float %298, %279
>  %300 = shl i32 %290, 4
>  %301 = add i32 %300, 8
>  %302 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %301)
>  %303 = fmul float %302, %113
>  %304 = fadd float %303, %284
>  %305 = shl i32 %290, 4
>  %306 = add i32 %305, 12
>  %307 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %306)
>  %308 = fmul float %307, %113
>  %309 = fadd float %308, %289
>  %310 = bitcast float %125 to i32
>  %311 = mul i32 %310, 3
>  %312 = add i32 %311, 43
>  %313 = bitcast i32 %312 to float
>  %314 = bitcast float %124 to i32
>  %315 = mul i32 %314, 3
>  %316 = add i32 %315, 43
>  %317 = bitcast i32 %316 to float
>  %318 = bitcast float %123 to i32
>  %319 = mul i32 %318, 3
>  %320 = add i32 %319, 43
>  %321 = bitcast i32 %320 to float
>  %322 = bitcast float %122 to i32
>  %323 = mul i32 %322, 3
>  %324 = add i32 %323, 43
>  %325 = bitcast i32 %324 to float
>  %326 = bitcast float %325 to i32
>  %327 = shl i32 %326, 4
>  %328 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %327)
>  %329 = fmul float %328, %83
>  %330 = shl i32 %326, 4
>  %331 = add i32 %330, 4
>  %332 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %331)
>  %333 = fmul float %332, %83
>  %334 = shl i32 %326, 4
>  %335 = add i32 %334, 8
>  %336 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %335)
>  %337 = fmul float %336, %83
>  %338 = shl i32 %326, 4
>  %339 = add i32 %338, 12
>  %340 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %339)
>  %341 = fmul float %340, %83
>  %342 = bitcast float %321 to i32
>  %343 = shl i32 %342, 4
>  %344 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %343)
>  %345 = fmul float %344, %84
>  %346 = fadd float %345, %329
>  %347 = shl i32 %342, 4
>  %348 = add i32 %347, 4
>  %349 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %348)
>  %350 = fmul float %349, %84
>  %351 = fadd float %350, %333
>  %352 = shl i32 %342, 4
>  %353 = add i32 %352, 8
>  %354 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %353)
>  %355 = fmul float %354, %84
>  %356 = fadd float %355, %337
>  %357 = shl i32 %342, 4
>  %358 = add i32 %357, 12
>  %359 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %358)
>  %360 = fmul float %359, %84
>  %361 = fadd float %360, %341
>  %362 = bitcast float %317 to i32
>  %363 = shl i32 %362, 4
>  %364 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %363)
>  %365 = fmul float %364, %85
>  %366 = fadd float %365, %346
>  %367 = shl i32 %362, 4
>  %368 = add i32 %367, 4
>  %369 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %368)
>  %370 = fmul float %369, %85
>  %371 = fadd float %370, %351
>  %372 = shl i32 %362, 4
>  %373 = add i32 %372, 8
>  %374 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %373)
>  %375 = fmul float %374, %85
>  %376 = fadd float %375, %356
>  %377 = shl i32 %362, 4
>  %378 = add i32 %377, 12
>  %379 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %378)
>  %380 = fmul float %379, %85
>  %381 = fadd float %380, %361
>  %382 = bitcast float %313 to i32
>  %383 = shl i32 %382, 4
>  %384 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %383)
>  %385 = fmul float %384, %113
>  %386 = fadd float %385, %366
>  %387 = shl i32 %382, 4
>  %388 = add i32 %387, 4
>  %389 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %388)
>  %390 = fmul float %389, %113
>  %391 = fadd float %390, %371
>  %392 = shl i32 %382, 4
>  %393 = add i32 %392, 8
>  %394 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %393)
>  %395 = fmul float %394, %113
>  %396 = fadd float %395, %376
>  %397 = shl i32 %382, 4
>  %398 = add i32 %397, 12
>  %399 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %398)
>  %400 = fmul float %399, %113
>  %401 = fadd float %400, %381
>  %402 = fmul float %56, %202
>  %403 = fmul float %57, %207
>  %404 = fadd float %402, %403
>  %405 = fmul float %58, %212
>  %406 = fadd float %404, %405
>  %407 = fmul float %59, %217
>  %408 = fadd float %406, %407
>  %409 = fmul float %56, %294
>  %410 = fmul float %57, %299
>  %411 = fadd float %409, %410
>  %412 = fmul float %58, %304
>  %413 = fadd float %411, %412
>  %414 = fmul float %59, %309
>  %415 = fadd float %413, %414
>  %416 = fmul float %56, %386
>  %417 = fmul float %57, %391
>  %418 = fadd float %416, %417
>  %419 = fmul float %58, %396
>  %420 = fadd float %418, %419
>  %421 = fmul float %59, %401
>  %422 = fadd float %420, %421
>  %423 = fmul float %99, %202
>  %424 = fmul float %104, %207
>  %425 = fadd float %424, %423
>  %426 = fmul float %103, %212
>  %427 = fadd float %425, %426
>  %428 = fmul float %99, %294
>  %429 = fmul float %104, %299
>  %430 = fadd float %429, %428
>  %431 = fmul float %103, %304
>  %432 = fadd float %430, %431
>  %433 = fmul float %99, %386
>  %434 = fmul float %104, %391
>  %435 = fadd float %434, %433
>  %436 = fmul float %103, %396
>  %437 = fadd float %435, %436
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %408, %IF ], [ %56, %main_body ]
>  %temp1.0 = phi float [ %415, %IF ], [ %57, %main_body ]
>  %temp2.0 = phi float [ %422, %IF ], [ %58, %main_body ]
>  %temp8.0 = phi float [ %427, %IF ], [ %99, %main_body ]
>  %temp9.0 = phi float [ %432, %IF ], [ %104, %main_body ]
>  %temp10.0 = phi float [ %437, %IF ], [ %103, %main_body ]
>  %438 = fmul float %temp.0, %11
>  %439 = fmul float %temp1.0, %12
>  %440 = fadd float %438, %439
>  %441 = fmul float %temp2.0, %13
>  %442 = fadd float %440, %441
>  %443 = fmul float %59, %14
>  %444 = fadd float %442, %443
>  %445 = fmul float %temp.0, %15
>  %446 = fmul float %temp1.0, %16
>  %447 = fadd float %445, %446
>  %448 = fmul float %temp2.0, %17
>  %449 = fadd float %447, %448
>  %450 = fmul float %59, %18
>  %451 = fadd float %449, %450
>  %452 = fmul float %temp.0, %19
>  %453 = fmul float %temp1.0, %20
>  %454 = fadd float %452, %453
>  %455 = fmul float %temp2.0, %21
>  %456 = fadd float %454, %455
>  %457 = fmul float %59, %22
>  %458 = fadd float %456, %457
>  %459 = fmul float %temp.0, %23
>  %460 = fmul float %temp1.0, %24
>  %461 = fadd float %459, %460
>  %462 = fmul float %temp2.0, %25
>  %463 = fadd float %461, %462
>  %464 = fmul float %59, %26
>  %465 = fadd float %463, %464
>  %466 = fmul float %temp8.0, %27
>  %467 = fmul float %temp9.0, %28
>  %468 = fadd float %467, %466
>  %469 = fmul float %temp10.0, %29
>  %470 = fadd float %468, %469
>  %471 = fmul float %temp8.0, %30
>  %472 = fmul float %temp9.0, %31
>  %473 = fadd float %472, %471
>  %474 = fmul float %temp10.0, %32
>  %475 = fadd float %473, %474
>  %476 = fmul float %temp8.0, %33
>  %477 = fmul float %temp9.0, %34
>  %478 = fadd float %477, %476
>  %479 = fmul float %temp10.0, %35
>  %480 = fadd float %478, %479
>  %481 = fsub float -0.000000e+00, %475
>  %482 = fmul float %temp.0, %44
>  %483 = fmul float %temp1.0, %45
>  %484 = fadd float %482, %483
>  %485 = fmul float %temp2.0, %46
>  %486 = fadd float %484, %485
>  %487 = fmul float %59, %47
>  %488 = fadd float %486, %487
>  %489 = fadd float %488, 0xBFB99999A0000000
>  %490 = fmul float %69, %36
>  %491 = fmul float %70, %37
>  %492 = fadd float %490, %491
>  %493 = fmul float %71, %38
>  %494 = fadd float %492, %493
>  %495 = fmul float %72, %39
>  %496 = fadd float %494, %495
>  %497 = fmul float %69, %40
>  %498 = fmul float %70, %41
>  %499 = fadd float %497, %498
>  %500 = fmul float %71, %42
>  %501 = fadd float %499, %500
>  %502 = fmul float %72, %43
>  %503 = fadd float %501, %502
>  %504 = fmul float %96, %48
>  %505 = fadd float %504, %49
>  %506 = fmul float %95, %48
>  %507 = fadd float %506, %49
>  %508 = fmul float %94, %48
>  %509 = fadd float %508, %49
>  %510 = fmul float %97, %48
>  %511 = fadd float %510, %49
>  %512 = fmul float %505, %505
>  %513 = fmul float %507, %507
>  %514 = fmul float %509, %509
>  %515 = call float @llvm.AMDGPU.lrp(float %511, float %512, float 1.000000e+00)
>  %516 = call float @llvm.AMDGPU.lrp(float %511, float %513, float 1.000000e+00)
>  %517 = call float @llvm.AMDGPU.lrp(float %511, float %514, float 1.000000e+00)
>  %518 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %519 = load <16 x i8> addrspace(2)* %518, !tbaa !0
>  %520 = call float @llvm.SI.load.const(<16 x i8> %519, i32 0)
>  %521 = fmul float %520, %444
>  %522 = call float @llvm.SI.load.const(<16 x i8> %519, i32 4)
>  %523 = fmul float %522, %451
>  %524 = fadd float %521, %523
>  %525 = call float @llvm.SI.load.const(<16 x i8> %519, i32 8)
>  %526 = fmul float %525, %458
>  %527 = fadd float %524, %526
>  %528 = call float @llvm.SI.load.const(<16 x i8> %519, i32 12)
>  %529 = fmul float %528, %465
>  %530 = fadd float %527, %529
>  %531 = call float @llvm.SI.load.const(<16 x i8> %519, i32 16)
>  %532 = fmul float %531, %444
>  %533 = call float @llvm.SI.load.const(<16 x i8> %519, i32 20)
>  %534 = fmul float %533, %451
>  %535 = fadd float %532, %534
>  %536 = call float @llvm.SI.load.const(<16 x i8> %519, i32 24)
>  %537 = fmul float %536, %458
>  %538 = fadd float %535, %537
>  %539 = call float @llvm.SI.load.const(<16 x i8> %519, i32 28)
>  %540 = fmul float %539, %465
>  %541 = fadd float %538, %540
>  %542 = call float @llvm.SI.load.const(<16 x i8> %519, i32 32)
>  %543 = fmul float %542, %444
>  %544 = call float @llvm.SI.load.const(<16 x i8> %519, i32 36)
>  %545 = fmul float %544, %451
>  %546 = fadd float %543, %545
>  %547 = call float @llvm.SI.load.const(<16 x i8> %519, i32 40)
>  %548 = fmul float %547, %458
>  %549 = fadd float %546, %548
>  %550 = call float @llvm.SI.load.const(<16 x i8> %519, i32 44)
>  %551 = fmul float %550, %465
>  %552 = fadd float %549, %551
>  %553 = call float @llvm.SI.load.const(<16 x i8> %519, i32 48)
>  %554 = fmul float %553, %444
>  %555 = call float @llvm.SI.load.const(<16 x i8> %519, i32 52)
>  %556 = fmul float %555, %451
>  %557 = fadd float %554, %556
>  %558 = call float @llvm.SI.load.const(<16 x i8> %519, i32 56)
>  %559 = fmul float %558, %458
>  %560 = fadd float %557, %559
>  %561 = call float @llvm.SI.load.const(<16 x i8> %519, i32 60)
>  %562 = fmul float %561, %465
>  %563 = fadd float %560, %562
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %530, float %541, float %552, float %563)
>  %564 = call float @llvm.SI.load.const(<16 x i8> %519, i32 64)
>  %565 = fmul float %564, %444
>  %566 = call float @llvm.SI.load.const(<16 x i8> %519, i32 68)
>  %567 = fmul float %566, %451
>  %568 = fadd float %565, %567
>  %569 = call float @llvm.SI.load.const(<16 x i8> %519, i32 72)
>  %570 = fmul float %569, %458
>  %571 = fadd float %568, %570
>  %572 = call float @llvm.SI.load.const(<16 x i8> %519, i32 76)
>  %573 = fmul float %572, %465
>  %574 = fadd float %571, %573
>  %575 = call float @llvm.SI.load.const(<16 x i8> %519, i32 80)
>  %576 = fmul float %575, %444
>  %577 = call float @llvm.SI.load.const(<16 x i8> %519, i32 84)
>  %578 = fmul float %577, %451
>  %579 = fadd float %576, %578
>  %580 = call float @llvm.SI.load.const(<16 x i8> %519, i32 88)
>  %581 = fmul float %580, %458
>  %582 = fadd float %579, %581
>  %583 = call float @llvm.SI.load.const(<16 x i8> %519, i32 92)
>  %584 = fmul float %583, %465
>  %585 = fadd float %582, %584
>  %586 = call float @llvm.SI.load.const(<16 x i8> %519, i32 96)
>  %587 = fmul float %586, %444
>  %588 = call float @llvm.SI.load.const(<16 x i8> %519, i32 100)
>  %589 = fmul float %588, %451
>  %590 = fadd float %587, %589
>  %591 = call float @llvm.SI.load.const(<16 x i8> %519, i32 104)
>  %592 = fmul float %591, %458
>  %593 = fadd float %590, %592
>  %594 = call float @llvm.SI.load.const(<16 x i8> %519, i32 108)
>  %595 = fmul float %594, %465
>  %596 = fadd float %593, %595
>  %597 = call float @llvm.SI.load.const(<16 x i8> %519, i32 112)
>  %598 = fmul float %597, %444
>  %599 = call float @llvm.SI.load.const(<16 x i8> %519, i32 116)
>  %600 = fmul float %599, %451
>  %601 = fadd float %598, %600
>  %602 = call float @llvm.SI.load.const(<16 x i8> %519, i32 120)
>  %603 = fmul float %602, %458
>  %604 = fadd float %601, %603
>  %605 = call float @llvm.SI.load.const(<16 x i8> %519, i32 124)
>  %606 = fmul float %605, %465
>  %607 = fadd float %604, %606
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %574, float %585, float %596, float %607)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %496, float %503, float %89, float %90)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %470, float %481, float %480, float %489)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %515, float %516, float %517, float %511)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %444, float %451, float %458, float %465)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80021300
>c0840100
>bf8c0070
>c201092a
>c201892b
>bf8c007f
>7e2e0203
>d2820012
>045c0515
>d2820005
>045c0513
>c0860718
>bf8c007f
>e00c2000
>80030100
>c0860714
>bf8c0070
>e00c2000
>80030600
>c0860710
>bf8c0070
>e00c2000
>80032a00
>c086070c
>bf8c0070
>e00c2000
>80034200
>c0860708
>bf8c0070
>e00c2000
>80030e00
>c0820700
>bf8c0070
>e00c2000
>80010a00
>d2820000
>045c0514
>064600ff
>3a83126f
>be8203ff
>00000f00
>c2010802
>bf8c0070
>d10a0002
>02010002
>c2020929
>c2028928
>c2030927
>c2038926
>c2060925
>c2068924
>c2070923
>c2078922
>c2080921
>c2088920
>c209091f
>c209891e
>c20a091d
>c20a891c
>c20b091a
>c20b8919
>c20c0918
>c20c8916
>c20d0915
>c20d8914
>c20e0912
>c20e8911
>c20f0910
>c20f890f
>c210090e
>c210890d
>c211090c
>c211890b
>c212090a
>c2128909
>c2130908
>c2138907
>c2140906
>c2148905
>c2150904
>c2158903
>c2160902
>c2168901
>c2170900
>bf8c007f
>7e000204
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>7e280206
>7e2a0207
>7e2e020c
>7e2c020d
>7e38020e
>7e40020f
>7e500210
>7e4e0211
>7e360212
>7e3e0213
>7e4c0214
>7e4a0215
>7e340216
>7e3c0217
>7e440218
>7e300219
>7e32021a
>7e3a021b
>7e42021c
>7e48021d
>7e52021e
>7e5c021f
>7e5e0220
>7e620221
>7e600222
>7e640223
>7e660224
>7e6a0225
>7e680226
>7e6c0227
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>7e720229
>7e70022a
>7e74022b
>7e76022c
>7e7a022d
>7e78022e
>7e7c030a
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>be822402
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>4a7c92ab
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>e0301000
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>e0301000
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>bf8c0770
>10a25551
>d282004b
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>e0301000
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>05527d55
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>04b25404
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>04b2693e
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>04b2650d
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>04b65804
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>d282002d
>04b6613e
>d282002d
>04b65f3f
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>04b65d0d
>c202010f
>bf8c007f
>d282002e
>04ca5a04
>c2020109
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>105e5604
>c2020108
>bf8c007f
>d282002f
>04be5404
>c202010a
>bf8c007f
>d282002f
>04be5804
>c202010b
>bf8c007f
>d282002f
>04be5a04
>c2020105
>bf8c007f
>10605604
>c2020104
>bf8c007f
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>c2020106
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>d2820030
>04c25804
>c2020107
>bf8c007f
>d2820030
>04c25a04
>c2020101
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>10625604
>c2020100
>bf8c007f
>d2820031
>04c65404
>c2020102
>bf8c007f
>d2820031
>04c65804
>c2020103
>bf8c007f
>d2820031
>04c65a04
>f80000ef
>2e2f3031
>c202011d
>bf8c000f
>105c5604
>c202011c
>bf8c007f
>d282002e
>04ba5404
>c202011e
>bf8c007f
>d282002e
>04ba5804
>c202011f
>bf8c007f
>d282002e
>04ba5a04
>c2020119
>bf8c007f
>105e5604
>c2020118
>bf8c007f
>d282002f
>04be5404
>c202011a
>bf8c007f
>d282002f
>04be5804
>c202011b
>bf8c007f
>d282002f
>04be5a04
>c2020115
>bf8c007f
>10605604
>c2020114
>bf8c007f
>d2820030
>04c25404
>c2020116
>bf8c007f
>d2820030
>04c25804
>c2020117
>bf8c007f
>d2820030
>04c25a04
>c2020111
>bf8c007f
>10625604
>c2020110
>bf8c007f
>d2820031
>04c65404
>c2020112
>bf8c007f
>d2820031
>04c65804
>c2000113
>bf8c007f
>d2820031
>04c65a00
>f80000ff
>2e2f3031
>1050510f
>d2820027
>04a24f0e
>d2820020
>049e4110
>d282001c
>04823911
>10404d0f
>d2820020
>04824b0e
>d282001f
>04823f10
>d282000e
>047e3711
>f800020f
>07061c0e
>bf8c070f
>100c4505
>d2820006
>041a3d23
>d2820006
>041a3512
>100e5305
>d2820007
>041e4923
>d2820007
>041e4312
>100a3b05
>d2820005
>04163323
>d2820005
>04163112
>d2060005
>22010105
>10102f41
>d2820008
>04222d3e
>d2820008
>04222b3f
>d2820008
>0422290d
>061010ff
>bdcccccd
>f800021f
>08060507
>bf8c070f
>d2820005
>04022704
>080c0af2
>d2820007
>04022701
>100e0f07
>d2820007
>041a0f05
>d2820008
>04022702
>10101108
>d2820008
>041a1105
>d2820000
>04022703
>10000100
>d2820000
>041a0105
>f800022f
>05070800
>f80008cf
>2d2c2b2a
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV OUT[0], IMM[0].xxxx
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
>  %21 = bitcast i32 %20 to float
>  %22 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
>  %23 = bitcast i32 %22 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %21, float %23, float %21, float %23)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>SI CODE:
>d25e0000
>0201e4f2
>f8001c0f
>00000000
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..6]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: MOV TEMP[0].xyz, TEMP[0].xyzx
>  6: MOV TEMP[0].w, IMM[0].xxxx
>  7: DP4 TEMP[1].x, TEMP[0], CONST[3]
>  8: DP4 TEMP[2].x, TEMP[0], CONST[4]
>  9: MOV TEMP[1].y, TEMP[2].xxxx
> 10: DP4 TEMP[2].x, TEMP[0], CONST[5]
> 11: MOV TEMP[1].z, TEMP[2].xxxx
> 12: DP4 TEMP[0].x, TEMP[0], CONST[6]
> 13: MOV TEMP[1].w, TEMP[0].xxxx
> 14: MOV OUT[0], TEMP[1]
> 15: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %40, i32 0, i32 %5)
>  %42 = extractelement <4 x float> %41, i32 0
>  %43 = extractelement <4 x float> %41, i32 1
>  %44 = extractelement <4 x float> %41, i32 2
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %42, %11
>  %47 = fmul float %43, %12
>  %48 = fadd float %46, %47
>  %49 = fmul float %44, %13
>  %50 = fadd float %48, %49
>  %51 = fmul float %45, %14
>  %52 = fadd float %50, %51
>  %53 = fmul float %42, %15
>  %54 = fmul float %43, %16
>  %55 = fadd float %53, %54
>  %56 = fmul float %44, %17
>  %57 = fadd float %55, %56
>  %58 = fmul float %45, %18
>  %59 = fadd float %57, %58
>  %60 = fmul float %42, %19
>  %61 = fmul float %43, %20
>  %62 = fadd float %60, %61
>  %63 = fmul float %44, %21
>  %64 = fadd float %62, %63
>  %65 = fmul float %45, %22
>  %66 = fadd float %64, %65
>  %67 = fmul float %52, %23
>  %68 = fmul float %59, %24
>  %69 = fadd float %67, %68
>  %70 = fmul float %66, %25
>  %71 = fadd float %69, %70
>  %72 = fmul float 1.000000e+00, %26
>  %73 = fadd float %71, %72
>  %74 = fmul float %52, %27
>  %75 = fmul float %59, %28
>  %76 = fadd float %74, %75
>  %77 = fmul float %66, %29
>  %78 = fadd float %76, %77
>  %79 = fmul float 1.000000e+00, %30
>  %80 = fadd float %78, %79
>  %81 = fmul float %52, %31
>  %82 = fmul float %59, %32
>  %83 = fadd float %81, %82
>  %84 = fmul float %66, %33
>  %85 = fadd float %83, %84
>  %86 = fmul float 1.000000e+00, %34
>  %87 = fadd float %85, %86
>  %88 = fmul float %52, %35
>  %89 = fmul float %59, %36
>  %90 = fadd float %88, %89
>  %91 = fmul float %66, %37
>  %92 = fadd float %90, %91
>  %93 = fmul float 1.000000e+00, %38
>  %94 = fadd float %92, %93
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %73, float %80, float %87, float %94)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010200
>c0800100
>bf8c0070
>c2020101
>bf8c007f
>10000604
>c2020100
>bf8c007f
>d2820000
>04000902
>c2020102
>bf8c007f
>d2820000
>04000904
>c2020103
>bf8c007f
>d2820000
>04000905
>c2020105
>bf8c007f
>10020604
>c2020104
>bf8c007f
>d2820001
>04040902
>c2020106
>bf8c007f
>d2820001
>04040904
>c2020107
>bf8c007f
>d2820001
>04040905
>c2020119
>bf8c007f
>100c0204
>c2020118
>bf8c007f
>d2820006
>04180900
>c2020109
>bf8c007f
>100e0604
>c2020108
>bf8c007f
>d2820007
>041c0902
>c202010a
>bf8c007f
>d2820007
>041c0904
>c202010b
>bf8c007f
>d2820002
>041c0905
>c202011a
>bf8c007f
>d2820003
>04180902
>c202011b
>bf8c007f
>06060604
>c2020115
>bf8c007f
>10080204
>c2020114
>bf8c007f
>d2820004
>04100900
>c2020116
>bf8c007f
>d2820004
>04100902
>c2020117
>bf8c007f
>06080804
>c2020111
>bf8c007f
>100a0204
>c2020110
>bf8c007f
>d2820005
>04140900
>c2020112
>bf8c007f
>d2820005
>04140902
>c2020113
>bf8c007f
>060a0a04
>c202010d
>bf8c007f
>10020204
>c202010c
>bf8c007f
>d2820000
>04040900
>c202010e
>bf8c007f
>d2820000
>04000902
>c200010f
>bf8c007f
>06000000
>f80008cf
>03040500
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {32767.0000,     7.9688,     0.0000,   128.0000}
>IMM[1] FLT32 {    0.0039,     0.0000,    32.0000,   -16.0000}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  2: MIN TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
>  3: MAX TEMP[1].x, TEMP[0].xxxx, TEMP[0].yyyy
>  4: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[0].zzzz
>  5: ADD TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
>  6: LG2 TEMP[1].x, TEMP[1].xxxx
>  7: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].wwww
>  8: CEIL TEMP[1].x, TEMP[1].xxxx
>  9: MUL TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
> 10: MAX TEMP[1].x, TEMP[1].xxxx, IMM[1].yyyy
> 11: MAD TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz, IMM[1].wwww
> 12: EX2 TEMP[2].x, TEMP[2].xxxx
> 13: RCP TEMP[2].x, TEMP[2].xxxx
> 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
> 15: MOV TEMP[0].w, TEMP[1].xxxx
> 16: MOV OUT[0], TEMP[0]
> 17: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %21 = load <32 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %25 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %26 = bitcast float %24 to i32
>  %27 = bitcast float %25 to i32
>  %28 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %29 = insertelement <2 x i32> %28, i32 %27, i32 1
>  %30 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %29, <32 x i8> %21, <16 x i8> %23, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = extractelement <4 x float> %30, i32 2
>  %34 = fcmp uge float %31, 3.276700e+04
>  %35 = select i1 %34, float 3.276700e+04, float %31
>  %36 = fcmp uge float %32, 3.276700e+04
>  %37 = select i1 %36, float 3.276700e+04, float %32
>  %38 = fcmp uge float %33, 3.276700e+04
>  %39 = select i1 %38, float 3.276700e+04, float %33
>  %40 = fcmp uge float %35, %37
>  %41 = select i1 %40, float %35, float %37
>  %42 = fcmp uge float %41, %39
>  %43 = select i1 %42, float %41, float %39
>  %44 = fadd float %43, 0x3EE0000000000000
>  %45 = call float @llvm.log2.f32(float %44)
>  %46 = fmul float 7.968750e+00, %45
>  %47 = fadd float %46, 1.280000e+02
>  %48 = call float @ceil(float %47)
>  %49 = fmul float %48, 0x3F70101020000000
>  %50 = fcmp uge float %49, 0.000000e+00
>  %51 = select i1 %50, float %49, float 0.000000e+00
>  %52 = fmul float %51, 3.200000e+01
>  %53 = fadd float %52, -1.600000e+01
>  %54 = call float @llvm.AMDIL.exp.(float %53)
>  %55 = fdiv float 1.000000e+00, %54
>  %56 = fmul float %35, %55
>  %57 = fmul float %37, %55
>  %58 = fmul float %39, %55
>  %59 = call i32 @llvm.SI.packf16(float %56, float %57)
>  %60 = bitcast i32 %59 to float
>  %61 = call i32 @llvm.SI.packf16(float %58, float %51)
>  %62 = bitcast i32 %61 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.log2.f32(float) #2
>
>; Function Attrs: readonly
>declare float @ceil(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #4
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>attributes #3 = { readonly }
>attributes #4 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0800300
>c0c20500
>bf8c007f
>f0800700
>00010202
>7e0a02ff
>46fffe00
>bf8c0770
>d00c0000
>02020b03
>d2000000
>00020b03
>d00c0000
>02020b02
>d2000001
>00020b02
>d00c0000
>02020101
>d2000006
>00020300
>d00c0000
>02020b04
>d2000002
>00020b04
>d00c0000
>02020506
>d2000003
>00020d02
>060606ff
>37000000
>7e064f03
>7e0802ff
>43000000
>7e0a02ff
>40ff0000
>d2820003
>04120b03
>7e064503
>100606ff
>3b808081
>d00c0000
>02010103
>d2000003
>00020680
>7e0802ff
>c1800000
>7e0a02ff
>42000000
>d2820004
>04120b03
>7e084b04
>7e085504
>10040902
>5e040702
>10000900
>10020901
>5e000101
>f8001c0f
>02000200
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..13]
>DCL TEMP[0], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].w, IMM[0].xxxx
>  1: MOV TEMP[0].z, IMM[0].yyyy
>  2: MAD TEMP[0].x, IN[0].zzzz, CONST[0].zzzz, CONST[0].yyyy
>  3: MOV_SAT TEMP[0].x, TEMP[0].xxxx
>  4: MOV TEMP[0].x, TEMP[0].xxxx
>  5: MUL TEMP[0].x, TEMP[0].xxxx, CONST[0].wwww
>  6: MOV TEMP[0].y, IMM[0].yyyy
>  7: MOV OUT[0], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %26 = fmul float %25, %23
>  %27 = fadd float %26, %22
>  %28 = call float @llvm.AMDIL.clamp.(float %27, float 0.000000e+00, float 1.000000e+00)
>  %29 = fmul float %28, %24
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %29, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080200
>c8090201
>c0800100
>bf8c007f
>c2020102
>c2028101
>bf8c007f
>7e000205
>d2820000
>04000902
>d2060800
>02010100
>c2000103
>bf8c007f
>10000000
>7e0202f2
>7e040280
>f800180f
>01020200
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL CONST[0..240]
>DCL TEMP[0..7], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    1.0000,   255.0100,     0.0000,     0.0000}
>IMM[1] INT32 {3, 41, 42, 43}
>  0: MOV TEMP[0], IN[0]
>  1: UIF CONST[240].xxxx :0
>  2:   DP3 TEMP[1].x, IN[3].xyzz, IMM[0].xxxx
>  3:   ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
>  4:   MUL TEMP[2], IN[2], IMM[0].yyyy
>  5:   F2I TEMP[2], TEMP[2]
>  6:   UMAD TEMP[3].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].yyyy
>  7:   UMAD TEMP[4].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].yyyy
>  8:   UMAD TEMP[5].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].yyyy
>  9:   UMAD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy
> 10:   UARL ADDR[0].x, TEMP[6].xxxx
> 11:   MUL TEMP[6], CONST[ADDR[0].x], IN[3].xxxx
> 12:   UARL ADDR[0].x, TEMP[5].xxxx
> 13:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].yyyy, TEMP[6]
> 14:   UARL ADDR[0].x, TEMP[4].xxxx
> 15:   MAD TEMP[4], CONST[ADDR[0].x], IN[3].zzzz, TEMP[5]
> 16:   UARL ADDR[0].x, TEMP[3].xxxx
> 17:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[4]
> 18:   DP4 TEMP[3].x, IN[0], TEMP[3]
> 19:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].zzzz
> 20:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].zzzz
> 21:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].zzzz
> 22:   UMAD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].zzzz
> 23:   UARL ADDR[0].x, TEMP[7].xxxx
> 24:   MUL TEMP[7], CONST[ADDR[0].x], IN[3].xxxx
> 25:   UARL ADDR[0].x, TEMP[6].xxxx
> 26:   MAD TEMP[6], CONST[ADDR[0].x], IN[3].yyyy, TEMP[7]
> 27:   UARL ADDR[0].x, TEMP[5].xxxx
> 28:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].zzzz, TEMP[6]
> 29:   UARL ADDR[0].x, TEMP[4].xxxx
> 30:   MAD TEMP[4], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[5]
> 31:   DP4 TEMP[4].x, IN[0], TEMP[4]
> 32:   MOV TEMP[3].y, TEMP[4].xxxx
> 33:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].wwww
> 34:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].wwww
> 35:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].wwww
> 36:   UMAD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].wwww
> 37:   UARL ADDR[0].x, TEMP[2].xxxx
> 38:   MUL TEMP[2], CONST[ADDR[0].x], IN[3].xxxx
> 39:   UARL ADDR[0].x, TEMP[6].xxxx
> 40:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].yyyy, TEMP[2]
> 41:   UARL ADDR[0].x, TEMP[5].xxxx
> 42:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].zzzz, TEMP[2]
> 43:   UARL ADDR[0].x, TEMP[4].xxxx
> 44:   MAD TEMP[1], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[2]
> 45:   DP4 TEMP[1].x, IN[0], TEMP[1]
> 46:   MOV TEMP[3].z, TEMP[1].xxxx
> 47:   MOV TEMP[0].xyz, TEMP[3].xyzx
> 48: ENDIF
> 49: DP4 TEMP[1].x, TEMP[0], CONST[0]
> 50: DP4 TEMP[2].x, TEMP[0], CONST[1]
> 51: MOV TEMP[1].y, TEMP[2].xxxx
> 52: DP4 TEMP[2].x, TEMP[0], CONST[2]
> 53: MOV TEMP[1].z, TEMP[2].xxxx
> 54: DP4 TEMP[2].x, TEMP[0], CONST[3]
> 55: MOV TEMP[1].w, TEMP[2].xxxx
> 56: DP4 TEMP[0].x, TEMP[0], CONST[9]
> 57: MOV TEMP[0].z, TEMP[0].xxxx
> 58: DP4 TEMP[2].x, IN[1], CONST[7]
> 59: DP4 TEMP[3].x, IN[1], CONST[8]
> 60: MOV TEMP[2].y, TEMP[3].xxxx
> 61: MOV TEMP[0].xy, TEMP[2].xyxx
> 62: MOV TEMP[0].w, IMM[0].xxxx
> 63: MOV OUT[0], TEMP[1]
> 64: MOV OUT[2], TEMP[0]
> 65: MOV OUT[1], TEMP[1]
> 66: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 144)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 148)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 152)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 156)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3840)
>  %40 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
>  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %5)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
>  %49 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %48, i32 0, i32 %5)
>  %50 = extractelement <4 x float> %49, i32 0
>  %51 = extractelement <4 x float> %49, i32 1
>  %52 = extractelement <4 x float> %49, i32 2
>  %53 = extractelement <4 x float> %49, i32 3
>  %54 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
>  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %5)
>  %57 = extractelement <4 x float> %56, i32 0
>  %58 = extractelement <4 x float> %56, i32 1
>  %59 = extractelement <4 x float> %56, i32 2
>  %60 = extractelement <4 x float> %56, i32 3
>  %61 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %5)
>  %64 = extractelement <4 x float> %63, i32 0
>  %65 = extractelement <4 x float> %63, i32 1
>  %66 = extractelement <4 x float> %63, i32 2
>  %67 = bitcast float %39 to i32
>  %68 = icmp ne i32 %67, 0
>  br i1 %68, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %69 = fmul float %64, 1.000000e+00
>  %70 = fmul float %65, 1.000000e+00
>  %71 = fadd float %70, %69
>  %72 = fmul float %66, 1.000000e+00
>  %73 = fadd float %71, %72
>  %74 = fsub float -0.000000e+00, %73
>  %75 = fadd float 1.000000e+00, %74
>  %76 = fmul float %57, 0x406FE051E0000000
>  %77 = fmul float %58, 0x406FE051E0000000
>  %78 = fmul float %59, 0x406FE051E0000000
>  %79 = fmul float %60, 0x406FE051E0000000
>  %80 = fptosi float %76 to i32
>  %81 = fptosi float %77 to i32
>  %82 = fptosi float %78 to i32
>  %83 = fptosi float %79 to i32
>  %84 = bitcast i32 %80 to float
>  %85 = bitcast i32 %81 to float
>  %86 = bitcast i32 %82 to float
>  %87 = bitcast i32 %83 to float
>  %88 = bitcast float %87 to i32
>  %89 = mul i32 %88, 3
>  %90 = add i32 %89, 41
>  %91 = bitcast i32 %90 to float
>  %92 = bitcast float %86 to i32
>  %93 = mul i32 %92, 3
>  %94 = add i32 %93, 41
>  %95 = bitcast i32 %94 to float
>  %96 = bitcast float %85 to i32
>  %97 = mul i32 %96, 3
>  %98 = add i32 %97, 41
>  %99 = bitcast i32 %98 to float
>  %100 = bitcast float %84 to i32
>  %101 = mul i32 %100, 3
>  %102 = add i32 %101, 41
>  %103 = bitcast i32 %102 to float
>  %104 = bitcast float %103 to i32
>  %105 = shl i32 %104, 4
>  %106 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %105)
>  %107 = fmul float %106, %64
>  %108 = shl i32 %104, 4
>  %109 = add i32 %108, 4
>  %110 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %109)
>  %111 = fmul float %110, %64
>  %112 = shl i32 %104, 4
>  %113 = add i32 %112, 8
>  %114 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %113)
>  %115 = fmul float %114, %64
>  %116 = shl i32 %104, 4
>  %117 = add i32 %116, 12
>  %118 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %117)
>  %119 = fmul float %118, %64
>  %120 = bitcast float %99 to i32
>  %121 = shl i32 %120, 4
>  %122 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %121)
>  %123 = fmul float %122, %65
>  %124 = fadd float %123, %107
>  %125 = shl i32 %120, 4
>  %126 = add i32 %125, 4
>  %127 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %126)
>  %128 = fmul float %127, %65
>  %129 = fadd float %128, %111
>  %130 = shl i32 %120, 4
>  %131 = add i32 %130, 8
>  %132 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %131)
>  %133 = fmul float %132, %65
>  %134 = fadd float %133, %115
>  %135 = shl i32 %120, 4
>  %136 = add i32 %135, 12
>  %137 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %136)
>  %138 = fmul float %137, %65
>  %139 = fadd float %138, %119
>  %140 = bitcast float %95 to i32
>  %141 = shl i32 %140, 4
>  %142 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %141)
>  %143 = fmul float %142, %66
>  %144 = fadd float %143, %124
>  %145 = shl i32 %140, 4
>  %146 = add i32 %145, 4
>  %147 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %146)
>  %148 = fmul float %147, %66
>  %149 = fadd float %148, %129
>  %150 = shl i32 %140, 4
>  %151 = add i32 %150, 8
>  %152 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %151)
>  %153 = fmul float %152, %66
>  %154 = fadd float %153, %134
>  %155 = shl i32 %140, 4
>  %156 = add i32 %155, 12
>  %157 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %156)
>  %158 = fmul float %157, %66
>  %159 = fadd float %158, %139
>  %160 = bitcast float %91 to i32
>  %161 = shl i32 %160, 4
>  %162 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %161)
>  %163 = fmul float %162, %75
>  %164 = fadd float %163, %144
>  %165 = shl i32 %160, 4
>  %166 = add i32 %165, 4
>  %167 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %166)
>  %168 = fmul float %167, %75
>  %169 = fadd float %168, %149
>  %170 = shl i32 %160, 4
>  %171 = add i32 %170, 8
>  %172 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %171)
>  %173 = fmul float %172, %75
>  %174 = fadd float %173, %154
>  %175 = shl i32 %160, 4
>  %176 = add i32 %175, 12
>  %177 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %176)
>  %178 = fmul float %177, %75
>  %179 = fadd float %178, %159
>  %180 = fmul float %43, %164
>  %181 = fmul float %44, %169
>  %182 = fadd float %180, %181
>  %183 = fmul float %45, %174
>  %184 = fadd float %182, %183
>  %185 = fmul float %46, %179
>  %186 = fadd float %184, %185
>  %187 = bitcast float %87 to i32
>  %188 = mul i32 %187, 3
>  %189 = add i32 %188, 42
>  %190 = bitcast i32 %189 to float
>  %191 = bitcast float %86 to i32
>  %192 = mul i32 %191, 3
>  %193 = add i32 %192, 42
>  %194 = bitcast i32 %193 to float
>  %195 = bitcast float %85 to i32
>  %196 = mul i32 %195, 3
>  %197 = add i32 %196, 42
>  %198 = bitcast i32 %197 to float
>  %199 = bitcast float %84 to i32
>  %200 = mul i32 %199, 3
>  %201 = add i32 %200, 42
>  %202 = bitcast i32 %201 to float
>  %203 = bitcast float %202 to i32
>  %204 = shl i32 %203, 4
>  %205 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %204)
>  %206 = fmul float %205, %64
>  %207 = shl i32 %203, 4
>  %208 = add i32 %207, 4
>  %209 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %208)
>  %210 = fmul float %209, %64
>  %211 = shl i32 %203, 4
>  %212 = add i32 %211, 8
>  %213 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %212)
>  %214 = fmul float %213, %64
>  %215 = shl i32 %203, 4
>  %216 = add i32 %215, 12
>  %217 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %216)
>  %218 = fmul float %217, %64
>  %219 = bitcast float %198 to i32
>  %220 = shl i32 %219, 4
>  %221 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %220)
>  %222 = fmul float %221, %65
>  %223 = fadd float %222, %206
>  %224 = shl i32 %219, 4
>  %225 = add i32 %224, 4
>  %226 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %225)
>  %227 = fmul float %226, %65
>  %228 = fadd float %227, %210
>  %229 = shl i32 %219, 4
>  %230 = add i32 %229, 8
>  %231 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %230)
>  %232 = fmul float %231, %65
>  %233 = fadd float %232, %214
>  %234 = shl i32 %219, 4
>  %235 = add i32 %234, 12
>  %236 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %235)
>  %237 = fmul float %236, %65
>  %238 = fadd float %237, %218
>  %239 = bitcast float %194 to i32
>  %240 = shl i32 %239, 4
>  %241 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %240)
>  %242 = fmul float %241, %66
>  %243 = fadd float %242, %223
>  %244 = shl i32 %239, 4
>  %245 = add i32 %244, 4
>  %246 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %245)
>  %247 = fmul float %246, %66
>  %248 = fadd float %247, %228
>  %249 = shl i32 %239, 4
>  %250 = add i32 %249, 8
>  %251 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %250)
>  %252 = fmul float %251, %66
>  %253 = fadd float %252, %233
>  %254 = shl i32 %239, 4
>  %255 = add i32 %254, 12
>  %256 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %255)
>  %257 = fmul float %256, %66
>  %258 = fadd float %257, %238
>  %259 = bitcast float %190 to i32
>  %260 = shl i32 %259, 4
>  %261 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %260)
>  %262 = fmul float %261, %75
>  %263 = fadd float %262, %243
>  %264 = shl i32 %259, 4
>  %265 = add i32 %264, 4
>  %266 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %265)
>  %267 = fmul float %266, %75
>  %268 = fadd float %267, %248
>  %269 = shl i32 %259, 4
>  %270 = add i32 %269, 8
>  %271 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %270)
>  %272 = fmul float %271, %75
>  %273 = fadd float %272, %253
>  %274 = shl i32 %259, 4
>  %275 = add i32 %274, 12
>  %276 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %275)
>  %277 = fmul float %276, %75
>  %278 = fadd float %277, %258
>  %279 = fmul float %43, %263
>  %280 = fmul float %44, %268
>  %281 = fadd float %279, %280
>  %282 = fmul float %45, %273
>  %283 = fadd float %281, %282
>  %284 = fmul float %46, %278
>  %285 = fadd float %283, %284
>  %286 = bitcast float %87 to i32
>  %287 = mul i32 %286, 3
>  %288 = add i32 %287, 43
>  %289 = bitcast i32 %288 to float
>  %290 = bitcast float %86 to i32
>  %291 = mul i32 %290, 3
>  %292 = add i32 %291, 43
>  %293 = bitcast i32 %292 to float
>  %294 = bitcast float %85 to i32
>  %295 = mul i32 %294, 3
>  %296 = add i32 %295, 43
>  %297 = bitcast i32 %296 to float
>  %298 = bitcast float %84 to i32
>  %299 = mul i32 %298, 3
>  %300 = add i32 %299, 43
>  %301 = bitcast i32 %300 to float
>  %302 = bitcast float %301 to i32
>  %303 = shl i32 %302, 4
>  %304 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %303)
>  %305 = fmul float %304, %64
>  %306 = shl i32 %302, 4
>  %307 = add i32 %306, 4
>  %308 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %307)
>  %309 = fmul float %308, %64
>  %310 = shl i32 %302, 4
>  %311 = add i32 %310, 8
>  %312 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %311)
>  %313 = fmul float %312, %64
>  %314 = shl i32 %302, 4
>  %315 = add i32 %314, 12
>  %316 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %315)
>  %317 = fmul float %316, %64
>  %318 = bitcast float %297 to i32
>  %319 = shl i32 %318, 4
>  %320 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %319)
>  %321 = fmul float %320, %65
>  %322 = fadd float %321, %305
>  %323 = shl i32 %318, 4
>  %324 = add i32 %323, 4
>  %325 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %324)
>  %326 = fmul float %325, %65
>  %327 = fadd float %326, %309
>  %328 = shl i32 %318, 4
>  %329 = add i32 %328, 8
>  %330 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %329)
>  %331 = fmul float %330, %65
>  %332 = fadd float %331, %313
>  %333 = shl i32 %318, 4
>  %334 = add i32 %333, 12
>  %335 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %334)
>  %336 = fmul float %335, %65
>  %337 = fadd float %336, %317
>  %338 = bitcast float %293 to i32
>  %339 = shl i32 %338, 4
>  %340 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %339)
>  %341 = fmul float %340, %66
>  %342 = fadd float %341, %322
>  %343 = shl i32 %338, 4
>  %344 = add i32 %343, 4
>  %345 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %344)
>  %346 = fmul float %345, %66
>  %347 = fadd float %346, %327
>  %348 = shl i32 %338, 4
>  %349 = add i32 %348, 8
>  %350 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %349)
>  %351 = fmul float %350, %66
>  %352 = fadd float %351, %332
>  %353 = shl i32 %338, 4
>  %354 = add i32 %353, 12
>  %355 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %354)
>  %356 = fmul float %355, %66
>  %357 = fadd float %356, %337
>  %358 = bitcast float %289 to i32
>  %359 = shl i32 %358, 4
>  %360 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %359)
>  %361 = fmul float %360, %75
>  %362 = fadd float %361, %342
>  %363 = shl i32 %358, 4
>  %364 = add i32 %363, 4
>  %365 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %364)
>  %366 = fmul float %365, %75
>  %367 = fadd float %366, %347
>  %368 = shl i32 %358, 4
>  %369 = add i32 %368, 8
>  %370 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %369)
>  %371 = fmul float %370, %75
>  %372 = fadd float %371, %352
>  %373 = shl i32 %358, 4
>  %374 = add i32 %373, 12
>  %375 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %374)
>  %376 = fmul float %375, %75
>  %377 = fadd float %376, %357
>  %378 = fmul float %43, %362
>  %379 = fmul float %44, %367
>  %380 = fadd float %378, %379
>  %381 = fmul float %45, %372
>  %382 = fadd float %380, %381
>  %383 = fmul float %46, %377
>  %384 = fadd float %382, %383
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %186, %IF ], [ %43, %main_body ]
>  %temp1.0 = phi float [ %285, %IF ], [ %44, %main_body ]
>  %temp2.0 = phi float [ %384, %IF ], [ %45, %main_body ]
>  %385 = fmul float %temp.0, %11
>  %386 = fmul float %temp1.0, %12
>  %387 = fadd float %385, %386
>  %388 = fmul float %temp2.0, %13
>  %389 = fadd float %387, %388
>  %390 = fmul float %46, %14
>  %391 = fadd float %389, %390
>  %392 = fmul float %temp.0, %15
>  %393 = fmul float %temp1.0, %16
>  %394 = fadd float %392, %393
>  %395 = fmul float %temp2.0, %17
>  %396 = fadd float %394, %395
>  %397 = fmul float %46, %18
>  %398 = fadd float %396, %397
>  %399 = fmul float %temp.0, %19
>  %400 = fmul float %temp1.0, %20
>  %401 = fadd float %399, %400
>  %402 = fmul float %temp2.0, %21
>  %403 = fadd float %401, %402
>  %404 = fmul float %46, %22
>  %405 = fadd float %403, %404
>  %406 = fmul float %temp.0, %23
>  %407 = fmul float %temp1.0, %24
>  %408 = fadd float %406, %407
>  %409 = fmul float %temp2.0, %25
>  %410 = fadd float %408, %409
>  %411 = fmul float %46, %26
>  %412 = fadd float %410, %411
>  %413 = fmul float %temp.0, %35
>  %414 = fmul float %temp1.0, %36
>  %415 = fadd float %413, %414
>  %416 = fmul float %temp2.0, %37
>  %417 = fadd float %415, %416
>  %418 = fmul float %46, %38
>  %419 = fadd float %417, %418
>  %420 = fmul float %50, %27
>  %421 = fmul float %51, %28
>  %422 = fadd float %420, %421
>  %423 = fmul float %52, %29
>  %424 = fadd float %422, %423
>  %425 = fmul float %53, %30
>  %426 = fadd float %424, %425
>  %427 = fmul float %50, %31
>  %428 = fmul float %51, %32
>  %429 = fadd float %427, %428
>  %430 = fmul float %52, %33
>  %431 = fadd float %429, %430
>  %432 = fmul float %53, %34
>  %433 = fadd float %431, %432
>  %434 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %435 = load <16 x i8> addrspace(2)* %434, !tbaa !0
>  %436 = call float @llvm.SI.load.const(<16 x i8> %435, i32 0)
>  %437 = fmul float %436, %391
>  %438 = call float @llvm.SI.load.const(<16 x i8> %435, i32 4)
>  %439 = fmul float %438, %398
>  %440 = fadd float %437, %439
>  %441 = call float @llvm.SI.load.const(<16 x i8> %435, i32 8)
>  %442 = fmul float %441, %405
>  %443 = fadd float %440, %442
>  %444 = call float @llvm.SI.load.const(<16 x i8> %435, i32 12)
>  %445 = fmul float %444, %412
>  %446 = fadd float %443, %445
>  %447 = call float @llvm.SI.load.const(<16 x i8> %435, i32 16)
>  %448 = fmul float %447, %391
>  %449 = call float @llvm.SI.load.const(<16 x i8> %435, i32 20)
>  %450 = fmul float %449, %398
>  %451 = fadd float %448, %450
>  %452 = call float @llvm.SI.load.const(<16 x i8> %435, i32 24)
>  %453 = fmul float %452, %405
>  %454 = fadd float %451, %453
>  %455 = call float @llvm.SI.load.const(<16 x i8> %435, i32 28)
>  %456 = fmul float %455, %412
>  %457 = fadd float %454, %456
>  %458 = call float @llvm.SI.load.const(<16 x i8> %435, i32 32)
>  %459 = fmul float %458, %391
>  %460 = call float @llvm.SI.load.const(<16 x i8> %435, i32 36)
>  %461 = fmul float %460, %398
>  %462 = fadd float %459, %461
>  %463 = call float @llvm.SI.load.const(<16 x i8> %435, i32 40)
>  %464 = fmul float %463, %405
>  %465 = fadd float %462, %464
>  %466 = call float @llvm.SI.load.const(<16 x i8> %435, i32 44)
>  %467 = fmul float %466, %412
>  %468 = fadd float %465, %467
>  %469 = call float @llvm.SI.load.const(<16 x i8> %435, i32 48)
>  %470 = fmul float %469, %391
>  %471 = call float @llvm.SI.load.const(<16 x i8> %435, i32 52)
>  %472 = fmul float %471, %398
>  %473 = fadd float %470, %472
>  %474 = call float @llvm.SI.load.const(<16 x i8> %435, i32 56)
>  %475 = fmul float %474, %405
>  %476 = fadd float %473, %475
>  %477 = call float @llvm.SI.load.const(<16 x i8> %435, i32 60)
>  %478 = fmul float %477, %412
>  %479 = fadd float %476, %478
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %446, float %457, float %468, float %479)
>  %480 = call float @llvm.SI.load.const(<16 x i8> %435, i32 64)
>  %481 = fmul float %480, %391
>  %482 = call float @llvm.SI.load.const(<16 x i8> %435, i32 68)
>  %483 = fmul float %482, %398
>  %484 = fadd float %481, %483
>  %485 = call float @llvm.SI.load.const(<16 x i8> %435, i32 72)
>  %486 = fmul float %485, %405
>  %487 = fadd float %484, %486
>  %488 = call float @llvm.SI.load.const(<16 x i8> %435, i32 76)
>  %489 = fmul float %488, %412
>  %490 = fadd float %487, %489
>  %491 = call float @llvm.SI.load.const(<16 x i8> %435, i32 80)
>  %492 = fmul float %491, %391
>  %493 = call float @llvm.SI.load.const(<16 x i8> %435, i32 84)
>  %494 = fmul float %493, %398
>  %495 = fadd float %492, %494
>  %496 = call float @llvm.SI.load.const(<16 x i8> %435, i32 88)
>  %497 = fmul float %496, %405
>  %498 = fadd float %495, %497
>  %499 = call float @llvm.SI.load.const(<16 x i8> %435, i32 92)
>  %500 = fmul float %499, %412
>  %501 = fadd float %498, %500
>  %502 = call float @llvm.SI.load.const(<16 x i8> %435, i32 96)
>  %503 = fmul float %502, %391
>  %504 = call float @llvm.SI.load.const(<16 x i8> %435, i32 100)
>  %505 = fmul float %504, %398
>  %506 = fadd float %503, %505
>  %507 = call float @llvm.SI.load.const(<16 x i8> %435, i32 104)
>  %508 = fmul float %507, %405
>  %509 = fadd float %506, %508
>  %510 = call float @llvm.SI.load.const(<16 x i8> %435, i32 108)
>  %511 = fmul float %510, %412
>  %512 = fadd float %509, %511
>  %513 = call float @llvm.SI.load.const(<16 x i8> %435, i32 112)
>  %514 = fmul float %513, %391
>  %515 = call float @llvm.SI.load.const(<16 x i8> %435, i32 116)
>  %516 = fmul float %515, %398
>  %517 = fadd float %514, %516
>  %518 = call float @llvm.SI.load.const(<16 x i8> %435, i32 120)
>  %519 = fmul float %518, %405
>  %520 = fadd float %517, %519
>  %521 = call float @llvm.SI.load.const(<16 x i8> %435, i32 124)
>  %522 = fmul float %521, %412
>  %523 = fadd float %520, %522
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %490, float %501, float %512, float %523)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %426, float %433, float %419, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %391, float %398, float %405, float %412)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
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>046a2e04
>c2020111
>bf8c007f
>10362a04
>c2020110
>bf8c007f
>d282001b
>046e2804
>c2020112
>bf8c007f
>d282001b
>046e2c04
>c2000113
>bf8c007f
>d282001b
>046e2e00
>f80000ff
>18191a1b
>1026272a
>d2820012
>044e2529
>d282000d
>044a1b26
>d2820005
>04361508
>100c2302
>d2820006
>041a2101
>d2820006
>041a1903
>d2820006
>041a1304
>100e1f02
>d2820007
>041e1d01
>d2820007
>041e1703
>d2820000
>041e0104
>7e0202f2
>f800020f
>01050600
>f80008cf
>17161514
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..223]
>DCL TEMP[0..26], LOCAL
>IMM[0] FLT32 {    0.0000,     0.5000,     0.9500,    -1.0000}
>IMM[1] FLT32 {    2.0000,    -2.0000,    -1.0000,     1.0000}
>IMM[2] FLT32 {    0.2500,     0.5000,    -0.5000,     4.0000}
>IMM[3] FLT32 {    0.0000,     1.0000,     2.0000,     3.0000}
>IMM[4] INT32 {1, -1, 0, 0}
>IMM[5] FLT32 {   16.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].x, IMM[0].xxxx
>  1: MAD TEMP[1].xy, IN[0].xyyy, CONST[4].xyyy, IMM[0].yyyy
>  2: FRC TEMP[2].xy, TEMP[1].xyyy
>  3: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
>  4: ADD TEMP[1].xy, TEMP[1].xyyy, IMM[0].yyyy
>  5: MUL TEMP[1].xy, TEMP[1].xyyy, CONST[4].zwww
>  6: MOV TEMP[2].xy, TEMP[1].xyyy
>  7: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
>  8: ABS TEMP[3].x, TEMP[2].xxxx
>  9: MAD TEMP[3].x, TEMP[3].xxxx, CONST[1].yyyy, -CONST[1].xxxx
> 10: SLT TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz
> 11: F2I TEMP[4].x, -TEMP[4]
> 12: UIF TEMP[4].xxxx :0
> 13:   MOV TEMP[4].z, TEMP[3].xxxx
> 14:   MAD TEMP[4].xy, TEMP[1].xyyy, IMM[1].xyyy, IMM[1].zwww
> 15:   ADD TEMP[5].xy, TEMP[4].xyyy, CONST[2].ywww
> 16:   MUL TEMP[5].xy, -TEMP[3].xxxx, TEMP[5].xyyy
> 17:   RCP TEMP[6].x, CONST[2].xxxx
> 18:   RCP TEMP[6].y, CONST[2].zzzz
> 19:   MUL TEMP[4].xy, TEMP[5].xyyy, TEMP[6].xyyy
> 20:   MOV TEMP[5].y, IMM[0].xxxx
> 21:   MOV TEMP[5].x, -CONST[4].zzzz
> 22:   MOV TEMP[5].z, CONST[4].zzzz
> 23:   ADD TEMP[5].xyz, TEMP[1].xyxx, TEMP[5].xyzz
> 24:   MOV TEMP[6].x, IMM[0].xxxx
> 25:   MOV TEMP[6].y, -CONST[4].wwww
> 26:   MOV TEMP[6].z, CONST[4].wwww
> 27:   ADD TEMP[6].xyz, TEMP[1].xyyy, TEMP[6].xyzz
> 28:   MOV TEMP[7].xy, TEMP[5].xyyy
> 29:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 30:   MOV TEMP[7].x, TEMP[7].xxxx
> 31:   MOV TEMP[8].xy, TEMP[5].zyyy
> 32:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 33:   MOV TEMP[7].y, TEMP[8].xxxx
> 34:   MOV TEMP[8].xy, TEMP[6].xyyy
> 35:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 36:   MOV TEMP[7].z, TEMP[8].xxxx
> 37:   MOV TEMP[8].xy, TEMP[6].xzzz
> 38:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
> 39:   MOV TEMP[7].w, TEMP[8].xxxx
> 40:   ABS TEMP[7], TEMP[7]
> 41:   MAD TEMP[7], TEMP[7], CONST[1].yyyy, -CONST[1].xxxx
> 42:   ADD TEMP[8], TEMP[7], -TEMP[3].xxxx
> 43:   ABS TEMP[8], TEMP[8]
> 44:   MOV TEMP[9].w, IMM[0].wwww
> 45:   MOV TEMP[9].xy, TEMP[5].xyxx
> 46:   MOV TEMP[9].z, TEMP[7].xxxx
> 47:   MOV TEMP[10].w, IMM[1].wwww
> 48:   MOV TEMP[10].xy, TEMP[5].zyzz
> 49:   MOV TEMP[10].z, TEMP[7].yyyy
> 50:   MOV TEMP[5].w, IMM[0].wwww
> 51:   MOV TEMP[5].xy, TEMP[6].xyxx
> 52:   MOV TEMP[5].z, TEMP[7].zzzz
> 53:   MOV TEMP[11].w, IMM[1].wwww
> 54:   MOV TEMP[11].xy, TEMP[6].xzxx
> 55:   MOV TEMP[11].z, TEMP[7].wwww
> 56:   SLT TEMP[6].x, TEMP[8].xxxx, TEMP[8].yyyy
> 57:   F2I TEMP[6].x, -TEMP[6]
> 58:   UIF TEMP[6].xxxx :0
> 59:     MOV TEMP[6], TEMP[9]
> 60:   ELSE :0
> 61:     MOV TEMP[6], TEMP[10]
> 62:   ENDIF
> 63:   SLT TEMP[7].x, TEMP[8].zzzz, TEMP[8].wwww
> 64:   F2I TEMP[7].x, -TEMP[7]
> 65:   UIF TEMP[7].xxxx :0
> 66:     MOV TEMP[5], TEMP[5]
> 67:   ELSE :0
> 68:     MOV TEMP[5], TEMP[11]
> 69:   ENDIF
> 70:   MOV TEMP[7].z, TEMP[6].zzzz
> 71:   MAD TEMP[7].xy, TEMP[6].xyyy, IMM[1].xyyy, IMM[1].zwww
> 72:   ADD TEMP[8].xy, TEMP[7].xyyy, CONST[2].ywww
> 73:   MUL TEMP[8].xy, -TEMP[6].zzzz, TEMP[8].xyyy
> 74:   RCP TEMP[9].x, CONST[2].xxxx
> 75:   RCP TEMP[9].y, CONST[2].zzzz
> 76:   MUL TEMP[7].xy, TEMP[8].xyyy, TEMP[9].xyyy
> 77:   MOV TEMP[8].z, TEMP[5].zzzz
> 78:   MAD TEMP[8].xy, TEMP[5].xyyy, IMM[1].xyyy, IMM[1].zwww
> 79:   ADD TEMP[9].xy, TEMP[8].xyyy, CONST[2].ywww
> 80:   MUL TEMP[9].xy, -TEMP[5].zzzz, TEMP[9].xyyy
> 81:   RCP TEMP[10].x, CONST[2].xxxx
> 82:   RCP TEMP[10].y, CONST[2].zzzz
> 83:   MUL TEMP[8].xy, TEMP[9].xyyy, TEMP[10].xyyy
> 84:   ADD TEMP[7].xyz, TEMP[7].xyzz, -TEMP[4].xyzz
> 85:   MUL TEMP[6].xyz, TEMP[7].xyzz, TEMP[6].wwww
> 86:   ADD TEMP[7].xyz, TEMP[8].xyzz, -TEMP[4].xyzz
> 87:   MUL TEMP[5].xyz, TEMP[7].xyzz, TEMP[5].wwww
> 88:   MUL TEMP[7].xyz, TEMP[5].zxyy, TEMP[6].yzxx
> 89:   MAD TEMP[5].xyz, TEMP[5].yzxx, TEMP[6].zxyy, -TEMP[7].xyzz
> 90:   DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
> 91:   RSQ TEMP[6].x, TEMP[6].xxxx
> 92:   MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
> 93:   MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[3].xxxx
> 94:   MUL TEMP[6].xyz, TEMP[6].xyzz, CONST[0].zzzz
> 95:   ADD TEMP[4].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 96:   MUL TEMP[6].xy, CONST[3].xyyy, IMM[2].xxxx
> 97:   MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[6].xyyy
> 98:   MOV TEMP[1].xy, TEMP[1].xyyy
> 99:   TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
>100:   MAD TEMP[1].xyz, TEMP[1].xyzz, IMM[1].xxxx, IMM[0].wwww
>101:   MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[0].wwww
>102:   ADD TEMP[6].x, -TEMP[3].xxxx, -CONST[5].xxxx
>103:   MUL_SAT TEMP[6].x, TEMP[6].xxxx, CONST[5].wwww
>104:   MAD TEMP[6].x, CONST[5].zzzz, TEMP[6].xxxx, IMM[1].wwww
>105:   MUL_SAT TEMP[3].x, -TEMP[3].xxxx, CONST[5].yyyy
>106:   MUL TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
>107:   SLT TEMP[6].x, TEMP[2].xxxx, IMM[0].xxxx
>108:   F2I TEMP[6].x, -TEMP[6]
>109:   UIF TEMP[6].xxxx :0
>110:     MOV TEMP[6].x, CONST[6].xxxx
>111:   ELSE :0
>112:     MOV TEMP[6].x, TEMP[3].xxxx
>113:   ENDIF
>114:   MUL TEMP[3].x, TEMP[6].xxxx, CONST[6].zzzz
>115:   MUL TEMP[6].x, CONST[0].yyyy, TEMP[3].xxxx
>116:   SGE TEMP[7].x, TEMP[2].xxxx, IMM[0].xxxx
>117:   F2I TEMP[7].x, -TEMP[7]
>118:   AND TEMP[7].x, TEMP[7].xxxx, IMM[1].wwww
>119:   MUL TEMP[8], TEMP[6].xxxx, IMM[3]
>120:   MAD TEMP[3], CONST[0].xxxx, TEMP[3].xxxx, -TEMP[8]
>121:   DP3 TEMP[8].x, TEMP[1].xyzz, CONST[7].xyzz
>122:   MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[1].xyzz
>123:   MUL TEMP[8].xyz, IMM[1].xxxx, TEMP[8].xyzz
>124:   ADD TEMP[8].xyz, CONST[7].xyzz, -TEMP[8].xyzz
>125:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[3].xxxx
>126:   DP3 TEMP[9].x, TEMP[1].xyzz, CONST[8].xyzz
>127:   MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[1].xyzz
>128:   MUL TEMP[9].xyz, IMM[1].xxxx, TEMP[9].xyzz
>129:   ADD TEMP[9].xyz, CONST[8].xyzz, -TEMP[9].xyzz
>130:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[3].yyyy
>131:   DP3 TEMP[10].x, TEMP[1].xyzz, CONST[9].xyzz
>132:   MUL TEMP[10].xyz, TEMP[10].xxxx, TEMP[1].xyzz
>133:   MUL TEMP[10].xyz, IMM[1].xxxx, TEMP[10].xyzz
>134:   ADD TEMP[10].xyz, CONST[9].xyzz, -TEMP[10].xyzz
>135:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[3].zzzz
>136:   DP3 TEMP[11].x, TEMP[1].xyzz, CONST[10].xyzz
>137:   MUL TEMP[11].xyz, TEMP[11].xxxx, TEMP[1].xyzz
>138:   MUL TEMP[11].xyz, IMM[1].xxxx, TEMP[11].xyzz
>139:   ADD TEMP[11].xyz, CONST[10].xyzz, -TEMP[11].xyzz
>140:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[3].wwww
>141:   DP3 TEMP[12].x, TEMP[8].xyzz, TEMP[5].xyzz
>142:   DP3 TEMP[13].x, TEMP[9].xyzz, TEMP[5].xyzz
>143:   DP3 TEMP[14].x, TEMP[10].xyzz, TEMP[5].xyzz
>144:   DP3 TEMP[15].x, TEMP[11].xyzz, TEMP[5].xyzz
>145:   SGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
>146:   F2I TEMP[12].x, -TEMP[12]
>147:   UIF TEMP[12].xxxx :0
>148:     MOV TEMP[12].x, IMM[4].xxxx
>149:   ELSE :0
>150:     MOV TEMP[12].x, IMM[4].yyyy
>151:   ENDIF
>152:   I2F TEMP[12].x, TEMP[12].xxxx
>153:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[12].xxxx
>154:   SGE TEMP[12].x, TEMP[13].xxxx, IMM[0].xxxx
>155:   F2I TEMP[12].x, -TEMP[12]
>156:   UIF TEMP[12].xxxx :0
>157:     MOV TEMP[12].x, IMM[4].xxxx
>158:   ELSE :0
>159:     MOV TEMP[12].x, IMM[4].yyyy
>160:   ENDIF
>161:   I2F TEMP[12].x, TEMP[12].xxxx
>162:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[12].xxxx
>163:   SGE TEMP[12].x, TEMP[14].xxxx, IMM[0].xxxx
>164:   F2I TEMP[12].x, -TEMP[12]
>165:   UIF TEMP[12].xxxx :0
>166:     MOV TEMP[12].x, IMM[4].xxxx
>167:   ELSE :0
>168:     MOV TEMP[12].x, IMM[4].yyyy
>169:   ENDIF
>170:   I2F TEMP[12].x, TEMP[12].xxxx
>171:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[12].xxxx
>172:   SGE TEMP[12].x, TEMP[15].xxxx, IMM[0].xxxx
>173:   F2I TEMP[12].x, -TEMP[12]
>174:   UIF TEMP[12].xxxx :0
>175:     MOV TEMP[12].x, IMM[4].xxxx
>176:   ELSE :0
>177:     MOV TEMP[12].x, IMM[4].yyyy
>178:   ENDIF
>179:   I2F TEMP[12].x, TEMP[12].xxxx
>180:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].xxxx
>181:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>182:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[9].xyyy
>183:   MOV TEMP[12].zw, TEMP[13].yyxy
>184:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>185:   ADD TEMP[14].xy, TEMP[4].xyyy, TEMP[11].xyyy
>186:   MOV TEMP[13].zw, TEMP[14].yyxy
>187:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>188:   ADD TEMP[15].x, TEMP[4].zzzz, TEMP[9].zzzz
>189:   MOV TEMP[14].y, TEMP[15].xxxx
>190:   ADD TEMP[16].x, TEMP[4].zzzz, TEMP[10].zzzz
>191:   MOV TEMP[14].z, TEMP[16].xxxx
>192:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[11].zzzz
>193:   MOV TEMP[14].w, TEMP[17].xxxx
>194:   RCP TEMP[18].xy, -TEMP[14].xxxx
>195:   RCP TEMP[18].zw, -TEMP[15].xxxx
>196:   MUL TEMP[15], TEMP[12], TEMP[18]
>197:   MAD TEMP[15], TEMP[15], CONST[2].xzxz, -CONST[2].ywyw
>198:   RCP TEMP[16].xy, -TEMP[16].xxxx
>199:   RCP TEMP[16].zw, -TEMP[17].xxxx
>200:   MUL TEMP[16], TEMP[13], TEMP[16]
>201:   MAD TEMP[16], TEMP[16], CONST[2].xzxz, -CONST[2].ywyw
>202:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>203:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>204:   MOV_SAT TEMP[17], TEMP[15]
>205:   MOV_SAT TEMP[18], TEMP[16]
>206:   MOV TEMP[19].xy, TEMP[17].xyyy
>207:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>208:   MOV TEMP[20].x, TEMP[19].xxxx
>209:   MOV TEMP[17].xy, TEMP[17].zwww
>210:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>211:   MOV TEMP[20].y, TEMP[17].xxxx
>212:   MOV TEMP[21].xy, TEMP[18].xyyy
>213:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>214:   MOV TEMP[20].z, TEMP[21].xxxx
>215:   MOV TEMP[18].xy, TEMP[18].zwww
>216:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>217:   MOV TEMP[20].w, TEMP[18].xxxx
>218:   ABS TEMP[20], TEMP[20]
>219:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>220:   ADD TEMP[22], TEMP[20], -TEMP[14]
>221:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>222:   SGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>223:   F2I TEMP[24].x, -TEMP[24]
>224:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>225:   SGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>226:   F2I TEMP[25].x, -TEMP[25]
>227:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>228:   MOV TEMP[24].y, TEMP[25].xxxx
>229:   SGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>230:   F2I TEMP[25].x, -TEMP[25]
>231:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>232:   MOV TEMP[24].z, TEMP[25].xxxx
>233:   SGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>234:   F2I TEMP[23].x, -TEMP[23]
>235:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>236:   MOV TEMP[24].w, TEMP[23].xxxx
>237:   SEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>238:   F2I TEMP[23].x, -TEMP[23]
>239:   UIF TEMP[23].xxxx :0
>240:     MOV TEMP[23].x, IMM[4].xxxx
>241:   ELSE :0
>242:     MOV TEMP[23].x, IMM[4].zzzz
>243:   ENDIF
>244:   SEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>245:   F2I TEMP[25].x, -TEMP[25]
>246:   UIF TEMP[25].xxxx :0
>247:     MOV TEMP[25].x, IMM[4].xxxx
>248:   ELSE :0
>249:     MOV TEMP[25].x, IMM[4].zzzz
>250:   ENDIF
>251:   SEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>252:   F2I TEMP[26].x, -TEMP[26]
>253:   UIF TEMP[26].xxxx :0
>254:     MOV TEMP[26].x, IMM[4].xxxx
>255:   ELSE :0
>256:     MOV TEMP[26].x, IMM[4].zzzz
>257:   ENDIF
>258:   SEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>259:   F2I TEMP[20].x, -TEMP[20]
>260:   UIF TEMP[20].xxxx :0
>261:     MOV TEMP[20].x, IMM[4].xxxx
>262:   ELSE :0
>263:     MOV TEMP[20].x, IMM[4].zzzz
>264:   ENDIF
>265:   I2F TEMP[23].x, TEMP[23].xxxx
>266:   I2F TEMP[25].x, TEMP[25].xxxx
>267:   MOV TEMP[23].y, TEMP[25].xxxx
>268:   I2F TEMP[25].x, TEMP[26].xxxx
>269:   MOV TEMP[23].z, TEMP[25].xxxx
>270:   I2F TEMP[20].x, TEMP[20].xxxx
>271:   MOV TEMP[23].w, TEMP[20].xxxx
>272:   SGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>273:   F2I TEMP[19].x, -TEMP[19]
>274:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>275:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>276:   F2I TEMP[17].x, -TEMP[17]
>277:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>278:   MOV TEMP[19].y, TEMP[17].xxxx
>279:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>280:   F2I TEMP[17].x, -TEMP[17]
>281:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>282:   MOV TEMP[19].z, TEMP[17].xxxx
>283:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>284:   F2I TEMP[17].x, -TEMP[17]
>285:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>286:   MOV TEMP[19].w, TEMP[17].xxxx
>287:   ADD TEMP[17], TEMP[24], TEMP[23]
>288:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>289:   DP4 TEMP[2].x, TEMP[17], IMM[1].wwww
>290:   SGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>291:   F2I TEMP[18].x, -TEMP[18]
>292:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>293:   SGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>294:   F2I TEMP[19].x, -TEMP[19]
>295:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>296:   MOV TEMP[18].y, TEMP[19].xxxx
>297:   SGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>298:   F2I TEMP[19].x, -TEMP[19]
>299:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>300:   MOV TEMP[18].z, TEMP[19].xxxx
>301:   SGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>302:   F2I TEMP[19].x, -TEMP[19]
>303:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>304:   MOV TEMP[18].w, TEMP[19].xxxx
>305:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>306:   MUL TEMP[17], TEMP[18], TEMP[17]
>307:   DP4 TEMP[0].x, TEMP[17], IMM[1].wwww
>308:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
>309:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
>310:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[11].xyzz
>311:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>312:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>313:   ADD TEMP[17].xyz, CONST[11].xyzz, -TEMP[17].xyzz
>314:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
>315:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[12].xyzz
>316:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>317:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>318:   ADD TEMP[17].xyz, CONST[12].xyzz, -TEMP[17].xyzz
>319:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
>320:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[13].xyzz
>321:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>322:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>323:   ADD TEMP[17].xyz, CONST[13].xyzz, -TEMP[17].xyzz
>324:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
>325:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[14].xyzz
>326:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>327:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>328:   ADD TEMP[17].xyz, CONST[14].xyzz, -TEMP[17].xyzz
>329:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
>330:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
>331:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
>332:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
>333:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
>334:   SGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
>335:   F2I TEMP[17].x, -TEMP[17]
>336:   UIF TEMP[17].xxxx :0
>337:     MOV TEMP[17].x, IMM[4].xxxx
>338:   ELSE :0
>339:     MOV TEMP[17].x, IMM[4].yyyy
>340:   ENDIF
>341:   I2F TEMP[17].x, TEMP[17].xxxx
>342:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
>343:   SGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
>344:   F2I TEMP[17].x, -TEMP[17]
>345:   UIF TEMP[17].xxxx :0
>346:     MOV TEMP[17].x, IMM[4].xxxx
>347:   ELSE :0
>348:     MOV TEMP[17].x, IMM[4].yyyy
>349:   ENDIF
>350:   I2F TEMP[17].x, TEMP[17].xxxx
>351:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
>352:   SGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
>353:   F2I TEMP[17].x, -TEMP[17]
>354:   UIF TEMP[17].xxxx :0
>355:     MOV TEMP[17].x, IMM[4].xxxx
>356:   ELSE :0
>357:     MOV TEMP[17].x, IMM[4].yyyy
>358:   ENDIF
>359:   I2F TEMP[17].x, TEMP[17].xxxx
>360:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
>361:   SGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
>362:   F2I TEMP[17].x, -TEMP[17]
>363:   UIF TEMP[17].xxxx :0
>364:     MOV TEMP[17].x, IMM[4].xxxx
>365:   ELSE :0
>366:     MOV TEMP[17].x, IMM[4].yyyy
>367:   ENDIF
>368:   I2F TEMP[17].x, TEMP[17].xxxx
>369:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
>370:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>371:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
>372:   MOV TEMP[12].zw, TEMP[17].yyxy
>373:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>374:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
>375:   MOV TEMP[13].zw, TEMP[17].yyxy
>376:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>377:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
>378:   MOV TEMP[14].y, TEMP[17].xxxx
>379:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
>380:   MOV TEMP[14].z, TEMP[18].xxxx
>381:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
>382:   MOV TEMP[14].w, TEMP[19].xxxx
>383:   RCP TEMP[20].xy, -TEMP[14].xxxx
>384:   RCP TEMP[20].zw, -TEMP[17].xxxx
>385:   MUL TEMP[17], TEMP[12], TEMP[20]
>386:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>387:   RCP TEMP[17].xy, -TEMP[18].xxxx
>388:   RCP TEMP[17].zw, -TEMP[19].xxxx
>389:   MUL TEMP[17], TEMP[13], TEMP[17]
>390:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>391:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>392:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>393:   MOV_SAT TEMP[17], TEMP[15]
>394:   MOV_SAT TEMP[18], TEMP[16]
>395:   MOV TEMP[19].xy, TEMP[17].xyyy
>396:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>397:   MOV TEMP[20].x, TEMP[19].xxxx
>398:   MOV TEMP[17].xy, TEMP[17].zwww
>399:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>400:   MOV TEMP[20].y, TEMP[17].xxxx
>401:   MOV TEMP[21].xy, TEMP[18].xyyy
>402:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>403:   MOV TEMP[20].z, TEMP[21].xxxx
>404:   MOV TEMP[18].xy, TEMP[18].zwww
>405:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>406:   MOV TEMP[20].w, TEMP[18].xxxx
>407:   ABS TEMP[20], TEMP[20]
>408:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>409:   ADD TEMP[22], TEMP[20], -TEMP[14]
>410:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>411:   SGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>412:   F2I TEMP[24].x, -TEMP[24]
>413:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>414:   SGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>415:   F2I TEMP[25].x, -TEMP[25]
>416:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>417:   MOV TEMP[24].y, TEMP[25].xxxx
>418:   SGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>419:   F2I TEMP[25].x, -TEMP[25]
>420:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>421:   MOV TEMP[24].z, TEMP[25].xxxx
>422:   SGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>423:   F2I TEMP[23].x, -TEMP[23]
>424:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>425:   MOV TEMP[24].w, TEMP[23].xxxx
>426:   SEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>427:   F2I TEMP[23].x, -TEMP[23]
>428:   UIF TEMP[23].xxxx :0
>429:     MOV TEMP[23].x, IMM[4].xxxx
>430:   ELSE :0
>431:     MOV TEMP[23].x, IMM[4].zzzz
>432:   ENDIF
>433:   SEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>434:   F2I TEMP[25].x, -TEMP[25]
>435:   UIF TEMP[25].xxxx :0
>436:     MOV TEMP[25].x, IMM[4].xxxx
>437:   ELSE :0
>438:     MOV TEMP[25].x, IMM[4].zzzz
>439:   ENDIF
>440:   SEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>441:   F2I TEMP[26].x, -TEMP[26]
>442:   UIF TEMP[26].xxxx :0
>443:     MOV TEMP[26].x, IMM[4].xxxx
>444:   ELSE :0
>445:     MOV TEMP[26].x, IMM[4].zzzz
>446:   ENDIF
>447:   SEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>448:   F2I TEMP[20].x, -TEMP[20]
>449:   UIF TEMP[20].xxxx :0
>450:     MOV TEMP[20].x, IMM[4].xxxx
>451:   ELSE :0
>452:     MOV TEMP[20].x, IMM[4].zzzz
>453:   ENDIF
>454:   I2F TEMP[23].x, TEMP[23].xxxx
>455:   I2F TEMP[25].x, TEMP[25].xxxx
>456:   MOV TEMP[23].y, TEMP[25].xxxx
>457:   I2F TEMP[25].x, TEMP[26].xxxx
>458:   MOV TEMP[23].z, TEMP[25].xxxx
>459:   I2F TEMP[20].x, TEMP[20].xxxx
>460:   MOV TEMP[23].w, TEMP[20].xxxx
>461:   SGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>462:   F2I TEMP[19].x, -TEMP[19]
>463:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>464:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>465:   F2I TEMP[17].x, -TEMP[17]
>466:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>467:   MOV TEMP[19].y, TEMP[17].xxxx
>468:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>469:   F2I TEMP[17].x, -TEMP[17]
>470:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>471:   MOV TEMP[19].z, TEMP[17].xxxx
>472:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>473:   F2I TEMP[17].x, -TEMP[17]
>474:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>475:   MOV TEMP[19].w, TEMP[17].xxxx
>476:   ADD TEMP[17], TEMP[24], TEMP[23]
>477:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>478:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
>479:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
>480:   SGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>481:   F2I TEMP[18].x, -TEMP[18]
>482:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>483:   SGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>484:   F2I TEMP[19].x, -TEMP[19]
>485:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>486:   MOV TEMP[18].y, TEMP[19].xxxx
>487:   SGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>488:   F2I TEMP[19].x, -TEMP[19]
>489:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>490:   MOV TEMP[18].z, TEMP[19].xxxx
>491:   SGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>492:   F2I TEMP[19].x, -TEMP[19]
>493:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>494:   MOV TEMP[18].w, TEMP[19].xxxx
>495:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>496:   MUL TEMP[17], TEMP[18], TEMP[17]
>497:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
>498:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
>499:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
>500:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
>501:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[15].xyzz
>502:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>503:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>504:   ADD TEMP[17].xyz, CONST[15].xyzz, -TEMP[17].xyzz
>505:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
>506:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[16].xyzz
>507:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>508:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>509:   ADD TEMP[17].xyz, CONST[16].xyzz, -TEMP[17].xyzz
>510:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
>511:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[17].xyzz
>512:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>513:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>514:   ADD TEMP[17].xyz, CONST[17].xyzz, -TEMP[17].xyzz
>515:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
>516:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[18].xyzz
>517:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
>518:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
>519:   ADD TEMP[17].xyz, CONST[18].xyzz, -TEMP[17].xyzz
>520:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
>521:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
>522:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
>523:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
>524:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
>525:   SGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
>526:   F2I TEMP[17].x, -TEMP[17]
>527:   UIF TEMP[17].xxxx :0
>528:     MOV TEMP[17].x, IMM[4].xxxx
>529:   ELSE :0
>530:     MOV TEMP[17].x, IMM[4].yyyy
>531:   ENDIF
>532:   I2F TEMP[17].x, TEMP[17].xxxx
>533:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
>534:   SGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
>535:   F2I TEMP[17].x, -TEMP[17]
>536:   UIF TEMP[17].xxxx :0
>537:     MOV TEMP[17].x, IMM[4].xxxx
>538:   ELSE :0
>539:     MOV TEMP[17].x, IMM[4].yyyy
>540:   ENDIF
>541:   I2F TEMP[17].x, TEMP[17].xxxx
>542:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
>543:   SGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
>544:   F2I TEMP[17].x, -TEMP[17]
>545:   UIF TEMP[17].xxxx :0
>546:     MOV TEMP[17].x, IMM[4].xxxx
>547:   ELSE :0
>548:     MOV TEMP[17].x, IMM[4].yyyy
>549:   ENDIF
>550:   I2F TEMP[17].x, TEMP[17].xxxx
>551:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
>552:   SGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
>553:   F2I TEMP[17].x, -TEMP[17]
>554:   UIF TEMP[17].xxxx :0
>555:     MOV TEMP[17].x, IMM[4].xxxx
>556:   ELSE :0
>557:     MOV TEMP[17].x, IMM[4].yyyy
>558:   ENDIF
>559:   I2F TEMP[17].x, TEMP[17].xxxx
>560:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
>561:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>562:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
>563:   MOV TEMP[12].zw, TEMP[17].yyxy
>564:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>565:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
>566:   MOV TEMP[13].zw, TEMP[17].yyxy
>567:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>568:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
>569:   MOV TEMP[14].y, TEMP[17].xxxx
>570:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
>571:   MOV TEMP[14].z, TEMP[18].xxxx
>572:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
>573:   MOV TEMP[14].w, TEMP[19].xxxx
>574:   RCP TEMP[20].xy, -TEMP[14].xxxx
>575:   RCP TEMP[20].zw, -TEMP[17].xxxx
>576:   MUL TEMP[17], TEMP[12], TEMP[20]
>577:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>578:   RCP TEMP[17].xy, -TEMP[18].xxxx
>579:   RCP TEMP[17].zw, -TEMP[19].xxxx
>580:   MUL TEMP[17], TEMP[13], TEMP[17]
>581:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
>582:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>583:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>584:   MOV_SAT TEMP[17], TEMP[15]
>585:   MOV_SAT TEMP[18], TEMP[16]
>586:   MOV TEMP[19].xy, TEMP[17].xyyy
>587:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
>588:   MOV TEMP[20].x, TEMP[19].xxxx
>589:   MOV TEMP[17].xy, TEMP[17].zwww
>590:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
>591:   MOV TEMP[20].y, TEMP[17].xxxx
>592:   MOV TEMP[21].xy, TEMP[18].xyyy
>593:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
>594:   MOV TEMP[20].z, TEMP[21].xxxx
>595:   MOV TEMP[18].xy, TEMP[18].zwww
>596:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
>597:   MOV TEMP[20].w, TEMP[18].xxxx
>598:   ABS TEMP[20], TEMP[20]
>599:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
>600:   ADD TEMP[22], TEMP[20], -TEMP[14]
>601:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
>602:   SGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
>603:   F2I TEMP[24].x, -TEMP[24]
>604:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
>605:   SGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
>606:   F2I TEMP[25].x, -TEMP[25]
>607:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>608:   MOV TEMP[24].y, TEMP[25].xxxx
>609:   SGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
>610:   F2I TEMP[25].x, -TEMP[25]
>611:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
>612:   MOV TEMP[24].z, TEMP[25].xxxx
>613:   SGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
>614:   F2I TEMP[23].x, -TEMP[23]
>615:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
>616:   MOV TEMP[24].w, TEMP[23].xxxx
>617:   SEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
>618:   F2I TEMP[23].x, -TEMP[23]
>619:   UIF TEMP[23].xxxx :0
>620:     MOV TEMP[23].x, IMM[4].xxxx
>621:   ELSE :0
>622:     MOV TEMP[23].x, IMM[4].zzzz
>623:   ENDIF
>624:   SEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
>625:   F2I TEMP[25].x, -TEMP[25]
>626:   UIF TEMP[25].xxxx :0
>627:     MOV TEMP[25].x, IMM[4].xxxx
>628:   ELSE :0
>629:     MOV TEMP[25].x, IMM[4].zzzz
>630:   ENDIF
>631:   SEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
>632:   F2I TEMP[26].x, -TEMP[26]
>633:   UIF TEMP[26].xxxx :0
>634:     MOV TEMP[26].x, IMM[4].xxxx
>635:   ELSE :0
>636:     MOV TEMP[26].x, IMM[4].zzzz
>637:   ENDIF
>638:   SEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
>639:   F2I TEMP[20].x, -TEMP[20]
>640:   UIF TEMP[20].xxxx :0
>641:     MOV TEMP[20].x, IMM[4].xxxx
>642:   ELSE :0
>643:     MOV TEMP[20].x, IMM[4].zzzz
>644:   ENDIF
>645:   I2F TEMP[23].x, TEMP[23].xxxx
>646:   I2F TEMP[25].x, TEMP[25].xxxx
>647:   MOV TEMP[23].y, TEMP[25].xxxx
>648:   I2F TEMP[25].x, TEMP[26].xxxx
>649:   MOV TEMP[23].z, TEMP[25].xxxx
>650:   I2F TEMP[20].x, TEMP[20].xxxx
>651:   MOV TEMP[23].w, TEMP[20].xxxx
>652:   SGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
>653:   F2I TEMP[19].x, -TEMP[19]
>654:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>655:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
>656:   F2I TEMP[17].x, -TEMP[17]
>657:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>658:   MOV TEMP[19].y, TEMP[17].xxxx
>659:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
>660:   F2I TEMP[17].x, -TEMP[17]
>661:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>662:   MOV TEMP[19].z, TEMP[17].xxxx
>663:   SGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
>664:   F2I TEMP[17].x, -TEMP[17]
>665:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
>666:   MOV TEMP[19].w, TEMP[17].xxxx
>667:   ADD TEMP[17], TEMP[24], TEMP[23]
>668:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
>669:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
>670:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
>671:   SGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
>672:   F2I TEMP[18].x, -TEMP[18]
>673:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
>674:   SGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
>675:   F2I TEMP[19].x, -TEMP[19]
>676:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>677:   MOV TEMP[18].y, TEMP[19].xxxx
>678:   SGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
>679:   F2I TEMP[19].x, -TEMP[19]
>680:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>681:   MOV TEMP[18].z, TEMP[19].xxxx
>682:   SGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
>683:   F2I TEMP[19].x, -TEMP[19]
>684:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
>685:   MOV TEMP[18].w, TEMP[19].xxxx
>686:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
>687:   MUL TEMP[17], TEMP[18], TEMP[17]
>688:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
>689:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
>690:   MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].wwww
>691:   ADD TEMP[3], TEMP[3], -TEMP[6].xxxx
>692:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[19].xyzz
>693:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>694:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>695:   ADD TEMP[6].xyz, CONST[19].xyzz, -TEMP[6].xyzz
>696:   MUL TEMP[8].xyz, TEMP[6].xyzz, TEMP[3].xxxx
>697:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[20].xyzz
>698:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>699:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>700:   ADD TEMP[6].xyz, CONST[20].xyzz, -TEMP[6].xyzz
>701:   MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[3].yyyy
>702:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[21].xyzz
>703:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>704:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
>705:   ADD TEMP[6].xyz, CONST[21].xyzz, -TEMP[6].xyzz
>706:   MUL TEMP[10].xyz, TEMP[6].xyzz, TEMP[3].zzzz
>707:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[22].xyzz
>708:   MUL TEMP[1].xyz, TEMP[6].xxxx, TEMP[1].xyzz
>709:   MUL TEMP[1].xyz, IMM[1].xxxx, TEMP[1].xyzz
>710:   ADD TEMP[1].xyz, CONST[22].xyzz, -TEMP[1].xyzz
>711:   MUL TEMP[11].xyz, TEMP[1].xyzz, TEMP[3].wwww
>712:   DP3 TEMP[1].x, TEMP[8].xyzz, TEMP[5].xyzz
>713:   DP3 TEMP[6].x, TEMP[9].xyzz, TEMP[5].xyzz
>714:   DP3 TEMP[17].x, TEMP[10].xyzz, TEMP[5].xyzz
>715:   DP3 TEMP[5].x, TEMP[11].xyzz, TEMP[5].xyzz
>716:   SGE TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
>717:   F2I TEMP[1].x, -TEMP[1]
>718:   UIF TEMP[1].xxxx :0
>719:     MOV TEMP[1].x, IMM[4].xxxx
>720:   ELSE :0
>721:     MOV TEMP[1].x, IMM[4].yyyy
>722:   ENDIF
>723:   I2F TEMP[1].x, TEMP[1].xxxx
>724:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[1].xxxx
>725:   SGE TEMP[1].x, TEMP[6].xxxx, IMM[0].xxxx
>726:   F2I TEMP[1].x, -TEMP[1]
>727:   UIF TEMP[1].xxxx :0
>728:     MOV TEMP[1].x, IMM[4].xxxx
>729:   ELSE :0
>730:     MOV TEMP[1].x, IMM[4].yyyy
>731:   ENDIF
>732:   I2F TEMP[1].x, TEMP[1].xxxx
>733:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[1].xxxx
>734:   SGE TEMP[1].x, TEMP[17].xxxx, IMM[0].xxxx
>735:   F2I TEMP[1].x, -TEMP[1]
>736:   UIF TEMP[1].xxxx :0
>737:     MOV TEMP[1].x, IMM[4].xxxx
>738:   ELSE :0
>739:     MOV TEMP[1].x, IMM[4].yyyy
>740:   ENDIF
>741:   I2F TEMP[1].x, TEMP[1].xxxx
>742:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[1].xxxx
>743:   SGE TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx
>744:   F2I TEMP[1].x, -TEMP[1]
>745:   UIF TEMP[1].xxxx :0
>746:     MOV TEMP[1].x, IMM[4].xxxx
>747:   ELSE :0
>748:     MOV TEMP[1].x, IMM[4].yyyy
>749:   ENDIF
>750:   I2F TEMP[1].x, TEMP[1].xxxx
>751:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[1].xxxx
>752:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
>753:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[9].xyyy
>754:   MOV TEMP[12].zw, TEMP[1].yyxy
>755:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
>756:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[11].xyyy
>757:   MOV TEMP[13].zw, TEMP[1].yyxy
>758:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
>759:   ADD TEMP[1].x, TEMP[4].zzzz, TEMP[9].zzzz
>760:   MOV TEMP[14].y, TEMP[1].xxxx
>761:   ADD TEMP[5].x, TEMP[4].zzzz, TEMP[10].zzzz
>762:   MOV TEMP[14].z, TEMP[5].xxxx
>763:   ADD TEMP[4].x, TEMP[4].zzzz, TEMP[11].zzzz
>764:   MOV TEMP[14].w, TEMP[4].xxxx
>765:   RCP TEMP[6].xy, -TEMP[14].xxxx
>766:   RCP TEMP[6].zw, -TEMP[1].xxxx
>767:   MUL TEMP[1], TEMP[12], TEMP[6]
>768:   MAD TEMP[15], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
>769:   RCP TEMP[1].xy, -TEMP[5].xxxx
>770:   RCP TEMP[1].zw, -TEMP[4].xxxx
>771:   MUL TEMP[1], TEMP[13], TEMP[1]
>772:   MAD TEMP[16], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
>773:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
>774:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
>775:   MOV_SAT TEMP[1], TEMP[15]
>776:   MOV_SAT TEMP[4], TEMP[16]
>777:   MOV TEMP[5].xy, TEMP[1].xyyy
>778:   TEX TEMP[5].x, TEMP[5], SAMP[0], 2D
>779:   MOV TEMP[6].x, TEMP[5].xxxx
>780:   MOV TEMP[1].xy, TEMP[1].zwww
>781:   TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
>782:   MOV TEMP[6].y, TEMP[1].xxxx
>783:   MOV TEMP[8].xy, TEMP[4].xyyy
>784:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
>785:   MOV TEMP[6].z, TEMP[8].xxxx
>786:   MOV TEMP[4].xy, TEMP[4].zwww
>787:   TEX TEMP[4].x, TEMP[4], SAMP[0], 2D
>788:   MOV TEMP[6].w, TEMP[4].xxxx
>789:   ABS TEMP[6], TEMP[6]
>790:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
>791:   ADD TEMP[9], TEMP[6], -TEMP[14]
>792:   MUL TEMP[3], TEMP[3], IMM[1].xxxx
>793:   SGE TEMP[10].x, TEMP[9].xxxx, TEMP[3].xxxx
>794:   F2I TEMP[10].x, -TEMP[10]
>795:   AND TEMP[10].x, TEMP[10].xxxx, IMM[1].wwww
>796:   SGE TEMP[11].x, TEMP[9].yyyy, TEMP[3].yyyy
>797:   F2I TEMP[11].x, -TEMP[11]
>798:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
>799:   MOV TEMP[10].y, TEMP[11].xxxx
>800:   SGE TEMP[11].x, TEMP[9].zzzz, TEMP[3].zzzz
>801:   F2I TEMP[11].x, -TEMP[11]
>802:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
>803:   MOV TEMP[10].z, TEMP[11].xxxx
>804:   SGE TEMP[3].x, TEMP[9].wwww, TEMP[3].wwww
>805:   F2I TEMP[3].x, -TEMP[3]
>806:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>807:   MOV TEMP[10].w, TEMP[3].xxxx
>808:   SEQ TEMP[3].x, TEMP[6].xxxx, IMM[0].xxxx
>809:   F2I TEMP[3].x, -TEMP[3]
>810:   UIF TEMP[3].xxxx :0
>811:     MOV TEMP[3].x, IMM[4].xxxx
>812:   ELSE :0
>813:     MOV TEMP[3].x, IMM[4].zzzz
>814:   ENDIF
>815:   SEQ TEMP[11].x, TEMP[6].yyyy, IMM[0].xxxx
>816:   F2I TEMP[11].x, -TEMP[11]
>817:   UIF TEMP[11].xxxx :0
>818:     MOV TEMP[11].x, IMM[4].xxxx
>819:   ELSE :0
>820:     MOV TEMP[11].x, IMM[4].zzzz
>821:   ENDIF
>822:   SEQ TEMP[12].x, TEMP[6].zzzz, IMM[0].xxxx
>823:   F2I TEMP[12].x, -TEMP[12]
>824:   UIF TEMP[12].xxxx :0
>825:     MOV TEMP[12].x, IMM[4].xxxx
>826:   ELSE :0
>827:     MOV TEMP[12].x, IMM[4].zzzz
>828:   ENDIF
>829:   SEQ TEMP[6].x, TEMP[6].wwww, IMM[0].xxxx
>830:   F2I TEMP[6].x, -TEMP[6]
>831:   UIF TEMP[6].xxxx :0
>832:     MOV TEMP[6].x, IMM[4].xxxx
>833:   ELSE :0
>834:     MOV TEMP[6].x, IMM[4].zzzz
>835:   ENDIF
>836:   I2F TEMP[3].x, TEMP[3].xxxx
>837:   I2F TEMP[11].x, TEMP[11].xxxx
>838:   MOV TEMP[3].y, TEMP[11].xxxx
>839:   I2F TEMP[11].x, TEMP[12].xxxx
>840:   MOV TEMP[3].z, TEMP[11].xxxx
>841:   I2F TEMP[6].x, TEMP[6].xxxx
>842:   MOV TEMP[3].w, TEMP[6].xxxx
>843:   SGE TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
>844:   F2I TEMP[5].x, -TEMP[5]
>845:   AND TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww
>846:   SGE TEMP[1].x, IMM[0].xxxx, TEMP[1].xxxx
>847:   F2I TEMP[1].x, -TEMP[1]
>848:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>849:   MOV TEMP[5].y, TEMP[1].xxxx
>850:   SGE TEMP[1].x, IMM[0].xxxx, TEMP[8].xxxx
>851:   F2I TEMP[1].x, -TEMP[1]
>852:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>853:   MOV TEMP[5].z, TEMP[1].xxxx
>854:   SGE TEMP[1].x, IMM[0].xxxx, TEMP[4].xxxx
>855:   F2I TEMP[1].x, -TEMP[1]
>856:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
>857:   MOV TEMP[5].w, TEMP[1].xxxx
>858:   ADD TEMP[1], TEMP[10], TEMP[3]
>859:   MAD_SAT TEMP[1], TEMP[5], TEMP[7].xxxx, TEMP[1]
>860:   DP4 TEMP[3].x, TEMP[1], IMM[1].wwww
>861:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
>862:   SGE TEMP[3].x, TEMP[9].xxxx, IMM[0].xxxx
>863:   F2I TEMP[3].x, -TEMP[3]
>864:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>865:   SGE TEMP[4].x, TEMP[9].yyyy, IMM[0].xxxx
>866:   F2I TEMP[4].x, -TEMP[4]
>867:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>868:   MOV TEMP[3].y, TEMP[4].xxxx
>869:   SGE TEMP[4].x, TEMP[9].zzzz, IMM[0].xxxx
>870:   F2I TEMP[4].x, -TEMP[4]
>871:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>872:   MOV TEMP[3].z, TEMP[4].xxxx
>873:   SGE TEMP[4].x, TEMP[9].wwww, IMM[0].xxxx
>874:   F2I TEMP[4].x, -TEMP[4]
>875:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
>876:   MOV TEMP[3].w, TEMP[4].xxxx
>877:   ADD TEMP[1], IMM[1].wwww, -TEMP[1]
>878:   MUL TEMP[1], TEMP[3], TEMP[1]
>879:   DP4 TEMP[1].x, TEMP[1], IMM[1].wwww
>880:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>881:   ADD TEMP[1].x, IMM[5].xxxx, -TEMP[2].xxxx
>882:   RCP TEMP[1].x, TEMP[1].xxxx
>883:   MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
>884: ENDIF
>885: MUL_SAT TEMP[0].x, TEMP[0].xxxx, CONST[6].yyyy
>886: ADD TEMP[0].x, IMM[1].wwww, -TEMP[0].xxxx
>887: MOV TEMP[1].xyz, IMM[0].xxxx
>888: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
>889: MOV TEMP[1].w, TEMP[0].xxxx
>890: MOV OUT[0], TEMP[1]
>891: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 128)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 132)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 136)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 152)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 180)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 212)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 216)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 240)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 244)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 248)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 256)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 260)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 264)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 272)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 276)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 280)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 288)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 292)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %21, i32 296)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %21, i32 304)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %21, i32 308)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %21, i32 312)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %21, i32 320)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %21, i32 324)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %21, i32 328)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %21, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %21, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %21, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %21, i32 352)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %21, i32 356)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %21, i32 360)
>  %93 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %94 = load <32 x i8> addrspace(2)* %93, !tbaa !0
>  %95 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %98 = load <32 x i8> addrspace(2)* %97, !tbaa !0
>  %99 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %100 = load <16 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %102 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %103 = fmul float %101, %34
>  %104 = fadd float %103, 5.000000e-01
>  %105 = fmul float %102, %35
>  %106 = fadd float %105, 5.000000e-01
>  %107 = call float @llvm.AMDIL.fraction.(float %104)
>  %108 = call float @llvm.AMDIL.fraction.(float %106)
>  %109 = fsub float -0.000000e+00, %107
>  %110 = fadd float %104, %109
>  %111 = fsub float -0.000000e+00, %108
>  %112 = fadd float %106, %111
>  %113 = fadd float %110, 5.000000e-01
>  %114 = fadd float %112, 5.000000e-01
>  %115 = fmul float %113, %36
>  %116 = fmul float %114, %37
>  %117 = bitcast float %115 to i32
>  %118 = bitcast float %116 to i32
>  %119 = insertelement <2 x i32> undef, i32 %117, i32 0
>  %120 = insertelement <2 x i32> %119, i32 %118, i32 1
>  %121 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %120, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = call float @fabs(float %122)
>  %124 = fsub float -0.000000e+00, %26
>  %125 = fmul float %123, %27
>  %126 = fadd float %125, %124
>  %127 = fcmp ult float %122, 0x3FEE666660000000
>  %128 = select i1 %127, float 1.000000e+00, float 0.000000e+00
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fptosi float %129 to i32
>  %131 = bitcast i32 %130 to float
>  %132 = bitcast float %131 to i32
>  %133 = icmp ne i32 %132, 0
>  br i1 %133, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %134 = fmul float %115, 2.000000e+00
>  %135 = fadd float %134, -1.000000e+00
>  %136 = fmul float %116, -2.000000e+00
>  %137 = fadd float %136, 1.000000e+00
>  %138 = fadd float %135, %29
>  %139 = fadd float %137, %31
>  %140 = fsub float -0.000000e+00, %126
>  %141 = fmul float %140, %138
>  %142 = fsub float -0.000000e+00, %126
>  %143 = fmul float %142, %139
>  %144 = fdiv float 1.000000e+00, %28
>  %145 = fdiv float 1.000000e+00, %30
>  %146 = fmul float %141, %144
>  %147 = fmul float %143, %145
>  %148 = fsub float -0.000000e+00, %36
>  %149 = fadd float %115, %148
>  %150 = fadd float %116, 0.000000e+00
>  %151 = fadd float %115, %36
>  %152 = fsub float -0.000000e+00, %37
>  %153 = fadd float %115, 0.000000e+00
>  %154 = fadd float %116, %152
>  %155 = fadd float %116, %37
>  %156 = bitcast float %149 to i32
>  %157 = bitcast float %150 to i32
>  %158 = insertelement <2 x i32> undef, i32 %156, i32 0
>  %159 = insertelement <2 x i32> %158, i32 %157, i32 1
>  %160 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %159, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %161 = extractelement <4 x float> %160, i32 0
>  %162 = bitcast float %151 to i32
>  %163 = bitcast float %150 to i32
>  %164 = insertelement <2 x i32> undef, i32 %162, i32 0
>  %165 = insertelement <2 x i32> %164, i32 %163, i32 1
>  %166 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %165, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %167 = extractelement <4 x float> %166, i32 0
>  %168 = bitcast float %153 to i32
>  %169 = bitcast float %154 to i32
>  %170 = insertelement <2 x i32> undef, i32 %168, i32 0
>  %171 = insertelement <2 x i32> %170, i32 %169, i32 1
>  %172 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %171, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %173 = extractelement <4 x float> %172, i32 0
>  %174 = bitcast float %153 to i32
>  %175 = bitcast float %155 to i32
>  %176 = insertelement <2 x i32> undef, i32 %174, i32 0
>  %177 = insertelement <2 x i32> %176, i32 %175, i32 1
>  %178 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %177, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %179 = extractelement <4 x float> %178, i32 0
>  %180 = call float @fabs(float %161)
>  %181 = call float @fabs(float %167)
>  %182 = call float @fabs(float %173)
>  %183 = call float @fabs(float %179)
>  %184 = fsub float -0.000000e+00, %26
>  %185 = fmul float %180, %27
>  %186 = fadd float %185, %184
>  %187 = fsub float -0.000000e+00, %26
>  %188 = fmul float %181, %27
>  %189 = fadd float %188, %187
>  %190 = fsub float -0.000000e+00, %26
>  %191 = fmul float %182, %27
>  %192 = fadd float %191, %190
>  %193 = fsub float -0.000000e+00, %26
>  %194 = fmul float %183, %27
>  %195 = fadd float %194, %193
>  %196 = fsub float -0.000000e+00, %126
>  %197 = fadd float %186, %196
>  %198 = fsub float -0.000000e+00, %126
>  %199 = fadd float %189, %198
>  %200 = fsub float -0.000000e+00, %126
>  %201 = fadd float %192, %200
>  %202 = fsub float -0.000000e+00, %126
>  %203 = fadd float %195, %202
>  %204 = call float @fabs(float %197)
>  %205 = call float @fabs(float %199)
>  %206 = call float @fabs(float %201)
>  %207 = call float @fabs(float %203)
>  %208 = fcmp ult float %204, %205
>  %209 = select i1 %208, float 1.000000e+00, float 0.000000e+00
>  %210 = fsub float -0.000000e+00, %209
>  %211 = fptosi float %210 to i32
>  %212 = bitcast i32 %211 to float
>  %213 = bitcast float %212 to i32
>  %214 = icmp ne i32 %213, 0
>  %. = select i1 %214, float %149, float %151
>  %.213 = select i1 %214, float %186, float %189
>  %.214 = select i1 %214, float -1.000000e+00, float 1.000000e+00
>  %215 = fcmp ult float %206, %207
>  %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00
>  %217 = fsub float -0.000000e+00, %216
>  %218 = fptosi float %217 to i32
>  %219 = bitcast i32 %218 to float
>  %220 = bitcast float %219 to i32
>  %221 = icmp ne i32 %220, 0
>  %temp21.0 = select i1 %221, float %154, float %155
>  %temp22.0 = select i1 %221, float %192, float %195
>  %temp23.0 = select i1 %221, float -1.000000e+00, float 1.000000e+00
>  %222 = fmul float %., 2.000000e+00
>  %223 = fadd float %222, -1.000000e+00
>  %224 = fmul float %150, -2.000000e+00
>  %225 = fadd float %224, 1.000000e+00
>  %226 = fadd float %223, %29
>  %227 = fadd float %225, %31
>  %228 = fsub float -0.000000e+00, %.213
>  %229 = fmul float %228, %226
>  %230 = fsub float -0.000000e+00, %.213
>  %231 = fmul float %230, %227
>  %232 = fdiv float 1.000000e+00, %28
>  %233 = fdiv float 1.000000e+00, %30
>  %234 = fmul float %229, %232
>  %235 = fmul float %231, %233
>  %236 = fmul float %153, 2.000000e+00
>  %237 = fadd float %236, -1.000000e+00
>  %238 = fmul float %temp21.0, -2.000000e+00
>  %239 = fadd float %238, 1.000000e+00
>  %240 = fadd float %237, %29
>  %241 = fadd float %239, %31
>  %242 = fsub float -0.000000e+00, %temp22.0
>  %243 = fmul float %242, %240
>  %244 = fsub float -0.000000e+00, %temp22.0
>  %245 = fmul float %244, %241
>  %246 = fdiv float 1.000000e+00, %28
>  %247 = fdiv float 1.000000e+00, %30
>  %248 = fmul float %243, %246
>  %249 = fmul float %245, %247
>  %250 = fsub float -0.000000e+00, %146
>  %251 = fadd float %234, %250
>  %252 = fsub float -0.000000e+00, %147
>  %253 = fadd float %235, %252
>  %254 = fsub float -0.000000e+00, %126
>  %255 = fadd float %.213, %254
>  %256 = fmul float %251, %.214
>  %257 = fmul float %253, %.214
>  %258 = fmul float %255, %.214
>  %259 = fsub float -0.000000e+00, %146
>  %260 = fadd float %248, %259
>  %261 = fsub float -0.000000e+00, %147
>  %262 = fadd float %249, %261
>  %263 = fsub float -0.000000e+00, %126
>  %264 = fadd float %temp22.0, %263
>  %265 = fmul float %260, %temp23.0
>  %266 = fmul float %262, %temp23.0
>  %267 = fmul float %264, %temp23.0
>  %268 = fmul float %267, %257
>  %269 = fmul float %265, %258
>  %270 = fmul float %266, %256
>  %271 = fsub float -0.000000e+00, %268
>  %272 = fmul float %266, %258
>  %273 = fadd float %272, %271
>  %274 = fsub float -0.000000e+00, %269
>  %275 = fmul float %267, %256
>  %276 = fadd float %275, %274
>  %277 = fsub float -0.000000e+00, %270
>  %278 = fmul float %265, %257
>  %279 = fadd float %278, %277
>  %280 = fmul float %273, %273
>  %281 = fmul float %276, %276
>  %282 = fadd float %281, %280
>  %283 = fmul float %279, %279
>  %284 = fadd float %282, %283
>  %285 = call float @llvm.AMDGPU.rsq(float %284)
>  %286 = fmul float %273, %285
>  %287 = fmul float %276, %285
>  %288 = fmul float %279, %285
>  %289 = fmul float %286, %126
>  %290 = fmul float %287, %126
>  %291 = fmul float %288, %126
>  %292 = fmul float %289, %24
>  %293 = fmul float %290, %24
>  %294 = fmul float %291, %24
>  %295 = fsub float -0.000000e+00, %292
>  %296 = fadd float %146, %295
>  %297 = fsub float -0.000000e+00, %293
>  %298 = fadd float %147, %297
>  %299 = fsub float -0.000000e+00, %294
>  %300 = fadd float %126, %299
>  %301 = fmul float %32, 2.500000e-01
>  %302 = fmul float %33, 2.500000e-01
>  %303 = fmul float %115, %301
>  %304 = fmul float %116, %302
>  %305 = bitcast float %303 to i32
>  %306 = bitcast float %304 to i32
>  %307 = insertelement <2 x i32> undef, i32 %305, i32 0
>  %308 = insertelement <2 x i32> %307, i32 %306, i32 1
>  %309 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %308, <32 x i8> %98, <16 x i8> %100, i32 2)
>  %310 = extractelement <4 x float> %309, i32 0
>  %311 = extractelement <4 x float> %309, i32 1
>  %312 = extractelement <4 x float> %309, i32 2
>  %313 = fmul float %310, 2.000000e+00
>  %314 = fadd float %313, -1.000000e+00
>  %315 = fmul float %311, 2.000000e+00
>  %316 = fadd float %315, -1.000000e+00
>  %317 = fmul float %312, 2.000000e+00
>  %318 = fadd float %317, -1.000000e+00
>  %319 = fmul float %314, %25
>  %320 = fmul float %316, %25
>  %321 = fmul float %318, %25
>  %322 = fsub float -0.000000e+00, %126
>  %323 = fsub float -0.000000e+00, %38
>  %324 = fadd float %322, %323
>  %325 = fmul float %324, %41
>  %326 = call float @llvm.AMDIL.clamp.(float %325, float 0.000000e+00, float 1.000000e+00)
>  %327 = fmul float %40, %326
>  %328 = fadd float %327, 1.000000e+00
>  %329 = fsub float -0.000000e+00, %126
>  %330 = fmul float %329, %39
>  %331 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00)
>  %332 = fmul float %328, %331
>  %333 = fcmp ult float %122, 0.000000e+00
>  %334 = select i1 %333, float 1.000000e+00, float 0.000000e+00
>  %335 = fsub float -0.000000e+00, %334
>  %336 = fptosi float %335 to i32
>  %337 = bitcast i32 %336 to float
>  %338 = bitcast float %337 to i32
>  %339 = icmp ne i32 %338, 0
>  %.215 = select i1 %339, float %42, float %332
>  %340 = fmul float %.215, %44
>  %341 = fmul float %23, %340
>  %342 = fcmp uge float %122, 0.000000e+00
>  %343 = select i1 %342, float 1.000000e+00, float 0.000000e+00
>  %344 = fsub float -0.000000e+00, %343
>  %345 = fptosi float %344 to i32
>  %346 = bitcast i32 %345 to float
>  %347 = bitcast float %346 to i32
>  %348 = and i32 %347, 1065353216
>  %349 = bitcast i32 %348 to float
>  %350 = fmul float %341, 0.000000e+00
>  %351 = fmul float %341, 1.000000e+00
>  %352 = fmul float %341, 2.000000e+00
>  %353 = fmul float %341, 3.000000e+00
>  %354 = fsub float -0.000000e+00, %350
>  %355 = fmul float %22, %340
>  %356 = fadd float %355, %354
>  %357 = fsub float -0.000000e+00, %351
>  %358 = fmul float %22, %340
>  %359 = fadd float %358, %357
>  %360 = fsub float -0.000000e+00, %352
>  %361 = fmul float %22, %340
>  %362 = fadd float %361, %360
>  %363 = fsub float -0.000000e+00, %353
>  %364 = fmul float %22, %340
>  %365 = fadd float %364, %363
>  %366 = fmul float %319, %45
>  %367 = fmul float %320, %46
>  %368 = fadd float %367, %366
>  %369 = fmul float %321, %47
>  %370 = fadd float %368, %369
>  %371 = fmul float %370, %319
>  %372 = fmul float %370, %320
>  %373 = fmul float %370, %321
>  %374 = fmul float 2.000000e+00, %371
>  %375 = fmul float 2.000000e+00, %372
>  %376 = fmul float 2.000000e+00, %373
>  %377 = fsub float -0.000000e+00, %374
>  %378 = fadd float %45, %377
>  %379 = fsub float -0.000000e+00, %375
>  %380 = fadd float %46, %379
>  %381 = fsub float -0.000000e+00, %376
>  %382 = fadd float %47, %381
>  %383 = fmul float %378, %356
>  %384 = fmul float %380, %356
>  %385 = fmul float %382, %356
>  %386 = fmul float %319, %48
>  %387 = fmul float %320, %49
>  %388 = fadd float %387, %386
>  %389 = fmul float %321, %50
>  %390 = fadd float %388, %389
>  %391 = fmul float %390, %319
>  %392 = fmul float %390, %320
>  %393 = fmul float %390, %321
>  %394 = fmul float 2.000000e+00, %391
>  %395 = fmul float 2.000000e+00, %392
>  %396 = fmul float 2.000000e+00, %393
>  %397 = fsub float -0.000000e+00, %394
>  %398 = fadd float %48, %397
>  %399 = fsub float -0.000000e+00, %395
>  %400 = fadd float %49, %399
>  %401 = fsub float -0.000000e+00, %396
>  %402 = fadd float %50, %401
>  %403 = fmul float %398, %359
>  %404 = fmul float %400, %359
>  %405 = fmul float %402, %359
>  %406 = fmul float %319, %51
>  %407 = fmul float %320, %52
>  %408 = fadd float %407, %406
>  %409 = fmul float %321, %53
>  %410 = fadd float %408, %409
>  %411 = fmul float %410, %319
>  %412 = fmul float %410, %320
>  %413 = fmul float %410, %321
>  %414 = fmul float 2.000000e+00, %411
>  %415 = fmul float 2.000000e+00, %412
>  %416 = fmul float 2.000000e+00, %413
>  %417 = fsub float -0.000000e+00, %414
>  %418 = fadd float %51, %417
>  %419 = fsub float -0.000000e+00, %415
>  %420 = fadd float %52, %419
>  %421 = fsub float -0.000000e+00, %416
>  %422 = fadd float %53, %421
>  %423 = fmul float %418, %362
>  %424 = fmul float %420, %362
>  %425 = fmul float %422, %362
>  %426 = fmul float %319, %54
>  %427 = fmul float %320, %55
>  %428 = fadd float %427, %426
>  %429 = fmul float %321, %56
>  %430 = fadd float %428, %429
>  %431 = fmul float %430, %319
>  %432 = fmul float %430, %320
>  %433 = fmul float %430, %321
>  %434 = fmul float 2.000000e+00, %431
>  %435 = fmul float 2.000000e+00, %432
>  %436 = fmul float 2.000000e+00, %433
>  %437 = fsub float -0.000000e+00, %434
>  %438 = fadd float %54, %437
>  %439 = fsub float -0.000000e+00, %435
>  %440 = fadd float %55, %439
>  %441 = fsub float -0.000000e+00, %436
>  %442 = fadd float %56, %441
>  %443 = fmul float %438, %365
>  %444 = fmul float %440, %365
>  %445 = fmul float %442, %365
>  %446 = fmul float %383, %286
>  %447 = fmul float %384, %287
>  %448 = fadd float %447, %446
>  %449 = fmul float %385, %288
>  %450 = fadd float %448, %449
>  %451 = fmul float %403, %286
>  %452 = fmul float %404, %287
>  %453 = fadd float %452, %451
>  %454 = fmul float %405, %288
>  %455 = fadd float %453, %454
>  %456 = fmul float %423, %286
>  %457 = fmul float %424, %287
>  %458 = fadd float %457, %456
>  %459 = fmul float %425, %288
>  %460 = fadd float %458, %459
>  %461 = fmul float %443, %286
>  %462 = fmul float %444, %287
>  %463 = fadd float %462, %461
>  %464 = fmul float %445, %288
>  %465 = fadd float %463, %464
>  %466 = fcmp uge float %450, 0.000000e+00
>  %467 = select i1 %466, float 1.000000e+00, float 0.000000e+00
>  %468 = fsub float -0.000000e+00, %467
>  %469 = fptosi float %468 to i32
>  %470 = bitcast i32 %469 to float
>  %471 = bitcast float %470 to i32
>  %472 = icmp ne i32 %471, 0
>  %temp48.0 = select i1 %472, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %473 = bitcast float %temp48.0 to i32
>  %474 = sitofp i32 %473 to float
>  %475 = fmul float %383, %474
>  %476 = fmul float %384, %474
>  %477 = fmul float %385, %474
>  %478 = fcmp uge float %455, 0.000000e+00
>  %479 = select i1 %478, float 1.000000e+00, float 0.000000e+00
>  %480 = fsub float -0.000000e+00, %479
>  %481 = fptosi float %480 to i32
>  %482 = bitcast i32 %481 to float
>  %483 = bitcast float %482 to i32
>  %484 = icmp ne i32 %483, 0
>  %.216 = select i1 %484, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %485 = bitcast float %.216 to i32
>  %486 = sitofp i32 %485 to float
>  %487 = fmul float %403, %486
>  %488 = fmul float %404, %486
>  %489 = fmul float %405, %486
>  %490 = fcmp uge float %460, 0.000000e+00
>  %491 = select i1 %490, float 1.000000e+00, float 0.000000e+00
>  %492 = fsub float -0.000000e+00, %491
>  %493 = fptosi float %492 to i32
>  %494 = bitcast i32 %493 to float
>  %495 = bitcast float %494 to i32
>  %496 = icmp ne i32 %495, 0
>  %temp48.2 = select i1 %496, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %497 = bitcast float %temp48.2 to i32
>  %498 = sitofp i32 %497 to float
>  %499 = fmul float %423, %498
>  %500 = fmul float %424, %498
>  %501 = fmul float %425, %498
>  %502 = fcmp uge float %465, 0.000000e+00
>  %503 = select i1 %502, float 1.000000e+00, float 0.000000e+00
>  %504 = fsub float -0.000000e+00, %503
>  %505 = fptosi float %504 to i32
>  %506 = bitcast i32 %505 to float
>  %507 = bitcast float %506 to i32
>  %508 = icmp ne i32 %507, 0
>  %.217 = select i1 %508, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %509 = bitcast float %.217 to i32
>  %510 = sitofp i32 %509 to float
>  %511 = fmul float %443, %510
>  %512 = fmul float %444, %510
>  %513 = fmul float %445, %510
>  %514 = fadd float %296, %475
>  %515 = fadd float %298, %476
>  %516 = fadd float %296, %487
>  %517 = fadd float %298, %488
>  %518 = fadd float %296, %499
>  %519 = fadd float %298, %500
>  %520 = fadd float %296, %511
>  %521 = fadd float %298, %512
>  %522 = fadd float %300, %477
>  %523 = fadd float %300, %489
>  %524 = fadd float %300, %501
>  %525 = fadd float %300, %513
>  %526 = fsub float -0.000000e+00, %522
>  %527 = fdiv float 1.000000e+00, %526
>  %528 = fsub float -0.000000e+00, %523
>  %529 = fdiv float 1.000000e+00, %528
>  %530 = fmul float %514, %527
>  %531 = fmul float %515, %527
>  %532 = fmul float %516, %529
>  %533 = fmul float %517, %529
>  %534 = fsub float -0.000000e+00, %29
>  %535 = fmul float %530, %28
>  %536 = fadd float %535, %534
>  %537 = fsub float -0.000000e+00, %31
>  %538 = fmul float %531, %30
>  %539 = fadd float %538, %537
>  %540 = fsub float -0.000000e+00, %29
>  %541 = fmul float %532, %28
>  %542 = fadd float %541, %540
>  %543 = fsub float -0.000000e+00, %31
>  %544 = fmul float %533, %30
>  %545 = fadd float %544, %543
>  %546 = fsub float -0.000000e+00, %524
>  %547 = fdiv float 1.000000e+00, %546
>  %548 = fsub float -0.000000e+00, %525
>  %549 = fdiv float 1.000000e+00, %548
>  %550 = fmul float %518, %547
>  %551 = fmul float %519, %547
>  %552 = fmul float %520, %549
>  %553 = fmul float %521, %549
>  %554 = fsub float -0.000000e+00, %29
>  %555 = fmul float %550, %28
>  %556 = fadd float %555, %554
>  %557 = fsub float -0.000000e+00, %31
>  %558 = fmul float %551, %30
>  %559 = fadd float %558, %557
>  %560 = fsub float -0.000000e+00, %29
>  %561 = fmul float %552, %28
>  %562 = fadd float %561, %560
>  %563 = fsub float -0.000000e+00, %31
>  %564 = fmul float %553, %30
>  %565 = fadd float %564, %563
>  %566 = fmul float %536, 5.000000e-01
>  %567 = fadd float %566, 5.000000e-01
>  %568 = fmul float %539, -5.000000e-01
>  %569 = fadd float %568, 5.000000e-01
>  %570 = fmul float %542, 5.000000e-01
>  %571 = fadd float %570, 5.000000e-01
>  %572 = fmul float %545, -5.000000e-01
>  %573 = fadd float %572, 5.000000e-01
>  %574 = fmul float %556, 5.000000e-01
>  %575 = fadd float %574, 5.000000e-01
>  %576 = fmul float %559, -5.000000e-01
>  %577 = fadd float %576, 5.000000e-01
>  %578 = fmul float %562, 5.000000e-01
>  %579 = fadd float %578, 5.000000e-01
>  %580 = fmul float %565, -5.000000e-01
>  %581 = fadd float %580, 5.000000e-01
>  %582 = call float @llvm.AMDIL.clamp.(float %567, float 0.000000e+00, float 1.000000e+00)
>  %583 = call float @llvm.AMDIL.clamp.(float %569, float 0.000000e+00, float 1.000000e+00)
>  %584 = call float @llvm.AMDIL.clamp.(float %571, float 0.000000e+00, float 1.000000e+00)
>  %585 = call float @llvm.AMDIL.clamp.(float %573, float 0.000000e+00, float 1.000000e+00)
>  %586 = call float @llvm.AMDIL.clamp.(float %575, float 0.000000e+00, float 1.000000e+00)
>  %587 = call float @llvm.AMDIL.clamp.(float %577, float 0.000000e+00, float 1.000000e+00)
>  %588 = call float @llvm.AMDIL.clamp.(float %579, float 0.000000e+00, float 1.000000e+00)
>  %589 = call float @llvm.AMDIL.clamp.(float %581, float 0.000000e+00, float 1.000000e+00)
>  %590 = bitcast float %582 to i32
>  %591 = bitcast float %583 to i32
>  %592 = insertelement <2 x i32> undef, i32 %590, i32 0
>  %593 = insertelement <2 x i32> %592, i32 %591, i32 1
>  %594 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %593, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %595 = extractelement <4 x float> %594, i32 0
>  %596 = bitcast float %584 to i32
>  %597 = bitcast float %585 to i32
>  %598 = insertelement <2 x i32> undef, i32 %596, i32 0
>  %599 = insertelement <2 x i32> %598, i32 %597, i32 1
>  %600 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %599, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %601 = extractelement <4 x float> %600, i32 0
>  %602 = bitcast float %586 to i32
>  %603 = bitcast float %587 to i32
>  %604 = insertelement <2 x i32> undef, i32 %602, i32 0
>  %605 = insertelement <2 x i32> %604, i32 %603, i32 1
>  %606 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %605, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %607 = extractelement <4 x float> %606, i32 0
>  %608 = bitcast float %588 to i32
>  %609 = bitcast float %589 to i32
>  %610 = insertelement <2 x i32> undef, i32 %608, i32 0
>  %611 = insertelement <2 x i32> %610, i32 %609, i32 1
>  %612 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %611, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %613 = extractelement <4 x float> %612, i32 0
>  %614 = call float @fabs(float %595)
>  %615 = call float @fabs(float %601)
>  %616 = call float @fabs(float %607)
>  %617 = call float @fabs(float %613)
>  %618 = fsub float -0.000000e+00, %26
>  %619 = fmul float %614, %27
>  %620 = fadd float %619, %618
>  %621 = fsub float -0.000000e+00, %26
>  %622 = fmul float %615, %27
>  %623 = fadd float %622, %621
>  %624 = fsub float -0.000000e+00, %26
>  %625 = fmul float %616, %27
>  %626 = fadd float %625, %624
>  %627 = fsub float -0.000000e+00, %26
>  %628 = fmul float %617, %27
>  %629 = fadd float %628, %627
>  %630 = fsub float -0.000000e+00, %522
>  %631 = fadd float %620, %630
>  %632 = fsub float -0.000000e+00, %523
>  %633 = fadd float %623, %632
>  %634 = fsub float -0.000000e+00, %524
>  %635 = fadd float %626, %634
>  %636 = fsub float -0.000000e+00, %525
>  %637 = fadd float %629, %636
>  %638 = fmul float %356, 2.000000e+00
>  %639 = fmul float %359, 2.000000e+00
>  %640 = fmul float %362, 2.000000e+00
>  %641 = fmul float %365, 2.000000e+00
>  %642 = fcmp uge float %631, %638
>  %643 = select i1 %642, float 1.000000e+00, float 0.000000e+00
>  %644 = fsub float -0.000000e+00, %643
>  %645 = fptosi float %644 to i32
>  %646 = bitcast i32 %645 to float
>  %647 = bitcast float %646 to i32
>  %648 = and i32 %647, 1065353216
>  %649 = bitcast i32 %648 to float
>  %650 = fcmp uge float %633, %639
>  %651 = select i1 %650, float 1.000000e+00, float 0.000000e+00
>  %652 = fsub float -0.000000e+00, %651
>  %653 = fptosi float %652 to i32
>  %654 = bitcast i32 %653 to float
>  %655 = bitcast float %654 to i32
>  %656 = and i32 %655, 1065353216
>  %657 = bitcast i32 %656 to float
>  %658 = fcmp uge float %635, %640
>  %659 = select i1 %658, float 1.000000e+00, float 0.000000e+00
>  %660 = fsub float -0.000000e+00, %659
>  %661 = fptosi float %660 to i32
>  %662 = bitcast i32 %661 to float
>  %663 = bitcast float %662 to i32
>  %664 = and i32 %663, 1065353216
>  %665 = bitcast i32 %664 to float
>  %666 = fcmp uge float %637, %641
>  %667 = select i1 %666, float 1.000000e+00, float 0.000000e+00
>  %668 = fsub float -0.000000e+00, %667
>  %669 = fptosi float %668 to i32
>  %670 = bitcast i32 %669 to float
>  %671 = bitcast float %670 to i32
>  %672 = and i32 %671, 1065353216
>  %673 = bitcast i32 %672 to float
>  %674 = fcmp ueq float %620, 0.000000e+00
>  %675 = select i1 %674, float 1.000000e+00, float 0.000000e+00
>  %676 = fsub float -0.000000e+00, %675
>  %677 = fptosi float %676 to i32
>  %678 = bitcast i32 %677 to float
>  %679 = bitcast float %678 to i32
>  %680 = icmp ne i32 %679, 0
>  %temp92.0 = select i1 %680, float 0x36A0000000000000, float 0.000000e+00
>  %681 = fcmp ueq float %623, 0.000000e+00
>  %682 = select i1 %681, float 1.000000e+00, float 0.000000e+00
>  %683 = fsub float -0.000000e+00, %682
>  %684 = fptosi float %683 to i32
>  %685 = bitcast i32 %684 to float
>  %686 = bitcast float %685 to i32
>  %687 = icmp ne i32 %686, 0
>  %.218 = select i1 %687, float 0x36A0000000000000, float 0.000000e+00
>  %688 = fcmp ueq float %626, 0.000000e+00
>  %689 = select i1 %688, float 1.000000e+00, float 0.000000e+00
>  %690 = fsub float -0.000000e+00, %689
>  %691 = fptosi float %690 to i32
>  %692 = bitcast i32 %691 to float
>  %693 = bitcast float %692 to i32
>  %694 = icmp ne i32 %693, 0
>  %temp104.0 = select i1 %694, float 0x36A0000000000000, float 0.000000e+00
>  %695 = fcmp ueq float %629, 0.000000e+00
>  %696 = select i1 %695, float 1.000000e+00, float 0.000000e+00
>  %697 = fsub float -0.000000e+00, %696
>  %698 = fptosi float %697 to i32
>  %699 = bitcast i32 %698 to float
>  %700 = bitcast float %699 to i32
>  %701 = icmp ne i32 %700, 0
>  %.219 = select i1 %701, float 0x36A0000000000000, float 0.000000e+00
>  %702 = bitcast float %temp92.0 to i32
>  %703 = sitofp i32 %702 to float
>  %704 = bitcast float %.218 to i32
>  %705 = sitofp i32 %704 to float
>  %706 = bitcast float %temp104.0 to i32
>  %707 = sitofp i32 %706 to float
>  %708 = bitcast float %.219 to i32
>  %709 = sitofp i32 %708 to float
>  %710 = fcmp uge float 0.000000e+00, %595
>  %711 = select i1 %710, float 1.000000e+00, float 0.000000e+00
>  %712 = fsub float -0.000000e+00, %711
>  %713 = fptosi float %712 to i32
>  %714 = bitcast i32 %713 to float
>  %715 = bitcast float %714 to i32
>  %716 = and i32 %715, 1065353216
>  %717 = bitcast i32 %716 to float
>  %718 = fcmp uge float 0.000000e+00, %601
>  %719 = select i1 %718, float 1.000000e+00, float 0.000000e+00
>  %720 = fsub float -0.000000e+00, %719
>  %721 = fptosi float %720 to i32
>  %722 = bitcast i32 %721 to float
>  %723 = bitcast float %722 to i32
>  %724 = and i32 %723, 1065353216
>  %725 = bitcast i32 %724 to float
>  %726 = fcmp uge float 0.000000e+00, %607
>  %727 = select i1 %726, float 1.000000e+00, float 0.000000e+00
>  %728 = fsub float -0.000000e+00, %727
>  %729 = fptosi float %728 to i32
>  %730 = bitcast i32 %729 to float
>  %731 = bitcast float %730 to i32
>  %732 = and i32 %731, 1065353216
>  %733 = bitcast i32 %732 to float
>  %734 = fcmp uge float 0.000000e+00, %613
>  %735 = select i1 %734, float 1.000000e+00, float 0.000000e+00
>  %736 = fsub float -0.000000e+00, %735
>  %737 = fptosi float %736 to i32
>  %738 = bitcast i32 %737 to float
>  %739 = bitcast float %738 to i32
>  %740 = and i32 %739, 1065353216
>  %741 = bitcast i32 %740 to float
>  %742 = fadd float %649, %703
>  %743 = fadd float %657, %705
>  %744 = fadd float %665, %707
>  %745 = fadd float %673, %709
>  %746 = fmul float %717, %349
>  %747 = fadd float %746, %742
>  %748 = fmul float %725, %349
>  %749 = fadd float %748, %743
>  %750 = fmul float %733, %349
>  %751 = fadd float %750, %744
>  %752 = fmul float %741, %349
>  %753 = fadd float %752, %745
>  %754 = call float @llvm.AMDIL.clamp.(float %747, float 0.000000e+00, float 1.000000e+00)
>  %755 = call float @llvm.AMDIL.clamp.(float %749, float 0.000000e+00, float 1.000000e+00)
>  %756 = call float @llvm.AMDIL.clamp.(float %751, float 0.000000e+00, float 1.000000e+00)
>  %757 = call float @llvm.AMDIL.clamp.(float %753, float 0.000000e+00, float 1.000000e+00)
>  %758 = fmul float %754, 1.000000e+00
>  %759 = fmul float %755, 1.000000e+00
>  %760 = fadd float %758, %759
>  %761 = fmul float %756, 1.000000e+00
>  %762 = fadd float %760, %761
>  %763 = fmul float %757, 1.000000e+00
>  %764 = fadd float %762, %763
>  %765 = fcmp uge float %631, 0.000000e+00
>  %766 = select i1 %765, float 1.000000e+00, float 0.000000e+00
>  %767 = fsub float -0.000000e+00, %766
>  %768 = fptosi float %767 to i32
>  %769 = bitcast i32 %768 to float
>  %770 = bitcast float %769 to i32
>  %771 = and i32 %770, 1065353216
>  %772 = bitcast i32 %771 to float
>  %773 = fcmp uge float %633, 0.000000e+00
>  %774 = select i1 %773, float 1.000000e+00, float 0.000000e+00
>  %775 = fsub float -0.000000e+00, %774
>  %776 = fptosi float %775 to i32
>  %777 = bitcast i32 %776 to float
>  %778 = bitcast float %777 to i32
>  %779 = and i32 %778, 1065353216
>  %780 = bitcast i32 %779 to float
>  %781 = fcmp uge float %635, 0.000000e+00
>  %782 = select i1 %781, float 1.000000e+00, float 0.000000e+00
>  %783 = fsub float -0.000000e+00, %782
>  %784 = fptosi float %783 to i32
>  %785 = bitcast i32 %784 to float
>  %786 = bitcast float %785 to i32
>  %787 = and i32 %786, 1065353216
>  %788 = bitcast i32 %787 to float
>  %789 = fcmp uge float %637, 0.000000e+00
>  %790 = select i1 %789, float 1.000000e+00, float 0.000000e+00
>  %791 = fsub float -0.000000e+00, %790
>  %792 = fptosi float %791 to i32
>  %793 = bitcast i32 %792 to float
>  %794 = bitcast float %793 to i32
>  %795 = and i32 %794, 1065353216
>  %796 = bitcast i32 %795 to float
>  %797 = fsub float -0.000000e+00, %754
>  %798 = fadd float 1.000000e+00, %797
>  %799 = fsub float -0.000000e+00, %755
>  %800 = fadd float 1.000000e+00, %799
>  %801 = fsub float -0.000000e+00, %756
>  %802 = fadd float 1.000000e+00, %801
>  %803 = fsub float -0.000000e+00, %757
>  %804 = fadd float 1.000000e+00, %803
>  %805 = fmul float %772, %798
>  %806 = fmul float %780, %800
>  %807 = fmul float %788, %802
>  %808 = fmul float %796, %804
>  %809 = fmul float %805, 1.000000e+00
>  %810 = fmul float %806, 1.000000e+00
>  %811 = fadd float %809, %810
>  %812 = fmul float %807, 1.000000e+00
>  %813 = fadd float %811, %812
>  %814 = fmul float %808, 1.000000e+00
>  %815 = fadd float %813, %814
>  %816 = fmul float %341, 4.000000e+00
>  %817 = fsub float -0.000000e+00, %816
>  %818 = fadd float %356, %817
>  %819 = fsub float -0.000000e+00, %816
>  %820 = fadd float %359, %819
>  %821 = fsub float -0.000000e+00, %816
>  %822 = fadd float %362, %821
>  %823 = fsub float -0.000000e+00, %816
>  %824 = fadd float %365, %823
>  %825 = fmul float %319, %57
>  %826 = fmul float %320, %58
>  %827 = fadd float %826, %825
>  %828 = fmul float %321, %59
>  %829 = fadd float %827, %828
>  %830 = fmul float %829, %319
>  %831 = fmul float %829, %320
>  %832 = fmul float %829, %321
>  %833 = fmul float 2.000000e+00, %830
>  %834 = fmul float 2.000000e+00, %831
>  %835 = fmul float 2.000000e+00, %832
>  %836 = fsub float -0.000000e+00, %833
>  %837 = fadd float %57, %836
>  %838 = fsub float -0.000000e+00, %834
>  %839 = fadd float %58, %838
>  %840 = fsub float -0.000000e+00, %835
>  %841 = fadd float %59, %840
>  %842 = fmul float %837, %818
>  %843 = fmul float %839, %818
>  %844 = fmul float %841, %818
>  %845 = fmul float %319, %60
>  %846 = fmul float %320, %61
>  %847 = fadd float %846, %845
>  %848 = fmul float %321, %62
>  %849 = fadd float %847, %848
>  %850 = fmul float %849, %319
>  %851 = fmul float %849, %320
>  %852 = fmul float %849, %321
>  %853 = fmul float 2.000000e+00, %850
>  %854 = fmul float 2.000000e+00, %851
>  %855 = fmul float 2.000000e+00, %852
>  %856 = fsub float -0.000000e+00, %853
>  %857 = fadd float %60, %856
>  %858 = fsub float -0.000000e+00, %854
>  %859 = fadd float %61, %858
>  %860 = fsub float -0.000000e+00, %855
>  %861 = fadd float %62, %860
>  %862 = fmul float %857, %820
>  %863 = fmul float %859, %820
>  %864 = fmul float %861, %820
>  %865 = fmul float %319, %63
>  %866 = fmul float %320, %64
>  %867 = fadd float %866, %865
>  %868 = fmul float %321, %65
>  %869 = fadd float %867, %868
>  %870 = fmul float %869, %319
>  %871 = fmul float %869, %320
>  %872 = fmul float %869, %321
>  %873 = fmul float 2.000000e+00, %870
>  %874 = fmul float 2.000000e+00, %871
>  %875 = fmul float 2.000000e+00, %872
>  %876 = fsub float -0.000000e+00, %873
>  %877 = fadd float %63, %876
>  %878 = fsub float -0.000000e+00, %874
>  %879 = fadd float %64, %878
>  %880 = fsub float -0.000000e+00, %875
>  %881 = fadd float %65, %880
>  %882 = fmul float %877, %822
>  %883 = fmul float %879, %822
>  %884 = fmul float %881, %822
>  %885 = fmul float %319, %66
>  %886 = fmul float %320, %67
>  %887 = fadd float %886, %885
>  %888 = fmul float %321, %68
>  %889 = fadd float %887, %888
>  %890 = fmul float %889, %319
>  %891 = fmul float %889, %320
>  %892 = fmul float %889, %321
>  %893 = fmul float 2.000000e+00, %890
>  %894 = fmul float 2.000000e+00, %891
>  %895 = fmul float 2.000000e+00, %892
>  %896 = fsub float -0.000000e+00, %893
>  %897 = fadd float %66, %896
>  %898 = fsub float -0.000000e+00, %894
>  %899 = fadd float %67, %898
>  %900 = fsub float -0.000000e+00, %895
>  %901 = fadd float %68, %900
>  %902 = fmul float %897, %824
>  %903 = fmul float %899, %824
>  %904 = fmul float %901, %824
>  %905 = fmul float %842, %286
>  %906 = fmul float %843, %287
>  %907 = fadd float %906, %905
>  %908 = fmul float %844, %288
>  %909 = fadd float %907, %908
>  %910 = fmul float %862, %286
>  %911 = fmul float %863, %287
>  %912 = fadd float %911, %910
>  %913 = fmul float %864, %288
>  %914 = fadd float %912, %913
>  %915 = fmul float %882, %286
>  %916 = fmul float %883, %287
>  %917 = fadd float %916, %915
>  %918 = fmul float %884, %288
>  %919 = fadd float %917, %918
>  %920 = fmul float %902, %286
>  %921 = fmul float %903, %287
>  %922 = fadd float %921, %920
>  %923 = fmul float %904, %288
>  %924 = fadd float %922, %923
>  %925 = fcmp uge float %909, 0.000000e+00
>  %926 = select i1 %925, float 1.000000e+00, float 0.000000e+00
>  %927 = fsub float -0.000000e+00, %926
>  %928 = fptosi float %927 to i32
>  %929 = bitcast i32 %928 to float
>  %930 = bitcast float %929 to i32
>  %931 = icmp ne i32 %930, 0
>  %temp68.0 = select i1 %931, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %932 = bitcast float %temp68.0 to i32
>  %933 = sitofp i32 %932 to float
>  %934 = fmul float %842, %933
>  %935 = fmul float %843, %933
>  %936 = fmul float %844, %933
>  %937 = fcmp uge float %914, 0.000000e+00
>  %938 = select i1 %937, float 1.000000e+00, float 0.000000e+00
>  %939 = fsub float -0.000000e+00, %938
>  %940 = fptosi float %939 to i32
>  %941 = bitcast i32 %940 to float
>  %942 = bitcast float %941 to i32
>  %943 = icmp ne i32 %942, 0
>  %.220 = select i1 %943, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %944 = bitcast float %.220 to i32
>  %945 = sitofp i32 %944 to float
>  %946 = fmul float %862, %945
>  %947 = fmul float %863, %945
>  %948 = fmul float %864, %945
>  %949 = fcmp uge float %919, 0.000000e+00
>  %950 = select i1 %949, float 1.000000e+00, float 0.000000e+00
>  %951 = fsub float -0.000000e+00, %950
>  %952 = fptosi float %951 to i32
>  %953 = bitcast i32 %952 to float
>  %954 = bitcast float %953 to i32
>  %955 = icmp ne i32 %954, 0
>  %temp68.2 = select i1 %955, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %956 = bitcast float %temp68.2 to i32
>  %957 = sitofp i32 %956 to float
>  %958 = fmul float %882, %957
>  %959 = fmul float %883, %957
>  %960 = fmul float %884, %957
>  %961 = fcmp uge float %924, 0.000000e+00
>  %962 = select i1 %961, float 1.000000e+00, float 0.000000e+00
>  %963 = fsub float -0.000000e+00, %962
>  %964 = fptosi float %963 to i32
>  %965 = bitcast i32 %964 to float
>  %966 = bitcast float %965 to i32
>  %967 = icmp ne i32 %966, 0
>  %.221 = select i1 %967, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %968 = bitcast float %.221 to i32
>  %969 = sitofp i32 %968 to float
>  %970 = fmul float %902, %969
>  %971 = fmul float %903, %969
>  %972 = fmul float %904, %969
>  %973 = fadd float %296, %934
>  %974 = fadd float %298, %935
>  %975 = fadd float %296, %946
>  %976 = fadd float %298, %947
>  %977 = fadd float %296, %958
>  %978 = fadd float %298, %959
>  %979 = fadd float %296, %970
>  %980 = fadd float %298, %971
>  %981 = fadd float %300, %936
>  %982 = fadd float %300, %948
>  %983 = fadd float %300, %960
>  %984 = fadd float %300, %972
>  %985 = fsub float -0.000000e+00, %981
>  %986 = fdiv float 1.000000e+00, %985
>  %987 = fsub float -0.000000e+00, %982
>  %988 = fdiv float 1.000000e+00, %987
>  %989 = fmul float %973, %986
>  %990 = fmul float %974, %986
>  %991 = fmul float %975, %988
>  %992 = fmul float %976, %988
>  %993 = fsub float -0.000000e+00, %29
>  %994 = fmul float %989, %28
>  %995 = fadd float %994, %993
>  %996 = fsub float -0.000000e+00, %31
>  %997 = fmul float %990, %30
>  %998 = fadd float %997, %996
>  %999 = fsub float -0.000000e+00, %29
>  %1000 = fmul float %991, %28
>  %1001 = fadd float %1000, %999
>  %1002 = fsub float -0.000000e+00, %31
>  %1003 = fmul float %992, %30
>  %1004 = fadd float %1003, %1002
>  %1005 = fsub float -0.000000e+00, %983
>  %1006 = fdiv float 1.000000e+00, %1005
>  %1007 = fsub float -0.000000e+00, %984
>  %1008 = fdiv float 1.000000e+00, %1007
>  %1009 = fmul float %977, %1006
>  %1010 = fmul float %978, %1006
>  %1011 = fmul float %979, %1008
>  %1012 = fmul float %980, %1008
>  %1013 = fsub float -0.000000e+00, %29
>  %1014 = fmul float %1009, %28
>  %1015 = fadd float %1014, %1013
>  %1016 = fsub float -0.000000e+00, %31
>  %1017 = fmul float %1010, %30
>  %1018 = fadd float %1017, %1016
>  %1019 = fsub float -0.000000e+00, %29
>  %1020 = fmul float %1011, %28
>  %1021 = fadd float %1020, %1019
>  %1022 = fsub float -0.000000e+00, %31
>  %1023 = fmul float %1012, %30
>  %1024 = fadd float %1023, %1022
>  %1025 = fmul float %995, 5.000000e-01
>  %1026 = fadd float %1025, 5.000000e-01
>  %1027 = fmul float %998, -5.000000e-01
>  %1028 = fadd float %1027, 5.000000e-01
>  %1029 = fmul float %1001, 5.000000e-01
>  %1030 = fadd float %1029, 5.000000e-01
>  %1031 = fmul float %1004, -5.000000e-01
>  %1032 = fadd float %1031, 5.000000e-01
>  %1033 = fmul float %1015, 5.000000e-01
>  %1034 = fadd float %1033, 5.000000e-01
>  %1035 = fmul float %1018, -5.000000e-01
>  %1036 = fadd float %1035, 5.000000e-01
>  %1037 = fmul float %1021, 5.000000e-01
>  %1038 = fadd float %1037, 5.000000e-01
>  %1039 = fmul float %1024, -5.000000e-01
>  %1040 = fadd float %1039, 5.000000e-01
>  %1041 = call float @llvm.AMDIL.clamp.(float %1026, float 0.000000e+00, float 1.000000e+00)
>  %1042 = call float @llvm.AMDIL.clamp.(float %1028, float 0.000000e+00, float 1.000000e+00)
>  %1043 = call float @llvm.AMDIL.clamp.(float %1030, float 0.000000e+00, float 1.000000e+00)
>  %1044 = call float @llvm.AMDIL.clamp.(float %1032, float 0.000000e+00, float 1.000000e+00)
>  %1045 = call float @llvm.AMDIL.clamp.(float %1034, float 0.000000e+00, float 1.000000e+00)
>  %1046 = call float @llvm.AMDIL.clamp.(float %1036, float 0.000000e+00, float 1.000000e+00)
>  %1047 = call float @llvm.AMDIL.clamp.(float %1038, float 0.000000e+00, float 1.000000e+00)
>  %1048 = call float @llvm.AMDIL.clamp.(float %1040, float 0.000000e+00, float 1.000000e+00)
>  %1049 = bitcast float %1041 to i32
>  %1050 = bitcast float %1042 to i32
>  %1051 = insertelement <2 x i32> undef, i32 %1049, i32 0
>  %1052 = insertelement <2 x i32> %1051, i32 %1050, i32 1
>  %1053 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1052, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1054 = extractelement <4 x float> %1053, i32 0
>  %1055 = bitcast float %1043 to i32
>  %1056 = bitcast float %1044 to i32
>  %1057 = insertelement <2 x i32> undef, i32 %1055, i32 0
>  %1058 = insertelement <2 x i32> %1057, i32 %1056, i32 1
>  %1059 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1058, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1060 = extractelement <4 x float> %1059, i32 0
>  %1061 = bitcast float %1045 to i32
>  %1062 = bitcast float %1046 to i32
>  %1063 = insertelement <2 x i32> undef, i32 %1061, i32 0
>  %1064 = insertelement <2 x i32> %1063, i32 %1062, i32 1
>  %1065 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1064, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1066 = extractelement <4 x float> %1065, i32 0
>  %1067 = bitcast float %1047 to i32
>  %1068 = bitcast float %1048 to i32
>  %1069 = insertelement <2 x i32> undef, i32 %1067, i32 0
>  %1070 = insertelement <2 x i32> %1069, i32 %1068, i32 1
>  %1071 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1070, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1072 = extractelement <4 x float> %1071, i32 0
>  %1073 = call float @fabs(float %1054)
>  %1074 = call float @fabs(float %1060)
>  %1075 = call float @fabs(float %1066)
>  %1076 = call float @fabs(float %1072)
>  %1077 = fsub float -0.000000e+00, %26
>  %1078 = fmul float %1073, %27
>  %1079 = fadd float %1078, %1077
>  %1080 = fsub float -0.000000e+00, %26
>  %1081 = fmul float %1074, %27
>  %1082 = fadd float %1081, %1080
>  %1083 = fsub float -0.000000e+00, %26
>  %1084 = fmul float %1075, %27
>  %1085 = fadd float %1084, %1083
>  %1086 = fsub float -0.000000e+00, %26
>  %1087 = fmul float %1076, %27
>  %1088 = fadd float %1087, %1086
>  %1089 = fsub float -0.000000e+00, %981
>  %1090 = fadd float %1079, %1089
>  %1091 = fsub float -0.000000e+00, %982
>  %1092 = fadd float %1082, %1091
>  %1093 = fsub float -0.000000e+00, %983
>  %1094 = fadd float %1085, %1093
>  %1095 = fsub float -0.000000e+00, %984
>  %1096 = fadd float %1088, %1095
>  %1097 = fmul float %818, 2.000000e+00
>  %1098 = fmul float %820, 2.000000e+00
>  %1099 = fmul float %822, 2.000000e+00
>  %1100 = fmul float %824, 2.000000e+00
>  %1101 = fcmp uge float %1090, %1097
>  %1102 = select i1 %1101, float 1.000000e+00, float 0.000000e+00
>  %1103 = fsub float -0.000000e+00, %1102
>  %1104 = fptosi float %1103 to i32
>  %1105 = bitcast i32 %1104 to float
>  %1106 = bitcast float %1105 to i32
>  %1107 = and i32 %1106, 1065353216
>  %1108 = bitcast i32 %1107 to float
>  %1109 = fcmp uge float %1092, %1098
>  %1110 = select i1 %1109, float 1.000000e+00, float 0.000000e+00
>  %1111 = fsub float -0.000000e+00, %1110
>  %1112 = fptosi float %1111 to i32
>  %1113 = bitcast i32 %1112 to float
>  %1114 = bitcast float %1113 to i32
>  %1115 = and i32 %1114, 1065353216
>  %1116 = bitcast i32 %1115 to float
>  %1117 = fcmp uge float %1094, %1099
>  %1118 = select i1 %1117, float 1.000000e+00, float 0.000000e+00
>  %1119 = fsub float -0.000000e+00, %1118
>  %1120 = fptosi float %1119 to i32
>  %1121 = bitcast i32 %1120 to float
>  %1122 = bitcast float %1121 to i32
>  %1123 = and i32 %1122, 1065353216
>  %1124 = bitcast i32 %1123 to float
>  %1125 = fcmp uge float %1096, %1100
>  %1126 = select i1 %1125, float 1.000000e+00, float 0.000000e+00
>  %1127 = fsub float -0.000000e+00, %1126
>  %1128 = fptosi float %1127 to i32
>  %1129 = bitcast i32 %1128 to float
>  %1130 = bitcast float %1129 to i32
>  %1131 = and i32 %1130, 1065353216
>  %1132 = bitcast i32 %1131 to float
>  %1133 = fcmp ueq float %1079, 0.000000e+00
>  %1134 = select i1 %1133, float 1.000000e+00, float 0.000000e+00
>  %1135 = fsub float -0.000000e+00, %1134
>  %1136 = fptosi float %1135 to i32
>  %1137 = bitcast i32 %1136 to float
>  %1138 = bitcast float %1137 to i32
>  %1139 = icmp ne i32 %1138, 0
>  %temp92.1 = select i1 %1139, float 0x36A0000000000000, float 0.000000e+00
>  %1140 = fcmp ueq float %1082, 0.000000e+00
>  %1141 = select i1 %1140, float 1.000000e+00, float 0.000000e+00
>  %1142 = fsub float -0.000000e+00, %1141
>  %1143 = fptosi float %1142 to i32
>  %1144 = bitcast i32 %1143 to float
>  %1145 = bitcast float %1144 to i32
>  %1146 = icmp ne i32 %1145, 0
>  %.222 = select i1 %1146, float 0x36A0000000000000, float 0.000000e+00
>  %1147 = fcmp ueq float %1085, 0.000000e+00
>  %1148 = select i1 %1147, float 1.000000e+00, float 0.000000e+00
>  %1149 = fsub float -0.000000e+00, %1148
>  %1150 = fptosi float %1149 to i32
>  %1151 = bitcast i32 %1150 to float
>  %1152 = bitcast float %1151 to i32
>  %1153 = icmp ne i32 %1152, 0
>  %temp104.1 = select i1 %1153, float 0x36A0000000000000, float 0.000000e+00
>  %1154 = fcmp ueq float %1088, 0.000000e+00
>  %1155 = select i1 %1154, float 1.000000e+00, float 0.000000e+00
>  %1156 = fsub float -0.000000e+00, %1155
>  %1157 = fptosi float %1156 to i32
>  %1158 = bitcast i32 %1157 to float
>  %1159 = bitcast float %1158 to i32
>  %1160 = icmp ne i32 %1159, 0
>  %.223 = select i1 %1160, float 0x36A0000000000000, float 0.000000e+00
>  %1161 = bitcast float %temp92.1 to i32
>  %1162 = sitofp i32 %1161 to float
>  %1163 = bitcast float %.222 to i32
>  %1164 = sitofp i32 %1163 to float
>  %1165 = bitcast float %temp104.1 to i32
>  %1166 = sitofp i32 %1165 to float
>  %1167 = bitcast float %.223 to i32
>  %1168 = sitofp i32 %1167 to float
>  %1169 = fcmp uge float 0.000000e+00, %1054
>  %1170 = select i1 %1169, float 1.000000e+00, float 0.000000e+00
>  %1171 = fsub float -0.000000e+00, %1170
>  %1172 = fptosi float %1171 to i32
>  %1173 = bitcast i32 %1172 to float
>  %1174 = bitcast float %1173 to i32
>  %1175 = and i32 %1174, 1065353216
>  %1176 = bitcast i32 %1175 to float
>  %1177 = fcmp uge float 0.000000e+00, %1060
>  %1178 = select i1 %1177, float 1.000000e+00, float 0.000000e+00
>  %1179 = fsub float -0.000000e+00, %1178
>  %1180 = fptosi float %1179 to i32
>  %1181 = bitcast i32 %1180 to float
>  %1182 = bitcast float %1181 to i32
>  %1183 = and i32 %1182, 1065353216
>  %1184 = bitcast i32 %1183 to float
>  %1185 = fcmp uge float 0.000000e+00, %1066
>  %1186 = select i1 %1185, float 1.000000e+00, float 0.000000e+00
>  %1187 = fsub float -0.000000e+00, %1186
>  %1188 = fptosi float %1187 to i32
>  %1189 = bitcast i32 %1188 to float
>  %1190 = bitcast float %1189 to i32
>  %1191 = and i32 %1190, 1065353216
>  %1192 = bitcast i32 %1191 to float
>  %1193 = fcmp uge float 0.000000e+00, %1072
>  %1194 = select i1 %1193, float 1.000000e+00, float 0.000000e+00
>  %1195 = fsub float -0.000000e+00, %1194
>  %1196 = fptosi float %1195 to i32
>  %1197 = bitcast i32 %1196 to float
>  %1198 = bitcast float %1197 to i32
>  %1199 = and i32 %1198, 1065353216
>  %1200 = bitcast i32 %1199 to float
>  %1201 = fadd float %1108, %1162
>  %1202 = fadd float %1116, %1164
>  %1203 = fadd float %1124, %1166
>  %1204 = fadd float %1132, %1168
>  %1205 = fmul float %1176, %349
>  %1206 = fadd float %1205, %1201
>  %1207 = fmul float %1184, %349
>  %1208 = fadd float %1207, %1202
>  %1209 = fmul float %1192, %349
>  %1210 = fadd float %1209, %1203
>  %1211 = fmul float %1200, %349
>  %1212 = fadd float %1211, %1204
>  %1213 = call float @llvm.AMDIL.clamp.(float %1206, float 0.000000e+00, float 1.000000e+00)
>  %1214 = call float @llvm.AMDIL.clamp.(float %1208, float 0.000000e+00, float 1.000000e+00)
>  %1215 = call float @llvm.AMDIL.clamp.(float %1210, float 0.000000e+00, float 1.000000e+00)
>  %1216 = call float @llvm.AMDIL.clamp.(float %1212, float 0.000000e+00, float 1.000000e+00)
>  %1217 = fmul float %1213, 1.000000e+00
>  %1218 = fmul float %1214, 1.000000e+00
>  %1219 = fadd float %1217, %1218
>  %1220 = fmul float %1215, 1.000000e+00
>  %1221 = fadd float %1219, %1220
>  %1222 = fmul float %1216, 1.000000e+00
>  %1223 = fadd float %1221, %1222
>  %1224 = fadd float %764, %1223
>  %1225 = fcmp uge float %1090, 0.000000e+00
>  %1226 = select i1 %1225, float 1.000000e+00, float 0.000000e+00
>  %1227 = fsub float -0.000000e+00, %1226
>  %1228 = fptosi float %1227 to i32
>  %1229 = bitcast i32 %1228 to float
>  %1230 = bitcast float %1229 to i32
>  %1231 = and i32 %1230, 1065353216
>  %1232 = bitcast i32 %1231 to float
>  %1233 = fcmp uge float %1092, 0.000000e+00
>  %1234 = select i1 %1233, float 1.000000e+00, float 0.000000e+00
>  %1235 = fsub float -0.000000e+00, %1234
>  %1236 = fptosi float %1235 to i32
>  %1237 = bitcast i32 %1236 to float
>  %1238 = bitcast float %1237 to i32
>  %1239 = and i32 %1238, 1065353216
>  %1240 = bitcast i32 %1239 to float
>  %1241 = fcmp uge float %1094, 0.000000e+00
>  %1242 = select i1 %1241, float 1.000000e+00, float 0.000000e+00
>  %1243 = fsub float -0.000000e+00, %1242
>  %1244 = fptosi float %1243 to i32
>  %1245 = bitcast i32 %1244 to float
>  %1246 = bitcast float %1245 to i32
>  %1247 = and i32 %1246, 1065353216
>  %1248 = bitcast i32 %1247 to float
>  %1249 = fcmp uge float %1096, 0.000000e+00
>  %1250 = select i1 %1249, float 1.000000e+00, float 0.000000e+00
>  %1251 = fsub float -0.000000e+00, %1250
>  %1252 = fptosi float %1251 to i32
>  %1253 = bitcast i32 %1252 to float
>  %1254 = bitcast float %1253 to i32
>  %1255 = and i32 %1254, 1065353216
>  %1256 = bitcast i32 %1255 to float
>  %1257 = fsub float -0.000000e+00, %1213
>  %1258 = fadd float 1.000000e+00, %1257
>  %1259 = fsub float -0.000000e+00, %1214
>  %1260 = fadd float 1.000000e+00, %1259
>  %1261 = fsub float -0.000000e+00, %1215
>  %1262 = fadd float 1.000000e+00, %1261
>  %1263 = fsub float -0.000000e+00, %1216
>  %1264 = fadd float 1.000000e+00, %1263
>  %1265 = fmul float %1232, %1258
>  %1266 = fmul float %1240, %1260
>  %1267 = fmul float %1248, %1262
>  %1268 = fmul float %1256, %1264
>  %1269 = fmul float %1265, 1.000000e+00
>  %1270 = fmul float %1266, 1.000000e+00
>  %1271 = fadd float %1269, %1270
>  %1272 = fmul float %1267, 1.000000e+00
>  %1273 = fadd float %1271, %1272
>  %1274 = fmul float %1268, 1.000000e+00
>  %1275 = fadd float %1273, %1274
>  %1276 = fadd float %815, %1275
>  %1277 = fmul float %341, 4.000000e+00
>  %1278 = fsub float -0.000000e+00, %1277
>  %1279 = fadd float %818, %1278
>  %1280 = fsub float -0.000000e+00, %1277
>  %1281 = fadd float %820, %1280
>  %1282 = fsub float -0.000000e+00, %1277
>  %1283 = fadd float %822, %1282
>  %1284 = fsub float -0.000000e+00, %1277
>  %1285 = fadd float %824, %1284
>  %1286 = fmul float %319, %69
>  %1287 = fmul float %320, %70
>  %1288 = fadd float %1287, %1286
>  %1289 = fmul float %321, %71
>  %1290 = fadd float %1288, %1289
>  %1291 = fmul float %1290, %319
>  %1292 = fmul float %1290, %320
>  %1293 = fmul float %1290, %321
>  %1294 = fmul float 2.000000e+00, %1291
>  %1295 = fmul float 2.000000e+00, %1292
>  %1296 = fmul float 2.000000e+00, %1293
>  %1297 = fsub float -0.000000e+00, %1294
>  %1298 = fadd float %69, %1297
>  %1299 = fsub float -0.000000e+00, %1295
>  %1300 = fadd float %70, %1299
>  %1301 = fsub float -0.000000e+00, %1296
>  %1302 = fadd float %71, %1301
>  %1303 = fmul float %1298, %1279
>  %1304 = fmul float %1300, %1279
>  %1305 = fmul float %1302, %1279
>  %1306 = fmul float %319, %72
>  %1307 = fmul float %320, %73
>  %1308 = fadd float %1307, %1306
>  %1309 = fmul float %321, %74
>  %1310 = fadd float %1308, %1309
>  %1311 = fmul float %1310, %319
>  %1312 = fmul float %1310, %320
>  %1313 = fmul float %1310, %321
>  %1314 = fmul float 2.000000e+00, %1311
>  %1315 = fmul float 2.000000e+00, %1312
>  %1316 = fmul float 2.000000e+00, %1313
>  %1317 = fsub float -0.000000e+00, %1314
>  %1318 = fadd float %72, %1317
>  %1319 = fsub float -0.000000e+00, %1315
>  %1320 = fadd float %73, %1319
>  %1321 = fsub float -0.000000e+00, %1316
>  %1322 = fadd float %74, %1321
>  %1323 = fmul float %1318, %1281
>  %1324 = fmul float %1320, %1281
>  %1325 = fmul float %1322, %1281
>  %1326 = fmul float %319, %75
>  %1327 = fmul float %320, %76
>  %1328 = fadd float %1327, %1326
>  %1329 = fmul float %321, %77
>  %1330 = fadd float %1328, %1329
>  %1331 = fmul float %1330, %319
>  %1332 = fmul float %1330, %320
>  %1333 = fmul float %1330, %321
>  %1334 = fmul float 2.000000e+00, %1331
>  %1335 = fmul float 2.000000e+00, %1332
>  %1336 = fmul float 2.000000e+00, %1333
>  %1337 = fsub float -0.000000e+00, %1334
>  %1338 = fadd float %75, %1337
>  %1339 = fsub float -0.000000e+00, %1335
>  %1340 = fadd float %76, %1339
>  %1341 = fsub float -0.000000e+00, %1336
>  %1342 = fadd float %77, %1341
>  %1343 = fmul float %1338, %1283
>  %1344 = fmul float %1340, %1283
>  %1345 = fmul float %1342, %1283
>  %1346 = fmul float %319, %78
>  %1347 = fmul float %320, %79
>  %1348 = fadd float %1347, %1346
>  %1349 = fmul float %321, %80
>  %1350 = fadd float %1348, %1349
>  %1351 = fmul float %1350, %319
>  %1352 = fmul float %1350, %320
>  %1353 = fmul float %1350, %321
>  %1354 = fmul float 2.000000e+00, %1351
>  %1355 = fmul float 2.000000e+00, %1352
>  %1356 = fmul float 2.000000e+00, %1353
>  %1357 = fsub float -0.000000e+00, %1354
>  %1358 = fadd float %78, %1357
>  %1359 = fsub float -0.000000e+00, %1355
>  %1360 = fadd float %79, %1359
>  %1361 = fsub float -0.000000e+00, %1356
>  %1362 = fadd float %80, %1361
>  %1363 = fmul float %1358, %1285
>  %1364 = fmul float %1360, %1285
>  %1365 = fmul float %1362, %1285
>  %1366 = fmul float %1303, %286
>  %1367 = fmul float %1304, %287
>  %1368 = fadd float %1367, %1366
>  %1369 = fmul float %1305, %288
>  %1370 = fadd float %1368, %1369
>  %1371 = fmul float %1323, %286
>  %1372 = fmul float %1324, %287
>  %1373 = fadd float %1372, %1371
>  %1374 = fmul float %1325, %288
>  %1375 = fadd float %1373, %1374
>  %1376 = fmul float %1343, %286
>  %1377 = fmul float %1344, %287
>  %1378 = fadd float %1377, %1376
>  %1379 = fmul float %1345, %288
>  %1380 = fadd float %1378, %1379
>  %1381 = fmul float %1363, %286
>  %1382 = fmul float %1364, %287
>  %1383 = fadd float %1382, %1381
>  %1384 = fmul float %1365, %288
>  %1385 = fadd float %1383, %1384
>  %1386 = fcmp uge float %1370, 0.000000e+00
>  %1387 = select i1 %1386, float 1.000000e+00, float 0.000000e+00
>  %1388 = fsub float -0.000000e+00, %1387
>  %1389 = fptosi float %1388 to i32
>  %1390 = bitcast i32 %1389 to float
>  %1391 = bitcast float %1390 to i32
>  %1392 = icmp ne i32 %1391, 0
>  %temp68.4 = select i1 %1392, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1393 = bitcast float %temp68.4 to i32
>  %1394 = sitofp i32 %1393 to float
>  %1395 = fmul float %1303, %1394
>  %1396 = fmul float %1304, %1394
>  %1397 = fmul float %1305, %1394
>  %1398 = fcmp uge float %1375, 0.000000e+00
>  %1399 = select i1 %1398, float 1.000000e+00, float 0.000000e+00
>  %1400 = fsub float -0.000000e+00, %1399
>  %1401 = fptosi float %1400 to i32
>  %1402 = bitcast i32 %1401 to float
>  %1403 = bitcast float %1402 to i32
>  %1404 = icmp ne i32 %1403, 0
>  %.224 = select i1 %1404, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1405 = bitcast float %.224 to i32
>  %1406 = sitofp i32 %1405 to float
>  %1407 = fmul float %1323, %1406
>  %1408 = fmul float %1324, %1406
>  %1409 = fmul float %1325, %1406
>  %1410 = fcmp uge float %1380, 0.000000e+00
>  %1411 = select i1 %1410, float 1.000000e+00, float 0.000000e+00
>  %1412 = fsub float -0.000000e+00, %1411
>  %1413 = fptosi float %1412 to i32
>  %1414 = bitcast i32 %1413 to float
>  %1415 = bitcast float %1414 to i32
>  %1416 = icmp ne i32 %1415, 0
>  %temp68.6 = select i1 %1416, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1417 = bitcast float %temp68.6 to i32
>  %1418 = sitofp i32 %1417 to float
>  %1419 = fmul float %1343, %1418
>  %1420 = fmul float %1344, %1418
>  %1421 = fmul float %1345, %1418
>  %1422 = fcmp uge float %1385, 0.000000e+00
>  %1423 = select i1 %1422, float 1.000000e+00, float 0.000000e+00
>  %1424 = fsub float -0.000000e+00, %1423
>  %1425 = fptosi float %1424 to i32
>  %1426 = bitcast i32 %1425 to float
>  %1427 = bitcast float %1426 to i32
>  %1428 = icmp ne i32 %1427, 0
>  %.225 = select i1 %1428, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1429 = bitcast float %.225 to i32
>  %1430 = sitofp i32 %1429 to float
>  %1431 = fmul float %1363, %1430
>  %1432 = fmul float %1364, %1430
>  %1433 = fmul float %1365, %1430
>  %1434 = fadd float %296, %1395
>  %1435 = fadd float %298, %1396
>  %1436 = fadd float %296, %1407
>  %1437 = fadd float %298, %1408
>  %1438 = fadd float %296, %1419
>  %1439 = fadd float %298, %1420
>  %1440 = fadd float %296, %1431
>  %1441 = fadd float %298, %1432
>  %1442 = fadd float %300, %1397
>  %1443 = fadd float %300, %1409
>  %1444 = fadd float %300, %1421
>  %1445 = fadd float %300, %1433
>  %1446 = fsub float -0.000000e+00, %1442
>  %1447 = fdiv float 1.000000e+00, %1446
>  %1448 = fsub float -0.000000e+00, %1443
>  %1449 = fdiv float 1.000000e+00, %1448
>  %1450 = fmul float %1434, %1447
>  %1451 = fmul float %1435, %1447
>  %1452 = fmul float %1436, %1449
>  %1453 = fmul float %1437, %1449
>  %1454 = fsub float -0.000000e+00, %29
>  %1455 = fmul float %1450, %28
>  %1456 = fadd float %1455, %1454
>  %1457 = fsub float -0.000000e+00, %31
>  %1458 = fmul float %1451, %30
>  %1459 = fadd float %1458, %1457
>  %1460 = fsub float -0.000000e+00, %29
>  %1461 = fmul float %1452, %28
>  %1462 = fadd float %1461, %1460
>  %1463 = fsub float -0.000000e+00, %31
>  %1464 = fmul float %1453, %30
>  %1465 = fadd float %1464, %1463
>  %1466 = fsub float -0.000000e+00, %1444
>  %1467 = fdiv float 1.000000e+00, %1466
>  %1468 = fsub float -0.000000e+00, %1445
>  %1469 = fdiv float 1.000000e+00, %1468
>  %1470 = fmul float %1438, %1467
>  %1471 = fmul float %1439, %1467
>  %1472 = fmul float %1440, %1469
>  %1473 = fmul float %1441, %1469
>  %1474 = fsub float -0.000000e+00, %29
>  %1475 = fmul float %1470, %28
>  %1476 = fadd float %1475, %1474
>  %1477 = fsub float -0.000000e+00, %31
>  %1478 = fmul float %1471, %30
>  %1479 = fadd float %1478, %1477
>  %1480 = fsub float -0.000000e+00, %29
>  %1481 = fmul float %1472, %28
>  %1482 = fadd float %1481, %1480
>  %1483 = fsub float -0.000000e+00, %31
>  %1484 = fmul float %1473, %30
>  %1485 = fadd float %1484, %1483
>  %1486 = fmul float %1456, 5.000000e-01
>  %1487 = fadd float %1486, 5.000000e-01
>  %1488 = fmul float %1459, -5.000000e-01
>  %1489 = fadd float %1488, 5.000000e-01
>  %1490 = fmul float %1462, 5.000000e-01
>  %1491 = fadd float %1490, 5.000000e-01
>  %1492 = fmul float %1465, -5.000000e-01
>  %1493 = fadd float %1492, 5.000000e-01
>  %1494 = fmul float %1476, 5.000000e-01
>  %1495 = fadd float %1494, 5.000000e-01
>  %1496 = fmul float %1479, -5.000000e-01
>  %1497 = fadd float %1496, 5.000000e-01
>  %1498 = fmul float %1482, 5.000000e-01
>  %1499 = fadd float %1498, 5.000000e-01
>  %1500 = fmul float %1485, -5.000000e-01
>  %1501 = fadd float %1500, 5.000000e-01
>  %1502 = call float @llvm.AMDIL.clamp.(float %1487, float 0.000000e+00, float 1.000000e+00)
>  %1503 = call float @llvm.AMDIL.clamp.(float %1489, float 0.000000e+00, float 1.000000e+00)
>  %1504 = call float @llvm.AMDIL.clamp.(float %1491, float 0.000000e+00, float 1.000000e+00)
>  %1505 = call float @llvm.AMDIL.clamp.(float %1493, float 0.000000e+00, float 1.000000e+00)
>  %1506 = call float @llvm.AMDIL.clamp.(float %1495, float 0.000000e+00, float 1.000000e+00)
>  %1507 = call float @llvm.AMDIL.clamp.(float %1497, float 0.000000e+00, float 1.000000e+00)
>  %1508 = call float @llvm.AMDIL.clamp.(float %1499, float 0.000000e+00, float 1.000000e+00)
>  %1509 = call float @llvm.AMDIL.clamp.(float %1501, float 0.000000e+00, float 1.000000e+00)
>  %1510 = bitcast float %1502 to i32
>  %1511 = bitcast float %1503 to i32
>  %1512 = insertelement <2 x i32> undef, i32 %1510, i32 0
>  %1513 = insertelement <2 x i32> %1512, i32 %1511, i32 1
>  %1514 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1513, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1515 = extractelement <4 x float> %1514, i32 0
>  %1516 = bitcast float %1504 to i32
>  %1517 = bitcast float %1505 to i32
>  %1518 = insertelement <2 x i32> undef, i32 %1516, i32 0
>  %1519 = insertelement <2 x i32> %1518, i32 %1517, i32 1
>  %1520 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1519, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1521 = extractelement <4 x float> %1520, i32 0
>  %1522 = bitcast float %1506 to i32
>  %1523 = bitcast float %1507 to i32
>  %1524 = insertelement <2 x i32> undef, i32 %1522, i32 0
>  %1525 = insertelement <2 x i32> %1524, i32 %1523, i32 1
>  %1526 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1525, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1527 = extractelement <4 x float> %1526, i32 0
>  %1528 = bitcast float %1508 to i32
>  %1529 = bitcast float %1509 to i32
>  %1530 = insertelement <2 x i32> undef, i32 %1528, i32 0
>  %1531 = insertelement <2 x i32> %1530, i32 %1529, i32 1
>  %1532 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1531, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1533 = extractelement <4 x float> %1532, i32 0
>  %1534 = call float @fabs(float %1515)
>  %1535 = call float @fabs(float %1521)
>  %1536 = call float @fabs(float %1527)
>  %1537 = call float @fabs(float %1533)
>  %1538 = fsub float -0.000000e+00, %26
>  %1539 = fmul float %1534, %27
>  %1540 = fadd float %1539, %1538
>  %1541 = fsub float -0.000000e+00, %26
>  %1542 = fmul float %1535, %27
>  %1543 = fadd float %1542, %1541
>  %1544 = fsub float -0.000000e+00, %26
>  %1545 = fmul float %1536, %27
>  %1546 = fadd float %1545, %1544
>  %1547 = fsub float -0.000000e+00, %26
>  %1548 = fmul float %1537, %27
>  %1549 = fadd float %1548, %1547
>  %1550 = fsub float -0.000000e+00, %1442
>  %1551 = fadd float %1540, %1550
>  %1552 = fsub float -0.000000e+00, %1443
>  %1553 = fadd float %1543, %1552
>  %1554 = fsub float -0.000000e+00, %1444
>  %1555 = fadd float %1546, %1554
>  %1556 = fsub float -0.000000e+00, %1445
>  %1557 = fadd float %1549, %1556
>  %1558 = fmul float %1279, 2.000000e+00
>  %1559 = fmul float %1281, 2.000000e+00
>  %1560 = fmul float %1283, 2.000000e+00
>  %1561 = fmul float %1285, 2.000000e+00
>  %1562 = fcmp uge float %1551, %1558
>  %1563 = select i1 %1562, float 1.000000e+00, float 0.000000e+00
>  %1564 = fsub float -0.000000e+00, %1563
>  %1565 = fptosi float %1564 to i32
>  %1566 = bitcast i32 %1565 to float
>  %1567 = bitcast float %1566 to i32
>  %1568 = and i32 %1567, 1065353216
>  %1569 = bitcast i32 %1568 to float
>  %1570 = fcmp uge float %1553, %1559
>  %1571 = select i1 %1570, float 1.000000e+00, float 0.000000e+00
>  %1572 = fsub float -0.000000e+00, %1571
>  %1573 = fptosi float %1572 to i32
>  %1574 = bitcast i32 %1573 to float
>  %1575 = bitcast float %1574 to i32
>  %1576 = and i32 %1575, 1065353216
>  %1577 = bitcast i32 %1576 to float
>  %1578 = fcmp uge float %1555, %1560
>  %1579 = select i1 %1578, float 1.000000e+00, float 0.000000e+00
>  %1580 = fsub float -0.000000e+00, %1579
>  %1581 = fptosi float %1580 to i32
>  %1582 = bitcast i32 %1581 to float
>  %1583 = bitcast float %1582 to i32
>  %1584 = and i32 %1583, 1065353216
>  %1585 = bitcast i32 %1584 to float
>  %1586 = fcmp uge float %1557, %1561
>  %1587 = select i1 %1586, float 1.000000e+00, float 0.000000e+00
>  %1588 = fsub float -0.000000e+00, %1587
>  %1589 = fptosi float %1588 to i32
>  %1590 = bitcast i32 %1589 to float
>  %1591 = bitcast float %1590 to i32
>  %1592 = and i32 %1591, 1065353216
>  %1593 = bitcast i32 %1592 to float
>  %1594 = fcmp ueq float %1540, 0.000000e+00
>  %1595 = select i1 %1594, float 1.000000e+00, float 0.000000e+00
>  %1596 = fsub float -0.000000e+00, %1595
>  %1597 = fptosi float %1596 to i32
>  %1598 = bitcast i32 %1597 to float
>  %1599 = bitcast float %1598 to i32
>  %1600 = icmp ne i32 %1599, 0
>  %temp92.2 = select i1 %1600, float 0x36A0000000000000, float 0.000000e+00
>  %1601 = fcmp ueq float %1543, 0.000000e+00
>  %1602 = select i1 %1601, float 1.000000e+00, float 0.000000e+00
>  %1603 = fsub float -0.000000e+00, %1602
>  %1604 = fptosi float %1603 to i32
>  %1605 = bitcast i32 %1604 to float
>  %1606 = bitcast float %1605 to i32
>  %1607 = icmp ne i32 %1606, 0
>  %.226 = select i1 %1607, float 0x36A0000000000000, float 0.000000e+00
>  %1608 = fcmp ueq float %1546, 0.000000e+00
>  %1609 = select i1 %1608, float 1.000000e+00, float 0.000000e+00
>  %1610 = fsub float -0.000000e+00, %1609
>  %1611 = fptosi float %1610 to i32
>  %1612 = bitcast i32 %1611 to float
>  %1613 = bitcast float %1612 to i32
>  %1614 = icmp ne i32 %1613, 0
>  %temp104.2 = select i1 %1614, float 0x36A0000000000000, float 0.000000e+00
>  %1615 = fcmp ueq float %1549, 0.000000e+00
>  %1616 = select i1 %1615, float 1.000000e+00, float 0.000000e+00
>  %1617 = fsub float -0.000000e+00, %1616
>  %1618 = fptosi float %1617 to i32
>  %1619 = bitcast i32 %1618 to float
>  %1620 = bitcast float %1619 to i32
>  %1621 = icmp ne i32 %1620, 0
>  %.227 = select i1 %1621, float 0x36A0000000000000, float 0.000000e+00
>  %1622 = bitcast float %temp92.2 to i32
>  %1623 = sitofp i32 %1622 to float
>  %1624 = bitcast float %.226 to i32
>  %1625 = sitofp i32 %1624 to float
>  %1626 = bitcast float %temp104.2 to i32
>  %1627 = sitofp i32 %1626 to float
>  %1628 = bitcast float %.227 to i32
>  %1629 = sitofp i32 %1628 to float
>  %1630 = fcmp uge float 0.000000e+00, %1515
>  %1631 = select i1 %1630, float 1.000000e+00, float 0.000000e+00
>  %1632 = fsub float -0.000000e+00, %1631
>  %1633 = fptosi float %1632 to i32
>  %1634 = bitcast i32 %1633 to float
>  %1635 = bitcast float %1634 to i32
>  %1636 = and i32 %1635, 1065353216
>  %1637 = bitcast i32 %1636 to float
>  %1638 = fcmp uge float 0.000000e+00, %1521
>  %1639 = select i1 %1638, float 1.000000e+00, float 0.000000e+00
>  %1640 = fsub float -0.000000e+00, %1639
>  %1641 = fptosi float %1640 to i32
>  %1642 = bitcast i32 %1641 to float
>  %1643 = bitcast float %1642 to i32
>  %1644 = and i32 %1643, 1065353216
>  %1645 = bitcast i32 %1644 to float
>  %1646 = fcmp uge float 0.000000e+00, %1527
>  %1647 = select i1 %1646, float 1.000000e+00, float 0.000000e+00
>  %1648 = fsub float -0.000000e+00, %1647
>  %1649 = fptosi float %1648 to i32
>  %1650 = bitcast i32 %1649 to float
>  %1651 = bitcast float %1650 to i32
>  %1652 = and i32 %1651, 1065353216
>  %1653 = bitcast i32 %1652 to float
>  %1654 = fcmp uge float 0.000000e+00, %1533
>  %1655 = select i1 %1654, float 1.000000e+00, float 0.000000e+00
>  %1656 = fsub float -0.000000e+00, %1655
>  %1657 = fptosi float %1656 to i32
>  %1658 = bitcast i32 %1657 to float
>  %1659 = bitcast float %1658 to i32
>  %1660 = and i32 %1659, 1065353216
>  %1661 = bitcast i32 %1660 to float
>  %1662 = fadd float %1569, %1623
>  %1663 = fadd float %1577, %1625
>  %1664 = fadd float %1585, %1627
>  %1665 = fadd float %1593, %1629
>  %1666 = fmul float %1637, %349
>  %1667 = fadd float %1666, %1662
>  %1668 = fmul float %1645, %349
>  %1669 = fadd float %1668, %1663
>  %1670 = fmul float %1653, %349
>  %1671 = fadd float %1670, %1664
>  %1672 = fmul float %1661, %349
>  %1673 = fadd float %1672, %1665
>  %1674 = call float @llvm.AMDIL.clamp.(float %1667, float 0.000000e+00, float 1.000000e+00)
>  %1675 = call float @llvm.AMDIL.clamp.(float %1669, float 0.000000e+00, float 1.000000e+00)
>  %1676 = call float @llvm.AMDIL.clamp.(float %1671, float 0.000000e+00, float 1.000000e+00)
>  %1677 = call float @llvm.AMDIL.clamp.(float %1673, float 0.000000e+00, float 1.000000e+00)
>  %1678 = fmul float %1674, 1.000000e+00
>  %1679 = fmul float %1675, 1.000000e+00
>  %1680 = fadd float %1678, %1679
>  %1681 = fmul float %1676, 1.000000e+00
>  %1682 = fadd float %1680, %1681
>  %1683 = fmul float %1677, 1.000000e+00
>  %1684 = fadd float %1682, %1683
>  %1685 = fadd float %1224, %1684
>  %1686 = fcmp uge float %1551, 0.000000e+00
>  %1687 = select i1 %1686, float 1.000000e+00, float 0.000000e+00
>  %1688 = fsub float -0.000000e+00, %1687
>  %1689 = fptosi float %1688 to i32
>  %1690 = bitcast i32 %1689 to float
>  %1691 = bitcast float %1690 to i32
>  %1692 = and i32 %1691, 1065353216
>  %1693 = bitcast i32 %1692 to float
>  %1694 = fcmp uge float %1553, 0.000000e+00
>  %1695 = select i1 %1694, float 1.000000e+00, float 0.000000e+00
>  %1696 = fsub float -0.000000e+00, %1695
>  %1697 = fptosi float %1696 to i32
>  %1698 = bitcast i32 %1697 to float
>  %1699 = bitcast float %1698 to i32
>  %1700 = and i32 %1699, 1065353216
>  %1701 = bitcast i32 %1700 to float
>  %1702 = fcmp uge float %1555, 0.000000e+00
>  %1703 = select i1 %1702, float 1.000000e+00, float 0.000000e+00
>  %1704 = fsub float -0.000000e+00, %1703
>  %1705 = fptosi float %1704 to i32
>  %1706 = bitcast i32 %1705 to float
>  %1707 = bitcast float %1706 to i32
>  %1708 = and i32 %1707, 1065353216
>  %1709 = bitcast i32 %1708 to float
>  %1710 = fcmp uge float %1557, 0.000000e+00
>  %1711 = select i1 %1710, float 1.000000e+00, float 0.000000e+00
>  %1712 = fsub float -0.000000e+00, %1711
>  %1713 = fptosi float %1712 to i32
>  %1714 = bitcast i32 %1713 to float
>  %1715 = bitcast float %1714 to i32
>  %1716 = and i32 %1715, 1065353216
>  %1717 = bitcast i32 %1716 to float
>  %1718 = fsub float -0.000000e+00, %1674
>  %1719 = fadd float 1.000000e+00, %1718
>  %1720 = fsub float -0.000000e+00, %1675
>  %1721 = fadd float 1.000000e+00, %1720
>  %1722 = fsub float -0.000000e+00, %1676
>  %1723 = fadd float 1.000000e+00, %1722
>  %1724 = fsub float -0.000000e+00, %1677
>  %1725 = fadd float 1.000000e+00, %1724
>  %1726 = fmul float %1693, %1719
>  %1727 = fmul float %1701, %1721
>  %1728 = fmul float %1709, %1723
>  %1729 = fmul float %1717, %1725
>  %1730 = fmul float %1726, 1.000000e+00
>  %1731 = fmul float %1727, 1.000000e+00
>  %1732 = fadd float %1730, %1731
>  %1733 = fmul float %1728, 1.000000e+00
>  %1734 = fadd float %1732, %1733
>  %1735 = fmul float %1729, 1.000000e+00
>  %1736 = fadd float %1734, %1735
>  %1737 = fadd float %1276, %1736
>  %1738 = fmul float %341, 4.000000e+00
>  %1739 = fsub float -0.000000e+00, %1738
>  %1740 = fadd float %1279, %1739
>  %1741 = fsub float -0.000000e+00, %1738
>  %1742 = fadd float %1281, %1741
>  %1743 = fsub float -0.000000e+00, %1738
>  %1744 = fadd float %1283, %1743
>  %1745 = fsub float -0.000000e+00, %1738
>  %1746 = fadd float %1285, %1745
>  %1747 = fmul float %319, %81
>  %1748 = fmul float %320, %82
>  %1749 = fadd float %1748, %1747
>  %1750 = fmul float %321, %83
>  %1751 = fadd float %1749, %1750
>  %1752 = fmul float %1751, %319
>  %1753 = fmul float %1751, %320
>  %1754 = fmul float %1751, %321
>  %1755 = fmul float 2.000000e+00, %1752
>  %1756 = fmul float 2.000000e+00, %1753
>  %1757 = fmul float 2.000000e+00, %1754
>  %1758 = fsub float -0.000000e+00, %1755
>  %1759 = fadd float %81, %1758
>  %1760 = fsub float -0.000000e+00, %1756
>  %1761 = fadd float %82, %1760
>  %1762 = fsub float -0.000000e+00, %1757
>  %1763 = fadd float %83, %1762
>  %1764 = fmul float %1759, %1740
>  %1765 = fmul float %1761, %1740
>  %1766 = fmul float %1763, %1740
>  %1767 = fmul float %319, %84
>  %1768 = fmul float %320, %85
>  %1769 = fadd float %1768, %1767
>  %1770 = fmul float %321, %86
>  %1771 = fadd float %1769, %1770
>  %1772 = fmul float %1771, %319
>  %1773 = fmul float %1771, %320
>  %1774 = fmul float %1771, %321
>  %1775 = fmul float 2.000000e+00, %1772
>  %1776 = fmul float 2.000000e+00, %1773
>  %1777 = fmul float 2.000000e+00, %1774
>  %1778 = fsub float -0.000000e+00, %1775
>  %1779 = fadd float %84, %1778
>  %1780 = fsub float -0.000000e+00, %1776
>  %1781 = fadd float %85, %1780
>  %1782 = fsub float -0.000000e+00, %1777
>  %1783 = fadd float %86, %1782
>  %1784 = fmul float %1779, %1742
>  %1785 = fmul float %1781, %1742
>  %1786 = fmul float %1783, %1742
>  %1787 = fmul float %319, %87
>  %1788 = fmul float %320, %88
>  %1789 = fadd float %1788, %1787
>  %1790 = fmul float %321, %89
>  %1791 = fadd float %1789, %1790
>  %1792 = fmul float %1791, %319
>  %1793 = fmul float %1791, %320
>  %1794 = fmul float %1791, %321
>  %1795 = fmul float 2.000000e+00, %1792
>  %1796 = fmul float 2.000000e+00, %1793
>  %1797 = fmul float 2.000000e+00, %1794
>  %1798 = fsub float -0.000000e+00, %1795
>  %1799 = fadd float %87, %1798
>  %1800 = fsub float -0.000000e+00, %1796
>  %1801 = fadd float %88, %1800
>  %1802 = fsub float -0.000000e+00, %1797
>  %1803 = fadd float %89, %1802
>  %1804 = fmul float %1799, %1744
>  %1805 = fmul float %1801, %1744
>  %1806 = fmul float %1803, %1744
>  %1807 = fmul float %319, %90
>  %1808 = fmul float %320, %91
>  %1809 = fadd float %1808, %1807
>  %1810 = fmul float %321, %92
>  %1811 = fadd float %1809, %1810
>  %1812 = fmul float %1811, %319
>  %1813 = fmul float %1811, %320
>  %1814 = fmul float %1811, %321
>  %1815 = fmul float 2.000000e+00, %1812
>  %1816 = fmul float 2.000000e+00, %1813
>  %1817 = fmul float 2.000000e+00, %1814
>  %1818 = fsub float -0.000000e+00, %1815
>  %1819 = fadd float %90, %1818
>  %1820 = fsub float -0.000000e+00, %1816
>  %1821 = fadd float %91, %1820
>  %1822 = fsub float -0.000000e+00, %1817
>  %1823 = fadd float %92, %1822
>  %1824 = fmul float %1819, %1746
>  %1825 = fmul float %1821, %1746
>  %1826 = fmul float %1823, %1746
>  %1827 = fmul float %1764, %286
>  %1828 = fmul float %1765, %287
>  %1829 = fadd float %1828, %1827
>  %1830 = fmul float %1766, %288
>  %1831 = fadd float %1829, %1830
>  %1832 = fmul float %1784, %286
>  %1833 = fmul float %1785, %287
>  %1834 = fadd float %1833, %1832
>  %1835 = fmul float %1786, %288
>  %1836 = fadd float %1834, %1835
>  %1837 = fmul float %1804, %286
>  %1838 = fmul float %1805, %287
>  %1839 = fadd float %1838, %1837
>  %1840 = fmul float %1806, %288
>  %1841 = fadd float %1839, %1840
>  %1842 = fmul float %1824, %286
>  %1843 = fmul float %1825, %287
>  %1844 = fadd float %1843, %1842
>  %1845 = fmul float %1826, %288
>  %1846 = fadd float %1844, %1845
>  %1847 = fcmp uge float %1831, 0.000000e+00
>  %1848 = select i1 %1847, float 1.000000e+00, float 0.000000e+00
>  %1849 = fsub float -0.000000e+00, %1848
>  %1850 = fptosi float %1849 to i32
>  %1851 = bitcast i32 %1850 to float
>  %1852 = bitcast float %1851 to i32
>  %1853 = icmp ne i32 %1852, 0
>  %temp4.0 = select i1 %1853, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1854 = bitcast float %temp4.0 to i32
>  %1855 = sitofp i32 %1854 to float
>  %1856 = fmul float %1764, %1855
>  %1857 = fmul float %1765, %1855
>  %1858 = fmul float %1766, %1855
>  %1859 = fcmp uge float %1836, 0.000000e+00
>  %1860 = select i1 %1859, float 1.000000e+00, float 0.000000e+00
>  %1861 = fsub float -0.000000e+00, %1860
>  %1862 = fptosi float %1861 to i32
>  %1863 = bitcast i32 %1862 to float
>  %1864 = bitcast float %1863 to i32
>  %1865 = icmp ne i32 %1864, 0
>  %.228 = select i1 %1865, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1866 = bitcast float %.228 to i32
>  %1867 = sitofp i32 %1866 to float
>  %1868 = fmul float %1784, %1867
>  %1869 = fmul float %1785, %1867
>  %1870 = fmul float %1786, %1867
>  %1871 = fcmp uge float %1841, 0.000000e+00
>  %1872 = select i1 %1871, float 1.000000e+00, float 0.000000e+00
>  %1873 = fsub float -0.000000e+00, %1872
>  %1874 = fptosi float %1873 to i32
>  %1875 = bitcast i32 %1874 to float
>  %1876 = bitcast float %1875 to i32
>  %1877 = icmp ne i32 %1876, 0
>  %temp4.2 = select i1 %1877, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1878 = bitcast float %temp4.2 to i32
>  %1879 = sitofp i32 %1878 to float
>  %1880 = fmul float %1804, %1879
>  %1881 = fmul float %1805, %1879
>  %1882 = fmul float %1806, %1879
>  %1883 = fcmp uge float %1846, 0.000000e+00
>  %1884 = select i1 %1883, float 1.000000e+00, float 0.000000e+00
>  %1885 = fsub float -0.000000e+00, %1884
>  %1886 = fptosi float %1885 to i32
>  %1887 = bitcast i32 %1886 to float
>  %1888 = bitcast float %1887 to i32
>  %1889 = icmp ne i32 %1888, 0
>  %.229 = select i1 %1889, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
>  %1890 = bitcast float %.229 to i32
>  %1891 = sitofp i32 %1890 to float
>  %1892 = fmul float %1824, %1891
>  %1893 = fmul float %1825, %1891
>  %1894 = fmul float %1826, %1891
>  %1895 = fadd float %296, %1856
>  %1896 = fadd float %298, %1857
>  %1897 = fadd float %296, %1868
>  %1898 = fadd float %298, %1869
>  %1899 = fadd float %296, %1880
>  %1900 = fadd float %298, %1881
>  %1901 = fadd float %296, %1892
>  %1902 = fadd float %298, %1893
>  %1903 = fadd float %300, %1858
>  %1904 = fadd float %300, %1870
>  %1905 = fadd float %300, %1882
>  %1906 = fadd float %300, %1894
>  %1907 = fsub float -0.000000e+00, %1903
>  %1908 = fdiv float 1.000000e+00, %1907
>  %1909 = fsub float -0.000000e+00, %1904
>  %1910 = fdiv float 1.000000e+00, %1909
>  %1911 = fmul float %1895, %1908
>  %1912 = fmul float %1896, %1908
>  %1913 = fmul float %1897, %1910
>  %1914 = fmul float %1898, %1910
>  %1915 = fsub float -0.000000e+00, %29
>  %1916 = fmul float %1911, %28
>  %1917 = fadd float %1916, %1915
>  %1918 = fsub float -0.000000e+00, %31
>  %1919 = fmul float %1912, %30
>  %1920 = fadd float %1919, %1918
>  %1921 = fsub float -0.000000e+00, %29
>  %1922 = fmul float %1913, %28
>  %1923 = fadd float %1922, %1921
>  %1924 = fsub float -0.000000e+00, %31
>  %1925 = fmul float %1914, %30
>  %1926 = fadd float %1925, %1924
>  %1927 = fsub float -0.000000e+00, %1905
>  %1928 = fdiv float 1.000000e+00, %1927
>  %1929 = fsub float -0.000000e+00, %1906
>  %1930 = fdiv float 1.000000e+00, %1929
>  %1931 = fmul float %1899, %1928
>  %1932 = fmul float %1900, %1928
>  %1933 = fmul float %1901, %1930
>  %1934 = fmul float %1902, %1930
>  %1935 = fsub float -0.000000e+00, %29
>  %1936 = fmul float %1931, %28
>  %1937 = fadd float %1936, %1935
>  %1938 = fsub float -0.000000e+00, %31
>  %1939 = fmul float %1932, %30
>  %1940 = fadd float %1939, %1938
>  %1941 = fsub float -0.000000e+00, %29
>  %1942 = fmul float %1933, %28
>  %1943 = fadd float %1942, %1941
>  %1944 = fsub float -0.000000e+00, %31
>  %1945 = fmul float %1934, %30
>  %1946 = fadd float %1945, %1944
>  %1947 = fmul float %1917, 5.000000e-01
>  %1948 = fadd float %1947, 5.000000e-01
>  %1949 = fmul float %1920, -5.000000e-01
>  %1950 = fadd float %1949, 5.000000e-01
>  %1951 = fmul float %1923, 5.000000e-01
>  %1952 = fadd float %1951, 5.000000e-01
>  %1953 = fmul float %1926, -5.000000e-01
>  %1954 = fadd float %1953, 5.000000e-01
>  %1955 = fmul float %1937, 5.000000e-01
>  %1956 = fadd float %1955, 5.000000e-01
>  %1957 = fmul float %1940, -5.000000e-01
>  %1958 = fadd float %1957, 5.000000e-01
>  %1959 = fmul float %1943, 5.000000e-01
>  %1960 = fadd float %1959, 5.000000e-01
>  %1961 = fmul float %1946, -5.000000e-01
>  %1962 = fadd float %1961, 5.000000e-01
>  %1963 = call float @llvm.AMDIL.clamp.(float %1948, float 0.000000e+00, float 1.000000e+00)
>  %1964 = call float @llvm.AMDIL.clamp.(float %1950, float 0.000000e+00, float 1.000000e+00)
>  %1965 = call float @llvm.AMDIL.clamp.(float %1952, float 0.000000e+00, float 1.000000e+00)
>  %1966 = call float @llvm.AMDIL.clamp.(float %1954, float 0.000000e+00, float 1.000000e+00)
>  %1967 = call float @llvm.AMDIL.clamp.(float %1956, float 0.000000e+00, float 1.000000e+00)
>  %1968 = call float @llvm.AMDIL.clamp.(float %1958, float 0.000000e+00, float 1.000000e+00)
>  %1969 = call float @llvm.AMDIL.clamp.(float %1960, float 0.000000e+00, float 1.000000e+00)
>  %1970 = call float @llvm.AMDIL.clamp.(float %1962, float 0.000000e+00, float 1.000000e+00)
>  %1971 = bitcast float %1963 to i32
>  %1972 = bitcast float %1964 to i32
>  %1973 = insertelement <2 x i32> undef, i32 %1971, i32 0
>  %1974 = insertelement <2 x i32> %1973, i32 %1972, i32 1
>  %1975 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1974, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1976 = extractelement <4 x float> %1975, i32 0
>  %1977 = bitcast float %1965 to i32
>  %1978 = bitcast float %1966 to i32
>  %1979 = insertelement <2 x i32> undef, i32 %1977, i32 0
>  %1980 = insertelement <2 x i32> %1979, i32 %1978, i32 1
>  %1981 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1980, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1982 = extractelement <4 x float> %1981, i32 0
>  %1983 = bitcast float %1967 to i32
>  %1984 = bitcast float %1968 to i32
>  %1985 = insertelement <2 x i32> undef, i32 %1983, i32 0
>  %1986 = insertelement <2 x i32> %1985, i32 %1984, i32 1
>  %1987 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1986, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1988 = extractelement <4 x float> %1987, i32 0
>  %1989 = bitcast float %1969 to i32
>  %1990 = bitcast float %1970 to i32
>  %1991 = insertelement <2 x i32> undef, i32 %1989, i32 0
>  %1992 = insertelement <2 x i32> %1991, i32 %1990, i32 1
>  %1993 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1992, <32 x i8> %94, <16 x i8> %96, i32 2)
>  %1994 = extractelement <4 x float> %1993, i32 0
>  %1995 = call float @fabs(float %1976)
>  %1996 = call float @fabs(float %1982)
>  %1997 = call float @fabs(float %1988)
>  %1998 = call float @fabs(float %1994)
>  %1999 = fsub float -0.000000e+00, %26
>  %2000 = fmul float %1995, %27
>  %2001 = fadd float %2000, %1999
>  %2002 = fsub float -0.000000e+00, %26
>  %2003 = fmul float %1996, %27
>  %2004 = fadd float %2003, %2002
>  %2005 = fsub float -0.000000e+00, %26
>  %2006 = fmul float %1997, %27
>  %2007 = fadd float %2006, %2005
>  %2008 = fsub float -0.000000e+00, %26
>  %2009 = fmul float %1998, %27
>  %2010 = fadd float %2009, %2008
>  %2011 = fsub float -0.000000e+00, %1903
>  %2012 = fadd float %2001, %2011
>  %2013 = fsub float -0.000000e+00, %1904
>  %2014 = fadd float %2004, %2013
>  %2015 = fsub float -0.000000e+00, %1905
>  %2016 = fadd float %2007, %2015
>  %2017 = fsub float -0.000000e+00, %1906
>  %2018 = fadd float %2010, %2017
>  %2019 = fmul float %1740, 2.000000e+00
>  %2020 = fmul float %1742, 2.000000e+00
>  %2021 = fmul float %1744, 2.000000e+00
>  %2022 = fmul float %1746, 2.000000e+00
>  %2023 = fcmp uge float %2012, %2019
>  %2024 = select i1 %2023, float 1.000000e+00, float 0.000000e+00
>  %2025 = fsub float -0.000000e+00, %2024
>  %2026 = fptosi float %2025 to i32
>  %2027 = bitcast i32 %2026 to float
>  %2028 = bitcast float %2027 to i32
>  %2029 = and i32 %2028, 1065353216
>  %2030 = bitcast i32 %2029 to float
>  %2031 = fcmp uge float %2014, %2020
>  %2032 = select i1 %2031, float 1.000000e+00, float 0.000000e+00
>  %2033 = fsub float -0.000000e+00, %2032
>  %2034 = fptosi float %2033 to i32
>  %2035 = bitcast i32 %2034 to float
>  %2036 = bitcast float %2035 to i32
>  %2037 = and i32 %2036, 1065353216
>  %2038 = bitcast i32 %2037 to float
>  %2039 = fcmp uge float %2016, %2021
>  %2040 = select i1 %2039, float 1.000000e+00, float 0.000000e+00
>  %2041 = fsub float -0.000000e+00, %2040
>  %2042 = fptosi float %2041 to i32
>  %2043 = bitcast i32 %2042 to float
>  %2044 = bitcast float %2043 to i32
>  %2045 = and i32 %2044, 1065353216
>  %2046 = bitcast i32 %2045 to float
>  %2047 = fcmp uge float %2018, %2022
>  %2048 = select i1 %2047, float 1.000000e+00, float 0.000000e+00
>  %2049 = fsub float -0.000000e+00, %2048
>  %2050 = fptosi float %2049 to i32
>  %2051 = bitcast i32 %2050 to float
>  %2052 = bitcast float %2051 to i32
>  %2053 = and i32 %2052, 1065353216
>  %2054 = bitcast i32 %2053 to float
>  %2055 = fcmp ueq float %2001, 0.000000e+00
>  %2056 = select i1 %2055, float 1.000000e+00, float 0.000000e+00
>  %2057 = fsub float -0.000000e+00, %2056
>  %2058 = fptosi float %2057 to i32
>  %2059 = bitcast i32 %2058 to float
>  %2060 = bitcast float %2059 to i32
>  %2061 = icmp ne i32 %2060, 0
>  %temp12.0 = select i1 %2061, float 0x36A0000000000000, float 0.000000e+00
>  %2062 = fcmp ueq float %2004, 0.000000e+00
>  %2063 = select i1 %2062, float 1.000000e+00, float 0.000000e+00
>  %2064 = fsub float -0.000000e+00, %2063
>  %2065 = fptosi float %2064 to i32
>  %2066 = bitcast i32 %2065 to float
>  %2067 = bitcast float %2066 to i32
>  %2068 = icmp ne i32 %2067, 0
>  %.230 = select i1 %2068, float 0x36A0000000000000, float 0.000000e+00
>  %2069 = fcmp ueq float %2007, 0.000000e+00
>  %2070 = select i1 %2069, float 1.000000e+00, float 0.000000e+00
>  %2071 = fsub float -0.000000e+00, %2070
>  %2072 = fptosi float %2071 to i32
>  %2073 = bitcast i32 %2072 to float
>  %2074 = bitcast float %2073 to i32
>  %2075 = icmp ne i32 %2074, 0
>  %temp48.4 = select i1 %2075, float 0x36A0000000000000, float 0.000000e+00
>  %2076 = fcmp ueq float %2010, 0.000000e+00
>  %2077 = select i1 %2076, float 1.000000e+00, float 0.000000e+00
>  %2078 = fsub float -0.000000e+00, %2077
>  %2079 = fptosi float %2078 to i32
>  %2080 = bitcast i32 %2079 to float
>  %2081 = bitcast float %2080 to i32
>  %2082 = icmp ne i32 %2081, 0
>  %.231 = select i1 %2082, float 0x36A0000000000000, float 0.000000e+00
>  %2083 = bitcast float %temp12.0 to i32
>  %2084 = sitofp i32 %2083 to float
>  %2085 = bitcast float %.230 to i32
>  %2086 = sitofp i32 %2085 to float
>  %2087 = bitcast float %temp48.4 to i32
>  %2088 = sitofp i32 %2087 to float
>  %2089 = bitcast float %.231 to i32
>  %2090 = sitofp i32 %2089 to float
>  %2091 = fcmp uge float 0.000000e+00, %1976
>  %2092 = select i1 %2091, float 1.000000e+00, float 0.000000e+00
>  %2093 = fsub float -0.000000e+00, %2092
>  %2094 = fptosi float %2093 to i32
>  %2095 = bitcast i32 %2094 to float
>  %2096 = bitcast float %2095 to i32
>  %2097 = and i32 %2096, 1065353216
>  %2098 = bitcast i32 %2097 to float
>  %2099 = fcmp uge float 0.000000e+00, %1982
>  %2100 = select i1 %2099, float 1.000000e+00, float 0.000000e+00
>  %2101 = fsub float -0.000000e+00, %2100
>  %2102 = fptosi float %2101 to i32
>  %2103 = bitcast i32 %2102 to float
>  %2104 = bitcast float %2103 to i32
>  %2105 = and i32 %2104, 1065353216
>  %2106 = bitcast i32 %2105 to float
>  %2107 = fcmp uge float 0.000000e+00, %1988
>  %2108 = select i1 %2107, float 1.000000e+00, float 0.000000e+00
>  %2109 = fsub float -0.000000e+00, %2108
>  %2110 = fptosi float %2109 to i32
>  %2111 = bitcast i32 %2110 to float
>  %2112 = bitcast float %2111 to i32
>  %2113 = and i32 %2112, 1065353216
>  %2114 = bitcast i32 %2113 to float
>  %2115 = fcmp uge float 0.000000e+00, %1994
>  %2116 = select i1 %2115, float 1.000000e+00, float 0.000000e+00
>  %2117 = fsub float -0.000000e+00, %2116
>  %2118 = fptosi float %2117 to i32
>  %2119 = bitcast i32 %2118 to float
>  %2120 = bitcast float %2119 to i32
>  %2121 = and i32 %2120, 1065353216
>  %2122 = bitcast i32 %2121 to float
>  %2123 = fadd float %2030, %2084
>  %2124 = fadd float %2038, %2086
>  %2125 = fadd float %2046, %2088
>  %2126 = fadd float %2054, %2090
>  %2127 = fmul float %2098, %349
>  %2128 = fadd float %2127, %2123
>  %2129 = fmul float %2106, %349
>  %2130 = fadd float %2129, %2124
>  %2131 = fmul float %2114, %349
>  %2132 = fadd float %2131, %2125
>  %2133 = fmul float %2122, %349
>  %2134 = fadd float %2133, %2126
>  %2135 = call float @llvm.AMDIL.clamp.(float %2128, float 0.000000e+00, float 1.000000e+00)
>  %2136 = call float @llvm.AMDIL.clamp.(float %2130, float 0.000000e+00, float 1.000000e+00)
>  %2137 = call float @llvm.AMDIL.clamp.(float %2132, float 0.000000e+00, float 1.000000e+00)
>  %2138 = call float @llvm.AMDIL.clamp.(float %2134, float 0.000000e+00, float 1.000000e+00)
>  %2139 = fmul float %2135, 1.000000e+00
>  %2140 = fmul float %2136, 1.000000e+00
>  %2141 = fadd float %2139, %2140
>  %2142 = fmul float %2137, 1.000000e+00
>  %2143 = fadd float %2141, %2142
>  %2144 = fmul float %2138, 1.000000e+00
>  %2145 = fadd float %2143, %2144
>  %2146 = fadd float %1685, %2145
>  %2147 = fcmp uge float %2012, 0.000000e+00
>  %2148 = select i1 %2147, float 1.000000e+00, float 0.000000e+00
>  %2149 = fsub float -0.000000e+00, %2148
>  %2150 = fptosi float %2149 to i32
>  %2151 = bitcast i32 %2150 to float
>  %2152 = bitcast float %2151 to i32
>  %2153 = and i32 %2152, 1065353216
>  %2154 = bitcast i32 %2153 to float
>  %2155 = fcmp uge float %2014, 0.000000e+00
>  %2156 = select i1 %2155, float 1.000000e+00, float 0.000000e+00
>  %2157 = fsub float -0.000000e+00, %2156
>  %2158 = fptosi float %2157 to i32
>  %2159 = bitcast i32 %2158 to float
>  %2160 = bitcast float %2159 to i32
>  %2161 = and i32 %2160, 1065353216
>  %2162 = bitcast i32 %2161 to float
>  %2163 = fcmp uge float %2016, 0.000000e+00
>  %2164 = select i1 %2163, float 1.000000e+00, float 0.000000e+00
>  %2165 = fsub float -0.000000e+00, %2164
>  %2166 = fptosi float %2165 to i32
>  %2167 = bitcast i32 %2166 to float
>  %2168 = bitcast float %2167 to i32
>  %2169 = and i32 %2168, 1065353216
>  %2170 = bitcast i32 %2169 to float
>  %2171 = fcmp uge float %2018, 0.000000e+00
>  %2172 = select i1 %2171, float 1.000000e+00, float 0.000000e+00
>  %2173 = fsub float -0.000000e+00, %2172
>  %2174 = fptosi float %2173 to i32
>  %2175 = bitcast i32 %2174 to float
>  %2176 = bitcast float %2175 to i32
>  %2177 = and i32 %2176, 1065353216
>  %2178 = bitcast i32 %2177 to float
>  %2179 = fsub float -0.000000e+00, %2135
>  %2180 = fadd float 1.000000e+00, %2179
>  %2181 = fsub float -0.000000e+00, %2136
>  %2182 = fadd float 1.000000e+00, %2181
>  %2183 = fsub float -0.000000e+00, %2137
>  %2184 = fadd float 1.000000e+00, %2183
>  %2185 = fsub float -0.000000e+00, %2138
>  %2186 = fadd float 1.000000e+00, %2185
>  %2187 = fmul float %2154, %2180
>  %2188 = fmul float %2162, %2182
>  %2189 = fmul float %2170, %2184
>  %2190 = fmul float %2178, %2186
>  %2191 = fmul float %2187, 1.000000e+00
>  %2192 = fmul float %2188, 1.000000e+00
>  %2193 = fadd float %2191, %2192
>  %2194 = fmul float %2189, 1.000000e+00
>  %2195 = fadd float %2193, %2194
>  %2196 = fmul float %2190, 1.000000e+00
>  %2197 = fadd float %2195, %2196
>  %2198 = fadd float %1737, %2197
>  %2199 = fsub float -0.000000e+00, %2146
>  %2200 = fadd float 1.600000e+01, %2199
>  %2201 = fdiv float 1.000000e+00, %2200
>  %2202 = fmul float %2198, %2201
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %2202, %IF ], [ 0.000000e+00, %main_body ]
>  %2203 = fmul float %temp.0, %43
>  %2204 = call float @llvm.AMDIL.clamp.(float %2203, float 0.000000e+00, float 1.000000e+00)
>  %2205 = fsub float -0.000000e+00, %2204
>  %2206 = fadd float 1.000000e+00, %2205
>  %2207 = fmul float %2206, %2206
>  %2208 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %2209 = bitcast i32 %2208 to float
>  %2210 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %2207)
>  %2211 = bitcast i32 %2210 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %2209, float %2211, float %2209, float %2211)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>7e1a110d
>361a1af2
>d0040002
>02010125
>d200000f
>0009e480
>d206000f
>2201010f
>7e1e110f
>d10a0002
>0201010f
>d200000f
>00090280
>7e1e0b0f
>061a1f0d
>d0060002
>0201011e
>d200000f
>0009e480
>d206000f
>2201010f
>7e1e110f
>361e1ef2
>d282000d
>04363b0f
>d206080d
>0201010d
>081e1af2
>d00c0002
>0201010e
>d200000e
>0009e480
>d206000e
>2201010e
>7e1c110e
>361c1cf2
>d282000e
>046e1f0e
>101e1914
>d282000f
>043e1712
>d282001b
>043e1513
>101e291b
>d282000f
>043e291b
>081e1f0c
>d282000c
>0499ef16
>101e190f
>103c230f
>104a251b
>d2820025
>0496251b
>08164b0b
>1016190b
>d282001e
>047a210b
>104a271b
>d282001b
>0496271b
>0814370a
>1014190a
>d282001b
>047a2b0a
>d00c0002
>0201011b
>d200001b
>0009e480
>d206001b
>2201011b
>7e36111b
>d10a0002
>0201011b
>d200001b
>000902c1
>7e360b1b
>d282001e
>0462370f
>d282000a
>0466370a
>d206000f
>2201010a
>7e1e550f
>103c1f1e
>103c131e
>083c111e
>d282001e
>03c1e11e
>d2060825
>0201011e
>d282000b
>0472370b
>10161f0b
>10160f0b
>08160d0b
>d282000b
>03c1e30b
>d2060826
>0201010b
>f0800100
>00430f25
>bf8c0770
>d206010b
>0201010f
>10160b0b
>0836090b
>0816151b
>0614190c
>d00c0002
>0202150b
>d200000a
>0009e480
>d206000a
>2201010a
>7e14110a
>361414f2
>d0040002
>0201011b
>d200000c
>0009e480
>d206000c
>2201010c
>7e18110c
>d10a0002
>0201010c
>d200000c
>00090280
>7e180b0c
>0614190a
>d0060002
>0201010f
>d200000c
>0009e480
>d206000c
>2201010c
>7e18110c
>361818f2
>d282000a
>042a3b0c
>d206080a
>0201010a
>081814f2
>d00c0002
>0201010b
>d200000b
>0009e480
>d206000b
>2201010b
>7e16110b
>361616f2
>d282000b
>043a190b
>10180714
>d282000c
>04320512
>d282000e
>04320313
>1018290e
>d282000c
>0432290e
>08181903
>d2820003
>0489ef16
>1018070c
>101e230c
>1022250e
>d2820011
>0446250e
>08042302
>10040702
>d282000f
>043e2102
>1020270e
>d282000e
>0442270e
>08021d01
>10020701
>d282000e
>043e2b01
>d00c0002
>0201010e
>d200000e
>0009e480
>d206000e
>2201010e
>7e1c110e
>d10a0002
>0201010e
>d200000e
>000902c1
>7e1c0b0e
>d282000f
>04621d0c
>d2820001
>04661d01
>d206000c
>22010101
>7e18550c
>101e190f
>1012130f
>08101109
>d2820008
>03c1e108
>d2060808
>02010108
>d2820002
>04721d02
>10041902
>10040f02
>08040d02
>d2820002
>03c1e302
>d2060809
>02010102
>f0800100
>00430208
>bf8c0770
>d2060106
>02010102
>100a0b06
>08080905
>08020304
>06060703
>d00c0002
>02020701
>d2000003
>0009e480
>d2060003
>22010103
>7e061103
>360606f2
>d0040002
>02010104
>d2000004
>0009e480
>d2060004
>22010104
>7e081104
>d10a0002
>02010104
>d2000004
>00090280
>7e080b04
>06060903
>d0060002
>02010102
>d2000002
>0009e480
>d2060002
>22010102
>7e041102
>360404f2
>d2820002
>040e3b02
>d2060802
>02010102
>080604f2
>d00c0002
>02010101
>d2000001
>0009e480
>d2060001
>22010101
>7e021101
>360202f2
>d2820001
>042e0701
>06020321
>0606351f
>06064703
>06064f03
>0608572f
>06086704
>06086104
>06060704
>06085928
>06084904
>06084104
>06060903
>06082f0d
>06081504
>06040504
>06040503
>080404ff
>41800000
>7e045502
>10020501
>88fe007e
>10000101
>d2060800
>02010100
>080000f2
>10000100
>5e000080
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..223]
>DCL TEMP[0..11], LOCAL
>IMM[0] FLT32 {   -1.0000,     0.0000,     1.0000,     0.0000}
>  0: MAD TEMP[0], CONST[3].zwzw, IMM[0].xxyx, IN[0].xyxy
>  1: MOV TEMP[1].xy, TEMP[0].xyyy
>  2: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D
>  3: MOV TEMP[0].xy, TEMP[0].zwww
>  4: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
>  5: MAD TEMP[2], CONST[3].zwzw, IMM[0].zxxy, IN[0].xyxy
>  6: MOV TEMP[3].xy, TEMP[2].xyyy
>  7: TEX TEMP[3].w, TEMP[3], SAMP[0], 2D
>  8: MOV TEMP[2].xy, TEMP[2].zwww
>  9: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
> 10: MOV TEMP[4].xy, IN[0].xyyy
> 11: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
> 12: MAD TEMP[5], CONST[3].zwzw, IMM[0].zyxz, IN[0].xyxy
> 13: MOV TEMP[6].xy, TEMP[5].xyyy
> 14: TEX TEMP[6].w, TEMP[6], SAMP[0], 2D
> 15: MAD TEMP[7], CONST[3].zwzw, IMM[0].yzzz, IN[0].xyxy
> 16: MOV TEMP[8].xy, TEMP[7].xyyy
> 17: TEX TEMP[8].w, TEMP[8], SAMP[0], 2D
> 18: MOV TEMP[7].xy, TEMP[7].zwww
> 19: TEX TEMP[7].w, TEMP[7], SAMP[0], 2D
> 20: MIN TEMP[9].x, TEMP[1].wwww, TEMP[2].wwww
> 21: MIN TEMP[10].x, TEMP[0].wwww, TEMP[4].wwww
> 22: MAX TEMP[0].x, TEMP[0].wwww, TEMP[4].wwww
> 23: MAX TEMP[4].x, TEMP[3].wwww, TEMP[6].wwww
> 24: MAX TEMP[11].x, TEMP[9].xxxx, TEMP[10].xxxx
> 25: MIN TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
> 26: MIN TEMP[3].x, TEMP[3].wwww, TEMP[6].wwww
> 27: MAX TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx
> 28: MIN TEMP[6].x, TEMP[0].xxxx, TEMP[4].xxxx
> 29: MAX TEMP[1].x, TEMP[1].wwww, TEMP[2].wwww
> 30: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
> 31: MIN TEMP[0].x, TEMP[1].xxxx, TEMP[0].xxxx
> 32: MIN TEMP[1].x, TEMP[11].xxxx, TEMP[3].xxxx
> 33: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[6].xxxx
> 34: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[6].xxxx
> 35: MAX TEMP[4].x, TEMP[1].xxxx, TEMP[2].xxxx
> 36: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
> 37: MOV TEMP[2].xy, TEMP[5].zwww
> 38: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
> 39: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[2].wwww
> 40: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[1].xxxx
> 41: MAX TEMP[3].x, TEMP[11].xxxx, TEMP[3].xxxx
> 42: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
> 43: MIN TEMP[0].x, TEMP[3].xxxx, TEMP[0].xxxx
> 44: MIN TEMP[1].x, TEMP[0].xxxx, TEMP[4].xxxx
> 45: MIN TEMP[3].x, TEMP[2].xxxx, TEMP[8].wwww
> 46: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[3].xxxx
> 47: MOV TEMP[3].xyz, IMM[0].yyyy
> 48: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
> 49: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[8].wwww
> 50: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
> 51: MAX TEMP[2].x, TEMP[1].xxxx, TEMP[7].wwww
> 52: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
> 53: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[7].wwww
> 54: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
> 55: MOV TEMP[3].w, TEMP[0].xxxx
> 56: MOV OUT[0], TEMP[3]
> 57: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = fmul float %22, -1.000000e+00
>  %31 = fadd float %30, %28
>  %32 = fmul float %23, -1.000000e+00
>  %33 = fadd float %32, %29
>  %34 = fmul float %22, 0.000000e+00
>  %35 = fadd float %34, %28
>  %36 = fmul float %23, -1.000000e+00
>  %37 = fadd float %36, %29
>  %38 = bitcast float %31 to i32
>  %39 = bitcast float %33 to i32
>  %40 = insertelement <2 x i32> undef, i32 %38, i32 0
>  %41 = insertelement <2 x i32> %40, i32 %39, i32 1
>  %42 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %41, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %43 = extractelement <4 x float> %42, i32 3
>  %44 = bitcast float %35 to i32
>  %45 = bitcast float %37 to i32
>  %46 = insertelement <2 x i32> undef, i32 %44, i32 0
>  %47 = insertelement <2 x i32> %46, i32 %45, i32 1
>  %48 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %47, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %49 = extractelement <4 x float> %48, i32 3
>  %50 = fmul float %22, 1.000000e+00
>  %51 = fadd float %50, %28
>  %52 = fmul float %23, -1.000000e+00
>  %53 = fadd float %52, %29
>  %54 = fmul float %22, -1.000000e+00
>  %55 = fadd float %54, %28
>  %56 = fmul float %23, 0.000000e+00
>  %57 = fadd float %56, %29
>  %58 = bitcast float %51 to i32
>  %59 = bitcast float %53 to i32
>  %60 = insertelement <2 x i32> undef, i32 %58, i32 0
>  %61 = insertelement <2 x i32> %60, i32 %59, i32 1
>  %62 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %63 = extractelement <4 x float> %62, i32 3
>  %64 = bitcast float %55 to i32
>  %65 = bitcast float %57 to i32
>  %66 = insertelement <2 x i32> undef, i32 %64, i32 0
>  %67 = insertelement <2 x i32> %66, i32 %65, i32 1
>  %68 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %67, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %69 = extractelement <4 x float> %68, i32 3
>  %70 = bitcast float %28 to i32
>  %71 = bitcast float %29 to i32
>  %72 = insertelement <2 x i32> undef, i32 %70, i32 0
>  %73 = insertelement <2 x i32> %72, i32 %71, i32 1
>  %74 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %73, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %75 = extractelement <4 x float> %74, i32 3
>  %76 = fmul float %22, 1.000000e+00
>  %77 = fadd float %76, %28
>  %78 = fmul float %23, 0.000000e+00
>  %79 = fadd float %78, %29
>  %80 = fmul float %22, -1.000000e+00
>  %81 = fadd float %80, %28
>  %82 = fmul float %23, 1.000000e+00
>  %83 = fadd float %82, %29
>  %84 = bitcast float %77 to i32
>  %85 = bitcast float %79 to i32
>  %86 = insertelement <2 x i32> undef, i32 %84, i32 0
>  %87 = insertelement <2 x i32> %86, i32 %85, i32 1
>  %88 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %87, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %89 = extractelement <4 x float> %88, i32 3
>  %90 = fmul float %22, 0.000000e+00
>  %91 = fadd float %90, %28
>  %92 = fmul float %23, 1.000000e+00
>  %93 = fadd float %92, %29
>  %94 = fmul float %22, 1.000000e+00
>  %95 = fadd float %94, %28
>  %96 = fmul float %23, 1.000000e+00
>  %97 = fadd float %96, %29
>  %98 = bitcast float %91 to i32
>  %99 = bitcast float %93 to i32
>  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
>  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
>  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %103 = extractelement <4 x float> %102, i32 3
>  %104 = bitcast float %95 to i32
>  %105 = bitcast float %97 to i32
>  %106 = insertelement <2 x i32> undef, i32 %104, i32 0
>  %107 = insertelement <2 x i32> %106, i32 %105, i32 1
>  %108 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %107, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %109 = extractelement <4 x float> %108, i32 3
>  %110 = fcmp uge float %43, %69
>  %111 = select i1 %110, float %69, float %43
>  %112 = fcmp uge float %49, %75
>  %113 = select i1 %112, float %75, float %49
>  %114 = fcmp uge float %49, %75
>  %115 = select i1 %114, float %49, float %75
>  %116 = fcmp uge float %63, %89
>  %117 = select i1 %116, float %63, float %89
>  %118 = fcmp uge float %111, %113
>  %119 = select i1 %118, float %111, float %113
>  %120 = fcmp uge float %111, %113
>  %121 = select i1 %120, float %113, float %111
>  %122 = fcmp uge float %63, %89
>  %123 = select i1 %122, float %89, float %63
>  %124 = fcmp uge float %121, %123
>  %125 = select i1 %124, float %121, float %123
>  %126 = fcmp uge float %115, %117
>  %127 = select i1 %126, float %117, float %115
>  %128 = fcmp uge float %43, %69
>  %129 = select i1 %128, float %43, float %69
>  %130 = fcmp uge float %115, %117
>  %131 = select i1 %130, float %115, float %117
>  %132 = fcmp uge float %129, %131
>  %133 = select i1 %132, float %131, float %129
>  %134 = fcmp uge float %119, %125
>  %135 = select i1 %134, float %125, float %119
>  %136 = fcmp uge float %133, %127
>  %137 = select i1 %136, float %127, float %133
>  %138 = fcmp uge float %133, %127
>  %139 = select i1 %138, float %133, float %127
>  %140 = fcmp uge float %135, %137
>  %141 = select i1 %140, float %135, float %137
>  %142 = fcmp uge float %135, %137
>  %143 = select i1 %142, float %137, float %135
>  %144 = bitcast float %81 to i32
>  %145 = bitcast float %83 to i32
>  %146 = insertelement <2 x i32> undef, i32 %144, i32 0
>  %147 = insertelement <2 x i32> %146, i32 %145, i32 1
>  %148 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %147, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %149 = extractelement <4 x float> %148, i32 3
>  %150 = fcmp uge float %143, %149
>  %151 = select i1 %150, float %143, float %149
>  %152 = fcmp uge float %139, %151
>  %153 = select i1 %152, float %151, float %139
>  %154 = fcmp uge float %119, %125
>  %155 = select i1 %154, float %119, float %125
>  %156 = fcmp uge float %139, %151
>  %157 = select i1 %156, float %139, float %151
>  %158 = fcmp uge float %155, %157
>  %159 = select i1 %158, float %157, float %155
>  %160 = fcmp uge float %159, %141
>  %161 = select i1 %160, float %141, float %159
>  %162 = fcmp uge float %153, %103
>  %163 = select i1 %162, float %103, float %153
>  %164 = fcmp uge float %161, %163
>  %165 = select i1 %164, float %161, float %163
>  %166 = fcmp uge float %159, %141
>  %167 = select i1 %166, float %159, float %141
>  %168 = fcmp uge float %153, %103
>  %169 = select i1 %168, float %153, float %103
>  %170 = fcmp uge float %167, %169
>  %171 = select i1 %170, float %169, float %167
>  %172 = fcmp uge float %165, %109
>  %173 = select i1 %172, float %165, float %109
>  %174 = fcmp uge float %171, %173
>  %175 = select i1 %174, float %173, float %171
>  %176 = fcmp uge float %165, %109
>  %177 = select i1 %176, float %109, float %165
>  %178 = fcmp uge float %175, %177
>  %179 = select i1 %178, float %175, float %177
>  %180 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %181 = bitcast i32 %180 to float
>  %182 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %179)
>  %183 = bitcast i32 %182 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %181, float %183, float %181, float %183)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8140100
>c8150101
>c0840100
>bf8c007f
>c206090f
>bf8c007f
>d2820003
>0415000c
>c8100000
>c8110001
>c206890e
>bf8c007f
>0604080d
>c0800300
>c0c20500
>bf8c007f
>f0800800
>00010802
>0a020a0c
>7e0c0302
>7e0e0303
>7e0e0301
>f0800800
>00010906
>bf8c0770
>d00c000e
>02021109
>d200000a
>003a1308
>f0800800
>00010b04
>d2820000
>0411000d
>f0800800
>00010c00
>bf8c0770
>d00c0010
>0202170c
>d200000e
>0042190b
>d00c0012
>0202150e
>d200000d
>004a1d0a
>0a0c080d
>7e0e0303
>f0800800
>00010f06
>7e0e0301
>f0800800
>00011006
>bf8c0770
>d00c0014
>02021f10
>d2000011
>0052210f
>d00c0016
>02021b11
>d200000d
>005a1b11
>d200000e
>004a150e
>d00c0012
>02021d0d
>d200000a
>004a1d0d
>d200000b
>0042170c
>d200000c
>00521f10
>d00c0010
>0202170c
>d200000f
>0042170c
>d2000008
>003a1109
>d00c000e
>0202110f
>d2000008
>003a1f08
>d200000b
>0042190b
>d00c0010
>0202110b
>d2000009
>0042110b
>d00c000e
>02021509
>d200000c
>003a1509
>060e0a0c
>f0800800
>00010406
>bf8c0770
>d00c000c
>0202090c
>d200000c
>00321904
>d200000d
>004a1b0e
>d00c0012
>0202190d
>d2000004
>004a1b0c
>d2000005
>00421708
>d00c000c
>02020905
>d2000004
>00320905
>d2000005
>003a130a
>d00c000c
>02020b04
>d2000009
>00320b04
>d2000008
>004a190d
>7e020307
>f0800800
>00010000
>bf8c0770
>d00c000e
>02020108
>d2000001
>003a0108
>d00c0010
>02020309
>d2000001
>00421301
>7e060307
>f0800800
>00010202
>bf8c0770
>d00c0000
>02020501
>d2000003
>00020302
>d2000004
>00320905
>d2000000
>003a1100
>d00c0002
>02020104
>d2000000
>000a0104
>d00c0002
>02020700
>d2000000
>000a0700
>d2000001
>00020501
>d00c0000
>02020300
>d2000000
>00020101
>5e000080
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..3]
>DCL TEMP[0..13], LOCAL
>IMM[0] FLT32 {    0.0000,     0.9500,     1.0000,     0.2216}
>IMM[1] FLT32 {   -1.5000,     1.5000,    -1.0000,     1.0000}
>IMM[2] FLT32 {   -2.0000,     2.0000,     0.1899,     0.1196}
>IMM[3] FLT32 {    0.0553,     0.0188,     0.0000,     0.0000}
>  0: MOV TEMP[0].xyz, IMM[0].xxxx
>  1: MOV TEMP[1].xy, IN[0].xyyy
>  2: TEX TEMP[1].w, TEMP[1], SAMP[1], 2D
>  3: MOV TEMP[0].w, TEMP[1].wwww
>  4: MOV TEMP[2].xy, IN[0].zwww
>  5: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
>  6: SLT TEMP[3].x, IMM[0].yyyy, TEMP[2].xxxx
>  7: F2I TEMP[3].x, -TEMP[3]
>  8: UIF TEMP[3].xxxx :0
>  9:   MOV TEMP[3], TEMP[0]
> 10: ELSE :0
> 11:   ABS TEMP[4].x, TEMP[2].xxxx
> 12:   MAD TEMP[4].x, TEMP[4].xxxx, CONST[1].yyyy, -CONST[1].xxxx
> 13:   ADD TEMP[5].x, -TEMP[4].xxxx, -CONST[3].xxxx
> 14:   MUL_SAT TEMP[5].x, TEMP[5].xxxx, CONST[3].wwww
> 15:   MAD TEMP[5].x, CONST[3].zzzz, TEMP[5].xxxx, IMM[0].zzzz
> 16:   MUL_SAT TEMP[6].x, -TEMP[4].xxxx, CONST[3].yyyy
> 17:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
> 18:   SLT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
> 19:   F2I TEMP[2].x, -TEMP[2]
> 20:   UIF TEMP[2].xxxx :0
> 21:     MOV TEMP[2].x, CONST[0].yyyy
> 22:   ELSE :0
> 23:     MOV TEMP[2].x, TEMP[5].xxxx
> 24:   ENDIF
> 25:   MUL TEMP[2].x, TEMP[2].xxxx, CONST[0].zzzz
> 26:   MUL TEMP[2].x, CONST[0].xxxx, TEMP[2].xxxx
> 27:   MUL TEMP[5].x, TEMP[1].wwww, IMM[0].wwww
> 28:   MAD TEMP[6], CONST[2].xyxy, IMM[1].xxyy, IN[0].xyxy
> 29:   MAD TEMP[7], CONST[2].zwzw, IMM[1].zzww, IN[0].zwzw
> 30:   MAD TEMP[8], CONST[2].zwzw, IMM[2].xxyy, IN[0].zwzw
> 31:   MOV TEMP[9].xy, TEMP[7].xyyy
> 32:   TEX TEMP[9].x, TEMP[9], SAMP[0], 2D
> 33:   MOV TEMP[9].x, TEMP[9].xxxx
> 34:   MOV TEMP[10].xy, TEMP[7].zwww
> 35:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 36:   MOV TEMP[9].y, TEMP[10].xxxx
> 37:   MOV TEMP[10].xy, TEMP[8].xyyy
> 38:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 39:   MOV TEMP[9].z, TEMP[10].xxxx
> 40:   MOV TEMP[10].xy, TEMP[8].zwww
> 41:   TEX TEMP[10].x, TEMP[10], SAMP[0], 2D
> 42:   MOV TEMP[9].w, TEMP[10].xxxx
> 43:   MOV TEMP[10].xy, TEMP[6].xyyy
> 44:   TEX TEMP[10].w, TEMP[10], SAMP[1], 2D
> 45:   MOV TEMP[10].x, TEMP[10].wwww
> 46:   MOV TEMP[11].xy, TEMP[6].zwww
> 47:   TEX TEMP[11].w, TEMP[11], SAMP[1], 2D
> 48:   MOV TEMP[10].y, TEMP[11].wwww
> 49:   ABS TEMP[11], TEMP[9]
> 50:   MAD TEMP[11], TEMP[11], CONST[1].yyyy, -CONST[1].xxxx
> 51:   ADD TEMP[11], TEMP[11], -TEMP[4].xxxx
> 52:   ABS TEMP[11], TEMP[11]
> 53:   SGE TEMP[12].x, TEMP[11].xxxx, TEMP[2].xxxx
> 54:   F2I TEMP[12].x, -TEMP[12]
> 55:   UIF TEMP[12].xxxx :0
> 56:     MOV TEMP[12].x, IMM[0].xxxx
> 57:   ELSE :0
> 58:     MOV TEMP[12].x, IMM[2].zzzz
> 59:   ENDIF
> 60:   MOV TEMP[12].x, TEMP[12].xxxx
> 61:   SGE TEMP[13].x, TEMP[11].yyyy, TEMP[2].xxxx
> 62:   F2I TEMP[13].x, -TEMP[13]
> 63:   UIF TEMP[13].xxxx :0
> 64:     MOV TEMP[13].x, IMM[0].xxxx
> 65:   ELSE :0
> 66:     MOV TEMP[13].x, IMM[2].zzzz
> 67:   ENDIF
> 68:   MOV TEMP[12].y, TEMP[13].xxxx
> 69:   SGE TEMP[13].x, TEMP[11].zzzz, TEMP[2].xxxx
> 70:   F2I TEMP[13].x, -TEMP[13]
> 71:   UIF TEMP[13].xxxx :0
> 72:     MOV TEMP[13].x, IMM[0].xxxx
> 73:   ELSE :0
> 74:     MOV TEMP[13].x, IMM[2].wwww
> 75:   ENDIF
> 76:   MOV TEMP[12].z, TEMP[13].xxxx
> 77:   SGE TEMP[11].x, TEMP[11].wwww, TEMP[2].xxxx
> 78:   F2I TEMP[11].x, -TEMP[11]
> 79:   UIF TEMP[11].xxxx :0
> 80:     MOV TEMP[11].x, IMM[0].xxxx
> 81:   ELSE :0
> 82:     MOV TEMP[11].x, IMM[2].wwww
> 83:   ENDIF
> 84:   MOV TEMP[12].w, TEMP[11].xxxx
> 85:   DP4 TEMP[11].x, TEMP[10].xyxy, TEMP[12]
> 86:   ADD TEMP[5].x, TEMP[5].xxxx, TEMP[11].xxxx
> 87:   ADD TEMP[1], IMM[0].wxxx, TEMP[12]
> 88:   MAD TEMP[6], CONST[2].xyxy, IMM[2].xxyy, TEMP[6]
> 89:   MAD TEMP[7], CONST[2].zwzw, IMM[2].xxyy, TEMP[7]
> 90:   MAD TEMP[8], CONST[2].zwzw, IMM[2].xxyy, TEMP[8]
> 91:   MOV TEMP[11].xy, TEMP[7].xyyy
> 92:   TEX TEMP[11].x, TEMP[11], SAMP[0], 2D
> 93:   MOV TEMP[9].x, TEMP[11].xxxx
> 94:   MOV TEMP[7].xy, TEMP[7].zwww
> 95:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 96:   MOV TEMP[9].y, TEMP[7].xxxx
> 97:   MOV TEMP[7].xy, TEMP[8].xyyy
> 98:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
> 99:   MOV TEMP[9].z, TEMP[7].xxxx
>100:   MOV TEMP[7].xy, TEMP[8].zwww
>101:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
>102:   MOV TEMP[9].w, TEMP[7].xxxx
>103:   MOV TEMP[7].xy, TEMP[6].xyyy
>104:   TEX TEMP[7].w, TEMP[7], SAMP[1], 2D
>105:   MOV TEMP[10].x, TEMP[7].wwww
>106:   MOV TEMP[6].xy, TEMP[6].zwww
>107:   TEX TEMP[6].w, TEMP[6], SAMP[1], 2D
>108:   MOV TEMP[10].y, TEMP[6].wwww
>109:   ABS TEMP[6], TEMP[9]
>110:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
>111:   ADD TEMP[4], TEMP[6], -TEMP[4].xxxx
>112:   ABS TEMP[4], TEMP[4]
>113:   SGE TEMP[6].x, TEMP[4].xxxx, TEMP[2].xxxx
>114:   F2I TEMP[6].x, -TEMP[6]
>115:   UIF TEMP[6].xxxx :0
>116:     MOV TEMP[6].x, IMM[0].xxxx
>117:   ELSE :0
>118:     MOV TEMP[6].x, IMM[3].xxxx
>119:   ENDIF
>120:   MOV TEMP[12].x, TEMP[6].xxxx
>121:   SGE TEMP[6].x, TEMP[4].yyyy, TEMP[2].xxxx
>122:   F2I TEMP[6].x, -TEMP[6]
>123:   UIF TEMP[6].xxxx :0
>124:     MOV TEMP[6].x, IMM[0].xxxx
>125:   ELSE :0
>126:     MOV TEMP[6].x, IMM[3].xxxx
>127:   ENDIF
>128:   MOV TEMP[12].y, TEMP[6].xxxx
>129:   SGE TEMP[6].x, TEMP[4].zzzz, TEMP[2].xxxx
>130:   F2I TEMP[6].x, -TEMP[6]
>131:   UIF TEMP[6].xxxx :0
>132:     MOV TEMP[6].x, IMM[0].xxxx
>133:   ELSE :0
>134:     MOV TEMP[6].x, IMM[3].yyyy
>135:   ENDIF
>136:   MOV TEMP[12].z, TEMP[6].xxxx
>137:   SGE TEMP[2].x, TEMP[4].wwww, TEMP[2].xxxx
>138:   F2I TEMP[2].x, -TEMP[2]
>139:   UIF TEMP[2].xxxx :0
>140:     MOV TEMP[2].x, IMM[0].xxxx
>141:   ELSE :0
>142:     MOV TEMP[2].x, IMM[3].yyyy
>143:   ENDIF
>144:   MOV TEMP[12].w, TEMP[2].xxxx
>145:   DP4 TEMP[2].x, TEMP[10].xyxy, TEMP[12]
>146:   ADD TEMP[2].x, TEMP[5].xxxx, TEMP[2].xxxx
>147:   ADD TEMP[1], TEMP[1], TEMP[12]
>148:   DP4 TEMP[1].x, TEMP[1], IMM[0].zzzz
>149:   RCP TEMP[1].x, TEMP[1].xxxx
>150:   MUL TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx
>151:   MOV TEMP[0].w, TEMP[1].xxxx
>152:   MOV TEMP[3], TEMP[0]
>153: ENDIF
>154: MOV OUT[0], TEMP[3]
>155: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %35 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
>  %43 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %44 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %45 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %46 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %47 = bitcast float %43 to i32
>  %48 = bitcast float %44 to i32
>  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
>  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
>  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %52 = extractelement <4 x float> %51, i32 3
>  %53 = bitcast float %45 to i32
>  %54 = bitcast float %46 to i32
>  %55 = insertelement <2 x i32> undef, i32 %53, i32 0
>  %56 = insertelement <2 x i32> %55, i32 %54, i32 1
>  %57 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %56, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %58 = extractelement <4 x float> %57, i32 0
>  %59 = fcmp ult float 0x3FEE666660000000, %58
>  %60 = select i1 %59, float 1.000000e+00, float 0.000000e+00
>  %61 = fsub float -0.000000e+00, %60
>  %62 = fptosi float %61 to i32
>  %63 = bitcast i32 %62 to float
>  %64 = bitcast float %63 to i32
>  %65 = icmp ne i32 %64, 0
>  br i1 %65, label %ENDIF, label %ELSE
>
>ELSE:                                             ; preds = %main_body
>  %66 = call float @fabs(float %58)
>  %67 = fsub float -0.000000e+00, %25
>  %68 = fmul float %66, %26
>  %69 = fadd float %68, %67
>  %70 = fsub float -0.000000e+00, %69
>  %71 = fsub float -0.000000e+00, %31
>  %72 = fadd float %70, %71
>  %73 = fmul float %72, %34
>  %74 = call float @llvm.AMDIL.clamp.(float %73, float 0.000000e+00, float 1.000000e+00)
>  %75 = fmul float %33, %74
>  %76 = fadd float %75, 1.000000e+00
>  %77 = fsub float -0.000000e+00, %69
>  %78 = fmul float %77, %32
>  %79 = call float @llvm.AMDIL.clamp.(float %78, float 0.000000e+00, float 1.000000e+00)
>  %80 = fmul float %76, %79
>  %81 = fcmp ult float %58, 0.000000e+00
>  %82 = select i1 %81, float 1.000000e+00, float 0.000000e+00
>  %83 = fsub float -0.000000e+00, %82
>  %84 = fptosi float %83 to i32
>  %85 = bitcast i32 %84 to float
>  %86 = bitcast float %85 to i32
>  %87 = icmp ne i32 %86, 0
>  %. = select i1 %87, float %23, float %80
>  %88 = fmul float %., %24
>  %89 = fmul float %22, %88
>  %90 = fmul float %52, 0x3FCC5E8920000000
>  %91 = fmul float %27, -1.500000e+00
>  %92 = fadd float %91, %43
>  %93 = fmul float %28, -1.500000e+00
>  %94 = fadd float %93, %44
>  %95 = fmul float %27, 1.500000e+00
>  %96 = fadd float %95, %43
>  %97 = fmul float %28, 1.500000e+00
>  %98 = fadd float %97, %44
>  %99 = fmul float %29, -1.000000e+00
>  %100 = fadd float %99, %45
>  %101 = fmul float %30, -1.000000e+00
>  %102 = fadd float %101, %46
>  %103 = fmul float %29, 1.000000e+00
>  %104 = fadd float %103, %45
>  %105 = fmul float %30, 1.000000e+00
>  %106 = fadd float %105, %46
>  %107 = fmul float %29, -2.000000e+00
>  %108 = fadd float %107, %45
>  %109 = fmul float %30, -2.000000e+00
>  %110 = fadd float %109, %46
>  %111 = fmul float %29, 2.000000e+00
>  %112 = fadd float %111, %45
>  %113 = fmul float %30, 2.000000e+00
>  %114 = fadd float %113, %46
>  %115 = bitcast float %100 to i32
>  %116 = bitcast float %102 to i32
>  %117 = insertelement <2 x i32> undef, i32 %115, i32 0
>  %118 = insertelement <2 x i32> %117, i32 %116, i32 1
>  %119 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %118, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = bitcast float %104 to i32
>  %122 = bitcast float %106 to i32
>  %123 = insertelement <2 x i32> undef, i32 %121, i32 0
>  %124 = insertelement <2 x i32> %123, i32 %122, i32 1
>  %125 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %124, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = bitcast float %108 to i32
>  %128 = bitcast float %110 to i32
>  %129 = insertelement <2 x i32> undef, i32 %127, i32 0
>  %130 = insertelement <2 x i32> %129, i32 %128, i32 1
>  %131 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %130, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %132 = extractelement <4 x float> %131, i32 0
>  %133 = bitcast float %112 to i32
>  %134 = bitcast float %114 to i32
>  %135 = insertelement <2 x i32> undef, i32 %133, i32 0
>  %136 = insertelement <2 x i32> %135, i32 %134, i32 1
>  %137 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %136, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %138 = extractelement <4 x float> %137, i32 0
>  %139 = bitcast float %92 to i32
>  %140 = bitcast float %94 to i32
>  %141 = insertelement <2 x i32> undef, i32 %139, i32 0
>  %142 = insertelement <2 x i32> %141, i32 %140, i32 1
>  %143 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %142, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %144 = extractelement <4 x float> %143, i32 3
>  %145 = bitcast float %96 to i32
>  %146 = bitcast float %98 to i32
>  %147 = insertelement <2 x i32> undef, i32 %145, i32 0
>  %148 = insertelement <2 x i32> %147, i32 %146, i32 1
>  %149 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %148, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %150 = extractelement <4 x float> %149, i32 3
>  %151 = call float @fabs(float %120)
>  %152 = call float @fabs(float %126)
>  %153 = call float @fabs(float %132)
>  %154 = call float @fabs(float %138)
>  %155 = fsub float -0.000000e+00, %25
>  %156 = fmul float %151, %26
>  %157 = fadd float %156, %155
>  %158 = fsub float -0.000000e+00, %25
>  %159 = fmul float %152, %26
>  %160 = fadd float %159, %158
>  %161 = fsub float -0.000000e+00, %25
>  %162 = fmul float %153, %26
>  %163 = fadd float %162, %161
>  %164 = fsub float -0.000000e+00, %25
>  %165 = fmul float %154, %26
>  %166 = fadd float %165, %164
>  %167 = fsub float -0.000000e+00, %69
>  %168 = fadd float %157, %167
>  %169 = fsub float -0.000000e+00, %69
>  %170 = fadd float %160, %169
>  %171 = fsub float -0.000000e+00, %69
>  %172 = fadd float %163, %171
>  %173 = fsub float -0.000000e+00, %69
>  %174 = fadd float %166, %173
>  %175 = call float @fabs(float %168)
>  %176 = call float @fabs(float %170)
>  %177 = call float @fabs(float %172)
>  %178 = call float @fabs(float %174)
>  %179 = fcmp uge float %175, %89
>  %180 = select i1 %179, float 1.000000e+00, float 0.000000e+00
>  %181 = fsub float -0.000000e+00, %180
>  %182 = fptosi float %181 to i32
>  %183 = bitcast i32 %182 to float
>  %184 = bitcast float %183 to i32
>  %185 = icmp ne i32 %184, 0
>  %temp48.0 = select i1 %185, float 0.000000e+00, float 0x3FC84FF440000000
>  %186 = fcmp uge float %176, %89
>  %187 = select i1 %186, float 1.000000e+00, float 0.000000e+00
>  %188 = fsub float -0.000000e+00, %187
>  %189 = fptosi float %188 to i32
>  %190 = bitcast i32 %189 to float
>  %191 = bitcast float %190 to i32
>  %192 = icmp ne i32 %191, 0
>  %.83 = select i1 %192, float 0.000000e+00, float 0x3FC84FF440000000
>  %193 = fcmp uge float %177, %89
>  %194 = select i1 %193, float 1.000000e+00, float 0.000000e+00
>  %195 = fsub float -0.000000e+00, %194
>  %196 = fptosi float %195 to i32
>  %197 = bitcast i32 %196 to float
>  %198 = bitcast float %197 to i32
>  %199 = icmp ne i32 %198, 0
>  %temp52.1 = select i1 %199, float 0.000000e+00, float 0x3FBE9AE500000000
>  %200 = fcmp uge float %178, %89
>  %201 = select i1 %200, float 1.000000e+00, float 0.000000e+00
>  %202 = fsub float -0.000000e+00, %201
>  %203 = fptosi float %202 to i32
>  %204 = bitcast i32 %203 to float
>  %205 = bitcast float %204 to i32
>  %206 = icmp ne i32 %205, 0
>  %.84 = select i1 %206, float 0.000000e+00, float 0x3FBE9AE500000000
>  %207 = fmul float %144, %temp48.0
>  %208 = fmul float %150, %.83
>  %209 = fadd float %207, %208
>  %210 = fmul float %144, %temp52.1
>  %211 = fadd float %209, %210
>  %212 = fmul float %150, %.84
>  %213 = fadd float %211, %212
>  %214 = fadd float %90, %213
>  %215 = fadd float 0x3FCC5E8920000000, %temp48.0
>  %216 = fadd float 0.000000e+00, %.83
>  %217 = fadd float 0.000000e+00, %temp52.1
>  %218 = fadd float 0.000000e+00, %.84
>  %219 = fmul float %27, -2.000000e+00
>  %220 = fadd float %219, %92
>  %221 = fmul float %28, -2.000000e+00
>  %222 = fadd float %221, %94
>  %223 = fmul float %27, 2.000000e+00
>  %224 = fadd float %223, %96
>  %225 = fmul float %28, 2.000000e+00
>  %226 = fadd float %225, %98
>  %227 = fmul float %29, -2.000000e+00
>  %228 = fadd float %227, %100
>  %229 = fmul float %30, -2.000000e+00
>  %230 = fadd float %229, %102
>  %231 = fmul float %29, 2.000000e+00
>  %232 = fadd float %231, %104
>  %233 = fmul float %30, 2.000000e+00
>  %234 = fadd float %233, %106
>  %235 = fmul float %29, -2.000000e+00
>  %236 = fadd float %235, %108
>  %237 = fmul float %30, -2.000000e+00
>  %238 = fadd float %237, %110
>  %239 = fmul float %29, 2.000000e+00
>  %240 = fadd float %239, %112
>  %241 = fmul float %30, 2.000000e+00
>  %242 = fadd float %241, %114
>  %243 = bitcast float %228 to i32
>  %244 = bitcast float %230 to i32
>  %245 = insertelement <2 x i32> undef, i32 %243, i32 0
>  %246 = insertelement <2 x i32> %245, i32 %244, i32 1
>  %247 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %246, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %248 = extractelement <4 x float> %247, i32 0
>  %249 = bitcast float %232 to i32
>  %250 = bitcast float %234 to i32
>  %251 = insertelement <2 x i32> undef, i32 %249, i32 0
>  %252 = insertelement <2 x i32> %251, i32 %250, i32 1
>  %253 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %252, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %254 = extractelement <4 x float> %253, i32 0
>  %255 = bitcast float %236 to i32
>  %256 = bitcast float %238 to i32
>  %257 = insertelement <2 x i32> undef, i32 %255, i32 0
>  %258 = insertelement <2 x i32> %257, i32 %256, i32 1
>  %259 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %258, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %260 = extractelement <4 x float> %259, i32 0
>  %261 = bitcast float %240 to i32
>  %262 = bitcast float %242 to i32
>  %263 = insertelement <2 x i32> undef, i32 %261, i32 0
>  %264 = insertelement <2 x i32> %263, i32 %262, i32 1
>  %265 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %264, <32 x i8> %36, <16 x i8> %38, i32 2)
>  %266 = extractelement <4 x float> %265, i32 0
>  %267 = bitcast float %220 to i32
>  %268 = bitcast float %222 to i32
>  %269 = insertelement <2 x i32> undef, i32 %267, i32 0
>  %270 = insertelement <2 x i32> %269, i32 %268, i32 1
>  %271 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %270, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %272 = extractelement <4 x float> %271, i32 3
>  %273 = bitcast float %224 to i32
>  %274 = bitcast float %226 to i32
>  %275 = insertelement <2 x i32> undef, i32 %273, i32 0
>  %276 = insertelement <2 x i32> %275, i32 %274, i32 1
>  %277 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %276, <32 x i8> %40, <16 x i8> %42, i32 2)
>  %278 = extractelement <4 x float> %277, i32 3
>  %279 = call float @fabs(float %248)
>  %280 = call float @fabs(float %254)
>  %281 = call float @fabs(float %260)
>  %282 = call float @fabs(float %266)
>  %283 = fsub float -0.000000e+00, %25
>  %284 = fmul float %279, %26
>  %285 = fadd float %284, %283
>  %286 = fsub float -0.000000e+00, %25
>  %287 = fmul float %280, %26
>  %288 = fadd float %287, %286
>  %289 = fsub float -0.000000e+00, %25
>  %290 = fmul float %281, %26
>  %291 = fadd float %290, %289
>  %292 = fsub float -0.000000e+00, %25
>  %293 = fmul float %282, %26
>  %294 = fadd float %293, %292
>  %295 = fsub float -0.000000e+00, %69
>  %296 = fadd float %285, %295
>  %297 = fsub float -0.000000e+00, %69
>  %298 = fadd float %288, %297
>  %299 = fsub float -0.000000e+00, %69
>  %300 = fadd float %291, %299
>  %301 = fsub float -0.000000e+00, %69
>  %302 = fadd float %294, %301
>  %303 = call float @fabs(float %296)
>  %304 = call float @fabs(float %298)
>  %305 = call float @fabs(float %300)
>  %306 = call float @fabs(float %302)
>  %307 = fcmp uge float %303, %89
>  %308 = select i1 %307, float 1.000000e+00, float 0.000000e+00
>  %309 = fsub float -0.000000e+00, %308
>  %310 = fptosi float %309 to i32
>  %311 = bitcast i32 %310 to float
>  %312 = bitcast float %311 to i32
>  %313 = icmp ne i32 %312, 0
>  %temp24.0 = select i1 %313, float 0.000000e+00, float 0x3FAC4BB500000000
>  %314 = fcmp uge float %304, %89
>  %315 = select i1 %314, float 1.000000e+00, float 0.000000e+00
>  %316 = fsub float -0.000000e+00, %315
>  %317 = fptosi float %316 to i32
>  %318 = bitcast i32 %317 to float
>  %319 = bitcast float %318 to i32
>  %320 = icmp ne i32 %319, 0
>  %.85 = select i1 %320, float 0.000000e+00, float 0x3FAC4BB500000000
>  %321 = fcmp uge float %305, %89
>  %322 = select i1 %321, float 1.000000e+00, float 0.000000e+00
>  %323 = fsub float -0.000000e+00, %322
>  %324 = fptosi float %323 to i32
>  %325 = bitcast i32 %324 to float
>  %326 = bitcast float %325 to i32
>  %327 = icmp ne i32 %326, 0
>  %temp24.2 = select i1 %327, float 0.000000e+00, float 0x3F9336A260000000
>  %328 = fcmp uge float %306, %89
>  %329 = select i1 %328, float 1.000000e+00, float 0.000000e+00
>  %330 = fsub float -0.000000e+00, %329
>  %331 = fptosi float %330 to i32
>  %332 = bitcast i32 %331 to float
>  %333 = bitcast float %332 to i32
>  %334 = icmp ne i32 %333, 0
>  %.86 = select i1 %334, float 0.000000e+00, float 0x3F9336A260000000
>  %335 = fmul float %272, %temp24.0
>  %336 = fmul float %278, %.85
>  %337 = fadd float %335, %336
>  %338 = fmul float %272, %temp24.2
>  %339 = fadd float %337, %338
>  %340 = fmul float %278, %.86
>  %341 = fadd float %339, %340
>  %342 = fadd float %214, %341
>  %343 = fadd float %215, %temp24.0
>  %344 = fadd float %216, %.85
>  %345 = fadd float %217, %temp24.2
>  %346 = fadd float %218, %.86
>  %347 = fmul float %343, 1.000000e+00
>  %348 = fmul float %344, 1.000000e+00
>  %349 = fadd float %347, %348
>  %350 = fmul float %345, 1.000000e+00
>  %351 = fadd float %349, %350
>  %352 = fmul float %346, 1.000000e+00
>  %353 = fadd float %351, %352
>  %354 = fdiv float 1.000000e+00, %353
>  %355 = fmul float %342, %354
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %ELSE
>  %temp15.0 = phi float [ %355, %ELSE ], [ %52, %main_body ]
>  %356 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
>  %357 = bitcast i32 %356 to float
>  %358 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %temp15.0)
>  %359 = bitcast i32 %358 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %357, float %359, float %357, float %359)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8240100
>c8250101
>c8200000
>c8210001
>c08a0304
>c0cc0508
>bf8c007f
>f0800800
>00a60208
>c81c0300
>c81d0301
>c8180200
>c8190201
>c0840300
>c0c60500
>bf8c0070
>f0800100
>00430406
>7e0002ff
>3f733333
>bf8c0770
>d0080002
>02020104
>d2000000
>0009e480
>d2060000
>22010100
>7e001100
>d1040028
>02010100
>c0960100
>bf8c007f
>c2012d0f
>c201ad0e
>c2022d0d
>c202ad0c
>c2032d0b
>c203ad0a
>c2102d09
>c210ad08
>c2112d05
>c211ad04
>c2122d02
>c212ad01
>c2132d00
>bf8c007f
>be802428
>8980007e
>bf880133
>7e1c0202
>7e180203
>7e160204
>7e200205
>7e240206
>7e1e0207
>7e2c0220
>7e2a0221
>7e020222
>7e000223
>7e0a0224
>7e1a0225
>7e140226
>d2060103
>02010104
>10060303
>08060103
>d2060011
>22010103
>08202111
>101c1d10
>d206080e
>0201010e
>d282000c
>03ca1d0c
>10161711
>d206080b
>0201010b
>1016170c
>d0020002
>02010104
>d2000004
>0009e480
>d2060004
>22010104
>7e081104
>d10a0002
>02010104
>d2000004
>000a1b0b
>10080b04
>1008090a
>06180f12
>062e2512
>061c1917
>06160d0f
>06301f0f
>061a1718
>f0800100
>0043050d
>bf8c0770
>d2060105
>02010105
>100a0305
>080a0105
>080a0705
>d2060105
>02010105
>d00c0002
>02020905
>d2000005
>0009e480
>d2060005
>22010105
>7e0a1105
>d10a0002
>02010105
>7e1402ff
>3d625da8
>d2000005
>0009010a
>7e2602ff
>3fc00000
>d282000e
>04262716
>06202d16
>06221d10
>d282000d
>04222715
>06262b15
>06201b13
>f0800800
>00a61b10
>bf8c0770
>10320b1b
>08222507
>d2820014
>0445eb12
>08201f06
>d2820013
>0441eb0f
>f0800100
>00431313
>bf8c0770
>d2060113
>02010113
>10260313
>08260113
>08260713
>d2060113
>02010113
>d00c0002
>02020913
>d2000013
>0009e480
>d2060013
>22010113
>7e261113
>d10a0002
>02010113
>d200000a
>0009010a
>7e3402ff
>bfc00000
>d2820014
>04263516
>d282001d
>0451eb16
>d2820013
>04223515
>d282001c
>044deb15
>f0800800
>00a6091c
>bf8c0770
>d2820019
>04661509
>d2820016
>041deb12
>d282001d
>0459eb12
>d2820015
>0419eb0f
>d282001c
>0455eb0f
>f0800100
>0043081c
>bf8c0770
>d2060108
>02010108
>10100308
>08100108
>08100708
>d2060108
>02010108
>d00c0002
>02020908
>d2000008
>0009e480
>d2060008
>22010108
>7e101108
>d10a0002
>02010108
>7e1e02ff
>3c99b513
>d2000008
>0009010f
>d2820009
>04661109
>06340f17
>063a3517
>06320d18
>06383318
>f0800100
>0043061c
>bf8c0770
>d2060106
>02010106
>100c0306
>080c0106
>080c0706
>d2060106
>02010106
>d00c0002
>02020906
>d2000006
>0009e480
>d2060006
>22010106
>7e0c1106
>d10a0002
>02010106
>d2000006
>0009010f
>d2820007
>04260d1b
>f0800100
>0043090b
>bf8c0770
>d2060109
>02010109
>10120309
>08120109
>08120709
>d2060109
>02010109
>d00c0002
>02020909
>d2000009
>0009e480
>d2060009
>22010109
>7e121109
>d10a0002
>02010109
>7e1802ff
>3e427fa2
>d2000009
>0009010c
>f0800800
>00a60b0d
>bf8c0770
>101a130b
>f0800100
>00430e10
>bf8c0770
>d206010e
>0201010e
>101c030e
>081c010e
>081c070e
>d206010e
>0201010e
>d00c0002
>0202090e
>d200000e
>0009e480
>d206000e
>2201010e
>7e1c110e
>d10a0002
>0201010e
>d200000c
>0009010c
>f0800800
>00a60e13
>bf8c0770
>d282000f
>0436190e
>f0800100
>00430d15
>bf8c0770
>d206010d
>0201010d
>101a030d
>081a010d
>081a070d
>d206010d
>0201010d
>d00c0002
>0202090d
>d200000d
>0009e480
>d206000d
>2201010d
>7e1a110d
>d10a0002
>0201010d
>7e2002ff
>3df4d728
>d200000d
>00090110
>d282000e
>043e1b0e
>f0800100
>00430f19
>bf8c0770
>d206010f
>0201010f
>1002030f
>08000101
>08000700
>d2060100
>02010100
>d00c0002
>02020900
>d2000000
>0009e480
>d2060000
>22010100
>7e001100
>d10a0002
>02010100
>d2000000
>00090110
>d2820001
>043a010b
>7e0602ff
>3e62f449
>d2820001
>04060702
>06020f01
>06041280
>06040b02
>060618ff
>3e62f449
>06061503
>06040503
>06061a80
>06061103
>06040702
>06000080
>06000d00
>06000102
>7e005500
>10040101
>88fe007e
>5e000480
>d25e0001
>02010080
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL IN[1], GENERIC[20], PERSPECTIVE
>DCL IN[2], GENERIC[21], PERSPECTIVE
>DCL IN[3], GENERIC[22], PERSPECTIVE
>DCL IN[4], GENERIC[23], PERSPECTIVE
>DCL IN[5], GENERIC[24], PERSPECTIVE
>DCL IN[6], GENERIC[25], PERSPECTIVE
>DCL IN[7], GENERIC[26], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL CONST[0..12]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {    0.0000,     2.0000,    -1.0000,     1.0001}
>IMM[1] FLT32 {   32.0000,   -16.0000,     1.0000, 65504.0000}
>IMM[2] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].z, IN[7].xxxx
>  1: MOV TEMP[0].xy, IN[6].zwzz
>  2: MOV TEMP[1].yz, IN[6].yxyy
>  3: MOV TEMP[1].x, IN[5].wwww
>  4: MOV TEMP[2].xy, IN[4].xyyy
>  5: TEX TEMP[2].xw, TEMP[2], SAMP[1], 2D
>  6: MUL TEMP[2].xy, TEMP[2].wxxx, IN[4].zwww
>  7: RCP TEMP[3].xy, IN[1].wwww
>  8: MUL TEMP[3].xy, IN[0].xyyy, TEMP[3].xyyy
>  9: MOV TEMP[4].xy, IN[2].xyyy
> 10: TEX TEMP[4], TEMP[4], SAMP[2], 2D
> 11: SLT TEMP[5].x, IMM[0].xxxx, TEMP[4].zzzz
> 12: F2I TEMP[5].x, -TEMP[5]
> 13: UIF TEMP[5].xxxx :0
> 14:   MOV TEMP[5].xy, TEMP[4].ywyy
> 15: ELSE :0
> 16:   MOV TEMP[5].xy, TEMP[4].xyxx
> 17: ENDIF
> 18: MOV TEMP[4].xy, TEMP[5].xyxx
> 19: MOV TEMP[5].xy, IN[2].zwww
> 20: TEX TEMP[5], TEMP[5], SAMP[3], 2D
> 21: SLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
> 22: F2I TEMP[6].x, -TEMP[6]
> 23: UIF TEMP[6].xxxx :0
> 24:   MOV TEMP[6].xy, TEMP[5].ywyy
> 25: ELSE :0
> 26:   MOV TEMP[6].xy, TEMP[5].xyxx
> 27: ENDIF
> 28: MOV TEMP[4].zw, TEMP[6].yyxy
> 29: MOV TEMP[5].xy, IN[3].xyyy
> 30: TEX TEMP[5], TEMP[5], SAMP[4], 2D
> 31: SLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
> 32: F2I TEMP[6].x, -TEMP[6]
> 33: UIF TEMP[6].xxxx :0
> 34:   MOV TEMP[6].xy, TEMP[5].ywyy
> 35: ELSE :0
> 36:   MOV TEMP[6].xy, TEMP[5].xyxx
> 37: ENDIF
> 38: MOV TEMP[5].xy, TEMP[6].xyxx
> 39: MOV TEMP[6].xy, IN[3].zwww
> 40: TEX TEMP[6], TEMP[6], SAMP[5], 2D
> 41: SLT TEMP[7].x, IMM[0].xxxx, TEMP[6].zzzz
> 42: F2I TEMP[7].x, -TEMP[7]
> 43: UIF TEMP[7].xxxx :0
> 44:   MOV TEMP[7].xy, TEMP[6].ywyy
> 45: ELSE :0
> 46:   MOV TEMP[7].xy, TEMP[6].xyxx
> 47: ENDIF
> 48: MOV TEMP[5].zw, TEMP[7].yyxy
> 49: MAD TEMP[6], TEMP[4], IMM[0].yyyy, IMM[0].zzzz
> 50: MOV TEMP[4], -TEMP[6]
> 51: MAD TEMP[6], TEMP[5], IMM[0].yyyy, IMM[0].zzzz
> 52: MOV TEMP[5], -TEMP[6]
> 53: MUL TEMP[4], TEMP[4], CONST[1].xxyy
> 54: MUL TEMP[5], TEMP[5], CONST[1].zzww
> 55: ADD TEMP[4], TEMP[4], TEMP[5]
> 56: ADD TEMP[4].xy, TEMP[4].xyyy, TEMP[4].zwww
> 57: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[2].xxxx
> 58: MOV TEMP[5].xy, TEMP[4].xyxx
> 59: DP2 TEMP[6].x, TEMP[4].xyyy, TEMP[4].xyyy
> 60: ADD_SAT TEMP[6].x, IMM[0].wwww, -TEMP[6].xxxx
> 61: RSQ TEMP[7].x, TEMP[6].xxxx
> 62: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx
> 63: CMP TEMP[7].x, -TEMP[6].xxxx, TEMP[7].xxxx, IMM[0].xxxx
> 64: MOV TEMP[5].z, TEMP[7].xxxx
> 65: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
> 66: RSQ TEMP[6].x, TEMP[6].xxxx
> 67: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
> 68: ADD TEMP[6].xyz, CONST[12].xyzz, -IN[1].xyzz
> 69: MUL TEMP[7].xyz, IN[5].xyzz, TEMP[5].xxxx
> 70: MAD TEMP[1].xyz, TEMP[1].xyzz, TEMP[5].yyyy, TEMP[7].xyzz
> 71: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].zzzz, TEMP[1].xyzz
> 72: ADD TEMP[1].xy, TEMP[3].xyyy, TEMP[4].xyyy
> 73: MOV TEMP[1].xy, TEMP[1].xyyy
> 74: MOV TEMP[1].w, CONST[2].zzzz
> 75: TXL TEMP[1], TEMP[1], SAMP[0], 2D
> 76: MAD TEMP[3].x, TEMP[1].wwww, IMM[1].xxxx, IMM[1].yyyy
> 77: EX2 TEMP[3].x, TEMP[3].xxxx
> 78: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
> 79: MUL TEMP[1].xyz, CONST[0].xyzz, TEMP[1].xyzz
> 80: MOV TEMP[1].w, IMM[1].zzzz
> 81: MUL TEMP[2].x, CONST[0].wwww, TEMP[2].yyyy
> 82: DP3 TEMP[3].x, TEMP[6].xyzz, TEMP[6].xyzz
> 83: RSQ TEMP[3].x, TEMP[3].xxxx
> 84: MUL TEMP[3].xyz, TEMP[6].xyzz, TEMP[3].xxxx
> 85: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
> 86: RSQ TEMP[4].x, TEMP[4].xxxx
> 87: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
> 88: DP3_SAT TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz
> 89: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
> 90: POW TEMP[0].x, TEMP[0].xxxx, CONST[2].xxxx
> 91: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[0].xxxx
> 92: MOV TEMP[2].xz, IN[0].zzwz
> 93: MUL TEMP[3].xy, IN[0].zwww, IN[0].zwww
> 94: MAD TEMP[3].xy, IMM[0].yyyy, IN[0].zwww, -TEMP[3].xyyy
> 95: MOV TEMP[2].yw, TEMP[3].yxyy
> 96: MUL TEMP[2], TEMP[2], CONST[5]
> 97: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
> 98: MUL TEMP[0], CONST[3].zzzw, TEMP[0].xxxx
> 99: LRP TEMP[0], TEMP[0], CONST[3].xxxy, TEMP[1]
>100: LRP TEMP[0], TEMP[2].zzzw, CONST[7], TEMP[0]
>101: LRP TEMP[0], TEMP[2].xxxy, CONST[6], TEMP[0]
>102: MIN TEMP[2].xyz, TEMP[0].xyzz, IMM[1].wwww
>103: MAX TEMP[1].xyz, TEMP[2].xyzz, IMM[2].xxxx
>104: MAD_SAT TEMP[0].x, TEMP[0].wwww, CONST[4].xxxx, CONST[4].yyyy
>105: MOV TEMP[1].w, TEMP[0].xxxx
>106: MOV OUT[0], TEMP[1]
>107: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 96)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 100)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 104)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 108)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 112)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 116)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 120)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 124)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %53 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
>  %55 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
>  %57 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0
>  %59 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0
>  %61 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0
>  %63 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0
>  %65 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0
>  %67 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
>  %69 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %70 = load <32 x i8> addrspace(2)* %69, !tbaa !0
>  %71 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0
>  %73 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %74 = load <32 x i8> addrspace(2)* %73, !tbaa !0
>  %75 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0
>  %77 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %78 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %79 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %80 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %81 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %82 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %83 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %84 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %85 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %86 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %87 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %88 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %89 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %90 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %91 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %3, <2 x i32> %5)
>  %92 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %3, <2 x i32> %5)
>  %93 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %94 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %95 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %96 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %97 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %98 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %99 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
>  %100 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %101 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %102 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %103 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %3, <2 x i32> %5)
>  %104 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %3, <2 x i32> %5)
>  %105 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %3, <2 x i32> %5)
>  %106 = bitcast float %93 to i32
>  %107 = bitcast float %94 to i32
>  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
>  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
>  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %58, <16 x i8> %60, i32 2)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 3
>  %113 = fmul float %112, %95
>  %114 = fmul float %111, %96
>  %115 = fdiv float 1.000000e+00, %84
>  %116 = fmul float %77, %115
>  %117 = fmul float %78, %115
>  %118 = bitcast float %85 to i32
>  %119 = bitcast float %86 to i32
>  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
>  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
>  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %62, <16 x i8> %64, i32 2)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = fcmp ult float 0.000000e+00, %125
>  %128 = select i1 %127, float 1.000000e+00, float 0.000000e+00
>  %129 = fsub float -0.000000e+00, %128
>  %130 = fptosi float %129 to i32
>  %131 = bitcast i32 %130 to float
>  %132 = bitcast float %131 to i32
>  %133 = icmp ne i32 %132, 0
>  %. = select i1 %133, float %124, float %123
>  %.41 = select i1 %133, float %126, float %124
>  %134 = bitcast float %87 to i32
>  %135 = bitcast float %88 to i32
>  %136 = insertelement <2 x i32> undef, i32 %134, i32 0
>  %137 = insertelement <2 x i32> %136, i32 %135, i32 1
>  %138 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %137, <32 x i8> %66, <16 x i8> %68, i32 2)
>  %139 = extractelement <4 x float> %138, i32 0
>  %140 = extractelement <4 x float> %138, i32 1
>  %141 = extractelement <4 x float> %138, i32 2
>  %142 = extractelement <4 x float> %138, i32 3
>  %143 = fcmp ult float 0.000000e+00, %141
>  %144 = select i1 %143, float 1.000000e+00, float 0.000000e+00
>  %145 = fsub float -0.000000e+00, %144
>  %146 = fptosi float %145 to i32
>  %147 = bitcast i32 %146 to float
>  %148 = bitcast float %147 to i32
>  %149 = icmp ne i32 %148, 0
>  %temp24.0 = select i1 %149, float %140, float %139
>  %temp25.0 = select i1 %149, float %142, float %140
>  %150 = bitcast float %89 to i32
>  %151 = bitcast float %90 to i32
>  %152 = insertelement <2 x i32> undef, i32 %150, i32 0
>  %153 = insertelement <2 x i32> %152, i32 %151, i32 1
>  %154 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %153, <32 x i8> %70, <16 x i8> %72, i32 2)
>  %155 = extractelement <4 x float> %154, i32 0
>  %156 = extractelement <4 x float> %154, i32 1
>  %157 = extractelement <4 x float> %154, i32 2
>  %158 = extractelement <4 x float> %154, i32 3
>  %159 = fcmp ult float 0.000000e+00, %157
>  %160 = select i1 %159, float 1.000000e+00, float 0.000000e+00
>  %161 = fsub float -0.000000e+00, %160
>  %162 = fptosi float %161 to i32
>  %163 = bitcast i32 %162 to float
>  %164 = bitcast float %163 to i32
>  %165 = icmp ne i32 %164, 0
>  %.42 = select i1 %165, float %156, float %155
>  %.43 = select i1 %165, float %158, float %156
>  %166 = bitcast float %91 to i32
>  %167 = bitcast float %92 to i32
>  %168 = insertelement <2 x i32> undef, i32 %166, i32 0
>  %169 = insertelement <2 x i32> %168, i32 %167, i32 1
>  %170 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %169, <32 x i8> %74, <16 x i8> %76, i32 2)
>  %171 = extractelement <4 x float> %170, i32 0
>  %172 = extractelement <4 x float> %170, i32 1
>  %173 = extractelement <4 x float> %170, i32 2
>  %174 = extractelement <4 x float> %170, i32 3
>  %175 = fcmp ult float 0.000000e+00, %173
>  %176 = select i1 %175, float 1.000000e+00, float 0.000000e+00
>  %177 = fsub float -0.000000e+00, %176
>  %178 = fptosi float %177 to i32
>  %179 = bitcast i32 %178 to float
>  %180 = bitcast float %179 to i32
>  %181 = icmp ne i32 %180, 0
>  %temp28.0 = select i1 %181, float %172, float %171
>  %temp29.0 = select i1 %181, float %174, float %172
>  %182 = fmul float %., 2.000000e+00
>  %183 = fadd float %182, -1.000000e+00
>  %184 = fmul float %.41, 2.000000e+00
>  %185 = fadd float %184, -1.000000e+00
>  %186 = fmul float %temp24.0, 2.000000e+00
>  %187 = fadd float %186, -1.000000e+00
>  %188 = fmul float %temp25.0, 2.000000e+00
>  %189 = fadd float %188, -1.000000e+00
>  %190 = fsub float -0.000000e+00, %183
>  %191 = fsub float -0.000000e+00, %185
>  %192 = fsub float -0.000000e+00, %187
>  %193 = fsub float -0.000000e+00, %189
>  %194 = fmul float %.42, 2.000000e+00
>  %195 = fadd float %194, -1.000000e+00
>  %196 = fmul float %.43, 2.000000e+00
>  %197 = fadd float %196, -1.000000e+00
>  %198 = fmul float %temp28.0, 2.000000e+00
>  %199 = fadd float %198, -1.000000e+00
>  %200 = fmul float %temp29.0, 2.000000e+00
>  %201 = fadd float %200, -1.000000e+00
>  %202 = fsub float -0.000000e+00, %195
>  %203 = fsub float -0.000000e+00, %197
>  %204 = fsub float -0.000000e+00, %199
>  %205 = fsub float -0.000000e+00, %201
>  %206 = fmul float %190, %26
>  %207 = fmul float %191, %26
>  %208 = fmul float %192, %27
>  %209 = fmul float %193, %27
>  %210 = fmul float %202, %28
>  %211 = fmul float %203, %28
>  %212 = fmul float %204, %29
>  %213 = fmul float %205, %29
>  %214 = fadd float %206, %210
>  %215 = fadd float %207, %211
>  %216 = fadd float %208, %212
>  %217 = fadd float %209, %213
>  %218 = fadd float %214, %216
>  %219 = fadd float %215, %217
>  %220 = fmul float %218, %113
>  %221 = fmul float %219, %113
>  %222 = fmul float %220, %220
>  %223 = fmul float %221, %221
>  %224 = fadd float %222, %223
>  %225 = fsub float -0.000000e+00, %224
>  %226 = fadd float 0x3FF00068E0000000, %225
>  %227 = call float @llvm.AMDIL.clamp.(float %226, float 0.000000e+00, float 1.000000e+00)
>  %228 = call float @llvm.AMDGPU.rsq(float %227)
>  %229 = fmul float %228, %227
>  %230 = fsub float -0.000000e+00, %227
>  %231 = call float @llvm.AMDGPU.cndlt(float %230, float %229, float 0.000000e+00)
>  %232 = fmul float %220, %220
>  %233 = fmul float %221, %221
>  %234 = fadd float %233, %232
>  %235 = fmul float %231, %231
>  %236 = fadd float %234, %235
>  %237 = call float @llvm.AMDGPU.rsq(float %236)
>  %238 = fmul float %220, %237
>  %239 = fmul float %221, %237
>  %240 = fmul float %231, %237
>  %241 = fsub float -0.000000e+00, %81
>  %242 = fadd float %50, %241
>  %243 = fsub float -0.000000e+00, %82
>  %244 = fadd float %51, %243
>  %245 = fsub float -0.000000e+00, %83
>  %246 = fadd float %52, %245
>  %247 = fmul float %97, %238
>  %248 = fmul float %98, %238
>  %249 = fmul float %99, %238
>  %250 = fmul float %100, %239
>  %251 = fadd float %250, %247
>  %252 = fmul float %101, %239
>  %253 = fadd float %252, %248
>  %254 = fmul float %102, %239
>  %255 = fadd float %254, %249
>  %256 = fmul float %103, %240
>  %257 = fadd float %256, %251
>  %258 = fmul float %104, %240
>  %259 = fadd float %258, %253
>  %260 = fmul float %105, %240
>  %261 = fadd float %260, %255
>  %262 = fadd float %116, %220
>  %263 = fadd float %117, %221
>  %264 = bitcast float %262 to i32
>  %265 = bitcast float %263 to i32
>  %266 = bitcast float %31 to i32
>  %267 = insertelement <4 x i32> undef, i32 %264, i32 0
>  %268 = insertelement <4 x i32> %267, i32 %265, i32 1
>  %269 = insertelement <4 x i32> %268, i32 %266, i32 2
>  %270 = insertelement <4 x i32> %269, i32 undef, i32 3
>  %271 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %270, <32 x i8> %54, <16 x i8> %56, i32 2)
>  %272 = extractelement <4 x float> %271, i32 0
>  %273 = extractelement <4 x float> %271, i32 1
>  %274 = extractelement <4 x float> %271, i32 2
>  %275 = extractelement <4 x float> %271, i32 3
>  %276 = fmul float %275, 3.200000e+01
>  %277 = fadd float %276, -1.600000e+01
>  %278 = call float @llvm.AMDIL.exp.(float %277)
>  %279 = fmul float %272, %278
>  %280 = fmul float %273, %278
>  %281 = fmul float %274, %278
>  %282 = fmul float %22, %279
>  %283 = fmul float %23, %280
>  %284 = fmul float %24, %281
>  %285 = fmul float %25, %114
>  %286 = fmul float %242, %242
>  %287 = fmul float %244, %244
>  %288 = fadd float %287, %286
>  %289 = fmul float %246, %246
>  %290 = fadd float %288, %289
>  %291 = call float @llvm.AMDGPU.rsq(float %290)
>  %292 = fmul float %242, %291
>  %293 = fmul float %244, %291
>  %294 = fmul float %246, %291
>  %295 = fmul float %257, %257
>  %296 = fmul float %259, %259
>  %297 = fadd float %296, %295
>  %298 = fmul float %261, %261
>  %299 = fadd float %297, %298
>  %300 = call float @llvm.AMDGPU.rsq(float %299)
>  %301 = fmul float %257, %300
>  %302 = fmul float %259, %300
>  %303 = fmul float %261, %300
>  %304 = fmul float %292, %301
>  %305 = fmul float %293, %302
>  %306 = fadd float %305, %304
>  %307 = fmul float %294, %303
>  %308 = fadd float %306, %307
>  %309 = call float @llvm.AMDIL.clamp.(float %308, float 0.000000e+00, float 1.000000e+00)
>  %310 = fsub float -0.000000e+00, %309
>  %311 = fadd float 1.000000e+00, %310
>  %312 = call float @llvm.pow.f32(float %311, float %30)
>  %313 = fmul float %285, %312
>  %314 = fmul float %79, %79
>  %315 = fmul float %80, %80
>  %316 = fsub float -0.000000e+00, %314
>  %317 = fmul float 2.000000e+00, %79
>  %318 = fadd float %317, %316
>  %319 = fsub float -0.000000e+00, %315
>  %320 = fmul float 2.000000e+00, %80
>  %321 = fadd float %320, %319
>  %322 = fmul float %79, %38
>  %323 = fmul float %318, %39
>  %324 = fmul float %80, %40
>  %325 = fmul float %321, %41
>  %326 = fsub float -0.000000e+00, %313
>  %327 = fadd float 1.000000e+00, %326
>  %328 = fmul float %34, %327
>  %329 = fmul float %34, %327
>  %330 = fmul float %34, %327
>  %331 = fmul float %35, %327
>  %332 = call float @llvm.AMDGPU.lrp(float %328, float %32, float %282)
>  %333 = call float @llvm.AMDGPU.lrp(float %329, float %32, float %283)
>  %334 = call float @llvm.AMDGPU.lrp(float %330, float %32, float %284)
>  %335 = call float @llvm.AMDGPU.lrp(float %331, float %33, float 1.000000e+00)
>  %336 = call float @llvm.AMDGPU.lrp(float %324, float %46, float %332)
>  %337 = call float @llvm.AMDGPU.lrp(float %324, float %47, float %333)
>  %338 = call float @llvm.AMDGPU.lrp(float %324, float %48, float %334)
>  %339 = call float @llvm.AMDGPU.lrp(float %325, float %49, float %335)
>  %340 = call float @llvm.AMDGPU.lrp(float %322, float %42, float %336)
>  %341 = call float @llvm.AMDGPU.lrp(float %322, float %43, float %337)
>  %342 = call float @llvm.AMDGPU.lrp(float %322, float %44, float %338)
>  %343 = call float @llvm.AMDGPU.lrp(float %323, float %45, float %339)
>  %344 = fcmp uge float %340, 6.550400e+04
>  %345 = select i1 %344, float 6.550400e+04, float %340
>  %346 = fcmp uge float %341, 6.550400e+04
>  %347 = select i1 %346, float 6.550400e+04, float %341
>  %348 = fcmp uge float %342, 6.550400e+04
>  %349 = select i1 %348, float 6.550400e+04, float %342
>  %350 = fcmp uge float %345, 0x3E6FFFFE60000000
>  %351 = select i1 %350, float %345, float 0x3E6FFFFE60000000
>  %352 = fcmp uge float %347, 0x3E6FFFFE60000000
>  %353 = select i1 %352, float %347, float 0x3E6FFFFE60000000
>  %354 = fcmp uge float %349, 0x3E6FFFFE60000000
>  %355 = select i1 %354, float %349, float 0x3E6FFFFE60000000
>  %356 = fmul float %343, %36
>  %357 = fadd float %356, %37
>  %358 = call float @llvm.AMDIL.clamp.(float %357, float 0.000000e+00, float 1.000000e+00)
>  %359 = call i32 @llvm.SI.packf16(float %351, float %353)
>  %360 = bitcast i32 %359 to float
>  %361 = call i32 @llvm.SI.packf16(float %355, float %358)
>  %362 = bitcast i32 %361 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %360, float %362, float %360, float %362)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { nounwind readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>22010107
>d0080000
>02020e80
>d2000008
>00021080
>d2820006
>041a1108
>7e125b06
>100c1305
>100e1302
>c8281500
>c8291501
>10140f0a
>c82c1800
>c82d1801
>d282000a
>042a0d0b
>10101308
>c8241b00
>c8251b01
>d2820009
>042a1109
>c8281400
>c8291401
>10140f0a
>c82c1700
>c82d1701
>d282000a
>042a0d0b
>c82c1a00
>c82d1a01
>d282000a
>042a110b
>1016150a
>d282000b
>042e1309
>c8301600
>c8311601
>100e0f0c
>c8301900
>c8311901
>d2820006
>041e0d0c
>c81c1c00
>c81d1c01
>d2820006
>041a1107
>d2820007
>042e0d06
>7e0e5b07
>10100f09
>10120f0a
>c8280500
>c8290501
>c2000931
>bf8c007f
>08141400
>c82c0400
>c82d0401
>c2000930
>bf8c007f
>08161600
>1018170b
>d282000c
>0432150a
>c8340600
>c8350601
>c2000932
>bf8c007f
>081a1a00
>d282000c
>04321b0d
>7e185b0c
>1016190b
>1012130b
>1014190a
>d2820008
>0426110a
>100c0f06
>100e190d
>d2820006
>04220d07
>d2060806
>02010106
>080c0cf2
>7e0c4f06
>c2000908
>bf8c007f
>0e0c0c00
>7e0c4b06
>c81c1300
>c81d1301
>10060f03
>c2000903
>bf8c007f
>10060600
>10060d03
>080606f2
>c200090e
>bf8c007f
>10080600
>080c08f2
>c81c0100
>c81d0101
>c8200700
>c8210701
>7e165508
>d2820008
>04161707
>c8140000
>c8150001
>d2820007
>040a1705
>c200090a
>bf8c007f
>7e120200
>c0800300
>c0c60500
>bf8c007f
>f0900f00
>00030707
>7e0402ff
>c1800000
>7e0a02ff
>42000000
>bf8c0770
>d2820002
>040a0b0a
>7e164b02
>10041708
>c2000901
>bf8c007f
>10040400
>10040506
>c200090c
>bf8c007f
>d2820005
>04080104
>c8080300
>c8090301
>c2008916
>bf8c007f
>10180401
>081a18f2
>100a0b0d
>c200891d
>bf8c007f
>d282000f
>0414030c
>c8140200
>c8150201
>c2008914
>bf8c007f
>10020a01
>081c02f2
>10001f0e
>c2008919
>bf8c007f
>d2820000
>04000301
>7e1e02ff
>477fe000
>d00c0002
>02021f00
>d2000000
>000a1f00
>7e2002ff
>337ffff3
>d00c0002
>02022100
>d2000000
>000a0110
>10221707
>c2008900
>bf8c007f
>10222201
>10222306
>d2820011
>04440104
>1022230d
>c200891c
>bf8c007f
>d2820011
>0444030c
>1022230e
>c2008918
>bf8c007f
>d2820011
>04440301
>d00c0002
>02021f11
>d2000011
>000a1f11
>d00c0002
>02022111
>d2000011
>000a2310
>5e000111
>100e1709
>c2008902
>bf8c007f
>100e0e01
>100c0f06
>d2820004
>04180104
>1008090d
>c200091e
>bf8c007f
>d2820004
>0410010c
>1008090e
>c200091a
>bf8c007f
>d2820001
>04100101
>d00c0000
>02021f01
>d2000001
>00021f01
>d00c0000
>02022101
>d2000001
>00020310
>c200090f
>bf8c007f
>10060600
>080806f2
>c200090d
>bf8c007f
>d2820003
>04100103
>10080502
>06040502
>08040902
>c2000917
>bf8c007f
>10040400
>080804f2
>10060704
>c200091f
>bf8c007f
>d2820002
>040c0102
>10060b05
>06080b05
>08060704
>c2000915
>bf8c007f
>10060600
>080806f2
>10040504
>c200091b
>bf8c007f
>d2820002
>04080103
>c2000910
>c2008911
>bf8c007f
>7e060201
>d2820002
>040c0102
>d2060802
>02010102
>5e020501
>f8001c0f
>01000100
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL OUT[4], GENERIC[21]
>DCL OUT[5], GENERIC[22]
>DCL OUT[6], GENERIC[23]
>DCL OUT[7], GENERIC[24]
>DCL OUT[8], GENERIC[25]
>DCL OUT[9], GENERIC[26]
>DCL CONST[0..22]
>DCL TEMP[0..15], LOCAL
>IMM[0] FLT32 {    0.5000,     0.0010,     0.0000,     1.0000}
>IMM[1] FLT32 {    0.0001,     1.4427,     0.0000,     0.0000}
>  0: DP4 TEMP[0].x, IN[0], CONST[0]
>  1: DP4 TEMP[1].x, IN[0], CONST[1]
>  2: MOV TEMP[0].y, TEMP[1].xxxx
>  3: DP4 TEMP[1].x, IN[0], CONST[2]
>  4: MOV TEMP[0].z, TEMP[1].xxxx
>  5: DP4 TEMP[1].x, IN[0], CONST[3]
>  6: MOV TEMP[0].w, TEMP[1].xxxx
>  7: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].xxxx
>  8: MAD TEMP[2].xy, TEMP[1].xxxx, IMM[0].xxxx, TEMP[2].xyyy
>  9: DP4 TEMP[3].x, IN[0], CONST[4]
> 10: DP4 TEMP[4].x, IN[0], CONST[5]
> 11: MOV TEMP[3].y, TEMP[4].xxxx
> 12: DP4 TEMP[4].x, IN[0], CONST[6]
> 13: MOV TEMP[3].z, TEMP[4].xxxx
> 14: MOV TEMP[4].xyz, TEMP[3].xyzx
> 15: MOV TEMP[4].w, TEMP[1].xxxx
> 16: DP4 TEMP[1].x, IN[4], CONST[14]
> 17: DP4 TEMP[5].x, IN[4], CONST[15]
> 18: MOV TEMP[1].y, TEMP[5].xxxx
> 19: MOV TEMP[1].xy, TEMP[1].xyxx
> 20: DP4 TEMP[5].x, IN[5], CONST[16]
> 21: DP4 TEMP[6].x, IN[5], CONST[17]
> 22: MOV TEMP[5].y, TEMP[6].xxxx
> 23: MOV TEMP[1].zw, TEMP[5].yyxy
> 24: DP4 TEMP[5].x, IN[6], CONST[18]
> 25: DP4 TEMP[6].x, IN[6], CONST[19]
> 26: MOV TEMP[5].y, TEMP[6].xxxx
> 27: MOV TEMP[5].xy, TEMP[5].xyxx
> 28: DP4 TEMP[6].x, IN[7], CONST[20]
> 29: DP4 TEMP[7].x, IN[7], CONST[21]
> 30: MOV TEMP[6].y, TEMP[7].xxxx
> 31: MOV TEMP[5].zw, TEMP[6].yyxy
> 32: MAD TEMP[6].xy, IN[3].xyyy, CONST[7].xxxx, CONST[7].yyyy
> 33: MOV TEMP[6].zw, TEMP[6].yyxy
> 34: MOV TEMP[6].xy, IN[8].xyxx
> 35: MAD TEMP[7].xyz, IN[1].xyzz, CONST[22].xxxx, CONST[22].yyyy
> 36: MOV TEMP[8].xz, TEMP[7].xxzx
> 37: ADD TEMP[9].x, TEMP[7].yyyy, IMM[0].yyyy
> 38: MOV TEMP[8].y, TEMP[9].xxxx
> 39: MAD TEMP[10], IN[2], CONST[22].zzzz, CONST[22].wwww
> 40: MOV TEMP[11].yz, TEMP[10].zyzw
> 41: ADD TEMP[11].x, TEMP[10].xxxx, IMM[0].yyyy
> 42: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].wwww
> 43: MUL TEMP[12].xyz, TEMP[8].zxyy, TEMP[11].yzxx
> 44: MAD TEMP[8].xyz, TEMP[8].yzxx, TEMP[11].zxyy, -TEMP[12].xyzz
> 45: MOV TEMP[12].x, CONST[4].xxxx
> 46: MOV TEMP[13].x, CONST[4].yyyy
> 47: MOV TEMP[14].x, CONST[4].zzzz
> 48: MOV TEMP[12].y, CONST[5].xxxx
> 49: MOV TEMP[13].y, CONST[5].yyyy
> 50: MOV TEMP[14].y, CONST[5].zzzz
> 51: MOV TEMP[12].z, CONST[6].xxxx
> 52: MOV TEMP[13].z, CONST[6].yyyy
> 53: MOV TEMP[14].z, CONST[6].zzzz
> 54: DP3 TEMP[15].x, TEMP[12].xyzz, TEMP[12].xyzz
> 55: RCP TEMP[15].x, TEMP[15].xxxx
> 56: MUL TEMP[12].xyz, TEMP[12].xyzz, TEMP[15].xxxx
> 57: DP3 TEMP[15].x, TEMP[13].xyzz, TEMP[13].xyzz
> 58: RCP TEMP[15].x, TEMP[15].xxxx
> 59: MUL TEMP[13].xyz, TEMP[13].xyzz, TEMP[15].xxxx
> 60: DP3 TEMP[15].x, TEMP[14].xyzz, TEMP[14].xyzz
> 61: RCP TEMP[15].x, TEMP[15].xxxx
> 62: MUL TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xxxx
> 63: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].xxxx
> 64: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[10].yyyy, TEMP[11].xyzz
> 65: MAD TEMP[10].xyz, TEMP[14].xyzz, TEMP[10].zzzz, TEMP[11].xyzz
> 66: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[8].xxxx
> 67: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[8].yyyy, TEMP[11].xyzz
> 68: MAD TEMP[8].xyz, TEMP[14].xyzz, TEMP[8].zzzz, TEMP[11].xyzz
> 69: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[7].xxxx
> 70: MAD TEMP[9].xyz, TEMP[13].xyzz, TEMP[9].xxxx, TEMP[11].xyzz
> 71: MAD TEMP[7].xyz, TEMP[14].xyzz, TEMP[7].zzzz, TEMP[9].xyzz
> 72: DP3 TEMP[9].x, TEMP[10].xyzz, TEMP[10].xyzz
> 73: RSQ TEMP[9].x, TEMP[9].xxxx
> 74: MUL TEMP[9].xyz, TEMP[10].xyzz, TEMP[9].xxxx
> 75: DP3 TEMP[10].x, TEMP[8].xyzz, TEMP[8].xyzz
> 76: RSQ TEMP[10].x, TEMP[10].xxxx
> 77: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].xxxx
> 78: DP3 TEMP[10].x, TEMP[7].xyzz, TEMP[7].xyzz
> 79: RSQ TEMP[10].x, TEMP[10].xxxx
> 80: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[10].xxxx
> 81: ADD TEMP[10].xyz, TEMP[3].xyzz, -CONST[8].xyzz
> 82: DP3 TEMP[11].x, TEMP[10].xyzz, TEMP[10].xyzz
> 83: RSQ TEMP[12].x, TEMP[11].xxxx
> 84: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx
> 85: CMP TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[0].zzzz
> 86: MOV TEMP[12].w, IMM[0].wwww
> 87: MOV TEMP[12].xyz, TEMP[3].xyzx
> 88: MOV TEMP[3].x, IMM[0].zzzz
> 89: SLT TEMP[13].x, IMM[0].zzzz, CONST[10].xxxx
> 90: F2I TEMP[13].x, -TEMP[13]
> 91: UIF TEMP[13].xxxx :0
> 92:   DP4 TEMP[12].x, TEMP[12], CONST[12]
> 93:   MOV TEMP[13].x, TEMP[12].xxxx
> 94:   DP4 TEMP[14].x, CONST[8], CONST[12]
> 95:   MOV TEMP[13].y, TEMP[14].xxxx
> 96:   ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[14].xxxx
> 97:   SGE TEMP[14].x, TEMP[12].xxxx, IMM[0].zzzz
> 98:   F2I TEMP[14].x, -TEMP[14]
> 99:   UIF TEMP[14].xxxx :0
>100:     MOV TEMP[14].xy, TEMP[13].yxyy
>101:   ELSE :0
>102:     MOV TEMP[14].xy, TEMP[13].xyxx
>103:   ENDIF
>104:   ADD TEMP[13].xy, TEMP[14].xyyy, -CONST[11].xxxx
>105:   ADD TEMP[14].xy, CONST[11].zwww, -TEMP[13].xxxx
>106:   ABS TEMP[12].x, TEMP[12].xxxx
>107:   ADD TEMP[12].x, TEMP[12].xxxx, IMM[0].yyyy
>108:   RCP TEMP[12].x, TEMP[12].xxxx
>109:   MUL_SAT TEMP[12].xy, TEMP[14].xyyy, TEMP[12].xxxx
>110:   MUL TEMP[13].xy, TEMP[13].xyyy, CONST[10].yyyy
>111:   ADD_SAT TEMP[13].xy, IMM[0].wwww, -TEMP[13].xyyy
>112:   MUL TEMP[14].x, TEMP[11].xxxx, CONST[10].xxxx
>113:   ADD_SAT TEMP[12].x, TEMP[12].xxxx, -TEMP[12].yyyy
>114:   ADD TEMP[13].x, TEMP[13].xxxx, TEMP[13].yyyy
>115:   MUL_SAT TEMP[13].x, TEMP[13].xxxx, CONST[11].yyyy
>116:   MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx
>117:   MUL_SAT TEMP[12].x, TEMP[14].xxxx, TEMP[12].xxxx
>118:   MOV TEMP[3].x, TEMP[12].xxxx
>119: ENDIF
>120: MOV TEMP[2].z, TEMP[3].xxxx
>121: MOV TEMP[3].x, TEMP[10].yyyy
>122: MOV TEMP[12].x, IMM[0].zzzz
>123: SLT TEMP[13].x, IMM[0].zzzz, CONST[13].xxxx
>124: F2I TEMP[13].x, -TEMP[13]
>125: UIF TEMP[13].xxxx :0
>126:   MUL_SAT TEMP[13].x, TEMP[11].xxxx, IMM[1].xxxx
>127:   MUL TEMP[13].x, CONST[13].wwww, TEMP[13].xxxx
>128:   ADD TEMP[13].x, IMM[0].wwww, -TEMP[13].xxxx
>129:   MUL TEMP[3].x, TEMP[10].yyyy, TEMP[13].xxxx
>130:   MUL TEMP[3].x, TEMP[3].xxxx, CONST[13].yyyy
>131:   ADD_SAT TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx
>132:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
>133:   ADD TEMP[10].x, TEMP[11].xxxx, -CONST[13].zzzz
>134:   MUL TEMP[10].x, -CONST[13].xxxx, TEMP[10].xxxx
>135:   MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].yyyy
>136:   EX2 TEMP[10].x, TEMP[10].xxxx
>137:   ADD_SAT TEMP[10].x, IMM[0].wwww, -TEMP[10].xxxx
>138:   MUL TEMP[12].x, TEMP[10].xxxx, TEMP[3].xxxx
>139: ENDIF
>140: MOV TEMP[2].w, TEMP[12].xxxx
>141: MOV TEMP[3].xyz, TEMP[9].xyzx
>142: MOV TEMP[3].w, TEMP[8].xxxx
>143: MOV TEMP[8].xy, TEMP[8].yzyy
>144: MOV TEMP[8].zw, TEMP[7].yyxy
>145: MOV TEMP[7].x, TEMP[7].zzzz
>146: MOV OUT[6], TEMP[6]
>147: MOV OUT[5], TEMP[5]
>148: MOV OUT[9], TEMP[7]
>149: MOV OUT[3], TEMP[4]
>150: MOV OUT[2], TEMP[2]
>151: MOV OUT[8], TEMP[8]
>152: MOV OUT[7], TEMP[3]
>153: MOV OUT[0], TEMP[0]
>154: MOV OUT[4], TEMP[1]
>155: MOV OUT[1], TEMP[0]
>156: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 160)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 164)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 188)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 192)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 196)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 200)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 204)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 208)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 212)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 216)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 220)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 224)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 228)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 232)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 236)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 240)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 244)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 248)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 252)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 256)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 260)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 264)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 268)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 272)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 276)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 280)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 284)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 288)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 292)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 296)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 300)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 304)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 308)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 312)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 316)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 320)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 324)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 328)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 332)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 336)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 340)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 344)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 348)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 352)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 356)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 360)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %10, i32 364)
>  %95 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
>  %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %5)
>  %98 = extractelement <4 x float> %97, i32 0
>  %99 = extractelement <4 x float> %97, i32 1
>  %100 = extractelement <4 x float> %97, i32 2
>  %101 = extractelement <4 x float> %97, i32 3
>  %102 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
>  %104 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %103, i32 0, i32 %5)
>  %105 = extractelement <4 x float> %104, i32 0
>  %106 = extractelement <4 x float> %104, i32 1
>  %107 = extractelement <4 x float> %104, i32 2
>  %108 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %109 = load <16 x i8> addrspace(2)* %108, !tbaa !0
>  %110 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %109, i32 0, i32 %5)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 1
>  %113 = extractelement <4 x float> %110, i32 2
>  %114 = extractelement <4 x float> %110, i32 3
>  %115 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %116 = load <16 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %116, i32 0, i32 %5)
>  %118 = extractelement <4 x float> %117, i32 0
>  %119 = extractelement <4 x float> %117, i32 1
>  %120 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %121 = load <16 x i8> addrspace(2)* %120, !tbaa !0
>  %122 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %121, i32 0, i32 %5)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = extractelement <4 x float> %122, i32 1
>  %125 = extractelement <4 x float> %122, i32 2
>  %126 = extractelement <4 x float> %122, i32 3
>  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
>  %130 = extractelement <4 x float> %129, i32 0
>  %131 = extractelement <4 x float> %129, i32 1
>  %132 = extractelement <4 x float> %129, i32 2
>  %133 = extractelement <4 x float> %129, i32 3
>  %134 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
>  %136 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %135, i32 0, i32 %5)
>  %137 = extractelement <4 x float> %136, i32 0
>  %138 = extractelement <4 x float> %136, i32 1
>  %139 = extractelement <4 x float> %136, i32 2
>  %140 = extractelement <4 x float> %136, i32 3
>  %141 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %142 = load <16 x i8> addrspace(2)* %141, !tbaa !0
>  %143 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %142, i32 0, i32 %5)
>  %144 = extractelement <4 x float> %143, i32 0
>  %145 = extractelement <4 x float> %143, i32 1
>  %146 = extractelement <4 x float> %143, i32 2
>  %147 = extractelement <4 x float> %143, i32 3
>  %148 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %149 = load <16 x i8> addrspace(2)* %148, !tbaa !0
>  %150 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %149, i32 0, i32 %5)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = fmul float %98, %11
>  %154 = fmul float %99, %12
>  %155 = fadd float %153, %154
>  %156 = fmul float %100, %13
>  %157 = fadd float %155, %156
>  %158 = fmul float %101, %14
>  %159 = fadd float %157, %158
>  %160 = fmul float %98, %15
>  %161 = fmul float %99, %16
>  %162 = fadd float %160, %161
>  %163 = fmul float %100, %17
>  %164 = fadd float %162, %163
>  %165 = fmul float %101, %18
>  %166 = fadd float %164, %165
>  %167 = fmul float %98, %19
>  %168 = fmul float %99, %20
>  %169 = fadd float %167, %168
>  %170 = fmul float %100, %21
>  %171 = fadd float %169, %170
>  %172 = fmul float %101, %22
>  %173 = fadd float %171, %172
>  %174 = fmul float %98, %23
>  %175 = fmul float %99, %24
>  %176 = fadd float %174, %175
>  %177 = fmul float %100, %25
>  %178 = fadd float %176, %177
>  %179 = fmul float %101, %26
>  %180 = fadd float %178, %179
>  %181 = fmul float %159, 5.000000e-01
>  %182 = fmul float %166, 5.000000e-01
>  %183 = fmul float %180, 5.000000e-01
>  %184 = fadd float %183, %181
>  %185 = fmul float %180, 5.000000e-01
>  %186 = fadd float %185, %182
>  %187 = fmul float %98, %27
>  %188 = fmul float %99, %28
>  %189 = fadd float %187, %188
>  %190 = fmul float %100, %29
>  %191 = fadd float %189, %190
>  %192 = fmul float %101, %30
>  %193 = fadd float %191, %192
>  %194 = fmul float %98, %31
>  %195 = fmul float %99, %32
>  %196 = fadd float %194, %195
>  %197 = fmul float %100, %33
>  %198 = fadd float %196, %197
>  %199 = fmul float %101, %34
>  %200 = fadd float %198, %199
>  %201 = fmul float %98, %35
>  %202 = fmul float %99, %36
>  %203 = fadd float %201, %202
>  %204 = fmul float %100, %37
>  %205 = fadd float %203, %204
>  %206 = fmul float %101, %38
>  %207 = fadd float %205, %206
>  %208 = fmul float %123, %59
>  %209 = fmul float %124, %60
>  %210 = fadd float %208, %209
>  %211 = fmul float %125, %61
>  %212 = fadd float %210, %211
>  %213 = fmul float %126, %62
>  %214 = fadd float %212, %213
>  %215 = fmul float %123, %63
>  %216 = fmul float %124, %64
>  %217 = fadd float %215, %216
>  %218 = fmul float %125, %65
>  %219 = fadd float %217, %218
>  %220 = fmul float %126, %66
>  %221 = fadd float %219, %220
>  %222 = fmul float %130, %67
>  %223 = fmul float %131, %68
>  %224 = fadd float %222, %223
>  %225 = fmul float %132, %69
>  %226 = fadd float %224, %225
>  %227 = fmul float %133, %70
>  %228 = fadd float %226, %227
>  %229 = fmul float %130, %71
>  %230 = fmul float %131, %72
>  %231 = fadd float %229, %230
>  %232 = fmul float %132, %73
>  %233 = fadd float %231, %232
>  %234 = fmul float %133, %74
>  %235 = fadd float %233, %234
>  %236 = fmul float %137, %75
>  %237 = fmul float %138, %76
>  %238 = fadd float %236, %237
>  %239 = fmul float %139, %77
>  %240 = fadd float %238, %239
>  %241 = fmul float %140, %78
>  %242 = fadd float %240, %241
>  %243 = fmul float %137, %79
>  %244 = fmul float %138, %80
>  %245 = fadd float %243, %244
>  %246 = fmul float %139, %81
>  %247 = fadd float %245, %246
>  %248 = fmul float %140, %82
>  %249 = fadd float %247, %248
>  %250 = fmul float %144, %83
>  %251 = fmul float %145, %84
>  %252 = fadd float %250, %251
>  %253 = fmul float %146, %85
>  %254 = fadd float %252, %253
>  %255 = fmul float %147, %86
>  %256 = fadd float %254, %255
>  %257 = fmul float %144, %87
>  %258 = fmul float %145, %88
>  %259 = fadd float %257, %258
>  %260 = fmul float %146, %89
>  %261 = fadd float %259, %260
>  %262 = fmul float %147, %90
>  %263 = fadd float %261, %262
>  %264 = fmul float %118, %39
>  %265 = fadd float %264, %40
>  %266 = fmul float %119, %39
>  %267 = fadd float %266, %40
>  %268 = fmul float %105, %91
>  %269 = fadd float %268, %92
>  %270 = fmul float %106, %91
>  %271 = fadd float %270, %92
>  %272 = fmul float %107, %91
>  %273 = fadd float %272, %92
>  %274 = fadd float %271, 0x3F50624DE0000000
>  %275 = fmul float %111, %93
>  %276 = fadd float %275, %94
>  %277 = fmul float %112, %93
>  %278 = fadd float %277, %94
>  %279 = fmul float %113, %93
>  %280 = fadd float %279, %94
>  %281 = fmul float %114, %93
>  %282 = fadd float %281, %94
>  %283 = fadd float %276, 0x3F50624DE0000000
>  %284 = fmul float %269, %282
>  %285 = fmul float %274, %282
>  %286 = fmul float %273, %282
>  %287 = fmul float %286, %278
>  %288 = fmul float %284, %280
>  %289 = fmul float %285, %283
>  %290 = fsub float -0.000000e+00, %287
>  %291 = fmul float %285, %280
>  %292 = fadd float %291, %290
>  %293 = fsub float -0.000000e+00, %288
>  %294 = fmul float %286, %283
>  %295 = fadd float %294, %293
>  %296 = fsub float -0.000000e+00, %289
>  %297 = fmul float %284, %278
>  %298 = fadd float %297, %296
>  %299 = fmul float %27, %27
>  %300 = fmul float %31, %31
>  %301 = fadd float %300, %299
>  %302 = fmul float %35, %35
>  %303 = fadd float %301, %302
>  %304 = fdiv float 1.000000e+00, %303
>  %305 = fmul float %27, %304
>  %306 = fmul float %31, %304
>  %307 = fmul float %35, %304
>  %308 = fmul float %28, %28
>  %309 = fmul float %32, %32
>  %310 = fadd float %309, %308
>  %311 = fmul float %36, %36
>  %312 = fadd float %310, %311
>  %313 = fdiv float 1.000000e+00, %312
>  %314 = fmul float %28, %313
>  %315 = fmul float %32, %313
>  %316 = fmul float %36, %313
>  %317 = fmul float %29, %29
>  %318 = fmul float %33, %33
>  %319 = fadd float %318, %317
>  %320 = fmul float %37, %37
>  %321 = fadd float %319, %320
>  %322 = fdiv float 1.000000e+00, %321
>  %323 = fmul float %29, %322
>  %324 = fmul float %33, %322
>  %325 = fmul float %37, %322
>  %326 = fmul float %305, %283
>  %327 = fmul float %306, %283
>  %328 = fmul float %307, %283
>  %329 = fmul float %314, %278
>  %330 = fadd float %329, %326
>  %331 = fmul float %315, %278
>  %332 = fadd float %331, %327
>  %333 = fmul float %316, %278
>  %334 = fadd float %333, %328
>  %335 = fmul float %323, %280
>  %336 = fadd float %335, %330
>  %337 = fmul float %324, %280
>  %338 = fadd float %337, %332
>  %339 = fmul float %325, %280
>  %340 = fadd float %339, %334
>  %341 = fmul float %305, %292
>  %342 = fmul float %306, %292
>  %343 = fmul float %307, %292
>  %344 = fmul float %314, %295
>  %345 = fadd float %344, %341
>  %346 = fmul float %315, %295
>  %347 = fadd float %346, %342
>  %348 = fmul float %316, %295
>  %349 = fadd float %348, %343
>  %350 = fmul float %323, %298
>  %351 = fadd float %350, %345
>  %352 = fmul float %324, %298
>  %353 = fadd float %352, %347
>  %354 = fmul float %325, %298
>  %355 = fadd float %354, %349
>  %356 = fmul float %305, %269
>  %357 = fmul float %306, %269
>  %358 = fmul float %307, %269
>  %359 = fmul float %314, %274
>  %360 = fadd float %359, %356
>  %361 = fmul float %315, %274
>  %362 = fadd float %361, %357
>  %363 = fmul float %316, %274
>  %364 = fadd float %363, %358
>  %365 = fmul float %323, %273
>  %366 = fadd float %365, %360
>  %367 = fmul float %324, %273
>  %368 = fadd float %367, %362
>  %369 = fmul float %325, %273
>  %370 = fadd float %369, %364
>  %371 = fmul float %336, %336
>  %372 = fmul float %338, %338
>  %373 = fadd float %372, %371
>  %374 = fmul float %340, %340
>  %375 = fadd float %373, %374
>  %376 = call float @llvm.AMDGPU.rsq(float %375)
>  %377 = fmul float %336, %376
>  %378 = fmul float %338, %376
>  %379 = fmul float %340, %376
>  %380 = fmul float %351, %351
>  %381 = fmul float %353, %353
>  %382 = fadd float %381, %380
>  %383 = fmul float %355, %355
>  %384 = fadd float %382, %383
>  %385 = call float @llvm.AMDGPU.rsq(float %384)
>  %386 = fmul float %351, %385
>  %387 = fmul float %353, %385
>  %388 = fmul float %355, %385
>  %389 = fmul float %366, %366
>  %390 = fmul float %368, %368
>  %391 = fadd float %390, %389
>  %392 = fmul float %370, %370
>  %393 = fadd float %391, %392
>  %394 = call float @llvm.AMDGPU.rsq(float %393)
>  %395 = fmul float %366, %394
>  %396 = fmul float %368, %394
>  %397 = fmul float %370, %394
>  %398 = fsub float -0.000000e+00, %41
>  %399 = fadd float %193, %398
>  %400 = fsub float -0.000000e+00, %42
>  %401 = fadd float %200, %400
>  %402 = fsub float -0.000000e+00, %43
>  %403 = fadd float %207, %402
>  %404 = fmul float %399, %399
>  %405 = fmul float %401, %401
>  %406 = fadd float %405, %404
>  %407 = fmul float %403, %403
>  %408 = fadd float %406, %407
>  %409 = call float @llvm.AMDGPU.rsq(float %408)
>  %410 = fmul float %409, %408
>  %411 = fsub float -0.000000e+00, %408
>  %412 = call float @llvm.AMDGPU.cndlt(float %411, float %410, float 0.000000e+00)
>  %413 = fcmp ult float 0.000000e+00, %45
>  %414 = select i1 %413, float 1.000000e+00, float 0.000000e+00
>  %415 = fsub float -0.000000e+00, %414
>  %416 = fptosi float %415 to i32
>  %417 = bitcast i32 %416 to float
>  %418 = bitcast float %417 to i32
>  %419 = icmp ne i32 %418, 0
>  br i1 %419, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %420 = fmul float %193, %51
>  %421 = fmul float %200, %52
>  %422 = fadd float %420, %421
>  %423 = fmul float %207, %53
>  %424 = fadd float %422, %423
>  %425 = fmul float 1.000000e+00, %54
>  %426 = fadd float %424, %425
>  %427 = fmul float %41, %51
>  %428 = fmul float %42, %52
>  %429 = fadd float %427, %428
>  %430 = fmul float %43, %53
>  %431 = fadd float %429, %430
>  %432 = fmul float %44, %54
>  %433 = fadd float %431, %432
>  %434 = fsub float -0.000000e+00, %433
>  %435 = fadd float %426, %434
>  %436 = fcmp uge float %435, 0.000000e+00
>  %437 = select i1 %436, float 1.000000e+00, float 0.000000e+00
>  %438 = fsub float -0.000000e+00, %437
>  %439 = fptosi float %438 to i32
>  %440 = bitcast i32 %439 to float
>  %441 = bitcast float %440 to i32
>  %442 = icmp ne i32 %441, 0
>  %. = select i1 %442, float %433, float %426
>  %.70 = select i1 %442, float %426, float %433
>  %443 = fsub float -0.000000e+00, %47
>  %444 = fadd float %., %443
>  %445 = fsub float -0.000000e+00, %47
>  %446 = fadd float %.70, %445
>  %447 = fsub float -0.000000e+00, %444
>  %448 = fadd float %49, %447
>  %449 = fsub float -0.000000e+00, %444
>  %450 = fadd float %50, %449
>  %451 = call float @fabs(float %435)
>  %452 = fadd float %451, 0x3F50624DE0000000
>  %453 = fdiv float 1.000000e+00, %452
>  %454 = fmul float %448, %453
>  %455 = fmul float %450, %453
>  %456 = call float @llvm.AMDIL.clamp.(float %454, float 0.000000e+00, float 1.000000e+00)
>  %457 = call float @llvm.AMDIL.clamp.(float %455, float 0.000000e+00, float 1.000000e+00)
>  %458 = fmul float %444, %46
>  %459 = fmul float %446, %46
>  %460 = fsub float -0.000000e+00, %458
>  %461 = fadd float 1.000000e+00, %460
>  %462 = fsub float -0.000000e+00, %459
>  %463 = fadd float 1.000000e+00, %462
>  %464 = call float @llvm.AMDIL.clamp.(float %461, float 0.000000e+00, float 1.000000e+00)
>  %465 = call float @llvm.AMDIL.clamp.(float %463, float 0.000000e+00, float 1.000000e+00)
>  %466 = fmul float %412, %45
>  %467 = fsub float -0.000000e+00, %457
>  %468 = fadd float %456, %467
>  %469 = call float @llvm.AMDIL.clamp.(float %468, float 0.000000e+00, float 1.000000e+00)
>  %470 = fadd float %464, %465
>  %471 = fmul float %470, %48
>  %472 = call float @llvm.AMDIL.clamp.(float %471, float 0.000000e+00, float 1.000000e+00)
>  %473 = fmul float %469, %472
>  %474 = fmul float %466, %473
>  %475 = call float @llvm.AMDIL.clamp.(float %474, float 0.000000e+00, float 1.000000e+00)
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp12.0 = phi float [ %475, %IF ], [ 0.000000e+00, %main_body ]
>  %476 = fcmp ult float 0.000000e+00, %55
>  %477 = select i1 %476, float 1.000000e+00, float 0.000000e+00
>  %478 = fsub float -0.000000e+00, %477
>  %479 = fptosi float %478 to i32
>  %480 = bitcast i32 %479 to float
>  %481 = bitcast float %480 to i32
>  %482 = icmp ne i32 %481, 0
>  br i1 %482, label %IF68, label %ENDIF67
>
>IF68:                                             ; preds = %ENDIF
>  %483 = fmul float %412, 0x3F1D745260000000
>  %484 = call float @llvm.AMDIL.clamp.(float %483, float 0.000000e+00, float 1.000000e+00)
>  %485 = fmul float %58, %484
>  %486 = fsub float -0.000000e+00, %485
>  %487 = fadd float 1.000000e+00, %486
>  %488 = fmul float %401, %487
>  %489 = fmul float %488, %56
>  %490 = fsub float -0.000000e+00, %489
>  %491 = fadd float 1.000000e+00, %490
>  %492 = call float @llvm.AMDIL.clamp.(float %491, float 0.000000e+00, float 1.000000e+00)
>  %493 = fmul float %492, %492
>  %494 = fsub float -0.000000e+00, %57
>  %495 = fadd float %412, %494
>  %496 = fsub float -0.000000e+00, %55
>  %497 = fmul float %496, %495
>  %498 = fmul float %497, 0x3FF7154760000000
>  %499 = call float @llvm.AMDIL.exp.(float %498)
>  %500 = fsub float -0.000000e+00, %499
>  %501 = fadd float 1.000000e+00, %500
>  %502 = call float @llvm.AMDIL.clamp.(float %501, float 0.000000e+00, float 1.000000e+00)
>  %503 = fmul float %502, %493
>  br label %ENDIF67
>
>ENDIF67:                                          ; preds = %ENDIF, %IF68
>  %temp48.0 = phi float [ %503, %IF68 ], [ 0.000000e+00, %ENDIF ]
>  %504 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %505 = load <16 x i8> addrspace(2)* %504, !tbaa !0
>  %506 = call float @llvm.SI.load.const(<16 x i8> %505, i32 0)
>  %507 = fmul float %506, %159
>  %508 = call float @llvm.SI.load.const(<16 x i8> %505, i32 4)
>  %509 = fmul float %508, %166
>  %510 = fadd float %507, %509
>  %511 = call float @llvm.SI.load.const(<16 x i8> %505, i32 8)
>  %512 = fmul float %511, %173
>  %513 = fadd float %510, %512
>  %514 = call float @llvm.SI.load.const(<16 x i8> %505, i32 12)
>  %515 = fmul float %514, %180
>  %516 = fadd float %513, %515
>  %517 = call float @llvm.SI.load.const(<16 x i8> %505, i32 16)
>  %518 = fmul float %517, %159
>  %519 = call float @llvm.SI.load.const(<16 x i8> %505, i32 20)
>  %520 = fmul float %519, %166
>  %521 = fadd float %518, %520
>  %522 = call float @llvm.SI.load.const(<16 x i8> %505, i32 24)
>  %523 = fmul float %522, %173
>  %524 = fadd float %521, %523
>  %525 = call float @llvm.SI.load.const(<16 x i8> %505, i32 28)
>  %526 = fmul float %525, %180
>  %527 = fadd float %524, %526
>  %528 = call float @llvm.SI.load.const(<16 x i8> %505, i32 32)
>  %529 = fmul float %528, %159
>  %530 = call float @llvm.SI.load.const(<16 x i8> %505, i32 36)
>  %531 = fmul float %530, %166
>  %532 = fadd float %529, %531
>  %533 = call float @llvm.SI.load.const(<16 x i8> %505, i32 40)
>  %534 = fmul float %533, %173
>  %535 = fadd float %532, %534
>  %536 = call float @llvm.SI.load.const(<16 x i8> %505, i32 44)
>  %537 = fmul float %536, %180
>  %538 = fadd float %535, %537
>  %539 = call float @llvm.SI.load.const(<16 x i8> %505, i32 48)
>  %540 = fmul float %539, %159
>  %541 = call float @llvm.SI.load.const(<16 x i8> %505, i32 52)
>  %542 = fmul float %541, %166
>  %543 = fadd float %540, %542
>  %544 = call float @llvm.SI.load.const(<16 x i8> %505, i32 56)
>  %545 = fmul float %544, %173
>  %546 = fadd float %543, %545
>  %547 = call float @llvm.SI.load.const(<16 x i8> %505, i32 60)
>  %548 = fmul float %547, %180
>  %549 = fadd float %546, %548
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %516, float %527, float %538, float %549)
>  %550 = call float @llvm.SI.load.const(<16 x i8> %505, i32 64)
>  %551 = fmul float %550, %159
>  %552 = call float @llvm.SI.load.const(<16 x i8> %505, i32 68)
>  %553 = fmul float %552, %166
>  %554 = fadd float %551, %553
>  %555 = call float @llvm.SI.load.const(<16 x i8> %505, i32 72)
>  %556 = fmul float %555, %173
>  %557 = fadd float %554, %556
>  %558 = call float @llvm.SI.load.const(<16 x i8> %505, i32 76)
>  %559 = fmul float %558, %180
>  %560 = fadd float %557, %559
>  %561 = call float @llvm.SI.load.const(<16 x i8> %505, i32 80)
>  %562 = fmul float %561, %159
>  %563 = call float @llvm.SI.load.const(<16 x i8> %505, i32 84)
>  %564 = fmul float %563, %166
>  %565 = fadd float %562, %564
>  %566 = call float @llvm.SI.load.const(<16 x i8> %505, i32 88)
>  %567 = fmul float %566, %173
>  %568 = fadd float %565, %567
>  %569 = call float @llvm.SI.load.const(<16 x i8> %505, i32 92)
>  %570 = fmul float %569, %180
>  %571 = fadd float %568, %570
>  %572 = call float @llvm.SI.load.const(<16 x i8> %505, i32 96)
>  %573 = fmul float %572, %159
>  %574 = call float @llvm.SI.load.const(<16 x i8> %505, i32 100)
>  %575 = fmul float %574, %166
>  %576 = fadd float %573, %575
>  %577 = call float @llvm.SI.load.const(<16 x i8> %505, i32 104)
>  %578 = fmul float %577, %173
>  %579 = fadd float %576, %578
>  %580 = call float @llvm.SI.load.const(<16 x i8> %505, i32 108)
>  %581 = fmul float %580, %180
>  %582 = fadd float %579, %581
>  %583 = call float @llvm.SI.load.const(<16 x i8> %505, i32 112)
>  %584 = fmul float %583, %159
>  %585 = call float @llvm.SI.load.const(<16 x i8> %505, i32 116)
>  %586 = fmul float %585, %166
>  %587 = fadd float %584, %586
>  %588 = call float @llvm.SI.load.const(<16 x i8> %505, i32 120)
>  %589 = fmul float %588, %173
>  %590 = fadd float %587, %589
>  %591 = call float @llvm.SI.load.const(<16 x i8> %505, i32 124)
>  %592 = fmul float %591, %180
>  %593 = fadd float %590, %592
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %560, float %571, float %582, float %593)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %184, float %186, float %temp12.0, float %temp48.0)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %193, float %200, float %207, float %180)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %214, float %221, float %228, float %235)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %242, float %249, float %256, float %263)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %151, float %152, float %265, float %267)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %377, float %378, float %379, float %386)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %387, float %388, float %395, float %396)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %397, float %396, float %397, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %159, float %166, float %173, float %180)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: readonly
>declare float @fabs(float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
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>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], POSITION, LINEAR
>DCL IN[1], FACE, CONSTANT
>DCL IN[2], GENERIC[19], PERSPECTIVE
>DCL IN[3], GENERIC[20], PERSPECTIVE
>DCL IN[4], GENERIC[21], PERSPECTIVE
>DCL IN[5], GENERIC[22], PERSPECTIVE
>DCL IN[6], GENERIC[23], PERSPECTIVE
>DCL IN[7], GENERIC[24], PERSPECTIVE
>DCL IN[8], GENERIC[25], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL SAMP[6]
>DCL SAMP[7]
>DCL SAMP[8]
>DCL CONST[54]
>DCL CONST[0..44]
>DCL TEMP[0..1]
>DCL TEMP[2..22], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,    -1.0000,     4.5948}
>IMM[1] FLT32 {   32.0000,   -16.0000,     0.5000,     4.0000}
>IMM[2] FLT32 {    2.0000,    -0.0010,     0.0000,     0.0000}
>IMM[3] FLT32 {    0.0000,     0.0100,     0.2500,     3.0000}
>IMM[4] FLT32 {65504.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0], IN[0]
>  1: MAD TEMP[0].y, IN[0], CONST[54].xxxx, CONST[54].yyyy
>  2: MOV_SAT TEMP[1], IN[1]
>  3: MOV TEMP[2].yz, IN[8].yxyy
>  4: MOV TEMP[2].x, IN[7].wwww
>  5: UIF TEMP[1].xxxx :3
>  6:   MOV TEMP[3].x, IMM[0].zzzz
>  7: ELSE :3
>  8:   MOV TEMP[3].x, IMM[0].yyyy
>  9: ENDIF
> 10: ADD TEMP[4].xyz, CONST[11].xyzz, -IN[2].xyzz
> 11: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
> 12: RSQ TEMP[5].x, TEMP[5].xxxx
> 13: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 14: MUL TEMP[5].x, TEMP[3].xxxx, CONST[14].wwww
> 15: MUL TEMP[6].xy, TEMP[0].xyyy, CONST[12].xyyy
> 16: MOV TEMP[7].xy, IN[4].zwww
> 17: TEX TEMP[7], TEMP[7], SAMP[2], 2D
> 18: MOV TEMP[8].w, TEMP[7].wwww
> 19: MUL TEMP[8].xyz, TEMP[7].xyzz, IMM[0].wwww
> 20: LRP TEMP[8].xyz, CONST[1].wwww, TEMP[8].xyzz, IMM[0].yyyy
> 21: MOV TEMP[9].xy, IN[5].xyyy
> 22: TEX TEMP[9], TEMP[9], SAMP[4], 2D
> 23: MOV TEMP[10].xyz, TEMP[9]
> 24: MOV TEMP[11].xy, IN[3].xyyy
> 25: TEX TEMP[11], TEMP[11], SAMP[3], 2D
> 26: MUL TEMP[12], TEMP[11], CONST[0]
> 27: MUL TEMP[12], TEMP[12], IN[6]
> 28: MOV TEMP[13].w, TEMP[12].wwww
> 29: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].wwww
> 30: MUL TEMP[14].x, TEMP[14].xxxx, CONST[12].zzzz
> 31: LRP TEMP[13].xyz, TEMP[14].xxxx, TEMP[11].xyzz, TEMP[12].xyzz
> 32: MOV TEMP[11].xy, IN[3].zwww
> 33: TEX TEMP[11].xyw, TEMP[11], SAMP[5], 2D
> 34: MUL TEMP[12].xy, CONST[14].xyyy, TEMP[11].wxxx
> 35: ADD TEMP[12].xy, IMM[0].yyyy, -TEMP[12].xyyy
> 36: MUL TEMP[13], TEMP[13], TEMP[8]
> 37: DP3 TEMP[8].x, IN[7].xyzz, IN[7].xyzz
> 38: RSQ TEMP[8].x, TEMP[8].xxxx
> 39: MUL TEMP[8].xyz, IN[7].xyzz, TEMP[8].xxxx
> 40: SLT TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
> 41: F2I TEMP[5].x, -TEMP[5]
> 42: UIF TEMP[5].xxxx :3
> 43:   MOV TEMP[5].xyz, -TEMP[8].xyzx
> 44: ELSE :3
> 45:   MOV TEMP[5].xyz, TEMP[8].xyzx
> 46: ENDIF
> 47: MOV TEMP[8].w, TEMP[13].wwww
> 48: MOV TEMP[6].xy, TEMP[6].xyyy
> 49: TEX TEMP[6], TEMP[6], SAMP[8], 2D
> 50: MAD TEMP[3], TEMP[6], CONST[10].xxxz, CONST[10].yyyw
> 51: MOV TEMP[6].xy, IN[4].xyyy
> 52: TEX TEMP[6], TEMP[6], SAMP[6], 2D
> 53: MAD TEMP[14].x, TEMP[6].wwww, IMM[1].xxxx, IMM[1].yyyy
> 54: EX2 TEMP[14].x, TEMP[14].xxxx
> 55: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[14].xxxx
> 56: MAD TEMP[2].xyz, CONST[3].xyzz, TEMP[6].xyzz, TEMP[2].xyzz
> 57: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].wwww
> 58: MAD TEMP[6].x, TEMP[3].wwww, IMM[1].zzzz, IMM[1].zzzz
> 59: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[4].xyzz
> 60: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[14].xxxx
> 61: POW TEMP[14].x, TEMP[14].xxxx, IMM[1].wwww
> 62: MUL TEMP[14].x, TEMP[14].xxxx, CONST[3].wwww
> 63: MUL TEMP[15].xy, TEMP[12].xyyy, TEMP[14].xxxx
> 64: ADD TEMP[15].y, TEMP[12].xyyy, -TEMP[15].xyyy
> 65: DP3 TEMP[16].x, TEMP[5].xyzz, TEMP[4].xyzz
> 66: MUL TEMP[16].xyz, TEMP[16].xxxx, TEMP[5].xyzz
> 67: MUL TEMP[16].xyz, IMM[2].xxxx, TEMP[16].xyzz
> 68: ADD TEMP[16].xyz, TEMP[4].xyzz, -TEMP[16].xyzz
> 69: LRP TEMP[17].xyz, TEMP[15].yyyy, -TEMP[5].xyzz, TEMP[16].xyzz
> 70: ABS TEMP[18].xyz, TEMP[17].xyzz
> 71: MAX TEMP[19].x, TEMP[18].yyyy, TEMP[18].zzzz
> 72: MAX TEMP[19].x, TEMP[18].xxxx, TEMP[19].xxxx
> 73: ADD TEMP[20].x, TEMP[19].xxxx, IMM[2].yyyy
> 74: SGE TEMP[21].x, TEMP[20].xxxx, TEMP[18].xxxx
> 75: F2I TEMP[21].x, -TEMP[21]
> 76: AND TEMP[21].x, TEMP[21].xxxx, IMM[0].yyyy
> 77: SGE TEMP[22].x, TEMP[20].xxxx, TEMP[18].yyyy
> 78: F2I TEMP[22].x, -TEMP[22]
> 79: AND TEMP[22].x, TEMP[22].xxxx, IMM[0].yyyy
> 80: MOV TEMP[21].y, TEMP[22].xxxx
> 81: SGE TEMP[18].x, TEMP[20].xxxx, TEMP[18].zzzz
> 82: F2I TEMP[18].x, -TEMP[18]
> 83: AND TEMP[18].x, TEMP[18].xxxx, IMM[0].yyyy
> 84: MOV TEMP[21].z, TEMP[18].xxxx
> 85: RCP TEMP[18].x, TEMP[19].xxxx
> 86: MUL TEMP[18].xyz, IMM[0].zzyy, TEMP[18].xxxx
> 87: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[18].xyzz
> 88: ADD TEMP[17].x, CONST[14].zzzz, IMM[0].zzzz
> 89: MUL TEMP[17].x, TEMP[15].yyyy, TEMP[17].xxxx
> 90: MUL TEMP[18].xyz, TEMP[16].xyzz, TEMP[21].xyzz
> 91: FLR TEMP[19].x, TEMP[17].xxxx
> 92: ADD TEMP[19].x, CONST[14].zzzz, -TEMP[19].xxxx
> 93: EX2 TEMP[19].x, TEMP[19].xxxx
> 94: RCP TEMP[19].x, TEMP[19].xxxx
> 95: MUL TEMP[18].xyz, TEMP[18].xyzz, TEMP[19].xxxx
> 96: ADD TEMP[16].xyz, TEMP[16].xyzz, -TEMP[18].xyzz
> 97: MOV TEMP[16].xyz, TEMP[16].xyzz
> 98: MOV TEMP[16].w, TEMP[17].xxxx
> 99: TXL TEMP[16], TEMP[16], SAMP[7], CUBE
>100: MAD TEMP[17].x, TEMP[16].wwww, IMM[1].xxxx, IMM[1].yyyy
>101: EX2 TEMP[17].x, TEMP[17].xxxx
>102: MUL TEMP[16].xyz, TEMP[16].xyzz, TEMP[17].xxxx
>103: MUL TEMP[17].xyz, CONST[1].xyzz, TEMP[11].yyyy
>104: MUL TEMP[17].xyz, TEMP[17].xyzz, TEMP[11].yyyy
>105: MAD_SAT TEMP[15].x, TEMP[15].yyyy, IMM[2].xxxx, IMM[0].zzzz
>106: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[6].xxxx
>107: MUL TEMP[16].xyz, TEMP[16].xyzz, CONST[2].xyzz
>108: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[16].xyzz
>109: LRP TEMP[15].xyz, TEMP[15].xxxx, TEMP[17].xyzz, TEMP[16].xyzz
>110: LRP TEMP[14].xyz, TEMP[14].xxxx, IMM[0].yyyy, TEMP[17].xyzz
>111: LRP TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xyzz, TEMP[13].xyzz
>112: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[14].xyzz
>113: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[13].xyzz, TEMP[2].xyzz
>114: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[30].xyzz
>115: DP3 TEMP[14].x, TEMP[3].xyzz, TEMP[3].xyzz
>116: RSQ TEMP[14].x, TEMP[14].xxxx
>117: MUL TEMP[15].x, CONST[31].wwww, TEMP[14].xxxx
>118: RCP TEMP[15].x, TEMP[15].xxxx
>119: MOV_SAT TEMP[15].x, TEMP[15].xxxx
>120: ADD TEMP[15].x, IMM[0].yyyy, -TEMP[15].xxxx
>121: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
>122: MUL TEMP[3].xyz, -TEMP[3].xyzz, TEMP[14].xxxx
>123: DP3 TEMP[14].x, TEMP[3].xyzz, -CONST[31].xyzz
>124: MUL TEMP[14].x, TEMP[14].xxxx, CONST[29].wwww
>125: ADD_SAT TEMP[14].x, CONST[30].wwww, -TEMP[14].xxxx
>126: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
>127: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[3].xyzz
>128: ADD TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xyzz
>129: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[3].xyzz
>130: RSQ TEMP[16].x, TEMP[16].xxxx
>131: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[16].xxxx
>132: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[5].xyzz
>133: DDX TEMP[17].x, TEMP[16].xxxx
>134: ABS TEMP[17].x, TEMP[17].xxxx
>135: MUL TEMP[19], CONST[54].xxxx, TEMP[16].xxxx
>136: DDY TEMP[18].x, TEMP[19]
>137: ABS TEMP[18].x, TEMP[18].xxxx
>138: ADD TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
>139: MAD TEMP[17].x, TEMP[17].xxxx, IMM[1].zzzz, IMM[2].zzzz
>140: MAD_SAT TEMP[16].xy, TEMP[17].xxxx, IMM[0].zyyy, TEMP[16].xxxx
>141: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[4].xyzz
>142: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
>143: POW TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
>144: MUL TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww
>145: MUL TEMP[3].xy, TEMP[12].xyyy, TEMP[3].xxxx
>146: ADD TEMP[3].xy, TEMP[12].xyyy, -TEMP[3].xyyy
>147: POW TEMP[12].x, TEMP[3].xxxx, IMM[1].wwww
>148: POW TEMP[12].y, TEMP[3].yyyy, IMM[1].wwww
>149: ADD_SAT TEMP[3].xy, TEMP[12].xyyy, IMM[2].wwww
>150: MUL TEMP[12], TEMP[16].xyxy, TEMP[3].xxyy
>151: ADD TEMP[17], TEMP[3].xxyy, IMM[0].zzzz
>152: MAD TEMP[17], TEMP[16].xyxy, TEMP[17], IMM[0].yyyy
>153: RCP TEMP[18].x, TEMP[17].xxxx
>154: RCP TEMP[18].y, TEMP[17].yyyy
>155: RCP TEMP[18].z, TEMP[17].zzzz
>156: RCP TEMP[18].w, TEMP[17].wwww
>157: MUL_SAT TEMP[12], TEMP[12], TEMP[18]
>158: ADD TEMP[12].xy, TEMP[12].ywww, -TEMP[12].xzzz
>159: ADD TEMP[16].x, TEMP[16].yyyy, -TEMP[16].xxxx
>160: ADD TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx
>161: DP3_SAT TEMP[17].x, TEMP[5].xyzz, TEMP[4].xyzz
>162: MUL TEMP[17].x, TEMP[17].xxxx, TEMP[14].xxxx
>163: MAX TEMP[17].x, TEMP[17].xxxx, IMM[3].yyyy
>164: RSQ TEMP[18].x, TEMP[17].xxxx
>165: MUL TEMP[18].x, TEMP[18].xxxx, TEMP[17].xxxx
>166: CMP TEMP[18].x, -TEMP[17].xxxx, TEMP[18].xxxx, IMM[0].xxxx
>167: LRP TEMP[3].xy, TEMP[3].xyyy, IMM[0].yyyy, TEMP[18].xxxx
>168: MUL TEMP[3].xy, TEMP[16].xxxx, TEMP[3].xyyy
>169: RCP TEMP[16].x, TEMP[3].xxxx
>170: RCP TEMP[16].y, TEMP[3].yyyy
>171: MUL TEMP[3].y, TEMP[12].xyyy, TEMP[16].xyyy
>172: MUL TEMP[12].xyz, CONST[1].xyzz, TEMP[11].yyyy
>173: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].yyyy
>174: LRP TEMP[3].xyz, TEMP[11].xyzz, TEMP[3].yyyy, TEMP[13].xyzz
>175: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[14].xxxx
>176: MUL TEMP[3].xyz, TEMP[3].xyzz, CONST[29].xyzz
>177: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[15].xxxx
>178: DP4 TEMP[11].x, IN[2], CONST[35]
>179: DP4 TEMP[12].x, IN[2], CONST[36]
>180: MOV TEMP[11].y, TEMP[12].xxxx
>181: DP4 TEMP[12].x, IN[2], CONST[37]
>182: DP4 TEMP[13].x, IN[2], CONST[38]
>183: RCP TEMP[13].x, TEMP[13].xxxx
>184: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx
>185: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[1].zzzz, IMM[1].zzzz
>186: MAD TEMP[13].xy, TEMP[11].xyyy, CONST[34].xyyy, CONST[34].zwww
>187: MOV TEMP[13].xy, TEMP[13].xyyy
>188: TEX TEMP[13].xyz, TEMP[13], SAMP[1], 2D
>189: MOV TEMP[11].xy, TEMP[11].xyyy
>190: MOV TEMP[11].w, IMM[0].xxxx
>191: TXL TEMP[11].xy, TEMP[11], SAMP[0], 2D
>192: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].yyyy
>193: MUL TEMP[14].x, TEMP[14].xxxx, IMM[3].zzzz
>194: ADD TEMP[14].x, TEMP[11].xxxx, -TEMP[14].xxxx
>195: ADD TEMP[12].x, TEMP[11].xxxx, -TEMP[12].xxxx
>196: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx
>197: ADD TEMP[11].x, TEMP[14].xxxx, -TEMP[11].xxxx
>198: MAX TEMP[11].x, TEMP[11].xxxx, CONST[32].xxxx
>199: MAD TEMP[14].x, TEMP[12].xxxx, TEMP[12].xxxx, TEMP[11].xxxx
>200: RCP TEMP[14].x, TEMP[14].xxxx
>201: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[14].xxxx
>202: POW TEMP[11].x, TEMP[11].xxxx, CONST[32].yyyy
>203: MAD_SAT TEMP[11].x, TEMP[11].xxxx, CONST[33].zzzz, CONST[33].wwww
>204: MUL TEMP[14].x, TEMP[11].xxxx, TEMP[11].xxxx
>205: MUL TEMP[11].x, IMM[2].xxxx, TEMP[11].xxxx
>206: ADD TEMP[11].x, IMM[3].wwww, -TEMP[11].xxxx
>207: MUL TEMP[11].x, TEMP[14].xxxx, TEMP[11].xxxx
>208: SGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
>209: F2I TEMP[12].x, -TEMP[12]
>210: UIF TEMP[12].xxxx :3
>211:   MOV TEMP[12].x, IMM[0].yyyy
>212: ELSE :3
>213:   MOV TEMP[12].x, TEMP[11].xxxx
>214: ENDIF
>215: MUL TEMP[11].xyz, TEMP[13].xyzz, TEMP[12].xxxx
>216: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[11].xyzz
>217: MAD TEMP[8].xyz, TEMP[3].xyzz, TEMP[6].xxxx, TEMP[2].xyzz
>218: LRP TEMP[2].x, TEMP[7].wwww, TEMP[9].wwww, IMM[0].yyyy
>219: MOV TEMP[10].w, TEMP[2].xxxx
>220: LRP TEMP[2], CONST[9].xxxy, TEMP[10], IMM[0].yyyy
>221: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[2].wwww
>222: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[2].xyzz
>223: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[4].xyzz
>224: ABS TEMP[2].x, TEMP[2].xxxx
>225: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
>226: MAD_SAT TEMP[2].x, TEMP[2].xxxx, CONST[13].xxxx, CONST[13].yyyy
>227: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[2].xxxx
>228: MUL TEMP[2], CONST[4].zzzw, TEMP[2].xxxx
>229: LRP TEMP[2], TEMP[2], CONST[4].xxxy, TEMP[8]
>230: MIN TEMP[3].xyz, TEMP[2].xyzz, IMM[4].xxxx
>231: MAX TEMP[8].xyz, TEMP[3].xyzz, IMM[4].yyyy
>232: MAD_SAT TEMP[2].x, TEMP[2].wwww, CONST[13].zzzz, CONST[13].wwww
>233: MOV TEMP[8].w, TEMP[2].xxxx
>234: MOV OUT[0], TEMP[8]
>235: END
>; ModuleID = 'tgsi'
>
>@ddxy_lds = external addrspace(3) global [64 x i32]
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 60)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %21, i32 144)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %21, i32 148)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %21, i32 160)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %21, i32 164)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %21, i32 168)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %21, i32 172)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %21, i32 176)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %21, i32 180)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %21, i32 184)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %21, i32 192)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %21, i32 196)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %21, i32 200)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %21, i32 208)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %21, i32 212)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %21, i32 216)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %21, i32 220)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %21, i32 224)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %21, i32 228)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %21, i32 232)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %21, i32 236)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %21, i32 464)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %21, i32 468)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %21, i32 472)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %21, i32 476)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %21, i32 480)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %21, i32 484)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %21, i32 488)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %21, i32 492)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %21, i32 496)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %21, i32 500)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %21, i32 504)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %21, i32 508)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %21, i32 512)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %21, i32 516)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %21, i32 536)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %21, i32 540)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %21, i32 544)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %21, i32 548)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %21, i32 552)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %21, i32 556)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %21, i32 560)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %21, i32 564)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %21, i32 568)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %21, i32 572)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %21, i32 576)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %21, i32 580)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %21, i32 584)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %21, i32 588)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %21, i32 592)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %21, i32 596)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %21, i32 600)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %21, i32 604)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %21, i32 608)
>  %94 = call float @llvm.SI.load.const(<16 x i8> %21, i32 612)
>  %95 = call float @llvm.SI.load.const(<16 x i8> %21, i32 616)
>  %96 = call float @llvm.SI.load.const(<16 x i8> %21, i32 620)
>  %97 = call float @llvm.SI.load.const(<16 x i8> %21, i32 864)
>  %98 = call float @llvm.SI.load.const(<16 x i8> %21, i32 868)
>  %99 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %100 = load <32 x i8> addrspace(2)* %99, !tbaa !0
>  %101 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %104 = load <32 x i8> addrspace(2)* %103, !tbaa !0
>  %105 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %106 = load <16 x i8> addrspace(2)* %105, !tbaa !0
>  %107 = getelementptr <32 x i8> addrspace(2)* %2, i32 2
>  %108 = load <32 x i8> addrspace(2)* %107, !tbaa !0
>  %109 = getelementptr <16 x i8> addrspace(2)* %1, i32 2
>  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
>  %111 = getelementptr <32 x i8> addrspace(2)* %2, i32 3
>  %112 = load <32 x i8> addrspace(2)* %111, !tbaa !0
>  %113 = getelementptr <16 x i8> addrspace(2)* %1, i32 3
>  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
>  %115 = getelementptr <32 x i8> addrspace(2)* %2, i32 4
>  %116 = load <32 x i8> addrspace(2)* %115, !tbaa !0
>  %117 = getelementptr <16 x i8> addrspace(2)* %1, i32 4
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = getelementptr <32 x i8> addrspace(2)* %2, i32 5
>  %120 = load <32 x i8> addrspace(2)* %119, !tbaa !0
>  %121 = getelementptr <16 x i8> addrspace(2)* %1, i32 5
>  %122 = load <16 x i8> addrspace(2)* %121, !tbaa !0
>  %123 = getelementptr <32 x i8> addrspace(2)* %2, i32 6
>  %124 = load <32 x i8> addrspace(2)* %123, !tbaa !0
>  %125 = getelementptr <16 x i8> addrspace(2)* %1, i32 6
>  %126 = load <16 x i8> addrspace(2)* %125, !tbaa !0
>  %127 = getelementptr <32 x i8> addrspace(2)* %2, i32 7
>  %128 = load <32 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = getelementptr <16 x i8> addrspace(2)* %1, i32 7
>  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
>  %131 = getelementptr <32 x i8> addrspace(2)* %2, i32 8
>  %132 = load <32 x i8> addrspace(2)* %131, !tbaa !0
>  %133 = getelementptr <16 x i8> addrspace(2)* %1, i32 8
>  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
>  %135 = fcmp ugt float %16, 0.000000e+00
>  %136 = select i1 %135, float 1.000000e+00, float 0.000000e+00
>  %137 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %138 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %139 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %3, <2 x i32> %5)
>  %140 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %3, <2 x i32> %5)
>  %141 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5)
>  %142 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5)
>  %143 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5)
>  %144 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %3, <2 x i32> %5)
>  %145 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %3, <2 x i32> %5)
>  %146 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %3, <2 x i32> %5)
>  %147 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %3, <2 x i32> %5)
>  %148 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %3, <2 x i32> %5)
>  %149 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %3, <2 x i32> %5)
>  %150 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %3, <2 x i32> %5)
>  %151 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %3, <2 x i32> %5)
>  %152 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %3, <2 x i32> %5)
>  %153 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %3, <2 x i32> %5)
>  %154 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %3, <2 x i32> %5)
>  %155 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %3, <2 x i32> %5)
>  %156 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %3, <2 x i32> %5)
>  %157 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %3, <2 x i32> %5)
>  %158 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %3, <2 x i32> %5)
>  %159 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %3, <2 x i32> %5)
>  %160 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %3, <2 x i32> %5)
>  %161 = fmul float %13, %97
>  %162 = fadd float %161, %98
>  %163 = call float @llvm.AMDIL.clamp.(float %136, float 0.000000e+00, float 1.000000e+00)
>  %164 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %165 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %166 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %167 = bitcast float %163 to i32
>  %168 = icmp ne i32 %167, 0
>  %. = select i1 %168, float -1.000000e+00, float 1.000000e+00
>  %169 = fsub float -0.000000e+00, %137
>  %170 = fadd float %47, %169
>  %171 = fsub float -0.000000e+00, %138
>  %172 = fadd float %48, %171
>  %173 = fsub float -0.000000e+00, %139
>  %174 = fadd float %49, %173
>  %175 = fmul float %170, %170
>  %176 = fmul float %172, %172
>  %177 = fadd float %176, %175
>  %178 = fmul float %174, %174
>  %179 = fadd float %177, %178
>  %180 = call float @llvm.AMDGPU.rsq(float %179)
>  %181 = fmul float %170, %180
>  %182 = fmul float %172, %180
>  %183 = fmul float %174, %180
>  %184 = fmul float %., %60
>  %185 = fmul float %12, %50
>  %186 = fmul float %162, %51
>  %187 = bitcast float %147 to i32
>  %188 = bitcast float %148 to i32
>  %189 = insertelement <2 x i32> undef, i32 %187, i32 0
>  %190 = insertelement <2 x i32> %189, i32 %188, i32 1
>  %191 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %190, <32 x i8> %108, <16 x i8> %110, i32 2)
>  %192 = extractelement <4 x float> %191, i32 0
>  %193 = extractelement <4 x float> %191, i32 1
>  %194 = extractelement <4 x float> %191, i32 2
>  %195 = extractelement <4 x float> %191, i32 3
>  %196 = fmul float %192, 0x4012611180000000
>  %197 = fmul float %193, 0x4012611180000000
>  %198 = fmul float %194, 0x4012611180000000
>  %199 = call float @llvm.AMDGPU.lrp(float %29, float %196, float 1.000000e+00)
>  %200 = call float @llvm.AMDGPU.lrp(float %29, float %197, float 1.000000e+00)
>  %201 = call float @llvm.AMDGPU.lrp(float %29, float %198, float 1.000000e+00)
>  %202 = bitcast float %149 to i32
>  %203 = bitcast float %150 to i32
>  %204 = insertelement <2 x i32> undef, i32 %202, i32 0
>  %205 = insertelement <2 x i32> %204, i32 %203, i32 1
>  %206 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %205, <32 x i8> %116, <16 x i8> %118, i32 2)
>  %207 = extractelement <4 x float> %206, i32 0
>  %208 = extractelement <4 x float> %206, i32 1
>  %209 = extractelement <4 x float> %206, i32 2
>  %210 = extractelement <4 x float> %206, i32 3
>  %211 = bitcast float %141 to i32
>  %212 = bitcast float %142 to i32
>  %213 = insertelement <2 x i32> undef, i32 %211, i32 0
>  %214 = insertelement <2 x i32> %213, i32 %212, i32 1
>  %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %112, <16 x i8> %114, i32 2)
>  %216 = extractelement <4 x float> %215, i32 0
>  %217 = extractelement <4 x float> %215, i32 1
>  %218 = extractelement <4 x float> %215, i32 2
>  %219 = extractelement <4 x float> %215, i32 3
>  %220 = fmul float %216, %22
>  %221 = fmul float %217, %23
>  %222 = fmul float %218, %24
>  %223 = fmul float %219, %25
>  %224 = fmul float %220, %151
>  %225 = fmul float %221, %152
>  %226 = fmul float %222, %153
>  %227 = fmul float %223, %154
>  %228 = fsub float -0.000000e+00, %219
>  %229 = fadd float 1.000000e+00, %228
>  %230 = fmul float %229, %52
>  %231 = call float @llvm.AMDGPU.lrp(float %230, float %216, float %224)
>  %232 = call float @llvm.AMDGPU.lrp(float %230, float %217, float %225)
>  %233 = call float @llvm.AMDGPU.lrp(float %230, float %218, float %226)
>  %234 = bitcast float %143 to i32
>  %235 = bitcast float %144 to i32
>  %236 = insertelement <2 x i32> undef, i32 %234, i32 0
>  %237 = insertelement <2 x i32> %236, i32 %235, i32 1
>  %238 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %237, <32 x i8> %120, <16 x i8> %122, i32 2)
>  %239 = extractelement <4 x float> %238, i32 0
>  %240 = extractelement <4 x float> %238, i32 1
>  %241 = extractelement <4 x float> %238, i32 3
>  %242 = fmul float %57, %241
>  %243 = fmul float %58, %239
>  %244 = fsub float -0.000000e+00, %242
>  %245 = fadd float 1.000000e+00, %244
>  %246 = fsub float -0.000000e+00, %243
>  %247 = fadd float 1.000000e+00, %246
>  %248 = fmul float %231, %199
>  %249 = fmul float %232, %200
>  %250 = fmul float %233, %201
>  %251 = fmul float %227, %195
>  %252 = fmul float %155, %155
>  %253 = fmul float %156, %156
>  %254 = fadd float %253, %252
>  %255 = fmul float %157, %157
>  %256 = fadd float %254, %255
>  %257 = call float @llvm.AMDGPU.rsq(float %256)
>  %258 = fmul float %155, %257
>  %259 = fmul float %156, %257
>  %260 = fmul float %157, %257
>  %261 = fcmp ult float 0.000000e+00, %184
>  %262 = select i1 %261, float 1.000000e+00, float 0.000000e+00
>  %263 = fsub float -0.000000e+00, %262
>  %264 = fptosi float %263 to i32
>  %265 = bitcast i32 %264 to float
>  %266 = bitcast float %265 to i32
>  %267 = icmp ne i32 %266, 0
>  br i1 %267, label %IF93, label %ENDIF92
>
>IF93:                                             ; preds = %main_body
>  %268 = fsub float -0.000000e+00, %258
>  %269 = fsub float -0.000000e+00, %259
>  %270 = fsub float -0.000000e+00, %260
>  br label %ENDIF92
>
>ENDIF92:                                          ; preds = %main_body, %IF93
>  %temp20.0 = phi float [ %268, %IF93 ], [ %258, %main_body ]
>  %temp21.0 = phi float [ %269, %IF93 ], [ %259, %main_body ]
>  %temp22.0 = phi float [ %270, %IF93 ], [ %260, %main_body ]
>  %271 = bitcast float %185 to i32
>  %272 = bitcast float %186 to i32
>  %273 = insertelement <2 x i32> undef, i32 %271, i32 0
>  %274 = insertelement <2 x i32> %273, i32 %272, i32 1
>  %275 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %274, <32 x i8> %132, <16 x i8> %134, i32 2)
>  %276 = extractelement <4 x float> %275, i32 0
>  %277 = extractelement <4 x float> %275, i32 1
>  %278 = extractelement <4 x float> %275, i32 2
>  %279 = extractelement <4 x float> %275, i32 3
>  %280 = fmul float %276, %43
>  %281 = fadd float %280, %44
>  %282 = fmul float %277, %43
>  %283 = fadd float %282, %44
>  %284 = fmul float %278, %43
>  %285 = fadd float %284, %44
>  %286 = fmul float %279, %45
>  %287 = fadd float %286, %46
>  %288 = bitcast float %145 to i32
>  %289 = bitcast float %146 to i32
>  %290 = insertelement <2 x i32> undef, i32 %288, i32 0
>  %291 = insertelement <2 x i32> %290, i32 %289, i32 1
>  %292 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %291, <32 x i8> %124, <16 x i8> %126, i32 2)
>  %293 = extractelement <4 x float> %292, i32 0
>  %294 = extractelement <4 x float> %292, i32 1
>  %295 = extractelement <4 x float> %292, i32 2
>  %296 = extractelement <4 x float> %292, i32 3
>  %297 = fmul float %296, 3.200000e+01
>  %298 = fadd float %297, -1.600000e+01
>  %299 = call float @llvm.AMDIL.exp.(float %298)
>  %300 = fmul float %293, %299
>  %301 = fmul float %294, %299
>  %302 = fmul float %295, %299
>  %303 = fmul float %33, %300
>  %304 = fadd float %303, %158
>  %305 = fmul float %34, %301
>  %306 = fadd float %305, %159
>  %307 = fmul float %35, %302
>  %308 = fadd float %307, %160
>  %309 = fmul float %304, %287
>  %310 = fmul float %306, %287
>  %311 = fmul float %308, %287
>  %312 = fmul float %287, 5.000000e-01
>  %313 = fadd float %312, 5.000000e-01
>  %314 = fmul float %temp20.0, %181
>  %315 = fmul float %temp21.0, %182
>  %316 = fadd float %315, %314
>  %317 = fmul float %temp22.0, %183
>  %318 = fadd float %316, %317
>  %319 = call float @llvm.AMDIL.clamp.(float %318, float 0.000000e+00, float 1.000000e+00)
>  %320 = fsub float -0.000000e+00, %319
>  %321 = fadd float 1.000000e+00, %320
>  %322 = call float @llvm.pow.f32(float %321, float 4.000000e+00)
>  %323 = fmul float %322, %36
>  %324 = fmul float %247, %323
>  %325 = fsub float -0.000000e+00, %324
>  %326 = fadd float %247, %325
>  %327 = fmul float %temp20.0, %181
>  %328 = fmul float %temp21.0, %182
>  %329 = fadd float %328, %327
>  %330 = fmul float %temp22.0, %183
>  %331 = fadd float %329, %330
>  %332 = fmul float %331, %temp20.0
>  %333 = fmul float %331, %temp21.0
>  %334 = fmul float %331, %temp22.0
>  %335 = fmul float 2.000000e+00, %332
>  %336 = fmul float 2.000000e+00, %333
>  %337 = fmul float 2.000000e+00, %334
>  %338 = fsub float -0.000000e+00, %335
>  %339 = fadd float %181, %338
>  %340 = fsub float -0.000000e+00, %336
>  %341 = fadd float %182, %340
>  %342 = fsub float -0.000000e+00, %337
>  %343 = fadd float %183, %342
>  %344 = fsub float -0.000000e+00, %temp20.0
>  %345 = call float @llvm.AMDGPU.lrp(float %326, float %344, float %339)
>  %346 = fsub float -0.000000e+00, %temp21.0
>  %347 = call float @llvm.AMDGPU.lrp(float %326, float %346, float %341)
>  %348 = fsub float -0.000000e+00, %temp22.0
>  %349 = call float @llvm.AMDGPU.lrp(float %326, float %348, float %343)
>  %350 = call float @fabs(float %345)
>  %351 = call float @fabs(float %347)
>  %352 = call float @fabs(float %349)
>  %353 = fcmp uge float %351, %352
>  %354 = select i1 %353, float %351, float %352
>  %355 = fcmp uge float %350, %354
>  %356 = select i1 %355, float %350, float %354
>  %357 = fadd float %356, 0xBF50624DE0000000
>  %358 = fcmp uge float %357, %350
>  %359 = select i1 %358, float 1.000000e+00, float 0.000000e+00
>  %360 = fsub float -0.000000e+00, %359
>  %361 = fptosi float %360 to i32
>  %362 = bitcast i32 %361 to float
>  %363 = bitcast float %362 to i32
>  %364 = and i32 %363, 1065353216
>  %365 = bitcast i32 %364 to float
>  %366 = fcmp uge float %357, %351
>  %367 = select i1 %366, float 1.000000e+00, float 0.000000e+00
>  %368 = fsub float -0.000000e+00, %367
>  %369 = fptosi float %368 to i32
>  %370 = bitcast i32 %369 to float
>  %371 = bitcast float %370 to i32
>  %372 = and i32 %371, 1065353216
>  %373 = bitcast i32 %372 to float
>  %374 = fcmp uge float %357, %352
>  %375 = select i1 %374, float 1.000000e+00, float 0.000000e+00
>  %376 = fsub float -0.000000e+00, %375
>  %377 = fptosi float %376 to i32
>  %378 = bitcast i32 %377 to float
>  %379 = bitcast float %378 to i32
>  %380 = and i32 %379, 1065353216
>  %381 = bitcast i32 %380 to float
>  %382 = fdiv float 1.000000e+00, %356
>  %383 = fmul float -1.000000e+00, %382
>  %384 = fmul float -1.000000e+00, %382
>  %385 = fmul float 1.000000e+00, %382
>  %386 = fmul float %345, %383
>  %387 = fmul float %347, %384
>  %388 = fmul float %349, %385
>  %389 = fadd float %59, -1.000000e+00
>  %390 = fmul float %326, %389
>  %391 = fmul float %386, %365
>  %392 = fmul float %387, %373
>  %393 = fmul float %388, %381
>  %394 = call float @floor(float %390)
>  %395 = fsub float -0.000000e+00, %394
>  %396 = fadd float %59, %395
>  %397 = call float @llvm.AMDIL.exp.(float %396)
>  %398 = fdiv float 1.000000e+00, %397
>  %399 = fmul float %391, %398
>  %400 = fmul float %392, %398
>  %401 = fmul float %393, %398
>  %402 = fsub float -0.000000e+00, %399
>  %403 = fadd float %386, %402
>  %404 = fsub float -0.000000e+00, %400
>  %405 = fadd float %387, %404
>  %406 = fsub float -0.000000e+00, %401
>  %407 = fadd float %388, %406
>  %408 = insertelement <4 x float> undef, float %403, i32 0
>  %409 = insertelement <4 x float> %408, float %405, i32 1
>  %410 = insertelement <4 x float> %409, float %407, i32 2
>  %411 = insertelement <4 x float> %410, float %390, i32 3
>  %412 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %411)
>  %413 = extractelement <4 x float> %412, i32 0
>  %414 = extractelement <4 x float> %412, i32 1
>  %415 = extractelement <4 x float> %412, i32 2
>  %416 = extractelement <4 x float> %412, i32 3
>  %417 = call float @fabs(float %415)
>  %418 = fdiv float 1.000000e+00, %417
>  %419 = fmul float %413, %418
>  %420 = fadd float %419, 1.500000e+00
>  %421 = fmul float %414, %418
>  %422 = fadd float %421, 1.500000e+00
>  %423 = bitcast float %422 to i32
>  %424 = bitcast float %420 to i32
>  %425 = bitcast float %416 to i32
>  %426 = bitcast float %390 to i32
>  %427 = insertelement <4 x i32> undef, i32 %423, i32 0
>  %428 = insertelement <4 x i32> %427, i32 %424, i32 1
>  %429 = insertelement <4 x i32> %428, i32 %425, i32 2
>  %430 = insertelement <4 x i32> %429, i32 %426, i32 3
>  %431 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %430, <32 x i8> %128, <16 x i8> %130, i32 4)
>  %432 = extractelement <4 x float> %431, i32 0
>  %433 = extractelement <4 x float> %431, i32 1
>  %434 = extractelement <4 x float> %431, i32 2
>  %435 = extractelement <4 x float> %431, i32 3
>  %436 = fmul float %435, 3.200000e+01
>  %437 = fadd float %436, -1.600000e+01
>  %438 = call float @llvm.AMDIL.exp.(float %437)
>  %439 = fmul float %432, %438
>  %440 = fmul float %433, %438
>  %441 = fmul float %434, %438
>  %442 = fmul float %26, %240
>  %443 = fmul float %27, %240
>  %444 = fmul float %28, %240
>  %445 = fmul float %442, %240
>  %446 = fmul float %443, %240
>  %447 = fmul float %444, %240
>  %448 = fmul float %326, 2.000000e+00
>  %449 = fadd float %448, -1.000000e+00
>  %450 = call float @llvm.AMDIL.clamp.(float %449, float 0.000000e+00, float 1.000000e+00)
>  %451 = fmul float %281, %313
>  %452 = fmul float %283, %313
>  %453 = fmul float %285, %313
>  %454 = fmul float %439, %30
>  %455 = fmul float %440, %31
>  %456 = fmul float %441, %32
>  %457 = fmul float %445, %454
>  %458 = fmul float %446, %455
>  %459 = fmul float %447, %456
>  %460 = call float @llvm.AMDGPU.lrp(float %450, float %445, float %457)
>  %461 = call float @llvm.AMDGPU.lrp(float %450, float %446, float %458)
>  %462 = call float @llvm.AMDGPU.lrp(float %450, float %447, float %459)
>  %463 = call float @llvm.AMDGPU.lrp(float %323, float 1.000000e+00, float %445)
>  %464 = call float @llvm.AMDGPU.lrp(float %323, float 1.000000e+00, float %446)
>  %465 = call float @llvm.AMDGPU.lrp(float %323, float 1.000000e+00, float %447)
>  %466 = call float @llvm.AMDGPU.lrp(float %463, float %460, float %248)
>  %467 = call float @llvm.AMDGPU.lrp(float %464, float %461, float %249)
>  %468 = call float @llvm.AMDGPU.lrp(float %465, float %462, float %250)
>  %469 = fmul float %309, %466
>  %470 = fmul float %310, %467
>  %471 = fmul float %311, %468
>  %472 = fmul float %451, %248
>  %473 = fadd float %472, %469
>  %474 = fmul float %452, %249
>  %475 = fadd float %474, %470
>  %476 = fmul float %453, %250
>  %477 = fadd float %476, %471
>  %478 = fsub float -0.000000e+00, %65
>  %479 = fadd float %137, %478
>  %480 = fsub float -0.000000e+00, %66
>  %481 = fadd float %138, %480
>  %482 = fsub float -0.000000e+00, %67
>  %483 = fadd float %139, %482
>  %484 = fmul float %479, %479
>  %485 = fmul float %481, %481
>  %486 = fadd float %485, %484
>  %487 = fmul float %483, %483
>  %488 = fadd float %486, %487
>  %489 = call float @llvm.AMDGPU.rsq(float %488)
>  %490 = fmul float %72, %489
>  %491 = fdiv float 1.000000e+00, %490
>  %492 = call float @llvm.AMDIL.clamp.(float %491, float 0.000000e+00, float 1.000000e+00)
>  %493 = fsub float -0.000000e+00, %492
>  %494 = fadd float 1.000000e+00, %493
>  %495 = fmul float %494, %489
>  %496 = fsub float -0.000000e+00, %479
>  %497 = fmul float %496, %489
>  %498 = fsub float -0.000000e+00, %481
>  %499 = fmul float %498, %489
>  %500 = fsub float -0.000000e+00, %483
>  %501 = fmul float %500, %489
>  %502 = fsub float -0.000000e+00, %69
>  %503 = fsub float -0.000000e+00, %70
>  %504 = fsub float -0.000000e+00, %71
>  %505 = fmul float %497, %502
>  %506 = fmul float %499, %503
>  %507 = fadd float %506, %505
>  %508 = fmul float %501, %504
>  %509 = fadd float %507, %508
>  %510 = fmul float %509, %64
>  %511 = fsub float -0.000000e+00, %510
>  %512 = fadd float %68, %511
>  %513 = call float @llvm.AMDIL.clamp.(float %512, float 0.000000e+00, float 1.000000e+00)
>  %514 = fmul float %495, %513
>  %515 = fmul float %temp20.0, %497
>  %516 = fmul float %temp21.0, %499
>  %517 = fadd float %516, %515
>  %518 = fmul float %temp22.0, %501
>  %519 = fadd float %517, %518
>  %520 = call float @llvm.AMDIL.clamp.(float %519, float 0.000000e+00, float 1.000000e+00)
>  %521 = fadd float %181, %497
>  %522 = fadd float %182, %499
>  %523 = fadd float %183, %501
>  %524 = fmul float %521, %521
>  %525 = fmul float %522, %522
>  %526 = fadd float %525, %524
>  %527 = fmul float %523, %523
>  %528 = fadd float %526, %527
>  %529 = call float @llvm.AMDGPU.rsq(float %528)
>  %530 = fmul float %521, %529
>  %531 = fmul float %522, %529
>  %532 = fmul float %523, %529
>  %533 = fmul float %530, %temp20.0
>  %534 = fmul float %531, %temp21.0
>  %535 = fadd float %534, %533
>  %536 = fmul float %532, %temp22.0
>  %537 = fadd float %535, %536
>  %538 = call i32 @llvm.SI.tid()
>  %539 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %538
>  %540 = and i32 %538, -4
>  %541 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %540
>  %542 = add i32 %540, 1
>  %543 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %542
>  %544 = bitcast float %537 to i32
>  store i32 %544, i32 addrspace(3)* %539
>  %545 = load i32 addrspace(3)* %541
>  %546 = bitcast i32 %545 to float
>  %547 = load i32 addrspace(3)* %543
>  %548 = bitcast i32 %547 to float
>  %549 = fsub float %548, %546
>  %550 = insertelement <4 x float> undef, float %549, i32 0
>  %551 = insertelement <4 x float> %550, float %549, i32 1
>  %552 = insertelement <4 x float> %551, float %549, i32 2
>  %553 = insertelement <4 x float> %552, float %549, i32 3
>  %554 = extractelement <4 x float> %553, i32 0
>  %555 = call float @fabs(float %554)
>  %556 = fmul float %97, %537
>  %557 = fmul float %97, %537
>  %558 = fmul float %97, %537
>  %559 = fmul float %97, %537
>  %560 = call i32 @llvm.SI.tid()
>  %561 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %560
>  %562 = and i32 %560, -4
>  %563 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %562
>  %564 = add i32 %562, 2
>  %565 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %564
>  %566 = bitcast float %556 to i32
>  store i32 %566, i32 addrspace(3)* %561
>  %567 = load i32 addrspace(3)* %563
>  %568 = bitcast i32 %567 to float
>  %569 = load i32 addrspace(3)* %565
>  %570 = bitcast i32 %569 to float
>  %571 = fsub float %570, %568
>  %572 = bitcast float %557 to i32
>  store i32 %572, i32 addrspace(3)* %561
>  %573 = load i32 addrspace(3)* %563
>  %574 = bitcast i32 %573 to float
>  %575 = load i32 addrspace(3)* %565
>  %576 = bitcast i32 %575 to float
>  %577 = fsub float %576, %574
>  %578 = bitcast float %558 to i32
>  store i32 %578, i32 addrspace(3)* %561
>  %579 = load i32 addrspace(3)* %563
>  %580 = bitcast i32 %579 to float
>  %581 = load i32 addrspace(3)* %565
>  %582 = bitcast i32 %581 to float
>  %583 = fsub float %582, %580
>  %584 = bitcast float %559 to i32
>  store i32 %584, i32 addrspace(3)* %561
>  %585 = load i32 addrspace(3)* %563
>  %586 = bitcast i32 %585 to float
>  %587 = load i32 addrspace(3)* %565
>  %588 = bitcast i32 %587 to float
>  %589 = fsub float %588, %586
>  %590 = insertelement <4 x float> undef, float %571, i32 0
>  %591 = insertelement <4 x float> %590, float %577, i32 1
>  %592 = insertelement <4 x float> %591, float %583, i32 2
>  %593 = insertelement <4 x float> %592, float %589, i32 3
>  %594 = extractelement <4 x float> %593, i32 0
>  %595 = call float @fabs(float %594)
>  %596 = fadd float %555, %595
>  %597 = fmul float %596, 5.000000e-01
>  %598 = fadd float %597, 0x3EE4F8B580000000
>  %599 = fmul float %598, -1.000000e+00
>  %600 = fadd float %599, %537
>  %601 = fmul float %598, 1.000000e+00
>  %602 = fadd float %601, %537
>  %603 = call float @llvm.AMDIL.clamp.(float %600, float 0.000000e+00, float 1.000000e+00)
>  %604 = call float @llvm.AMDIL.clamp.(float %602, float 0.000000e+00, float 1.000000e+00)
>  %605 = fmul float %530, %181
>  %606 = fmul float %531, %182
>  %607 = fadd float %606, %605
>  %608 = fmul float %532, %183
>  %609 = fadd float %607, %608
>  %610 = call float @llvm.AMDIL.clamp.(float %609, float 0.000000e+00, float 1.000000e+00)
>  %611 = fsub float -0.000000e+00, %610
>  %612 = fadd float 1.000000e+00, %611
>  %613 = call float @llvm.pow.f32(float %612, float 4.000000e+00)
>  %614 = fmul float %613, %36
>  %615 = fmul float %245, %614
>  %616 = fmul float %247, %614
>  %617 = fsub float -0.000000e+00, %615
>  %618 = fadd float %245, %617
>  %619 = fsub float -0.000000e+00, %616
>  %620 = fadd float %247, %619
>  %621 = call float @llvm.pow.f32(float %618, float 4.000000e+00)
>  %622 = call float @llvm.pow.f32(float %620, float 4.000000e+00)
>  %623 = fadd float %621, 0x3E7AD7F2A0000000
>  %624 = fadd float %622, 0x3E7AD7F2A0000000
>  %625 = call float @llvm.AMDIL.clamp.(float %623, float 0.000000e+00, float 1.000000e+00)
>  %626 = call float @llvm.AMDIL.clamp.(float %624, float 0.000000e+00, float 1.000000e+00)
>  %627 = fmul float %603, %625
>  %628 = fmul float %604, %625
>  %629 = fmul float %603, %626
>  %630 = fmul float %604, %626
>  %631 = fadd float %625, -1.000000e+00
>  %632 = fadd float %625, -1.000000e+00
>  %633 = fadd float %626, -1.000000e+00
>  %634 = fadd float %626, -1.000000e+00
>  %635 = fmul float %603, %631
>  %636 = fadd float %635, 1.000000e+00
>  %637 = fmul float %604, %632
>  %638 = fadd float %637, 1.000000e+00
>  %639 = fmul float %603, %633
>  %640 = fadd float %639, 1.000000e+00
>  %641 = fmul float %604, %634
>  %642 = fadd float %641, 1.000000e+00
>  %643 = fdiv float 1.000000e+00, %636
>  %644 = fdiv float 1.000000e+00, %638
>  %645 = fdiv float 1.000000e+00, %640
>  %646 = fdiv float 1.000000e+00, %642
>  %647 = fmul float %627, %643
>  %648 = fmul float %628, %644
>  %649 = fmul float %629, %645
>  %650 = fmul float %630, %646
>  %651 = call float @llvm.AMDIL.clamp.(float %647, float 0.000000e+00, float 1.000000e+00)
>  %652 = call float @llvm.AMDIL.clamp.(float %648, float 0.000000e+00, float 1.000000e+00)
>  %653 = call float @llvm.AMDIL.clamp.(float %649, float 0.000000e+00, float 1.000000e+00)
>  %654 = call float @llvm.AMDIL.clamp.(float %650, float 0.000000e+00, float 1.000000e+00)
>  %655 = fsub float -0.000000e+00, %653
>  %656 = fadd float %654, %655
>  %657 = fsub float -0.000000e+00, %603
>  %658 = fadd float %604, %657
>  %659 = fadd float %658, 0x3EB0C6F7A0000000
>  %660 = fmul float %temp20.0, %181
>  %661 = fmul float %temp21.0, %182
>  %662 = fadd float %661, %660
>  %663 = fmul float %temp22.0, %183
>  %664 = fadd float %662, %663
>  %665 = call float @llvm.AMDIL.clamp.(float %664, float 0.000000e+00, float 1.000000e+00)
>  %666 = fmul float %665, %520
>  %667 = fcmp uge float %666, 0x3F847AE140000000
>  %668 = select i1 %667, float %666, float 0x3F847AE140000000
>  %669 = call float @llvm.AMDGPU.rsq(float %668)
>  %670 = fmul float %669, %668
>  %671 = fsub float -0.000000e+00, %668
>  %672 = call float @llvm.AMDGPU.cndlt(float %671, float %670, float 0.000000e+00)
>  %673 = call float @llvm.AMDGPU.lrp(float %625, float 1.000000e+00, float %672)
>  %674 = call float @llvm.AMDGPU.lrp(float %626, float 1.000000e+00, float %672)
>  %675 = fmul float %659, %674
>  %676 = fdiv float 1.000000e+00, %675
>  %677 = fmul float %656, %676
>  %678 = fmul float %26, %240
>  %679 = fmul float %27, %240
>  %680 = fmul float %28, %240
>  %681 = fmul float %678, %240
>  %682 = fmul float %679, %240
>  %683 = fmul float %680, %240
>  %684 = call float @llvm.AMDGPU.lrp(float %681, float %677, float %248)
>  %685 = call float @llvm.AMDGPU.lrp(float %682, float %677, float %249)
>  %686 = call float @llvm.AMDGPU.lrp(float %683, float %677, float %250)
>  %687 = fmul float %684, %520
>  %688 = fmul float %685, %520
>  %689 = fmul float %686, %520
>  %690 = fmul float %687, %61
>  %691 = fmul float %688, %62
>  %692 = fmul float %689, %63
>  %693 = fmul float %690, %514
>  %694 = fmul float %691, %514
>  %695 = fmul float %692, %514
>  %696 = fmul float %137, %81
>  %697 = fmul float %138, %82
>  %698 = fadd float %696, %697
>  %699 = fmul float %139, %83
>  %700 = fadd float %698, %699
>  %701 = fmul float %140, %84
>  %702 = fadd float %700, %701
>  %703 = fmul float %137, %85
>  %704 = fmul float %138, %86
>  %705 = fadd float %703, %704
>  %706 = fmul float %139, %87
>  %707 = fadd float %705, %706
>  %708 = fmul float %140, %88
>  %709 = fadd float %707, %708
>  %710 = fmul float %137, %89
>  %711 = fmul float %138, %90
>  %712 = fadd float %710, %711
>  %713 = fmul float %139, %91
>  %714 = fadd float %712, %713
>  %715 = fmul float %140, %92
>  %716 = fadd float %714, %715
>  %717 = fmul float %137, %93
>  %718 = fmul float %138, %94
>  %719 = fadd float %717, %718
>  %720 = fmul float %139, %95
>  %721 = fadd float %719, %720
>  %722 = fmul float %140, %96
>  %723 = fadd float %721, %722
>  %724 = fdiv float 1.000000e+00, %723
>  %725 = fmul float %702, %724
>  %726 = fmul float %709, %724
>  %727 = fmul float %725, 5.000000e-01
>  %728 = fadd float %727, 5.000000e-01
>  %729 = fmul float %726, 5.000000e-01
>  %730 = fadd float %729, 5.000000e-01
>  %731 = fmul float %728, %77
>  %732 = fadd float %731, %79
>  %733 = fmul float %730, %78
>  %734 = fadd float %733, %80
>  %735 = bitcast float %732 to i32
>  %736 = bitcast float %734 to i32
>  %737 = insertelement <2 x i32> undef, i32 %735, i32 0
>  %738 = insertelement <2 x i32> %737, i32 %736, i32 1
>  %739 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %738, <32 x i8> %104, <16 x i8> %106, i32 2)
>  %740 = extractelement <4 x float> %739, i32 0
>  %741 = extractelement <4 x float> %739, i32 1
>  %742 = extractelement <4 x float> %739, i32 2
>  %743 = bitcast float %728 to i32
>  %744 = bitcast float %730 to i32
>  %745 = bitcast float 0.000000e+00 to i32
>  %746 = insertelement <4 x i32> undef, i32 %743, i32 0
>  %747 = insertelement <4 x i32> %746, i32 %744, i32 1
>  %748 = insertelement <4 x i32> %747, i32 %745, i32 2
>  %749 = insertelement <4 x i32> %748, i32 undef, i32 3
>  %750 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %749, <32 x i8> %100, <16 x i8> %102, i32 2)
>  %751 = extractelement <4 x float> %750, i32 0
>  %752 = extractelement <4 x float> %750, i32 1
>  %753 = fsub float -0.000000e+00, %752
>  %754 = fadd float 1.000000e+00, %753
>  %755 = fmul float %754, 2.500000e-01
>  %756 = fsub float -0.000000e+00, %755
>  %757 = fadd float %751, %756
>  %758 = fsub float -0.000000e+00, %716
>  %759 = fadd float %751, %758
>  %760 = fmul float %751, %751
>  %761 = fsub float -0.000000e+00, %760
>  %762 = fadd float %757, %761
>  %763 = fcmp uge float %762, %73
>  %764 = select i1 %763, float %762, float %73
>  %765 = fmul float %759, %759
>  %766 = fadd float %765, %764
>  %767 = fdiv float 1.000000e+00, %766
>  %768 = fmul float %764, %767
>  %769 = call float @llvm.pow.f32(float %768, float %74)
>  %770 = fmul float %769, %75
>  %771 = fadd float %770, %76
>  %772 = call float @llvm.AMDIL.clamp.(float %771, float 0.000000e+00, float 1.000000e+00)
>  %773 = fmul float %772, %772
>  %774 = fmul float 2.000000e+00, %772
>  %775 = fsub float -0.000000e+00, %774
>  %776 = fadd float 3.000000e+00, %775
>  %777 = fmul float %773, %776
>  %778 = fcmp uge float %759, 0.000000e+00
>  %779 = select i1 %778, float 1.000000e+00, float 0.000000e+00
>  %780 = fsub float -0.000000e+00, %779
>  %781 = fptosi float %780 to i32
>  %782 = bitcast i32 %781 to float
>  %783 = bitcast float %782 to i32
>  %784 = icmp ne i32 %783, 0
>  %.98 = select i1 %784, float 1.000000e+00, float %777
>  %785 = fmul float %740, %.98
>  %786 = fmul float %741, %.98
>  %787 = fmul float %742, %.98
>  %788 = fmul float %693, %785
>  %789 = fmul float %694, %786
>  %790 = fmul float %695, %787
>  %791 = fmul float %788, %313
>  %792 = fadd float %791, %473
>  %793 = fmul float %789, %313
>  %794 = fadd float %793, %475
>  %795 = fmul float %790, %313
>  %796 = fadd float %795, %477
>  %797 = call float @llvm.AMDGPU.lrp(float %195, float %210, float 1.000000e+00)
>  %798 = call float @llvm.AMDGPU.lrp(float %41, float %207, float 1.000000e+00)
>  %799 = call float @llvm.AMDGPU.lrp(float %41, float %208, float 1.000000e+00)
>  %800 = call float @llvm.AMDGPU.lrp(float %41, float %209, float 1.000000e+00)
>  %801 = call float @llvm.AMDGPU.lrp(float %42, float %797, float 1.000000e+00)
>  %802 = fmul float %798, %801
>  %803 = fmul float %799, %801
>  %804 = fmul float %800, %801
>  %805 = fmul float %792, %802
>  %806 = fmul float %794, %803
>  %807 = fmul float %796, %804
>  %808 = fmul float %temp20.0, %181
>  %809 = fmul float %temp21.0, %182
>  %810 = fadd float %809, %808
>  %811 = fmul float %temp22.0, %183
>  %812 = fadd float %810, %811
>  %813 = call float @fabs(float %812)
>  %814 = fmul float %813, %813
>  %815 = fmul float %814, %53
>  %816 = fadd float %815, %54
>  %817 = call float @llvm.AMDIL.clamp.(float %816, float 0.000000e+00, float 1.000000e+00)
>  %818 = fsub float -0.000000e+00, %817
>  %819 = fadd float 1.000000e+00, %818
>  %820 = fmul float %39, %819
>  %821 = fmul float %39, %819
>  %822 = fmul float %39, %819
>  %823 = fmul float %40, %819
>  %824 = call float @llvm.AMDGPU.lrp(float %820, float %37, float %805)
>  %825 = call float @llvm.AMDGPU.lrp(float %821, float %37, float %806)
>  %826 = call float @llvm.AMDGPU.lrp(float %822, float %37, float %807)
>  %827 = call float @llvm.AMDGPU.lrp(float %823, float %38, float %251)
>  %828 = fcmp uge float %824, 6.550400e+04
>  %829 = select i1 %828, float 6.550400e+04, float %824
>  %830 = fcmp uge float %825, 6.550400e+04
>  %831 = select i1 %830, float 6.550400e+04, float %825
>  %832 = fcmp uge float %826, 6.550400e+04
>  %833 = select i1 %832, float 6.550400e+04, float %826
>  %834 = fcmp uge float %829, 0x3E6FFFFE60000000
>  %835 = select i1 %834, float %829, float 0x3E6FFFFE60000000
>  %836 = fcmp uge float %831, 0x3E6FFFFE60000000
>  %837 = select i1 %836, float %831, float 0x3E6FFFFE60000000
>  %838 = fcmp uge float %833, 0x3E6FFFFE60000000
>  %839 = select i1 %838, float %833, float 0x3E6FFFFE60000000
>  %840 = fmul float %827, %55
>  %841 = fadd float %840, %56
>  %842 = call float @llvm.AMDIL.clamp.(float %841, float 0.000000e+00, float 1.000000e+00)
>  %843 = call i32 @llvm.SI.packf16(float %835, float %837)
>  %844 = bitcast i32 %843 to float
>  %845 = call i32 @llvm.SI.packf16(float %839, float %842)
>  %846 = bitcast i32 %845 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %844, float %846, float %844, float %846)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.exp.(float) #2
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #3
>
>; Function Attrs: readonly
>declare float @fabs(float) #4
>
>; Function Attrs: readonly
>declare float @floor(float) #4
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readnone
>declare i32 @llvm.SI.tid() #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.cndlt(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>attributes #3 = { nounwind readonly }
>attributes #4 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc03c1
>befc0306
>c8180500
>c8190501
>c8140400
>c8150401
>c084030c
>c0c60518
>bf8c007f
>f0800f00
>00430b05
>c0a00100
>bf8c0070
>c2004103
>bf8c007f
>100a1c00
>c8181300
>c8191301
>100a0d05
>c81c0b00
>c81d0b01
>c8180a00
>c8190a01
>c0840308
>c0c60510
>bf8c007f
>f0800f00
>00430706
>bf8c0770
>100a1505
>c2004102
>bf8c007f
>100c1a00
>c83c1200
>c83d1201
>100c1f06
>081e1cf2
>c2004132
>bf8c007f
>101e1e00
>08201ef2
>100c0d10
>d2820006
>041a1b0f
>102412ff
>4093088c
>c2004107
>bf8c007f
>d2080011
>020000f2
>d2820012
>04462400
>100c2506
>c200c101
>bf8c007f
>10241801
>c84c1100
>c84d1101
>10242712
>10242510
>d2820012
>044a190f
>102610ff
>4093088c
>d2820013
>04462600
>10262712
>c200c100
>bf8c007f
>10241601
>c8501000
>c8511001
>10242912
>10202510
>d282000b
>0442170f
>10180eff
>4093088c
>d282000c
>04461800
>1016190b
>c8301500
>c8311501
>c8341400
>c8351401
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>043a1f0f
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>102a1d0f
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>10301d0d
>c8700100
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>10321d0f
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>c8340700
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>c0840314
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>f0800b00
>0043100c
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>c22241d8
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>c20041d9
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>7e000200
>d2820000
>04008903
>c2004131
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>107a0000
>c2004130
>bf8c007f
>10780400
>c200413b
>d0080006
>02010104
>d2000000
>0019e480
>d2060800
>02010100
>d10a0006
>02010100
>d2000000
>0019e6f2
>bf8c007f
>10000000
>d0080000
>02010100
>d2000000
>0001e480
>d2060000
>22010100
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>d10a0006
>02010100
>c08e0320
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>88fe007e
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>10060706
>10062703
>10062503
>d2820003
>04466f03
>d2820006
>04621d21
>100c1106
>10060d03
>1006070a
>d2820003
>040e4109
>d00c0000
>02023303
>d2000003
>00023303
>d00c0000
>02023503
>d2000003
>0002071a
>10080f04
>080c08f2
>100a0b06
>d2820002
>04160504
>d2820000
>04020302
>d2060800
>02010100
>5e000103
>f8001c0f
>000b000b
>bf810000
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL IN[6]
>DCL IN[7]
>DCL IN[8]
>DCL IN[9]
>DCL OUT[0], POSITION
>DCL OUT[1], CLIPVERTEX
>DCL OUT[2], GENERIC[19]
>DCL OUT[3], GENERIC[20]
>DCL OUT[4], GENERIC[21]
>DCL OUT[5], GENERIC[22]
>DCL OUT[6], GENERIC[23]
>DCL OUT[7], GENERIC[24]
>DCL OUT[8], GENERIC[25]
>DCL CONST[0..240]
>DCL TEMP[0..10], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,     0.0000}
>IMM[1] INT32 {3, 41, 42, 43}
>  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx
>  1: MOV TEMP[1].xz, TEMP[0].xxzx
>  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
>  3: MOV TEMP[1].y, TEMP[0].xxxx
>  4: MOV TEMP[0], IN[0]
>  5: MOV TEMP[2].xyz, TEMP[1].xyzx
>  6: UIF CONST[240].xxxx :0
>  7:   DP3 TEMP[3].x, IN[9].xyzz, IMM[0].yyyy
>  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
>  9:   MUL TEMP[4], IN[8], IMM[0].zzzz
> 10:   F2I TEMP[4], TEMP[4]
> 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
> 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
> 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
> 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
> 15:   UARL ADDR[0].x, TEMP[8].xxxx
> 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[9].xxxx
> 17:   UARL ADDR[0].x, TEMP[7].xxxx
> 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].yyyy, TEMP[8]
> 19:   UARL ADDR[0].x, TEMP[6].xxxx
> 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[9].zzzz, TEMP[7]
> 21:   UARL ADDR[0].x, TEMP[5].xxxx
> 22:   UARL ADDR[0].x, TEMP[5].xxxx
> 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
> 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
> 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
> 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
> 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
> 28:   UARL ADDR[0].x, TEMP[9].xxxx
> 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[9].xxxx
> 30:   UARL ADDR[0].x, TEMP[8].xxxx
> 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[9].yyyy, TEMP[9]
> 32:   UARL ADDR[0].x, TEMP[7].xxxx
> 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].zzzz, TEMP[8]
> 34:   UARL ADDR[0].x, TEMP[6].xxxx
> 35:   UARL ADDR[0].x, TEMP[6].xxxx
> 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
> 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
> 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
> 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
> 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
> 41:   UARL ADDR[0].x, TEMP[4].xxxx
> 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[9].xxxx
> 43:   UARL ADDR[0].x, TEMP[9].xxxx
> 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].yyyy, TEMP[4]
> 45:   UARL ADDR[0].x, TEMP[8].xxxx
> 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].zzzz, TEMP[4]
> 47:   UARL ADDR[0].x, TEMP[7].xxxx
> 48:   UARL ADDR[0].x, TEMP[7].xxxx
> 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
> 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
> 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
> 52:   MOV TEMP[4].y, TEMP[7].xxxx
> 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
> 54:   MOV TEMP[4].z, TEMP[7].xxxx
> 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
> 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
> 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
> 58:   MOV TEMP[4].y, TEMP[5].xxxx
> 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
> 60:   MOV TEMP[4].z, TEMP[1].xxxx
> 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
> 62: ENDIF
> 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
> 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
> 65: MOV TEMP[1].y, TEMP[3].xxxx
> 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
> 67: MOV TEMP[1].z, TEMP[3].xxxx
> 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
> 69: MOV TEMP[1].w, TEMP[3].xxxx
> 70: DP4 TEMP[3].x, TEMP[0], CONST[4]
> 71: DP4 TEMP[4].x, TEMP[0], CONST[5]
> 72: MOV TEMP[3].y, TEMP[4].xxxx
> 73: DP4 TEMP[0].x, TEMP[0], CONST[6]
> 74: MOV TEMP[3].z, TEMP[0].xxxx
> 75: MOV TEMP[0].xyz, TEMP[3].xyzx
> 76: MOV TEMP[0].w, IMM[0].yyyy
> 77: DP3 TEMP[4].x, CONST[4].xyzz, CONST[4].xyzz
> 78: RCP TEMP[4].x, TEMP[4].xxxx
> 79: MUL TEMP[4].xyz, CONST[4].xyzz, TEMP[4].xxxx
> 80: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[4].xyzz
> 81: DP3 TEMP[5].x, CONST[5].xyzz, CONST[5].xyzz
> 82: RCP TEMP[5].x, TEMP[5].xxxx
> 83: MUL TEMP[5].xyz, CONST[5].xyzz, TEMP[5].xxxx
> 84: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[5].xyzz
> 85: MOV TEMP[4].y, TEMP[5].xxxx
> 86: DP3 TEMP[5].x, CONST[6].xyzz, CONST[6].xyzz
> 87: RCP TEMP[5].x, TEMP[5].xxxx
> 88: MUL TEMP[5].xyz, CONST[6].xyzz, TEMP[5].xxxx
> 89: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[5].xyzz
> 90: MOV TEMP[4].z, TEMP[2].xxxx
> 91: DP3 TEMP[2].x, TEMP[4].xyzz, TEMP[4].xyzz
> 92: RSQ TEMP[2].x, TEMP[2].xxxx
> 93: MUL TEMP[2].xyz, TEMP[4].xyzz, TEMP[2].xxxx
> 94: SGE TEMP[5].x, CONST[31].zzzz, IMM[0].wwww
> 95: F2I TEMP[5].x, -TEMP[5]
> 96: UIF TEMP[5].xxxx :0
> 97:   MOV TEMP[5].x, TEMP[3].xxxx
> 98: ELSE :0
> 99:   MOV TEMP[5].x, IN[5].xxxx
>100: ENDIF
>101: SGE TEMP[6].x, CONST[31].zzzz, IMM[0].wwww
>102: F2I TEMP[6].x, -TEMP[6]
>103: UIF TEMP[6].xxxx :0
>104:   MOV TEMP[6].x, TEMP[3].yyyy
>105: ELSE :0
>106:   MOV TEMP[6].x, IN[5].yyyy
>107: ENDIF
>108: SGE TEMP[7].x, CONST[31].xxxx, IMM[0].wwww
>109: F2I TEMP[7].x, -TEMP[7]
>110: UIF TEMP[7].xxxx :0
>111:   MOV TEMP[7].x, TEMP[3].zzzz
>112: ELSE :0
>113:   MOV TEMP[7].x, TEMP[5].xxxx
>114: ENDIF
>115: MOV TEMP[4].x, TEMP[7].xxxx
>116: SGE TEMP[5].x, CONST[31].yyyy, IMM[0].wwww
>117: F2I TEMP[5].x, -TEMP[5]
>118: UIF TEMP[5].xxxx :0
>119:   MOV TEMP[5].x, TEMP[3].zzzz
>120: ELSE :0
>121:   MOV TEMP[5].x, TEMP[6].xxxx
>122: ENDIF
>123: MOV TEMP[4].y, TEMP[5].xxxx
>124: MOV TEMP[5].zw, IMM[0].yywy
>125: MOV TEMP[5].xy, TEMP[4].xyxx
>126: SGE TEMP[6].x, CONST[32].zzzz, IMM[0].wwww
>127: F2I TEMP[6].x, -TEMP[6]
>128: UIF TEMP[6].xxxx :0
>129:   MOV TEMP[6].x, TEMP[3].xxxx
>130: ELSE :0
>131:   MOV TEMP[6].x, IN[2].xxxx
>132: ENDIF
>133: SGE TEMP[7].x, CONST[32].zzzz, IMM[0].wwww
>134: F2I TEMP[7].x, -TEMP[7]
>135: UIF TEMP[7].xxxx :0
>136:   MOV TEMP[7].x, TEMP[3].yyyy
>137: ELSE :0
>138:   MOV TEMP[7].x, IN[2].yyyy
>139: ENDIF
>140: SGE TEMP[8].x, CONST[32].xxxx, IMM[0].wwww
>141: F2I TEMP[8].x, -TEMP[8]
>142: UIF TEMP[8].xxxx :0
>143:   MOV TEMP[8].x, TEMP[3].zzzz
>144: ELSE :0
>145:   MOV TEMP[8].x, TEMP[6].xxxx
>146: ENDIF
>147: MOV TEMP[4].x, TEMP[8].xxxx
>148: SGE TEMP[6].x, CONST[32].yyyy, IMM[0].wwww
>149: F2I TEMP[6].x, -TEMP[6]
>150: UIF TEMP[6].xxxx :0
>151:   MOV TEMP[6].x, TEMP[3].zzzz
>152: ELSE :0
>153:   MOV TEMP[6].x, TEMP[7].xxxx
>154: ENDIF
>155: MOV TEMP[4].y, TEMP[6].xxxx
>156: MOV TEMP[6].zw, IMM[0].yywy
>157: MOV TEMP[6].xy, TEMP[4].xyxx
>158: SGE TEMP[7].x, CONST[33].zzzz, IMM[0].wwww
>159: F2I TEMP[7].x, -TEMP[7]
>160: UIF TEMP[7].xxxx :0
>161:   MOV TEMP[7].x, TEMP[3].xxxx
>162: ELSE :0
>163:   MOV TEMP[7].x, IN[6].xxxx
>164: ENDIF
>165: SGE TEMP[8].x, CONST[33].zzzz, IMM[0].wwww
>166: F2I TEMP[8].x, -TEMP[8]
>167: UIF TEMP[8].xxxx :0
>168:   MOV TEMP[8].x, TEMP[3].yyyy
>169: ELSE :0
>170:   MOV TEMP[8].x, IN[6].yyyy
>171: ENDIF
>172: SGE TEMP[9].x, CONST[33].xxxx, IMM[0].wwww
>173: F2I TEMP[9].x, -TEMP[9]
>174: UIF TEMP[9].xxxx :0
>175:   MOV TEMP[9].x, TEMP[3].zzzz
>176: ELSE :0
>177:   MOV TEMP[9].x, TEMP[7].xxxx
>178: ENDIF
>179: MOV TEMP[4].x, TEMP[9].xxxx
>180: SGE TEMP[7].x, CONST[33].yyyy, IMM[0].wwww
>181: F2I TEMP[7].x, -TEMP[7]
>182: UIF TEMP[7].xxxx :0
>183:   MOV TEMP[7].x, TEMP[3].zzzz
>184: ELSE :0
>185:   MOV TEMP[7].x, TEMP[8].xxxx
>186: ENDIF
>187: MOV TEMP[4].y, TEMP[7].xxxx
>188: MOV TEMP[7].zw, IMM[0].yywy
>189: MOV TEMP[7].xy, TEMP[4].xyxx
>190: SGE TEMP[8].x, CONST[34].zzzz, IMM[0].wwww
>191: F2I TEMP[8].x, -TEMP[8]
>192: UIF TEMP[8].xxxx :0
>193:   MOV TEMP[8].x, TEMP[3].xxxx
>194: ELSE :0
>195:   MOV TEMP[8].x, IN[3].xxxx
>196: ENDIF
>197: SGE TEMP[9].x, CONST[34].zzzz, IMM[0].wwww
>198: F2I TEMP[9].x, -TEMP[9]
>199: UIF TEMP[9].xxxx :0
>200:   MOV TEMP[9].x, TEMP[3].yyyy
>201: ELSE :0
>202:   MOV TEMP[9].x, IN[3].yyyy
>203: ENDIF
>204: SGE TEMP[10].x, CONST[34].xxxx, IMM[0].wwww
>205: F2I TEMP[10].x, -TEMP[10]
>206: UIF TEMP[10].xxxx :0
>207:   MOV TEMP[10].x, TEMP[3].zzzz
>208: ELSE :0
>209:   MOV TEMP[10].x, TEMP[8].xxxx
>210: ENDIF
>211: MOV TEMP[4].x, TEMP[10].xxxx
>212: SGE TEMP[8].x, CONST[34].yyyy, IMM[0].wwww
>213: F2I TEMP[8].x, -TEMP[8]
>214: UIF TEMP[8].xxxx :0
>215:   MOV TEMP[3].x, TEMP[3].zzzz
>216: ELSE :0
>217:   MOV TEMP[3].x, TEMP[9].xxxx
>218: ENDIF
>219: MOV TEMP[4].y, TEMP[3].xxxx
>220: MOV TEMP[3].zw, IMM[0].yywy
>221: MOV TEMP[3].xy, TEMP[4].xyxx
>222: MAD TEMP[4].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww
>223: DP4 TEMP[8].x, TEMP[5], CONST[27]
>224: DP4 TEMP[5].x, TEMP[5], CONST[28]
>225: MOV TEMP[8].y, TEMP[5].xxxx
>226: MOV TEMP[4].zw, TEMP[8].yyxy
>227: DP4 TEMP[5].x, TEMP[6], CONST[7]
>228: DP4 TEMP[6].x, TEMP[6], CONST[8]
>229: MOV TEMP[5].y, TEMP[6].xxxx
>230: MOV TEMP[5].xy, TEMP[5].xyxx
>231: DP4 TEMP[6].x, TEMP[7], CONST[25]
>232: DP4 TEMP[7].x, TEMP[7], CONST[26]
>233: MOV TEMP[6].y, TEMP[7].xxxx
>234: MOV TEMP[5].zw, TEMP[6].yyxy
>235: DP4 TEMP[6].x, TEMP[3], CONST[23]
>236: DP4 TEMP[3].x, TEMP[3], CONST[24]
>237: MOV TEMP[6].y, TEMP[3].xxxx
>238: MOV TEMP[3].xy, TEMP[6].xyxx
>239: MOV TEMP[3].zw, IMM[0].wwww
>240: MAD TEMP[6], IN[7].zyxw, CONST[30].xxxy, CONST[30].zzzz
>241: MOV TEMP[7].w, TEMP[6].wwww
>242: MUL TEMP[7].xyz, TEMP[6].xyzz, TEMP[6].xyzz
>243: MOV TEMP[2].xyz, TEMP[2].xyzx
>244: MOV TEMP[2].w, IMM[0].wwww
>245: MOV TEMP[6].xy, IMM[0].wwww
>246: MOV OUT[3], TEMP[5]
>247: MOV OUT[7], TEMP[2]
>248: MOV OUT[2], TEMP[0]
>249: MOV OUT[4], TEMP[4]
>250: MOV OUT[0], TEMP[1]
>251: MOV OUT[8], TEMP[6]
>252: MOV OUT[6], TEMP[7]
>253: MOV OUT[1], TEMP[1]
>254: MOV OUT[5], TEMP[3]
>255: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %10, i32 32)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %10, i32 36)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %10, i32 40)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %10, i32 44)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %10, i32 48)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %10, i32 52)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %10, i32 56)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %10, i32 60)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %10, i32 64)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %10, i32 68)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %10, i32 72)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %10, i32 76)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %10, i32 80)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %10, i32 84)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %10, i32 88)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %10, i32 92)
>  %35 = call float @llvm.SI.load.const(<16 x i8> %10, i32 96)
>  %36 = call float @llvm.SI.load.const(<16 x i8> %10, i32 100)
>  %37 = call float @llvm.SI.load.const(<16 x i8> %10, i32 104)
>  %38 = call float @llvm.SI.load.const(<16 x i8> %10, i32 108)
>  %39 = call float @llvm.SI.load.const(<16 x i8> %10, i32 112)
>  %40 = call float @llvm.SI.load.const(<16 x i8> %10, i32 116)
>  %41 = call float @llvm.SI.load.const(<16 x i8> %10, i32 120)
>  %42 = call float @llvm.SI.load.const(<16 x i8> %10, i32 124)
>  %43 = call float @llvm.SI.load.const(<16 x i8> %10, i32 128)
>  %44 = call float @llvm.SI.load.const(<16 x i8> %10, i32 132)
>  %45 = call float @llvm.SI.load.const(<16 x i8> %10, i32 136)
>  %46 = call float @llvm.SI.load.const(<16 x i8> %10, i32 140)
>  %47 = call float @llvm.SI.load.const(<16 x i8> %10, i32 368)
>  %48 = call float @llvm.SI.load.const(<16 x i8> %10, i32 372)
>  %49 = call float @llvm.SI.load.const(<16 x i8> %10, i32 376)
>  %50 = call float @llvm.SI.load.const(<16 x i8> %10, i32 380)
>  %51 = call float @llvm.SI.load.const(<16 x i8> %10, i32 384)
>  %52 = call float @llvm.SI.load.const(<16 x i8> %10, i32 388)
>  %53 = call float @llvm.SI.load.const(<16 x i8> %10, i32 392)
>  %54 = call float @llvm.SI.load.const(<16 x i8> %10, i32 396)
>  %55 = call float @llvm.SI.load.const(<16 x i8> %10, i32 400)
>  %56 = call float @llvm.SI.load.const(<16 x i8> %10, i32 404)
>  %57 = call float @llvm.SI.load.const(<16 x i8> %10, i32 408)
>  %58 = call float @llvm.SI.load.const(<16 x i8> %10, i32 412)
>  %59 = call float @llvm.SI.load.const(<16 x i8> %10, i32 416)
>  %60 = call float @llvm.SI.load.const(<16 x i8> %10, i32 420)
>  %61 = call float @llvm.SI.load.const(<16 x i8> %10, i32 424)
>  %62 = call float @llvm.SI.load.const(<16 x i8> %10, i32 428)
>  %63 = call float @llvm.SI.load.const(<16 x i8> %10, i32 432)
>  %64 = call float @llvm.SI.load.const(<16 x i8> %10, i32 436)
>  %65 = call float @llvm.SI.load.const(<16 x i8> %10, i32 440)
>  %66 = call float @llvm.SI.load.const(<16 x i8> %10, i32 444)
>  %67 = call float @llvm.SI.load.const(<16 x i8> %10, i32 448)
>  %68 = call float @llvm.SI.load.const(<16 x i8> %10, i32 452)
>  %69 = call float @llvm.SI.load.const(<16 x i8> %10, i32 456)
>  %70 = call float @llvm.SI.load.const(<16 x i8> %10, i32 460)
>  %71 = call float @llvm.SI.load.const(<16 x i8> %10, i32 464)
>  %72 = call float @llvm.SI.load.const(<16 x i8> %10, i32 468)
>  %73 = call float @llvm.SI.load.const(<16 x i8> %10, i32 472)
>  %74 = call float @llvm.SI.load.const(<16 x i8> %10, i32 476)
>  %75 = call float @llvm.SI.load.const(<16 x i8> %10, i32 480)
>  %76 = call float @llvm.SI.load.const(<16 x i8> %10, i32 484)
>  %77 = call float @llvm.SI.load.const(<16 x i8> %10, i32 488)
>  %78 = call float @llvm.SI.load.const(<16 x i8> %10, i32 496)
>  %79 = call float @llvm.SI.load.const(<16 x i8> %10, i32 500)
>  %80 = call float @llvm.SI.load.const(<16 x i8> %10, i32 504)
>  %81 = call float @llvm.SI.load.const(<16 x i8> %10, i32 512)
>  %82 = call float @llvm.SI.load.const(<16 x i8> %10, i32 516)
>  %83 = call float @llvm.SI.load.const(<16 x i8> %10, i32 520)
>  %84 = call float @llvm.SI.load.const(<16 x i8> %10, i32 528)
>  %85 = call float @llvm.SI.load.const(<16 x i8> %10, i32 532)
>  %86 = call float @llvm.SI.load.const(<16 x i8> %10, i32 536)
>  %87 = call float @llvm.SI.load.const(<16 x i8> %10, i32 544)
>  %88 = call float @llvm.SI.load.const(<16 x i8> %10, i32 548)
>  %89 = call float @llvm.SI.load.const(<16 x i8> %10, i32 552)
>  %90 = call float @llvm.SI.load.const(<16 x i8> %10, i32 576)
>  %91 = call float @llvm.SI.load.const(<16 x i8> %10, i32 580)
>  %92 = call float @llvm.SI.load.const(<16 x i8> %10, i32 584)
>  %93 = call float @llvm.SI.load.const(<16 x i8> %10, i32 3840)
>  %94 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %95 = load <16 x i8> addrspace(2)* %94, !tbaa !0
>  %96 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %95, i32 0, i32 %5)
>  %97 = extractelement <4 x float> %96, i32 0
>  %98 = extractelement <4 x float> %96, i32 1
>  %99 = extractelement <4 x float> %96, i32 2
>  %100 = extractelement <4 x float> %96, i32 3
>  %101 = getelementptr <16 x i8> addrspace(2)* %3, i32 1
>  %102 = load <16 x i8> addrspace(2)* %101, !tbaa !0
>  %103 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %102, i32 0, i32 %5)
>  %104 = extractelement <4 x float> %103, i32 0
>  %105 = extractelement <4 x float> %103, i32 1
>  %106 = extractelement <4 x float> %103, i32 2
>  %107 = getelementptr <16 x i8> addrspace(2)* %3, i32 2
>  %108 = load <16 x i8> addrspace(2)* %107, !tbaa !0
>  %109 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %108, i32 0, i32 %5)
>  %110 = extractelement <4 x float> %109, i32 0
>  %111 = extractelement <4 x float> %109, i32 1
>  %112 = getelementptr <16 x i8> addrspace(2)* %3, i32 3
>  %113 = load <16 x i8> addrspace(2)* %112, !tbaa !0
>  %114 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %113, i32 0, i32 %5)
>  %115 = extractelement <4 x float> %114, i32 0
>  %116 = extractelement <4 x float> %114, i32 1
>  %117 = getelementptr <16 x i8> addrspace(2)* %3, i32 4
>  %118 = load <16 x i8> addrspace(2)* %117, !tbaa !0
>  %119 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %118, i32 0, i32 %5)
>  %120 = extractelement <4 x float> %119, i32 0
>  %121 = extractelement <4 x float> %119, i32 1
>  %122 = getelementptr <16 x i8> addrspace(2)* %3, i32 5
>  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
>  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %5)
>  %125 = extractelement <4 x float> %124, i32 0
>  %126 = extractelement <4 x float> %124, i32 1
>  %127 = getelementptr <16 x i8> addrspace(2)* %3, i32 6
>  %128 = load <16 x i8> addrspace(2)* %127, !tbaa !0
>  %129 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %128, i32 0, i32 %5)
>  %130 = extractelement <4 x float> %129, i32 0
>  %131 = extractelement <4 x float> %129, i32 1
>  %132 = getelementptr <16 x i8> addrspace(2)* %3, i32 7
>  %133 = load <16 x i8> addrspace(2)* %132, !tbaa !0
>  %134 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %133, i32 0, i32 %5)
>  %135 = extractelement <4 x float> %134, i32 0
>  %136 = extractelement <4 x float> %134, i32 1
>  %137 = extractelement <4 x float> %134, i32 2
>  %138 = extractelement <4 x float> %134, i32 3
>  %139 = getelementptr <16 x i8> addrspace(2)* %3, i32 8
>  %140 = load <16 x i8> addrspace(2)* %139, !tbaa !0
>  %141 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %140, i32 0, i32 %5)
>  %142 = extractelement <4 x float> %141, i32 0
>  %143 = extractelement <4 x float> %141, i32 1
>  %144 = extractelement <4 x float> %141, i32 2
>  %145 = extractelement <4 x float> %141, i32 3
>  %146 = getelementptr <16 x i8> addrspace(2)* %3, i32 9
>  %147 = load <16 x i8> addrspace(2)* %146, !tbaa !0
>  %148 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %147, i32 0, i32 %5)
>  %149 = extractelement <4 x float> %148, i32 0
>  %150 = extractelement <4 x float> %148, i32 1
>  %151 = extractelement <4 x float> %148, i32 2
>  %152 = fmul float %104, %92
>  %153 = fadd float %152, %90
>  %154 = fmul float %105, %92
>  %155 = fadd float %154, %91
>  %156 = fmul float %106, %92
>  %157 = fadd float %156, %90
>  %158 = fadd float %155, 0x3F50624DE0000000
>  %159 = bitcast float %93 to i32
>  %160 = icmp ne i32 %159, 0
>  br i1 %160, label %IF, label %ENDIF
>
>IF:                                               ; preds = %main_body
>  %161 = fmul float %149, 1.000000e+00
>  %162 = fmul float %150, 1.000000e+00
>  %163 = fadd float %162, %161
>  %164 = fmul float %151, 1.000000e+00
>  %165 = fadd float %163, %164
>  %166 = fsub float -0.000000e+00, %165
>  %167 = fadd float 1.000000e+00, %166
>  %168 = fmul float %142, 0x406FE051E0000000
>  %169 = fmul float %143, 0x406FE051E0000000
>  %170 = fmul float %144, 0x406FE051E0000000
>  %171 = fmul float %145, 0x406FE051E0000000
>  %172 = fptosi float %168 to i32
>  %173 = fptosi float %169 to i32
>  %174 = fptosi float %170 to i32
>  %175 = fptosi float %171 to i32
>  %176 = bitcast i32 %172 to float
>  %177 = bitcast i32 %173 to float
>  %178 = bitcast i32 %174 to float
>  %179 = bitcast i32 %175 to float
>  %180 = bitcast float %179 to i32
>  %181 = mul i32 %180, 3
>  %182 = add i32 %181, 41
>  %183 = bitcast i32 %182 to float
>  %184 = bitcast float %178 to i32
>  %185 = mul i32 %184, 3
>  %186 = add i32 %185, 41
>  %187 = bitcast i32 %186 to float
>  %188 = bitcast float %177 to i32
>  %189 = mul i32 %188, 3
>  %190 = add i32 %189, 41
>  %191 = bitcast i32 %190 to float
>  %192 = bitcast float %176 to i32
>  %193 = mul i32 %192, 3
>  %194 = add i32 %193, 41
>  %195 = bitcast i32 %194 to float
>  %196 = bitcast float %195 to i32
>  %197 = shl i32 %196, 4
>  %198 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %197)
>  %199 = fmul float %198, %149
>  %200 = shl i32 %196, 4
>  %201 = add i32 %200, 4
>  %202 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %201)
>  %203 = fmul float %202, %149
>  %204 = shl i32 %196, 4
>  %205 = add i32 %204, 8
>  %206 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %205)
>  %207 = fmul float %206, %149
>  %208 = shl i32 %196, 4
>  %209 = add i32 %208, 12
>  %210 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %209)
>  %211 = fmul float %210, %149
>  %212 = bitcast float %191 to i32
>  %213 = shl i32 %212, 4
>  %214 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %213)
>  %215 = fmul float %214, %150
>  %216 = fadd float %215, %199
>  %217 = shl i32 %212, 4
>  %218 = add i32 %217, 4
>  %219 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %218)
>  %220 = fmul float %219, %150
>  %221 = fadd float %220, %203
>  %222 = shl i32 %212, 4
>  %223 = add i32 %222, 8
>  %224 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %223)
>  %225 = fmul float %224, %150
>  %226 = fadd float %225, %207
>  %227 = shl i32 %212, 4
>  %228 = add i32 %227, 12
>  %229 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %228)
>  %230 = fmul float %229, %150
>  %231 = fadd float %230, %211
>  %232 = bitcast float %187 to i32
>  %233 = shl i32 %232, 4
>  %234 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %233)
>  %235 = fmul float %234, %151
>  %236 = fadd float %235, %216
>  %237 = shl i32 %232, 4
>  %238 = add i32 %237, 4
>  %239 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %238)
>  %240 = fmul float %239, %151
>  %241 = fadd float %240, %221
>  %242 = shl i32 %232, 4
>  %243 = add i32 %242, 8
>  %244 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %243)
>  %245 = fmul float %244, %151
>  %246 = fadd float %245, %226
>  %247 = shl i32 %232, 4
>  %248 = add i32 %247, 12
>  %249 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %248)
>  %250 = fmul float %249, %151
>  %251 = fadd float %250, %231
>  %252 = bitcast float %183 to i32
>  %253 = shl i32 %252, 4
>  %254 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %253)
>  %255 = fmul float %254, %167
>  %256 = fadd float %255, %236
>  %257 = shl i32 %252, 4
>  %258 = add i32 %257, 4
>  %259 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %258)
>  %260 = fmul float %259, %167
>  %261 = fadd float %260, %241
>  %262 = shl i32 %252, 4
>  %263 = add i32 %262, 8
>  %264 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %263)
>  %265 = fmul float %264, %167
>  %266 = fadd float %265, %246
>  %267 = shl i32 %252, 4
>  %268 = add i32 %267, 12
>  %269 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %268)
>  %270 = fmul float %269, %167
>  %271 = fadd float %270, %251
>  %272 = bitcast float %179 to i32
>  %273 = mul i32 %272, 3
>  %274 = add i32 %273, 42
>  %275 = bitcast i32 %274 to float
>  %276 = bitcast float %178 to i32
>  %277 = mul i32 %276, 3
>  %278 = add i32 %277, 42
>  %279 = bitcast i32 %278 to float
>  %280 = bitcast float %177 to i32
>  %281 = mul i32 %280, 3
>  %282 = add i32 %281, 42
>  %283 = bitcast i32 %282 to float
>  %284 = bitcast float %176 to i32
>  %285 = mul i32 %284, 3
>  %286 = add i32 %285, 42
>  %287 = bitcast i32 %286 to float
>  %288 = bitcast float %287 to i32
>  %289 = shl i32 %288, 4
>  %290 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %289)
>  %291 = fmul float %290, %149
>  %292 = shl i32 %288, 4
>  %293 = add i32 %292, 4
>  %294 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %293)
>  %295 = fmul float %294, %149
>  %296 = shl i32 %288, 4
>  %297 = add i32 %296, 8
>  %298 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %297)
>  %299 = fmul float %298, %149
>  %300 = shl i32 %288, 4
>  %301 = add i32 %300, 12
>  %302 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %301)
>  %303 = fmul float %302, %149
>  %304 = bitcast float %283 to i32
>  %305 = shl i32 %304, 4
>  %306 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %305)
>  %307 = fmul float %306, %150
>  %308 = fadd float %307, %291
>  %309 = shl i32 %304, 4
>  %310 = add i32 %309, 4
>  %311 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %310)
>  %312 = fmul float %311, %150
>  %313 = fadd float %312, %295
>  %314 = shl i32 %304, 4
>  %315 = add i32 %314, 8
>  %316 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %315)
>  %317 = fmul float %316, %150
>  %318 = fadd float %317, %299
>  %319 = shl i32 %304, 4
>  %320 = add i32 %319, 12
>  %321 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %320)
>  %322 = fmul float %321, %150
>  %323 = fadd float %322, %303
>  %324 = bitcast float %279 to i32
>  %325 = shl i32 %324, 4
>  %326 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %325)
>  %327 = fmul float %326, %151
>  %328 = fadd float %327, %308
>  %329 = shl i32 %324, 4
>  %330 = add i32 %329, 4
>  %331 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %330)
>  %332 = fmul float %331, %151
>  %333 = fadd float %332, %313
>  %334 = shl i32 %324, 4
>  %335 = add i32 %334, 8
>  %336 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %335)
>  %337 = fmul float %336, %151
>  %338 = fadd float %337, %318
>  %339 = shl i32 %324, 4
>  %340 = add i32 %339, 12
>  %341 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %340)
>  %342 = fmul float %341, %151
>  %343 = fadd float %342, %323
>  %344 = bitcast float %275 to i32
>  %345 = shl i32 %344, 4
>  %346 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %345)
>  %347 = fmul float %346, %167
>  %348 = fadd float %347, %328
>  %349 = shl i32 %344, 4
>  %350 = add i32 %349, 4
>  %351 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %350)
>  %352 = fmul float %351, %167
>  %353 = fadd float %352, %333
>  %354 = shl i32 %344, 4
>  %355 = add i32 %354, 8
>  %356 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %355)
>  %357 = fmul float %356, %167
>  %358 = fadd float %357, %338
>  %359 = shl i32 %344, 4
>  %360 = add i32 %359, 12
>  %361 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %360)
>  %362 = fmul float %361, %167
>  %363 = fadd float %362, %343
>  %364 = bitcast float %179 to i32
>  %365 = mul i32 %364, 3
>  %366 = add i32 %365, 43
>  %367 = bitcast i32 %366 to float
>  %368 = bitcast float %178 to i32
>  %369 = mul i32 %368, 3
>  %370 = add i32 %369, 43
>  %371 = bitcast i32 %370 to float
>  %372 = bitcast float %177 to i32
>  %373 = mul i32 %372, 3
>  %374 = add i32 %373, 43
>  %375 = bitcast i32 %374 to float
>  %376 = bitcast float %176 to i32
>  %377 = mul i32 %376, 3
>  %378 = add i32 %377, 43
>  %379 = bitcast i32 %378 to float
>  %380 = bitcast float %379 to i32
>  %381 = shl i32 %380, 4
>  %382 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %381)
>  %383 = fmul float %382, %149
>  %384 = shl i32 %380, 4
>  %385 = add i32 %384, 4
>  %386 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %385)
>  %387 = fmul float %386, %149
>  %388 = shl i32 %380, 4
>  %389 = add i32 %388, 8
>  %390 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %389)
>  %391 = fmul float %390, %149
>  %392 = shl i32 %380, 4
>  %393 = add i32 %392, 12
>  %394 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %393)
>  %395 = fmul float %394, %149
>  %396 = bitcast float %375 to i32
>  %397 = shl i32 %396, 4
>  %398 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %397)
>  %399 = fmul float %398, %150
>  %400 = fadd float %399, %383
>  %401 = shl i32 %396, 4
>  %402 = add i32 %401, 4
>  %403 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %402)
>  %404 = fmul float %403, %150
>  %405 = fadd float %404, %387
>  %406 = shl i32 %396, 4
>  %407 = add i32 %406, 8
>  %408 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %407)
>  %409 = fmul float %408, %150
>  %410 = fadd float %409, %391
>  %411 = shl i32 %396, 4
>  %412 = add i32 %411, 12
>  %413 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %412)
>  %414 = fmul float %413, %150
>  %415 = fadd float %414, %395
>  %416 = bitcast float %371 to i32
>  %417 = shl i32 %416, 4
>  %418 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %417)
>  %419 = fmul float %418, %151
>  %420 = fadd float %419, %400
>  %421 = shl i32 %416, 4
>  %422 = add i32 %421, 4
>  %423 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %422)
>  %424 = fmul float %423, %151
>  %425 = fadd float %424, %405
>  %426 = shl i32 %416, 4
>  %427 = add i32 %426, 8
>  %428 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %427)
>  %429 = fmul float %428, %151
>  %430 = fadd float %429, %410
>  %431 = shl i32 %416, 4
>  %432 = add i32 %431, 12
>  %433 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %432)
>  %434 = fmul float %433, %151
>  %435 = fadd float %434, %415
>  %436 = bitcast float %367 to i32
>  %437 = shl i32 %436, 4
>  %438 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %437)
>  %439 = fmul float %438, %167
>  %440 = fadd float %439, %420
>  %441 = shl i32 %436, 4
>  %442 = add i32 %441, 4
>  %443 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %442)
>  %444 = fmul float %443, %167
>  %445 = fadd float %444, %425
>  %446 = shl i32 %436, 4
>  %447 = add i32 %446, 8
>  %448 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %447)
>  %449 = fmul float %448, %167
>  %450 = fadd float %449, %430
>  %451 = shl i32 %436, 4
>  %452 = add i32 %451, 12
>  %453 = call float @llvm.SI.load.const(<16 x i8> %10, i32 %452)
>  %454 = fmul float %453, %167
>  %455 = fadd float %454, %435
>  %456 = fmul float %97, %256
>  %457 = fmul float %98, %261
>  %458 = fadd float %456, %457
>  %459 = fmul float %99, %266
>  %460 = fadd float %458, %459
>  %461 = fmul float %100, %271
>  %462 = fadd float %460, %461
>  %463 = fmul float %97, %348
>  %464 = fmul float %98, %353
>  %465 = fadd float %463, %464
>  %466 = fmul float %99, %358
>  %467 = fadd float %465, %466
>  %468 = fmul float %100, %363
>  %469 = fadd float %467, %468
>  %470 = fmul float %97, %440
>  %471 = fmul float %98, %445
>  %472 = fadd float %470, %471
>  %473 = fmul float %99, %450
>  %474 = fadd float %472, %473
>  %475 = fmul float %100, %455
>  %476 = fadd float %474, %475
>  %477 = fmul float %153, %256
>  %478 = fmul float %158, %261
>  %479 = fadd float %478, %477
>  %480 = fmul float %157, %266
>  %481 = fadd float %479, %480
>  %482 = fmul float %153, %348
>  %483 = fmul float %158, %353
>  %484 = fadd float %483, %482
>  %485 = fmul float %157, %358
>  %486 = fadd float %484, %485
>  %487 = fmul float %153, %440
>  %488 = fmul float %158, %445
>  %489 = fadd float %488, %487
>  %490 = fmul float %157, %450
>  %491 = fadd float %489, %490
>  br label %ENDIF
>
>ENDIF:                                            ; preds = %main_body, %IF
>  %temp.0 = phi float [ %462, %IF ], [ %97, %main_body ]
>  %temp1.0 = phi float [ %469, %IF ], [ %98, %main_body ]
>  %temp2.0 = phi float [ %476, %IF ], [ %99, %main_body ]
>  %temp8.0 = phi float [ %481, %IF ], [ %153, %main_body ]
>  %temp9.0 = phi float [ %486, %IF ], [ %158, %main_body ]
>  %temp10.0 = phi float [ %491, %IF ], [ %157, %main_body ]
>  %492 = fmul float %temp.0, %11
>  %493 = fmul float %temp1.0, %12
>  %494 = fadd float %492, %493
>  %495 = fmul float %temp2.0, %13
>  %496 = fadd float %494, %495
>  %497 = fmul float %100, %14
>  %498 = fadd float %496, %497
>  %499 = fmul float %temp.0, %15
>  %500 = fmul float %temp1.0, %16
>  %501 = fadd float %499, %500
>  %502 = fmul float %temp2.0, %17
>  %503 = fadd float %501, %502
>  %504 = fmul float %100, %18
>  %505 = fadd float %503, %504
>  %506 = fmul float %temp.0, %19
>  %507 = fmul float %temp1.0, %20
>  %508 = fadd float %506, %507
>  %509 = fmul float %temp2.0, %21
>  %510 = fadd float %508, %509
>  %511 = fmul float %100, %22
>  %512 = fadd float %510, %511
>  %513 = fmul float %temp.0, %23
>  %514 = fmul float %temp1.0, %24
>  %515 = fadd float %513, %514
>  %516 = fmul float %temp2.0, %25
>  %517 = fadd float %515, %516
>  %518 = fmul float %100, %26
>  %519 = fadd float %517, %518
>  %520 = fmul float %temp.0, %27
>  %521 = fmul float %temp1.0, %28
>  %522 = fadd float %520, %521
>  %523 = fmul float %temp2.0, %29
>  %524 = fadd float %522, %523
>  %525 = fmul float %100, %30
>  %526 = fadd float %524, %525
>  %527 = fmul float %temp.0, %31
>  %528 = fmul float %temp1.0, %32
>  %529 = fadd float %527, %528
>  %530 = fmul float %temp2.0, %33
>  %531 = fadd float %529, %530
>  %532 = fmul float %100, %34
>  %533 = fadd float %531, %532
>  %534 = fmul float %temp.0, %35
>  %535 = fmul float %temp1.0, %36
>  %536 = fadd float %534, %535
>  %537 = fmul float %temp2.0, %37
>  %538 = fadd float %536, %537
>  %539 = fmul float %100, %38
>  %540 = fadd float %538, %539
>  %541 = fmul float %27, %27
>  %542 = fmul float %28, %28
>  %543 = fadd float %542, %541
>  %544 = fmul float %29, %29
>  %545 = fadd float %543, %544
>  %546 = fdiv float 1.000000e+00, %545
>  %547 = fmul float %27, %546
>  %548 = fmul float %28, %546
>  %549 = fmul float %29, %546
>  %550 = fmul float %temp8.0, %547
>  %551 = fmul float %temp9.0, %548
>  %552 = fadd float %551, %550
>  %553 = fmul float %temp10.0, %549
>  %554 = fadd float %552, %553
>  %555 = fmul float %31, %31
>  %556 = fmul float %32, %32
>  %557 = fadd float %556, %555
>  %558 = fmul float %33, %33
>  %559 = fadd float %557, %558
>  %560 = fdiv float 1.000000e+00, %559
>  %561 = fmul float %31, %560
>  %562 = fmul float %32, %560
>  %563 = fmul float %33, %560
>  %564 = fmul float %temp8.0, %561
>  %565 = fmul float %temp9.0, %562
>  %566 = fadd float %565, %564
>  %567 = fmul float %temp10.0, %563
>  %568 = fadd float %566, %567
>  %569 = fmul float %35, %35
>  %570 = fmul float %36, %36
>  %571 = fadd float %570, %569
>  %572 = fmul float %37, %37
>  %573 = fadd float %571, %572
>  %574 = fdiv float 1.000000e+00, %573
>  %575 = fmul float %35, %574
>  %576 = fmul float %36, %574
>  %577 = fmul float %37, %574
>  %578 = fmul float %temp8.0, %575
>  %579 = fmul float %temp9.0, %576
>  %580 = fadd float %579, %578
>  %581 = fmul float %temp10.0, %577
>  %582 = fadd float %580, %581
>  %583 = fmul float %554, %554
>  %584 = fmul float %568, %568
>  %585 = fadd float %584, %583
>  %586 = fmul float %582, %582
>  %587 = fadd float %585, %586
>  %588 = call float @llvm.AMDGPU.rsq(float %587)
>  %589 = fmul float %554, %588
>  %590 = fmul float %568, %588
>  %591 = fmul float %582, %588
>  %592 = fcmp uge float %80, 0.000000e+00
>  %593 = select i1 %592, float 1.000000e+00, float 0.000000e+00
>  %594 = fsub float -0.000000e+00, %593
>  %595 = fptosi float %594 to i32
>  %596 = bitcast i32 %595 to float
>  %597 = bitcast float %596 to i32
>  %598 = icmp ne i32 %597, 0
>  %. = select i1 %598, float %526, float %125
>  %599 = fcmp uge float %80, 0.000000e+00
>  %600 = select i1 %599, float 1.000000e+00, float 0.000000e+00
>  %601 = fsub float -0.000000e+00, %600
>  %602 = fptosi float %601 to i32
>  %603 = bitcast i32 %602 to float
>  %604 = bitcast float %603 to i32
>  %605 = icmp ne i32 %604, 0
>  %temp24.0 = select i1 %605, float %533, float %126
>  %606 = fcmp uge float %78, 0.000000e+00
>  %607 = select i1 %606, float 1.000000e+00, float 0.000000e+00
>  %608 = fsub float -0.000000e+00, %607
>  %609 = fptosi float %608 to i32
>  %610 = bitcast i32 %609 to float
>  %611 = bitcast float %610 to i32
>  %612 = icmp ne i32 %611, 0
>  %.. = select i1 %612, float %540, float %.
>  %613 = fcmp uge float %79, 0.000000e+00
>  %614 = select i1 %613, float 1.000000e+00, float 0.000000e+00
>  %615 = fsub float -0.000000e+00, %614
>  %616 = fptosi float %615 to i32
>  %617 = bitcast i32 %616 to float
>  %618 = bitcast float %617 to i32
>  %619 = icmp ne i32 %618, 0
>  %temp20.1 = select i1 %619, float %540, float %temp24.0
>  %620 = fcmp uge float %83, 0.000000e+00
>  %621 = select i1 %620, float 1.000000e+00, float 0.000000e+00
>  %622 = fsub float -0.000000e+00, %621
>  %623 = fptosi float %622 to i32
>  %624 = bitcast i32 %623 to float
>  %625 = bitcast float %624 to i32
>  %626 = icmp ne i32 %625, 0
>  %.139 = select i1 %626, float %526, float %110
>  %627 = fcmp uge float %83, 0.000000e+00
>  %628 = select i1 %627, float 1.000000e+00, float 0.000000e+00
>  %629 = fsub float -0.000000e+00, %628
>  %630 = fptosi float %629 to i32
>  %631 = bitcast i32 %630 to float
>  %632 = bitcast float %631 to i32
>  %633 = icmp ne i32 %632, 0
>  %temp28.1 = select i1 %633, float %533, float %111
>  %634 = fcmp uge float %81, 0.000000e+00
>  %635 = select i1 %634, float 1.000000e+00, float 0.000000e+00
>  %636 = fsub float -0.000000e+00, %635
>  %637 = fptosi float %636 to i32
>  %638 = bitcast i32 %637 to float
>  %639 = bitcast float %638 to i32
>  %640 = icmp ne i32 %639, 0
>  %..139 = select i1 %640, float %540, float %.139
>  %641 = fcmp uge float %82, 0.000000e+00
>  %642 = select i1 %641, float 1.000000e+00, float 0.000000e+00
>  %643 = fsub float -0.000000e+00, %642
>  %644 = fptosi float %643 to i32
>  %645 = bitcast i32 %644 to float
>  %646 = bitcast float %645 to i32
>  %647 = icmp ne i32 %646, 0
>  %temp24.2 = select i1 %647, float %540, float %temp28.1
>  %648 = fcmp uge float %86, 0.000000e+00
>  %649 = select i1 %648, float 1.000000e+00, float 0.000000e+00
>  %650 = fsub float -0.000000e+00, %649
>  %651 = fptosi float %650 to i32
>  %652 = bitcast i32 %651 to float
>  %653 = bitcast float %652 to i32
>  %654 = icmp ne i32 %653, 0
>  %.140 = select i1 %654, float %526, float %130
>  %655 = fcmp uge float %86, 0.000000e+00
>  %656 = select i1 %655, float 1.000000e+00, float 0.000000e+00
>  %657 = fsub float -0.000000e+00, %656
>  %658 = fptosi float %657 to i32
>  %659 = bitcast i32 %658 to float
>  %660 = bitcast float %659 to i32
>  %661 = icmp ne i32 %660, 0
>  %temp32.1 = select i1 %661, float %533, float %131
>  %662 = fcmp uge float %84, 0.000000e+00
>  %663 = select i1 %662, float 1.000000e+00, float 0.000000e+00
>  %664 = fsub float -0.000000e+00, %663
>  %665 = fptosi float %664 to i32
>  %666 = bitcast i32 %665 to float
>  %667 = bitcast float %666 to i32
>  %668 = icmp ne i32 %667, 0
>  %..140 = select i1 %668, float %540, float %.140
>  %669 = fcmp uge float %85, 0.000000e+00
>  %670 = select i1 %669, float 1.000000e+00, float 0.000000e+00
>  %671 = fsub float -0.000000e+00, %670
>  %672 = fptosi float %671 to i32
>  %673 = bitcast i32 %672 to float
>  %674 = bitcast float %673 to i32
>  %675 = icmp ne i32 %674, 0
>  %temp28.3 = select i1 %675, float %540, float %temp32.1
>  %676 = fcmp uge float %89, 0.000000e+00
>  %677 = select i1 %676, float 1.000000e+00, float 0.000000e+00
>  %678 = fsub float -0.000000e+00, %677
>  %679 = fptosi float %678 to i32
>  %680 = bitcast i32 %679 to float
>  %681 = bitcast float %680 to i32
>  %682 = icmp ne i32 %681, 0
>  %.141 = select i1 %682, float %526, float %115
>  %683 = fcmp uge float %89, 0.000000e+00
>  %684 = select i1 %683, float 1.000000e+00, float 0.000000e+00
>  %685 = fsub float -0.000000e+00, %684
>  %686 = fptosi float %685 to i32
>  %687 = bitcast i32 %686 to float
>  %688 = bitcast float %687 to i32
>  %689 = icmp ne i32 %688, 0
>  %temp36.1 = select i1 %689, float %533, float %116
>  %690 = fcmp uge float %87, 0.000000e+00
>  %691 = select i1 %690, float 1.000000e+00, float 0.000000e+00
>  %692 = fsub float -0.000000e+00, %691
>  %693 = fptosi float %692 to i32
>  %694 = bitcast i32 %693 to float
>  %695 = bitcast float %694 to i32
>  %696 = icmp ne i32 %695, 0
>  %..141 = select i1 %696, float %540, float %.141
>  %697 = fcmp uge float %88, 0.000000e+00
>  %698 = select i1 %697, float 1.000000e+00, float 0.000000e+00
>  %699 = fsub float -0.000000e+00, %698
>  %700 = fptosi float %699 to i32
>  %701 = bitcast i32 %700 to float
>  %702 = bitcast float %701 to i32
>  %703 = icmp ne i32 %702, 0
>  %temp12.0 = select i1 %703, float %540, float %temp36.1
>  %704 = fmul float %120, %71
>  %705 = fadd float %704, %73
>  %706 = fmul float %121, %72
>  %707 = fadd float %706, %74
>  %708 = fmul float %.., %63
>  %709 = fmul float %temp20.1, %64
>  %710 = fadd float %708, %709
>  %711 = fmul float 0.000000e+00, %65
>  %712 = fadd float %710, %711
>  %713 = fmul float 1.000000e+00, %66
>  %714 = fadd float %712, %713
>  %715 = fmul float %.., %67
>  %716 = fmul float %temp20.1, %68
>  %717 = fadd float %715, %716
>  %718 = fmul float 0.000000e+00, %69
>  %719 = fadd float %717, %718
>  %720 = fmul float 1.000000e+00, %70
>  %721 = fadd float %719, %720
>  %722 = fmul float %..139, %39
>  %723 = fmul float %temp24.2, %40
>  %724 = fadd float %722, %723
>  %725 = fmul float 0.000000e+00, %41
>  %726 = fadd float %724, %725
>  %727 = fmul float 1.000000e+00, %42
>  %728 = fadd float %726, %727
>  %729 = fmul float %..139, %43
>  %730 = fmul float %temp24.2, %44
>  %731 = fadd float %729, %730
>  %732 = fmul float 0.000000e+00, %45
>  %733 = fadd float %731, %732
>  %734 = fmul float 1.000000e+00, %46
>  %735 = fadd float %733, %734
>  %736 = fmul float %..140, %55
>  %737 = fmul float %temp28.3, %56
>  %738 = fadd float %736, %737
>  %739 = fmul float 0.000000e+00, %57
>  %740 = fadd float %738, %739
>  %741 = fmul float 1.000000e+00, %58
>  %742 = fadd float %740, %741
>  %743 = fmul float %..140, %59
>  %744 = fmul float %temp28.3, %60
>  %745 = fadd float %743, %744
>  %746 = fmul float 0.000000e+00, %61
>  %747 = fadd float %745, %746
>  %748 = fmul float 1.000000e+00, %62
>  %749 = fadd float %747, %748
>  %750 = fmul float %..141, %47
>  %751 = fmul float %temp12.0, %48
>  %752 = fadd float %750, %751
>  %753 = fmul float 0.000000e+00, %49
>  %754 = fadd float %752, %753
>  %755 = fmul float 1.000000e+00, %50
>  %756 = fadd float %754, %755
>  %757 = fmul float %..141, %51
>  %758 = fmul float %temp12.0, %52
>  %759 = fadd float %757, %758
>  %760 = fmul float 0.000000e+00, %53
>  %761 = fadd float %759, %760
>  %762 = fmul float 1.000000e+00, %54
>  %763 = fadd float %761, %762
>  %764 = fmul float %137, %75
>  %765 = fadd float %764, %77
>  %766 = fmul float %136, %75
>  %767 = fadd float %766, %77
>  %768 = fmul float %135, %75
>  %769 = fadd float %768, %77
>  %770 = fmul float %138, %76
>  %771 = fadd float %770, %77
>  %772 = fmul float %765, %765
>  %773 = fmul float %767, %767
>  %774 = fmul float %769, %769
>  %775 = getelementptr <16 x i8> addrspace(2)* %0, i32 1
>  %776 = load <16 x i8> addrspace(2)* %775, !tbaa !0
>  %777 = call float @llvm.SI.load.const(<16 x i8> %776, i32 0)
>  %778 = fmul float %777, %498
>  %779 = call float @llvm.SI.load.const(<16 x i8> %776, i32 4)
>  %780 = fmul float %779, %505
>  %781 = fadd float %778, %780
>  %782 = call float @llvm.SI.load.const(<16 x i8> %776, i32 8)
>  %783 = fmul float %782, %512
>  %784 = fadd float %781, %783
>  %785 = call float @llvm.SI.load.const(<16 x i8> %776, i32 12)
>  %786 = fmul float %785, %519
>  %787 = fadd float %784, %786
>  %788 = call float @llvm.SI.load.const(<16 x i8> %776, i32 16)
>  %789 = fmul float %788, %498
>  %790 = call float @llvm.SI.load.const(<16 x i8> %776, i32 20)
>  %791 = fmul float %790, %505
>  %792 = fadd float %789, %791
>  %793 = call float @llvm.SI.load.const(<16 x i8> %776, i32 24)
>  %794 = fmul float %793, %512
>  %795 = fadd float %792, %794
>  %796 = call float @llvm.SI.load.const(<16 x i8> %776, i32 28)
>  %797 = fmul float %796, %519
>  %798 = fadd float %795, %797
>  %799 = call float @llvm.SI.load.const(<16 x i8> %776, i32 32)
>  %800 = fmul float %799, %498
>  %801 = call float @llvm.SI.load.const(<16 x i8> %776, i32 36)
>  %802 = fmul float %801, %505
>  %803 = fadd float %800, %802
>  %804 = call float @llvm.SI.load.const(<16 x i8> %776, i32 40)
>  %805 = fmul float %804, %512
>  %806 = fadd float %803, %805
>  %807 = call float @llvm.SI.load.const(<16 x i8> %776, i32 44)
>  %808 = fmul float %807, %519
>  %809 = fadd float %806, %808
>  %810 = call float @llvm.SI.load.const(<16 x i8> %776, i32 48)
>  %811 = fmul float %810, %498
>  %812 = call float @llvm.SI.load.const(<16 x i8> %776, i32 52)
>  %813 = fmul float %812, %505
>  %814 = fadd float %811, %813
>  %815 = call float @llvm.SI.load.const(<16 x i8> %776, i32 56)
>  %816 = fmul float %815, %512
>  %817 = fadd float %814, %816
>  %818 = call float @llvm.SI.load.const(<16 x i8> %776, i32 60)
>  %819 = fmul float %818, %519
>  %820 = fadd float %817, %819
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 14, i32 0, float %787, float %798, float %809, float %820)
>  %821 = call float @llvm.SI.load.const(<16 x i8> %776, i32 64)
>  %822 = fmul float %821, %498
>  %823 = call float @llvm.SI.load.const(<16 x i8> %776, i32 68)
>  %824 = fmul float %823, %505
>  %825 = fadd float %822, %824
>  %826 = call float @llvm.SI.load.const(<16 x i8> %776, i32 72)
>  %827 = fmul float %826, %512
>  %828 = fadd float %825, %827
>  %829 = call float @llvm.SI.load.const(<16 x i8> %776, i32 76)
>  %830 = fmul float %829, %519
>  %831 = fadd float %828, %830
>  %832 = call float @llvm.SI.load.const(<16 x i8> %776, i32 80)
>  %833 = fmul float %832, %498
>  %834 = call float @llvm.SI.load.const(<16 x i8> %776, i32 84)
>  %835 = fmul float %834, %505
>  %836 = fadd float %833, %835
>  %837 = call float @llvm.SI.load.const(<16 x i8> %776, i32 88)
>  %838 = fmul float %837, %512
>  %839 = fadd float %836, %838
>  %840 = call float @llvm.SI.load.const(<16 x i8> %776, i32 92)
>  %841 = fmul float %840, %519
>  %842 = fadd float %839, %841
>  %843 = call float @llvm.SI.load.const(<16 x i8> %776, i32 96)
>  %844 = fmul float %843, %498
>  %845 = call float @llvm.SI.load.const(<16 x i8> %776, i32 100)
>  %846 = fmul float %845, %505
>  %847 = fadd float %844, %846
>  %848 = call float @llvm.SI.load.const(<16 x i8> %776, i32 104)
>  %849 = fmul float %848, %512
>  %850 = fadd float %847, %849
>  %851 = call float @llvm.SI.load.const(<16 x i8> %776, i32 108)
>  %852 = fmul float %851, %519
>  %853 = fadd float %850, %852
>  %854 = call float @llvm.SI.load.const(<16 x i8> %776, i32 112)
>  %855 = fmul float %854, %498
>  %856 = call float @llvm.SI.load.const(<16 x i8> %776, i32 116)
>  %857 = fmul float %856, %505
>  %858 = fadd float %855, %857
>  %859 = call float @llvm.SI.load.const(<16 x i8> %776, i32 120)
>  %860 = fmul float %859, %512
>  %861 = fadd float %858, %860
>  %862 = call float @llvm.SI.load.const(<16 x i8> %776, i32 124)
>  %863 = fmul float %862, %519
>  %864 = fadd float %861, %863
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float %831, float %842, float %853, float %864)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %526, float %533, float %540, float 1.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %728, float %735, float %742, float %749)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %705, float %707, float %714, float %721)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %756, float %763, float 0.000000e+00, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %772, float %773, float %774, float %771)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %589, float %590, float %591, float 0.000000e+00)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float 0.000000e+00, float 0.000000e+00, float %769, float %771)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %498, float %505, float %512, float %519)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.rsq(float) #2
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0840704
>bf8c007f
>e00c2000
>80021b00
>c0840100
>bf8c0070
>c2010992
>c2018990
>bf8c007f
>7e020203
>d2820006
>0404051d
>d2820001
>0404051b
>c0860724
>bf8c007f
>e00c2000
>80034b00
>c0860720
>bf8c0070
>e00c2000
>80036a00
>c086071c
>bf8c0070
>e00c2000
>80030200
>c0860718
>bf8c0070
>e00c2000
>80031700
>c0860714
>bf8c0070
>e00c2000
>80030f00
>c0860710
>bf8c0070
>e00c2000
>80030b00
>c086070c
>bf8c0070
>e00c2000
>80030700
>c0860708
>bf8c0070
>e00c2000
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>10c69804
>c2020108
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>058e9604
>c202010a
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>c202010b
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>d2820063
>058e9c04
>c2020105
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>10c89804
>c2020104
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>05929604
>c2020106
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>05929a04
>c2020107
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>d2820064
>05929c04
>c2020101
>bf8c007f
>10ca9804
>c2020100
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>d2820065
>05969604
>c2020102
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>d2820065
>05969a04
>c2020103
>bf8c007f
>d2820065
>05969c04
>f80000ef
>62636465
>c202011d
>bf8c000f
>10c49804
>c202011c
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>d2820062
>058a9604
>c202011e
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>c202011f
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>c2020119
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>10c69804
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>c202011a
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>d2820062
>058a5378
>d2820062
>058a5176
>d2820023
>058abf26
>7e4802f2
>f800020f
>24616023
>d00c0000
>02010156
>bf8c070f
>d2000024
>0001e480
>d2060024
>22010124
>7e481124
>d10a0000
>02010124
>d2000024
>00024717
>d00c0002
>02010155
>d2000025
>0009e480
>d2060025
>22010125
>7e4a1125
>d10a0002
>02010125
>d2000024
>000ac324
>d2000017
>0002c118
>d00c0000
>02010148
>d2000018
>0001e480
>d2060018
>22010118
>7e301118
>d10a0000
>02010118
>d2000018
>0002c317
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>d2820017
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>d2820017
>045d015a
>062eb117
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>d2820018
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>02010147
>d2000019
>0001e480
>d2060019
>22010119
>7e321119
>d10a0000
>02010119
>d2000019
>00024713
>d00c0002
>02010146
>d200001a
>0009e480
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>2201011a
>7e34111a
>d10a0002
>0201011a
>d2000019
>000ac319
>d2000013
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>02010145
>d2000014
>0001e480
>d2060014
>22010114
>7e281114
>d10a0000
>02010114
>d2000013
>0002c313
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>0452a719
>d2820014
>04510150
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>1026a513
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>044ea319
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>044d014f
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>02010110
>d2000010
>0002c30f
>101e8510
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>043e8313
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>043d013e
>061e770f
>10208110
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>0441013d
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>0f10110b
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>0001e480
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>2201010b
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>d10a0000
>0201010b
>d200000b
>00024707
>d00c0002
>02010122
>d200000c
>0009e480
>d206000c
>2201010c
>7e18110c
>d10a0002
>0201010c
>d200000b
>000ac30b
>d2000007
>0002c108
>d00c0000
>0201011f
>d2000008
>0001e480
>d2060008
>22010108
>7e101108
>d10a0000
>02010108
>d2000007
>0002c307
>10106b07
>d2820008
>0422690b
>d2820008
>0421012f
>06105b08
>100e6707
>d2820007
>041e650b
>d2820007
>041d012e
>06125907
>7e0e0280
>f800023f
>07070809
>bf8c070f
>d2820008
>046e3b05
>d2820009
>046e3902
>10141309
>d282000b
>046e3903
>1016170b
>d2820002
>046e3904
>10040502
>f800024f
>080a0b02
>bf8c070f
>10046130
>d2820002
>040a6331
>d2820002
>040a572b
>7e045502
>10060531
>10080530
>10080901
>d2820003
>04120700
>1004052b
>d2820002
>040e0506
>10065329
>d2820003
>040e552a
>d2820003
>040e5128
>7e065503
>1008072a
>100a0729
>100a0b01
>d2820004
>04160900
>10060728
>d2820003
>04120706
>10080703
>d2820004
>04120502
>100a4120
>d2820005
>04164321
>d2820005
>04163d1e
>7e0a5505
>10140b21
>10160b20
>10021701
>d2820000
>04061500
>10020b1e
>d2820000
>04020306
>d2820001
>04120100
>7e025b01
>10000300
>10040302
>10020303
>f800025f
>07000201
>f800026f
>08090707
>f80008cf
>4e4d4c4b
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..1]
>DCL TEMP[0..4], LOCAL
>IMM[0] FLT32 {65504.0000,     0.0000,     0.5000,    12.9200}
>IMM[1] FLT32 {    0.4167,     1.0550,    -0.0550,     0.0031}
>IMM[2] FLT32 {    0.2125,     0.7154,     0.0721,     0.0000}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MIN TEMP[0], TEMP[0], IMM[0].xxxx
>  3: MAX TEMP[0], TEMP[0], IMM[0].yyyy
>  4: MOV TEMP[1].w, TEMP[0].wwww
>  5: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[0].xxxx
>  6: MOV TEMP[0].xy, IMM[0].zzzz
>  7: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
>  8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
>  9: MUL TEMP[2].xyz, TEMP[1].xyzz, IMM[0].wwww
> 10: POW TEMP[3].x, TEMP[1].xxxx, IMM[1].xxxx
> 11: POW TEMP[3].y, TEMP[1].yyyy, IMM[1].xxxx
> 12: POW TEMP[3].z, TEMP[1].zzzz, IMM[1].xxxx
> 13: MAD TEMP[3].xyz, TEMP[3].xyzz, IMM[1].yyyy, IMM[1].zzzz
> 14: SLT TEMP[4].x, TEMP[1].xxxx, IMM[1].wwww
> 15: F2I TEMP[4].x, -TEMP[4]
> 16: UIF TEMP[4].xxxx :0
> 17:   MOV TEMP[4].x, TEMP[2].xxxx
> 18: ELSE :0
> 19:   MOV TEMP[4].x, TEMP[3].xxxx
> 20: ENDIF
> 21: MOV TEMP[0].x, TEMP[4].xxxx
> 22: SLT TEMP[4].x, TEMP[1].yyyy, IMM[1].wwww
> 23: F2I TEMP[4].x, -TEMP[4]
> 24: UIF TEMP[4].xxxx :0
> 25:   MOV TEMP[4].x, TEMP[2].yyyy
> 26: ELSE :0
> 27:   MOV TEMP[4].x, TEMP[3].yyyy
> 28: ENDIF
> 29: MOV TEMP[0].y, TEMP[4].xxxx
> 30: SLT TEMP[4].x, TEMP[1].zzzz, IMM[1].wwww
> 31: F2I TEMP[4].x, -TEMP[4]
> 32: UIF TEMP[4].xxxx :0
> 33:   MOV TEMP[2].x, TEMP[2].zzzz
> 34: ELSE :0
> 35:   MOV TEMP[2].x, TEMP[3].zzzz
> 36: ENDIF
> 37: MOV TEMP[0].z, TEMP[2].xxxx
> 38: MOV_SAT TEMP[1].xyz, TEMP[0].xyzz
> 39: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[2].xyzz
> 40: LRP TEMP[0].xyz, CONST[1].yyyy, TEMP[1].xyzz, TEMP[0].xxxx
> 41: LRP TEMP[1].xyz, CONST[1].zzzz, CONST[1].wwww, TEMP[0].xyzz
> 42: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
> 43: MOV OUT[0], TEMP[1]
> 44: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0
>  %32 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0
>  %34 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %35 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %36 = bitcast float %34 to i32
>  %37 = bitcast float %35 to i32
>  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
>  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
>  %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = extractelement <4 x float> %40, i32 3
>  %45 = fcmp uge float %41, 6.550400e+04
>  %46 = select i1 %45, float 6.550400e+04, float %41
>  %47 = fcmp uge float %42, 6.550400e+04
>  %48 = select i1 %47, float 6.550400e+04, float %42
>  %49 = fcmp uge float %43, 6.550400e+04
>  %50 = select i1 %49, float 6.550400e+04, float %43
>  %51 = fcmp uge float %44, 6.550400e+04
>  %52 = select i1 %51, float 6.550400e+04, float %44
>  %53 = fcmp uge float %46, 0.000000e+00
>  %54 = select i1 %53, float %46, float 0.000000e+00
>  %55 = fcmp uge float %48, 0.000000e+00
>  %56 = select i1 %55, float %48, float 0.000000e+00
>  %57 = fcmp uge float %50, 0.000000e+00
>  %58 = select i1 %57, float %50, float 0.000000e+00
>  %59 = fcmp uge float %52, 0.000000e+00
>  %60 = select i1 %59, float %52, float 0.000000e+00
>  %61 = fmul float %54, %22
>  %62 = fmul float %56, %22
>  %63 = fmul float %58, %22
>  %64 = bitcast float 5.000000e-01 to i32
>  %65 = bitcast float 5.000000e-01 to i32
>  %66 = insertelement <2 x i32> undef, i32 %64, i32 0
>  %67 = insertelement <2 x i32> %66, i32 %65, i32 1
>  %68 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %67, <32 x i8> %31, <16 x i8> %33, i32 2)
>  %69 = extractelement <4 x float> %68, i32 0
>  %70 = fmul float %61, %69
>  %71 = fmul float %62, %69
>  %72 = fmul float %63, %69
>  %73 = fmul float %70, 0x4029D70A40000000
>  %74 = fmul float %71, 0x4029D70A40000000
>  %75 = fmul float %72, 0x4029D70A40000000
>  %76 = call float @llvm.pow.f32(float %70, float 0x3FDAAAAAA0000000)
>  %77 = call float @llvm.pow.f32(float %71, float 0x3FDAAAAAA0000000)
>  %78 = call float @llvm.pow.f32(float %72, float 0x3FDAAAAAA0000000)
>  %79 = fmul float %76, 0x3FF0E147A0000000
>  %80 = fadd float %79, 0xBFAC28F5C0000000
>  %81 = fmul float %77, 0x3FF0E147A0000000
>  %82 = fadd float %81, 0xBFAC28F5C0000000
>  %83 = fmul float %78, 0x3FF0E147A0000000
>  %84 = fadd float %83, 0xBFAC28F5C0000000
>  %85 = fcmp ult float %70, 0x3F69A5C380000000
>  %86 = select i1 %85, float 1.000000e+00, float 0.000000e+00
>  %87 = fsub float -0.000000e+00, %86
>  %88 = fptosi float %87 to i32
>  %89 = bitcast i32 %88 to float
>  %90 = bitcast float %89 to i32
>  %91 = icmp ne i32 %90, 0
>  %. = select i1 %91, float %73, float %80
>  %92 = fcmp ult float %71, 0x3F69A5C380000000
>  %93 = select i1 %92, float 1.000000e+00, float 0.000000e+00
>  %94 = fsub float -0.000000e+00, %93
>  %95 = fptosi float %94 to i32
>  %96 = bitcast i32 %95 to float
>  %97 = bitcast float %96 to i32
>  %98 = icmp ne i32 %97, 0
>  %temp16.1 = select i1 %98, float %74, float %82
>  %99 = fcmp ult float %72, 0x3F69A5C380000000
>  %100 = select i1 %99, float 1.000000e+00, float 0.000000e+00
>  %101 = fsub float -0.000000e+00, %100
>  %102 = fptosi float %101 to i32
>  %103 = bitcast i32 %102 to float
>  %104 = bitcast float %103 to i32
>  %105 = icmp ne i32 %104, 0
>  %.26 = select i1 %105, float %75, float %84
>  %106 = call float @llvm.AMDIL.clamp.(float %., float 0.000000e+00, float 1.000000e+00)
>  %107 = call float @llvm.AMDIL.clamp.(float %temp16.1, float 0.000000e+00, float 1.000000e+00)
>  %108 = call float @llvm.AMDIL.clamp.(float %.26, float 0.000000e+00, float 1.000000e+00)
>  %109 = fmul float %106, 0x3FCB333340000000
>  %110 = fmul float %107, 0x3FE6E48E80000000
>  %111 = fadd float %110, %109
>  %112 = fmul float %108, 0x3FB2752540000000
>  %113 = fadd float %111, %112
>  %114 = call float @llvm.AMDGPU.lrp(float %23, float %106, float %113)
>  %115 = call float @llvm.AMDGPU.lrp(float %23, float %107, float %113)
>  %116 = call float @llvm.AMDGPU.lrp(float %23, float %108, float %113)
>  %117 = call float @llvm.AMDGPU.lrp(float %24, float %25, float %114)
>  %118 = call float @llvm.AMDGPU.lrp(float %24, float %25, float %115)
>  %119 = call float @llvm.AMDGPU.lrp(float %24, float %25, float %116)
>  %120 = call float @llvm.AMDIL.clamp.(float %117, float 0.000000e+00, float 1.000000e+00)
>  %121 = call float @llvm.AMDIL.clamp.(float %118, float 0.000000e+00, float 1.000000e+00)
>  %122 = call float @llvm.AMDIL.clamp.(float %119, float 0.000000e+00, float 1.000000e+00)
>  %123 = call i32 @llvm.SI.packf16(float %120, float %121)
>  %124 = bitcast i32 %123 to float
>  %125 = call i32 @llvm.SI.packf16(float %122, float %60)
>  %126 = bitcast i32 %125 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %124, float %126, float %124, float %126)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.pow.f32(float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>7e0802ff
>477fe000
>bf8c0770
>d00c0006
>02020901
>d2000005
>001a0901
>d00c0006
>02010105
>d2000005
>001a0a80
>c0840100
>bf8c007f
>c2000900
>bf8c007f
>100a0a00
>7e0c02f0
>7e0e0306
>c0860304
>c0c80508
>bf8c007f
>f0800100
>00640606
>bf8c0770
>100a0d05
>7e0e4f05
>0e0e0eff
>3ed55555
>7e124b07
>7e0e02ff
>bd6147ae
>7e1002ff
>3f870a3d
>d282000a
>041e1109
>10160aff
>414eb852
>7e1202ff
>3b4d2e1c
>d0020002
>02021305
>d2000005
>0009e480
>d2060005
>22010105
>7e0a1105
>d10a0002
>02010105
>d2000005
>000a170a
>d2060805
>02010105
>d00c0002
>02020900
>d200000a
>000a0900
>d00c0002
>0201010a
>d200000a
>000a1480
>10141400
>10160d0a
>7e144f0b
>0e1414ff
>3ed55555
>7e144b0a
>d282000a
>041e110a
>101816ff
>414eb852
>d0020002
>0202130b
>d200000b
>0009e480
>d206000b
>2201010b
>7e16110b
>d10a0002
>0201010b
>d200000a
>000a190a
>d206080a
>0201010a
>101614ff
>3e59999a
>7e1802ff
>3f372474
>d282000b
>042e1905
>d00c0002
>02020902
>d200000c
>000a0902
>d00c0002
>0201010c
>d200000c
>000a1880
>10181800
>10180d0c
>7e0c4f0c
>0e0c0cff
>3ed55555
>7e0c4b06
>d2820006
>041e1106
>100e18ff
>414eb852
>d0020000
>0202130c
>d2000008
>0001e480
>d2060008
>22010108
>7e101108
>d10a0000
>02010108
>d2000006
>00020f06
>d2060806
>02010106
>7e0e02ff
>3d93a92a
>d2820007
>042e0f06
>c2000905
>bf8c007f
>d2080008
>020000f2
>100e0f08
>d2820008
>041e0a00
>c2008906
>bf8c007f
>d2080005
>020002f2
>10101105
>c2010907
>bf8c007f
>7e120202
>d2820008
>04221201
>d2060808
>02010108
>d282000a
>041e1400
>10141505
>d282000a
>042a1201
>d206080a
>0201010a
>5e10110a
>d2820006
>041e0c00
>100a0d05
>d2820005
>04161201
>d2060805
>02010105
>d00c0000
>02020903
>d2000000
>00020903
>d00c0000
>02010100
>d2000000
>00020080
>5e000105
>f8001c0f
>00080008
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL CONST[0..3]
>DCL TEMP[0..5], LOCAL
>IMM[0] FLT32 {    0.0200,    12.9898,    78.2330, 43758.5469}
>IMM[1] FLT32 {    0.0000,     1.0000,     0.9500,     0.9025}
>IMM[2] FLT32 {    0.8574,     0.8145,     0.7738,     0.7351}
>IMM[3] FLT32 {    0.6983,     0.6634,     0.6302,     0.5987}
>IMM[4] FLT32 {    0.5688,     0.5404,     0.5133,     0.4877}
>IMM[5] FLT32 {    0.4633,     0.4401,     0.4181,     0.3972}
>IMM[6] FLT32 {    0.3774,     0.3585,     0.3406,     0.3235}
>IMM[7] FLT32 {    0.3074,     0.2920,     0.2774,     0.2635}
>IMM[8] FLT32 {    0.2503,     0.2378,     0.2259,     0.2146}
>IMM[9] FLT32 {    0.2039,     0.1937,     0.1840,     0.1748}
>IMM[10] FLT32 {    0.1661,     0.1578,     0.1499,     0.1424}
>IMM[11] FLT32 {    0.1353,     0.1285,     0.1221,     0.1160}
>IMM[12] FLT32 {    0.1102,     0.1047,     0.0994,     0.0945}
>IMM[13] FLT32 {    0.0897,     0.0853,     0.0810,     0.0000}
>  0: MOV TEMP[0].xy, IN[0].xyxx
>  1: ADD TEMP[1].xy, IN[0].xyyy, -CONST[0].xyyy
>  2: MUL TEMP[2].x, IMM[0].xxxx, CONST[2].wwww
>  3: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
>  4: DP2 TEMP[2].x, IN[0].xyyy, IMM[0].yzzz
>  5: SIN TEMP[2].x, TEMP[2].xxxx
>  6: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
>  7: FRC TEMP[2].x, TEMP[2].xxxx
>  8: MAD TEMP[2].x, TEMP[2].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  9: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
> 10: MUL TEMP[2].xy, IN[0].xyyy, CONST[1].zwww
> 11: MOV TEMP[0].zw, TEMP[2].yyxy
> 12: MUL TEMP[2].xy, TEMP[1].xyyy, CONST[1].zwww
> 13: MOV TEMP[1].zw, TEMP[2].yyxy
> 14: MOV TEMP[2].w, IMM[1].xxxx
> 15: ADD TEMP[0], TEMP[0], -TEMP[1]
> 16: MOV TEMP[3].xy, TEMP[0].xyyy
> 17: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
> 18: MOV TEMP[4].xy, TEMP[0].zwww
> 19: TEX TEMP[4].x, TEMP[4], SAMP[1], 2D
> 20: ABS TEMP[4].x, TEMP[4].xxxx
> 21: SGE TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz
> 22: F2I TEMP[4].x, -TEMP[4]
> 23: AND TEMP[4].x, TEMP[4].xxxx, IMM[1].yyyy
> 24: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
> 25: MOV TEMP[2].xyz, TEMP[3].xyzx
> 26: ADD TEMP[0], TEMP[0], -TEMP[1]
> 27: MOV TEMP[4].xy, TEMP[0].xyyy
> 28: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 29: MOV TEMP[5].xy, TEMP[0].zwww
> 30: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 31: ABS TEMP[5].x, TEMP[5].xxxx
> 32: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 33: F2I TEMP[5].x, -TEMP[5]
> 34: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 35: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 36: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[1].zzzz
> 37: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 38: ADD TEMP[0], TEMP[0], -TEMP[1]
> 39: MOV TEMP[4].xy, TEMP[0].xyyy
> 40: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 41: MOV TEMP[5].xy, TEMP[0].zwww
> 42: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 43: ABS TEMP[5].x, TEMP[5].xxxx
> 44: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 45: F2I TEMP[5].x, -TEMP[5]
> 46: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 47: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 48: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[1].wwww
> 49: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 50: ADD TEMP[0], TEMP[0], -TEMP[1]
> 51: MOV TEMP[4].xy, TEMP[0].xyyy
> 52: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 53: MOV TEMP[5].xy, TEMP[0].zwww
> 54: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 55: ABS TEMP[5].x, TEMP[5].xxxx
> 56: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 57: F2I TEMP[5].x, -TEMP[5]
> 58: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 59: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 60: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].xxxx
> 61: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 62: ADD TEMP[0], TEMP[0], -TEMP[1]
> 63: MOV TEMP[4].xy, TEMP[0].xyyy
> 64: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 65: MOV TEMP[5].xy, TEMP[0].zwww
> 66: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 67: ABS TEMP[5].x, TEMP[5].xxxx
> 68: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 69: F2I TEMP[5].x, -TEMP[5]
> 70: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 71: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 72: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].yyyy
> 73: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 74: ADD TEMP[0], TEMP[0], -TEMP[1]
> 75: MOV TEMP[4].xy, TEMP[0].xyyy
> 76: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 77: MOV TEMP[5].xy, TEMP[0].zwww
> 78: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 79: ABS TEMP[5].x, TEMP[5].xxxx
> 80: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 81: F2I TEMP[5].x, -TEMP[5]
> 82: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 83: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 84: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].zzzz
> 85: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 86: ADD TEMP[0], TEMP[0], -TEMP[1]
> 87: MOV TEMP[4].xy, TEMP[0].xyyy
> 88: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
> 89: MOV TEMP[5].xy, TEMP[0].zwww
> 90: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
> 91: ABS TEMP[5].x, TEMP[5].xxxx
> 92: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
> 93: F2I TEMP[5].x, -TEMP[5]
> 94: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
> 95: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
> 96: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].wwww
> 97: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
> 98: ADD TEMP[0], TEMP[0], -TEMP[1]
> 99: MOV TEMP[4].xy, TEMP[0].xyyy
>100: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>101: MOV TEMP[5].xy, TEMP[0].zwww
>102: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>103: ABS TEMP[5].x, TEMP[5].xxxx
>104: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>105: F2I TEMP[5].x, -TEMP[5]
>106: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>107: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>108: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].xxxx
>109: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>110: ADD TEMP[0], TEMP[0], -TEMP[1]
>111: MOV TEMP[4].xy, TEMP[0].xyyy
>112: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>113: MOV TEMP[5].xy, TEMP[0].zwww
>114: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>115: ABS TEMP[5].x, TEMP[5].xxxx
>116: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>117: F2I TEMP[5].x, -TEMP[5]
>118: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>119: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>120: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].yyyy
>121: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>122: ADD TEMP[0], TEMP[0], -TEMP[1]
>123: MOV TEMP[4].xy, TEMP[0].xyyy
>124: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>125: MOV TEMP[5].xy, TEMP[0].zwww
>126: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>127: ABS TEMP[5].x, TEMP[5].xxxx
>128: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>129: F2I TEMP[5].x, -TEMP[5]
>130: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>131: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>132: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].zzzz
>133: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>134: ADD TEMP[0], TEMP[0], -TEMP[1]
>135: MOV TEMP[4].xy, TEMP[0].xyyy
>136: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>137: MOV TEMP[5].xy, TEMP[0].zwww
>138: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>139: ABS TEMP[5].x, TEMP[5].xxxx
>140: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>141: F2I TEMP[5].x, -TEMP[5]
>142: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>143: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>144: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].wwww
>145: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>146: ADD TEMP[0], TEMP[0], -TEMP[1]
>147: MOV TEMP[4].xy, TEMP[0].xyyy
>148: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>149: MOV TEMP[5].xy, TEMP[0].zwww
>150: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>151: ABS TEMP[5].x, TEMP[5].xxxx
>152: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>153: F2I TEMP[5].x, -TEMP[5]
>154: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>155: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>156: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].xxxx
>157: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>158: ADD TEMP[0], TEMP[0], -TEMP[1]
>159: MOV TEMP[4].xy, TEMP[0].xyyy
>160: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>161: MOV TEMP[5].xy, TEMP[0].zwww
>162: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>163: ABS TEMP[5].x, TEMP[5].xxxx
>164: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>165: F2I TEMP[5].x, -TEMP[5]
>166: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>167: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>168: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].yyyy
>169: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>170: ADD TEMP[0], TEMP[0], -TEMP[1]
>171: MOV TEMP[4].xy, TEMP[0].xyyy
>172: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>173: MOV TEMP[5].xy, TEMP[0].zwww
>174: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>175: ABS TEMP[5].x, TEMP[5].xxxx
>176: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>177: F2I TEMP[5].x, -TEMP[5]
>178: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>179: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>180: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].zzzz
>181: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>182: ADD TEMP[0], TEMP[0], -TEMP[1]
>183: MOV TEMP[4].xy, TEMP[0].xyyy
>184: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>185: MOV TEMP[5].xy, TEMP[0].zwww
>186: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>187: ABS TEMP[5].x, TEMP[5].xxxx
>188: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>189: F2I TEMP[5].x, -TEMP[5]
>190: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>191: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>192: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].wwww
>193: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>194: ADD TEMP[0], TEMP[0], -TEMP[1]
>195: MOV TEMP[4].xy, TEMP[0].xyyy
>196: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>197: MOV TEMP[5].xy, TEMP[0].zwww
>198: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>199: ABS TEMP[5].x, TEMP[5].xxxx
>200: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>201: F2I TEMP[5].x, -TEMP[5]
>202: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>203: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>204: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].xxxx
>205: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>206: ADD TEMP[0], TEMP[0], -TEMP[1]
>207: MOV TEMP[4].xy, TEMP[0].xyyy
>208: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>209: MOV TEMP[5].xy, TEMP[0].zwww
>210: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>211: ABS TEMP[5].x, TEMP[5].xxxx
>212: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>213: F2I TEMP[5].x, -TEMP[5]
>214: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>215: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>216: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].yyyy
>217: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>218: ADD TEMP[0], TEMP[0], -TEMP[1]
>219: MOV TEMP[4].xy, TEMP[0].xyyy
>220: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>221: MOV TEMP[5].xy, TEMP[0].zwww
>222: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>223: ABS TEMP[5].x, TEMP[5].xxxx
>224: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>225: F2I TEMP[5].x, -TEMP[5]
>226: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>227: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>228: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].zzzz
>229: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>230: ADD TEMP[0], TEMP[0], -TEMP[1]
>231: MOV TEMP[4].xy, TEMP[0].xyyy
>232: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>233: MOV TEMP[5].xy, TEMP[0].zwww
>234: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>235: ABS TEMP[5].x, TEMP[5].xxxx
>236: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>237: F2I TEMP[5].x, -TEMP[5]
>238: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>239: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>240: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].wwww
>241: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>242: ADD TEMP[0], TEMP[0], -TEMP[1]
>243: MOV TEMP[4].xy, TEMP[0].xyyy
>244: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>245: MOV TEMP[5].xy, TEMP[0].zwww
>246: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>247: ABS TEMP[5].x, TEMP[5].xxxx
>248: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>249: F2I TEMP[5].x, -TEMP[5]
>250: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>251: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>252: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].xxxx
>253: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>254: ADD TEMP[0], TEMP[0], -TEMP[1]
>255: MOV TEMP[4].xy, TEMP[0].xyyy
>256: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>257: MOV TEMP[5].xy, TEMP[0].zwww
>258: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>259: ABS TEMP[5].x, TEMP[5].xxxx
>260: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>261: F2I TEMP[5].x, -TEMP[5]
>262: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>263: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>264: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].yyyy
>265: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>266: ADD TEMP[0], TEMP[0], -TEMP[1]
>267: MOV TEMP[4].xy, TEMP[0].xyyy
>268: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>269: MOV TEMP[5].xy, TEMP[0].zwww
>270: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>271: ABS TEMP[5].x, TEMP[5].xxxx
>272: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>273: F2I TEMP[5].x, -TEMP[5]
>274: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>275: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>276: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].zzzz
>277: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>278: ADD TEMP[0], TEMP[0], -TEMP[1]
>279: MOV TEMP[4].xy, TEMP[0].xyyy
>280: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>281: MOV TEMP[5].xy, TEMP[0].zwww
>282: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>283: ABS TEMP[5].x, TEMP[5].xxxx
>284: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>285: F2I TEMP[5].x, -TEMP[5]
>286: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>287: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>288: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].wwww
>289: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>290: ADD TEMP[0], TEMP[0], -TEMP[1]
>291: MOV TEMP[4].xy, TEMP[0].xyyy
>292: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>293: MOV TEMP[5].xy, TEMP[0].zwww
>294: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>295: ABS TEMP[5].x, TEMP[5].xxxx
>296: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>297: F2I TEMP[5].x, -TEMP[5]
>298: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>299: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>300: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].xxxx
>301: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>302: ADD TEMP[0], TEMP[0], -TEMP[1]
>303: MOV TEMP[4].xy, TEMP[0].xyyy
>304: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>305: MOV TEMP[5].xy, TEMP[0].zwww
>306: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>307: ABS TEMP[5].x, TEMP[5].xxxx
>308: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>309: F2I TEMP[5].x, -TEMP[5]
>310: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>311: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>312: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].yyyy
>313: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>314: ADD TEMP[0], TEMP[0], -TEMP[1]
>315: MOV TEMP[4].xy, TEMP[0].xyyy
>316: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>317: MOV TEMP[5].xy, TEMP[0].zwww
>318: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>319: ABS TEMP[5].x, TEMP[5].xxxx
>320: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>321: F2I TEMP[5].x, -TEMP[5]
>322: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>323: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>324: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].zzzz
>325: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>326: ADD TEMP[0], TEMP[0], -TEMP[1]
>327: MOV TEMP[4].xy, TEMP[0].xyyy
>328: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>329: MOV TEMP[5].xy, TEMP[0].zwww
>330: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>331: ABS TEMP[5].x, TEMP[5].xxxx
>332: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>333: F2I TEMP[5].x, -TEMP[5]
>334: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>335: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>336: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].wwww
>337: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>338: ADD TEMP[0], TEMP[0], -TEMP[1]
>339: MOV TEMP[4].xy, TEMP[0].xyyy
>340: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>341: MOV TEMP[5].xy, TEMP[0].zwww
>342: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>343: ABS TEMP[5].x, TEMP[5].xxxx
>344: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>345: F2I TEMP[5].x, -TEMP[5]
>346: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>347: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>348: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].xxxx
>349: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>350: ADD TEMP[0], TEMP[0], -TEMP[1]
>351: MOV TEMP[4].xy, TEMP[0].xyyy
>352: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>353: MOV TEMP[5].xy, TEMP[0].zwww
>354: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>355: ABS TEMP[5].x, TEMP[5].xxxx
>356: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>357: F2I TEMP[5].x, -TEMP[5]
>358: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>359: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>360: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].yyyy
>361: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>362: ADD TEMP[0], TEMP[0], -TEMP[1]
>363: MOV TEMP[4].xy, TEMP[0].xyyy
>364: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>365: MOV TEMP[5].xy, TEMP[0].zwww
>366: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>367: ABS TEMP[5].x, TEMP[5].xxxx
>368: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>369: F2I TEMP[5].x, -TEMP[5]
>370: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>371: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>372: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].zzzz
>373: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>374: ADD TEMP[0], TEMP[0], -TEMP[1]
>375: MOV TEMP[4].xy, TEMP[0].xyyy
>376: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>377: MOV TEMP[5].xy, TEMP[0].zwww
>378: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>379: ABS TEMP[5].x, TEMP[5].xxxx
>380: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>381: F2I TEMP[5].x, -TEMP[5]
>382: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>383: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>384: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].wwww
>385: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>386: ADD TEMP[0], TEMP[0], -TEMP[1]
>387: MOV TEMP[4].xy, TEMP[0].xyyy
>388: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>389: MOV TEMP[5].xy, TEMP[0].zwww
>390: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>391: ABS TEMP[5].x, TEMP[5].xxxx
>392: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>393: F2I TEMP[5].x, -TEMP[5]
>394: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>395: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>396: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].xxxx
>397: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>398: ADD TEMP[0], TEMP[0], -TEMP[1]
>399: MOV TEMP[4].xy, TEMP[0].xyyy
>400: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>401: MOV TEMP[5].xy, TEMP[0].zwww
>402: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>403: ABS TEMP[5].x, TEMP[5].xxxx
>404: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>405: F2I TEMP[5].x, -TEMP[5]
>406: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>407: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>408: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].yyyy
>409: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>410: ADD TEMP[0], TEMP[0], -TEMP[1]
>411: MOV TEMP[4].xy, TEMP[0].xyyy
>412: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>413: MOV TEMP[5].xy, TEMP[0].zwww
>414: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>415: ABS TEMP[5].x, TEMP[5].xxxx
>416: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>417: F2I TEMP[5].x, -TEMP[5]
>418: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>419: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>420: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].zzzz
>421: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>422: ADD TEMP[0], TEMP[0], -TEMP[1]
>423: MOV TEMP[4].xy, TEMP[0].xyyy
>424: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>425: MOV TEMP[5].xy, TEMP[0].zwww
>426: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>427: ABS TEMP[5].x, TEMP[5].xxxx
>428: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>429: F2I TEMP[5].x, -TEMP[5]
>430: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>431: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>432: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].wwww
>433: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>434: ADD TEMP[0], TEMP[0], -TEMP[1]
>435: MOV TEMP[4].xy, TEMP[0].xyyy
>436: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>437: MOV TEMP[5].xy, TEMP[0].zwww
>438: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>439: ABS TEMP[5].x, TEMP[5].xxxx
>440: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>441: F2I TEMP[5].x, -TEMP[5]
>442: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>443: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>444: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[10].xxxx
>445: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>446: ADD TEMP[0], TEMP[0], -TEMP[1]
>447: MOV TEMP[4].xy, TEMP[0].xyyy
>448: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>449: MOV TEMP[5].xy, TEMP[0].zwww
>450: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>451: ABS TEMP[5].x, TEMP[5].xxxx
>452: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>453: F2I TEMP[5].x, -TEMP[5]
>454: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>455: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>456: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[10].yyyy
>457: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>458: ADD TEMP[0], TEMP[0], -TEMP[1]
>459: MOV TEMP[4].xy, TEMP[0].xyyy
>460: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>461: MOV TEMP[5].xy, TEMP[0].zwww
>462: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>463: ABS TEMP[5].x, TEMP[5].xxxx
>464: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>465: F2I TEMP[5].x, -TEMP[5]
>466: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>467: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>468: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[10].zzzz
>469: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>470: ADD TEMP[0], TEMP[0], -TEMP[1]
>471: MOV TEMP[4].xy, TEMP[0].xyyy
>472: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>473: MOV TEMP[5].xy, TEMP[0].zwww
>474: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>475: ABS TEMP[5].x, TEMP[5].xxxx
>476: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>477: F2I TEMP[5].x, -TEMP[5]
>478: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>479: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>480: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[10].wwww
>481: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>482: ADD TEMP[0], TEMP[0], -TEMP[1]
>483: MOV TEMP[4].xy, TEMP[0].xyyy
>484: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>485: MOV TEMP[5].xy, TEMP[0].zwww
>486: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>487: ABS TEMP[5].x, TEMP[5].xxxx
>488: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>489: F2I TEMP[5].x, -TEMP[5]
>490: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>491: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>492: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[11].xxxx
>493: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>494: ADD TEMP[0], TEMP[0], -TEMP[1]
>495: MOV TEMP[4].xy, TEMP[0].xyyy
>496: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>497: MOV TEMP[5].xy, TEMP[0].zwww
>498: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>499: ABS TEMP[5].x, TEMP[5].xxxx
>500: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>501: F2I TEMP[5].x, -TEMP[5]
>502: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>503: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>504: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[11].yyyy
>505: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>506: ADD TEMP[0], TEMP[0], -TEMP[1]
>507: MOV TEMP[4].xy, TEMP[0].xyyy
>508: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>509: MOV TEMP[5].xy, TEMP[0].zwww
>510: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>511: ABS TEMP[5].x, TEMP[5].xxxx
>512: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>513: F2I TEMP[5].x, -TEMP[5]
>514: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>515: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>516: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[11].zzzz
>517: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>518: ADD TEMP[0], TEMP[0], -TEMP[1]
>519: MOV TEMP[4].xy, TEMP[0].xyyy
>520: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>521: MOV TEMP[5].xy, TEMP[0].zwww
>522: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>523: ABS TEMP[5].x, TEMP[5].xxxx
>524: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>525: F2I TEMP[5].x, -TEMP[5]
>526: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>527: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>528: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[11].wwww
>529: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>530: ADD TEMP[0], TEMP[0], -TEMP[1]
>531: MOV TEMP[4].xy, TEMP[0].xyyy
>532: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>533: MOV TEMP[5].xy, TEMP[0].zwww
>534: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>535: ABS TEMP[5].x, TEMP[5].xxxx
>536: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>537: F2I TEMP[5].x, -TEMP[5]
>538: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>539: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>540: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[12].xxxx
>541: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>542: ADD TEMP[0], TEMP[0], -TEMP[1]
>543: MOV TEMP[4].xy, TEMP[0].xyyy
>544: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>545: MOV TEMP[5].xy, TEMP[0].zwww
>546: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>547: ABS TEMP[5].x, TEMP[5].xxxx
>548: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>549: F2I TEMP[5].x, -TEMP[5]
>550: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>551: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>552: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[12].yyyy
>553: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>554: ADD TEMP[0], TEMP[0], -TEMP[1]
>555: MOV TEMP[4].xy, TEMP[0].xyyy
>556: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>557: MOV TEMP[5].xy, TEMP[0].zwww
>558: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>559: ABS TEMP[5].x, TEMP[5].xxxx
>560: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>561: F2I TEMP[5].x, -TEMP[5]
>562: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>563: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>564: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[12].zzzz
>565: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>566: ADD TEMP[0], TEMP[0], -TEMP[1]
>567: MOV TEMP[4].xy, TEMP[0].xyyy
>568: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>569: MOV TEMP[5].xy, TEMP[0].zwww
>570: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>571: ABS TEMP[5].x, TEMP[5].xxxx
>572: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>573: F2I TEMP[5].x, -TEMP[5]
>574: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>575: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>576: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[12].wwww
>577: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>578: ADD TEMP[0], TEMP[0], -TEMP[1]
>579: MOV TEMP[4].xy, TEMP[0].xyyy
>580: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>581: MOV TEMP[5].xy, TEMP[0].zwww
>582: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>583: ABS TEMP[5].x, TEMP[5].xxxx
>584: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>585: F2I TEMP[5].x, -TEMP[5]
>586: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>587: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>588: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[13].xxxx
>589: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>590: ADD TEMP[0], TEMP[0], -TEMP[1]
>591: MOV TEMP[4].xy, TEMP[0].xyyy
>592: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
>593: MOV TEMP[5].xy, TEMP[0].zwww
>594: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
>595: ABS TEMP[5].x, TEMP[5].xxxx
>596: SGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
>597: F2I TEMP[5].x, -TEMP[5]
>598: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
>599: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
>600: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[13].yyyy
>601: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>602: ADD TEMP[0], TEMP[0], -TEMP[1]
>603: MOV TEMP[1].xy, TEMP[0].xyyy
>604: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
>605: MOV TEMP[0].xy, TEMP[0].zwww
>606: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
>607: ABS TEMP[0].x, TEMP[0].xxxx
>608: SGE TEMP[0].x, TEMP[0].xxxx, CONST[0].zzzz
>609: F2I TEMP[0].x, -TEMP[0]
>610: AND TEMP[0].x, TEMP[0].xxxx, IMM[1].yyyy
>611: MUL TEMP[3].xyz, TEMP[1].xyzz, TEMP[0].xxxx
>612: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[13].zzzz
>613: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
>614: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[2].xyzz
>615: MOV OUT[0], TEMP[2]
>616: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 20)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 24)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 28)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 44)
>  %33 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
>  %35 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
>  %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 1
>  %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0
>  %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 1
>  %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0
>  %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %43 = fsub float -0.000000e+00, %22
>  %44 = fadd float %41, %43
>  %45 = fsub float -0.000000e+00, %23
>  %46 = fadd float %42, %45
>  %47 = fmul float 0x3F947AE140000000, %32
>  %48 = fmul float %44, %47
>  %49 = fmul float %46, %47
>  %50 = fmul float %41, 0x4029FAC720000000
>  %51 = fmul float %42, 0x40538EE980000000
>  %52 = fadd float %50, %51
>  %53 = call float @llvm.sin.f32(float %52)
>  %54 = fmul float %53, 0x40E55DD180000000
>  %55 = call float @llvm.AMDIL.fraction.(float %54)
>  %56 = fmul float %55, %25
>  %57 = fadd float %56, %26
>  %58 = fmul float %48, %57
>  %59 = fmul float %49, %57
>  %60 = fmul float %41, %27
>  %61 = fmul float %42, %28
>  %62 = fmul float %58, %27
>  %63 = fmul float %59, %28
>  %64 = fsub float -0.000000e+00, %58
>  %65 = fadd float %41, %64
>  %66 = fsub float -0.000000e+00, %59
>  %67 = fadd float %42, %66
>  %68 = fsub float -0.000000e+00, %62
>  %69 = fadd float %60, %68
>  %70 = fsub float -0.000000e+00, %63
>  %71 = fadd float %61, %70
>  %72 = bitcast float %65 to i32
>  %73 = bitcast float %67 to i32
>  %74 = insertelement <2 x i32> undef, i32 %72, i32 0
>  %75 = insertelement <2 x i32> %74, i32 %73, i32 1
>  %76 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %75, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %77 = extractelement <4 x float> %76, i32 0
>  %78 = extractelement <4 x float> %76, i32 1
>  %79 = extractelement <4 x float> %76, i32 2
>  %80 = bitcast float %69 to i32
>  %81 = bitcast float %71 to i32
>  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
>  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
>  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = call float @fabs(float %85)
>  %87 = fcmp uge float %86, %24
>  %88 = select i1 %87, float 1.000000e+00, float 0.000000e+00
>  %89 = fsub float -0.000000e+00, %88
>  %90 = fptosi float %89 to i32
>  %91 = bitcast i32 %90 to float
>  %92 = bitcast float %91 to i32
>  %93 = and i32 %92, 1065353216
>  %94 = bitcast i32 %93 to float
>  %95 = fmul float %77, %94
>  %96 = fmul float %78, %94
>  %97 = fmul float %79, %94
>  %98 = fsub float -0.000000e+00, %58
>  %99 = fadd float %65, %98
>  %100 = fsub float -0.000000e+00, %59
>  %101 = fadd float %67, %100
>  %102 = fsub float -0.000000e+00, %62
>  %103 = fadd float %69, %102
>  %104 = fsub float -0.000000e+00, %63
>  %105 = fadd float %71, %104
>  %106 = bitcast float %99 to i32
>  %107 = bitcast float %101 to i32
>  %108 = insertelement <2 x i32> undef, i32 %106, i32 0
>  %109 = insertelement <2 x i32> %108, i32 %107, i32 1
>  %110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %109, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %111 = extractelement <4 x float> %110, i32 0
>  %112 = extractelement <4 x float> %110, i32 1
>  %113 = extractelement <4 x float> %110, i32 2
>  %114 = bitcast float %103 to i32
>  %115 = bitcast float %105 to i32
>  %116 = insertelement <2 x i32> undef, i32 %114, i32 0
>  %117 = insertelement <2 x i32> %116, i32 %115, i32 1
>  %118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %117, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %119 = extractelement <4 x float> %118, i32 0
>  %120 = call float @fabs(float %119)
>  %121 = fcmp uge float %120, %24
>  %122 = select i1 %121, float 1.000000e+00, float 0.000000e+00
>  %123 = fsub float -0.000000e+00, %122
>  %124 = fptosi float %123 to i32
>  %125 = bitcast i32 %124 to float
>  %126 = bitcast float %125 to i32
>  %127 = and i32 %126, 1065353216
>  %128 = bitcast i32 %127 to float
>  %129 = fmul float %111, %128
>  %130 = fmul float %112, %128
>  %131 = fmul float %113, %128
>  %132 = fmul float %129, 0x3FEE666660000000
>  %133 = fmul float %130, 0x3FEE666660000000
>  %134 = fmul float %131, 0x3FEE666660000000
>  %135 = fadd float %95, %132
>  %136 = fadd float %96, %133
>  %137 = fadd float %97, %134
>  %138 = fsub float -0.000000e+00, %58
>  %139 = fadd float %99, %138
>  %140 = fsub float -0.000000e+00, %59
>  %141 = fadd float %101, %140
>  %142 = fsub float -0.000000e+00, %62
>  %143 = fadd float %103, %142
>  %144 = fsub float -0.000000e+00, %63
>  %145 = fadd float %105, %144
>  %146 = bitcast float %139 to i32
>  %147 = bitcast float %141 to i32
>  %148 = insertelement <2 x i32> undef, i32 %146, i32 0
>  %149 = insertelement <2 x i32> %148, i32 %147, i32 1
>  %150 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %149, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %151 = extractelement <4 x float> %150, i32 0
>  %152 = extractelement <4 x float> %150, i32 1
>  %153 = extractelement <4 x float> %150, i32 2
>  %154 = bitcast float %143 to i32
>  %155 = bitcast float %145 to i32
>  %156 = insertelement <2 x i32> undef, i32 %154, i32 0
>  %157 = insertelement <2 x i32> %156, i32 %155, i32 1
>  %158 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %157, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %159 = extractelement <4 x float> %158, i32 0
>  %160 = call float @fabs(float %159)
>  %161 = fcmp uge float %160, %24
>  %162 = select i1 %161, float 1.000000e+00, float 0.000000e+00
>  %163 = fsub float -0.000000e+00, %162
>  %164 = fptosi float %163 to i32
>  %165 = bitcast i32 %164 to float
>  %166 = bitcast float %165 to i32
>  %167 = and i32 %166, 1065353216
>  %168 = bitcast i32 %167 to float
>  %169 = fmul float %151, %168
>  %170 = fmul float %152, %168
>  %171 = fmul float %153, %168
>  %172 = fmul float %169, 0x3FECE147A0000000
>  %173 = fmul float %170, 0x3FECE147A0000000
>  %174 = fmul float %171, 0x3FECE147A0000000
>  %175 = fadd float %135, %172
>  %176 = fadd float %136, %173
>  %177 = fadd float %137, %174
>  %178 = fsub float -0.000000e+00, %58
>  %179 = fadd float %139, %178
>  %180 = fsub float -0.000000e+00, %59
>  %181 = fadd float %141, %180
>  %182 = fsub float -0.000000e+00, %62
>  %183 = fadd float %143, %182
>  %184 = fsub float -0.000000e+00, %63
>  %185 = fadd float %145, %184
>  %186 = bitcast float %179 to i32
>  %187 = bitcast float %181 to i32
>  %188 = insertelement <2 x i32> undef, i32 %186, i32 0
>  %189 = insertelement <2 x i32> %188, i32 %187, i32 1
>  %190 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %189, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %191 = extractelement <4 x float> %190, i32 0
>  %192 = extractelement <4 x float> %190, i32 1
>  %193 = extractelement <4 x float> %190, i32 2
>  %194 = bitcast float %183 to i32
>  %195 = bitcast float %185 to i32
>  %196 = insertelement <2 x i32> undef, i32 %194, i32 0
>  %197 = insertelement <2 x i32> %196, i32 %195, i32 1
>  %198 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %197, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %199 = extractelement <4 x float> %198, i32 0
>  %200 = call float @fabs(float %199)
>  %201 = fcmp uge float %200, %24
>  %202 = select i1 %201, float 1.000000e+00, float 0.000000e+00
>  %203 = fsub float -0.000000e+00, %202
>  %204 = fptosi float %203 to i32
>  %205 = bitcast i32 %204 to float
>  %206 = bitcast float %205 to i32
>  %207 = and i32 %206, 1065353216
>  %208 = bitcast i32 %207 to float
>  %209 = fmul float %191, %208
>  %210 = fmul float %192, %208
>  %211 = fmul float %193, %208
>  %212 = fmul float %209, 0x3FEB6F9DA0000000
>  %213 = fmul float %210, 0x3FEB6F9DA0000000
>  %214 = fmul float %211, 0x3FEB6F9DA0000000
>  %215 = fadd float %175, %212
>  %216 = fadd float %176, %213
>  %217 = fadd float %177, %214
>  %218 = fsub float -0.000000e+00, %58
>  %219 = fadd float %179, %218
>  %220 = fsub float -0.000000e+00, %59
>  %221 = fadd float %181, %220
>  %222 = fsub float -0.000000e+00, %62
>  %223 = fadd float %183, %222
>  %224 = fsub float -0.000000e+00, %63
>  %225 = fadd float %185, %224
>  %226 = bitcast float %219 to i32
>  %227 = bitcast float %221 to i32
>  %228 = insertelement <2 x i32> undef, i32 %226, i32 0
>  %229 = insertelement <2 x i32> %228, i32 %227, i32 1
>  %230 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %229, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %231 = extractelement <4 x float> %230, i32 0
>  %232 = extractelement <4 x float> %230, i32 1
>  %233 = extractelement <4 x float> %230, i32 2
>  %234 = bitcast float %223 to i32
>  %235 = bitcast float %225 to i32
>  %236 = insertelement <2 x i32> undef, i32 %234, i32 0
>  %237 = insertelement <2 x i32> %236, i32 %235, i32 1
>  %238 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %237, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %239 = extractelement <4 x float> %238, i32 0
>  %240 = call float @fabs(float %239)
>  %241 = fcmp uge float %240, %24
>  %242 = select i1 %241, float 1.000000e+00, float 0.000000e+00
>  %243 = fsub float -0.000000e+00, %242
>  %244 = fptosi float %243 to i32
>  %245 = bitcast i32 %244 to float
>  %246 = bitcast float %245 to i32
>  %247 = and i32 %246, 1065353216
>  %248 = bitcast i32 %247 to float
>  %249 = fmul float %231, %248
>  %250 = fmul float %232, %248
>  %251 = fmul float %233, %248
>  %252 = fmul float %249, 0x3FEA106F60000000
>  %253 = fmul float %250, 0x3FEA106F60000000
>  %254 = fmul float %251, 0x3FEA106F60000000
>  %255 = fadd float %215, %252
>  %256 = fadd float %216, %253
>  %257 = fadd float %217, %254
>  %258 = fsub float -0.000000e+00, %58
>  %259 = fadd float %219, %258
>  %260 = fsub float -0.000000e+00, %59
>  %261 = fadd float %221, %260
>  %262 = fsub float -0.000000e+00, %62
>  %263 = fadd float %223, %262
>  %264 = fsub float -0.000000e+00, %63
>  %265 = fadd float %225, %264
>  %266 = bitcast float %259 to i32
>  %267 = bitcast float %261 to i32
>  %268 = insertelement <2 x i32> undef, i32 %266, i32 0
>  %269 = insertelement <2 x i32> %268, i32 %267, i32 1
>  %270 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %269, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %271 = extractelement <4 x float> %270, i32 0
>  %272 = extractelement <4 x float> %270, i32 1
>  %273 = extractelement <4 x float> %270, i32 2
>  %274 = bitcast float %263 to i32
>  %275 = bitcast float %265 to i32
>  %276 = insertelement <2 x i32> undef, i32 %274, i32 0
>  %277 = insertelement <2 x i32> %276, i32 %275, i32 1
>  %278 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %277, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %279 = extractelement <4 x float> %278, i32 0
>  %280 = call float @fabs(float %279)
>  %281 = fcmp uge float %280, %24
>  %282 = select i1 %281, float 1.000000e+00, float 0.000000e+00
>  %283 = fsub float -0.000000e+00, %282
>  %284 = fptosi float %283 to i32
>  %285 = bitcast i32 %284 to float
>  %286 = bitcast float %285 to i32
>  %287 = and i32 %286, 1065353216
>  %288 = bitcast i32 %287 to float
>  %289 = fmul float %271, %288
>  %290 = fmul float %272, %288
>  %291 = fmul float %273, %288
>  %292 = fmul float %289, 0x3FE8C2D020000000
>  %293 = fmul float %290, 0x3FE8C2D020000000
>  %294 = fmul float %291, 0x3FE8C2D020000000
>  %295 = fadd float %255, %292
>  %296 = fadd float %256, %293
>  %297 = fadd float %257, %294
>  %298 = fsub float -0.000000e+00, %58
>  %299 = fadd float %259, %298
>  %300 = fsub float -0.000000e+00, %59
>  %301 = fadd float %261, %300
>  %302 = fsub float -0.000000e+00, %62
>  %303 = fadd float %263, %302
>  %304 = fsub float -0.000000e+00, %63
>  %305 = fadd float %265, %304
>  %306 = bitcast float %299 to i32
>  %307 = bitcast float %301 to i32
>  %308 = insertelement <2 x i32> undef, i32 %306, i32 0
>  %309 = insertelement <2 x i32> %308, i32 %307, i32 1
>  %310 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %309, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %311 = extractelement <4 x float> %310, i32 0
>  %312 = extractelement <4 x float> %310, i32 1
>  %313 = extractelement <4 x float> %310, i32 2
>  %314 = bitcast float %303 to i32
>  %315 = bitcast float %305 to i32
>  %316 = insertelement <2 x i32> undef, i32 %314, i32 0
>  %317 = insertelement <2 x i32> %316, i32 %315, i32 1
>  %318 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %317, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %319 = extractelement <4 x float> %318, i32 0
>  %320 = call float @fabs(float %319)
>  %321 = fcmp uge float %320, %24
>  %322 = select i1 %321, float 1.000000e+00, float 0.000000e+00
>  %323 = fsub float -0.000000e+00, %322
>  %324 = fptosi float %323 to i32
>  %325 = bitcast i32 %324 to float
>  %326 = bitcast float %325 to i32
>  %327 = and i32 %326, 1065353216
>  %328 = bitcast i32 %327 to float
>  %329 = fmul float %311, %328
>  %330 = fmul float %312, %328
>  %331 = fmul float %313, %328
>  %332 = fmul float %329, 0x3FE785DF40000000
>  %333 = fmul float %330, 0x3FE785DF40000000
>  %334 = fmul float %331, 0x3FE785DF40000000
>  %335 = fadd float %295, %332
>  %336 = fadd float %296, %333
>  %337 = fadd float %297, %334
>  %338 = fsub float -0.000000e+00, %58
>  %339 = fadd float %299, %338
>  %340 = fsub float -0.000000e+00, %59
>  %341 = fadd float %301, %340
>  %342 = fsub float -0.000000e+00, %62
>  %343 = fadd float %303, %342
>  %344 = fsub float -0.000000e+00, %63
>  %345 = fadd float %305, %344
>  %346 = bitcast float %339 to i32
>  %347 = bitcast float %341 to i32
>  %348 = insertelement <2 x i32> undef, i32 %346, i32 0
>  %349 = insertelement <2 x i32> %348, i32 %347, i32 1
>  %350 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %349, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %351 = extractelement <4 x float> %350, i32 0
>  %352 = extractelement <4 x float> %350, i32 1
>  %353 = extractelement <4 x float> %350, i32 2
>  %354 = bitcast float %343 to i32
>  %355 = bitcast float %345 to i32
>  %356 = insertelement <2 x i32> undef, i32 %354, i32 0
>  %357 = insertelement <2 x i32> %356, i32 %355, i32 1
>  %358 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %357, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %359 = extractelement <4 x float> %358, i32 0
>  %360 = call float @fabs(float %359)
>  %361 = fcmp uge float %360, %24
>  %362 = select i1 %361, float 1.000000e+00, float 0.000000e+00
>  %363 = fsub float -0.000000e+00, %362
>  %364 = fptosi float %363 to i32
>  %365 = bitcast i32 %364 to float
>  %366 = bitcast float %365 to i32
>  %367 = and i32 %366, 1065353216
>  %368 = bitcast i32 %367 to float
>  %369 = fmul float %351, %368
>  %370 = fmul float %352, %368
>  %371 = fmul float %353, %368
>  %372 = fmul float %369, 0x3FE658C740000000
>  %373 = fmul float %370, 0x3FE658C740000000
>  %374 = fmul float %371, 0x3FE658C740000000
>  %375 = fadd float %335, %372
>  %376 = fadd float %336, %373
>  %377 = fadd float %337, %374
>  %378 = fsub float -0.000000e+00, %58
>  %379 = fadd float %339, %378
>  %380 = fsub float -0.000000e+00, %59
>  %381 = fadd float %341, %380
>  %382 = fsub float -0.000000e+00, %62
>  %383 = fadd float %343, %382
>  %384 = fsub float -0.000000e+00, %63
>  %385 = fadd float %345, %384
>  %386 = bitcast float %379 to i32
>  %387 = bitcast float %381 to i32
>  %388 = insertelement <2 x i32> undef, i32 %386, i32 0
>  %389 = insertelement <2 x i32> %388, i32 %387, i32 1
>  %390 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %389, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %391 = extractelement <4 x float> %390, i32 0
>  %392 = extractelement <4 x float> %390, i32 1
>  %393 = extractelement <4 x float> %390, i32 2
>  %394 = bitcast float %383 to i32
>  %395 = bitcast float %385 to i32
>  %396 = insertelement <2 x i32> undef, i32 %394, i32 0
>  %397 = insertelement <2 x i32> %396, i32 %395, i32 1
>  %398 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %397, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %399 = extractelement <4 x float> %398, i32 0
>  %400 = call float @fabs(float %399)
>  %401 = fcmp uge float %400, %24
>  %402 = select i1 %401, float 1.000000e+00, float 0.000000e+00
>  %403 = fsub float -0.000000e+00, %402
>  %404 = fptosi float %403 to i32
>  %405 = bitcast i32 %404 to float
>  %406 = bitcast float %405 to i32
>  %407 = and i32 %406, 1065353216
>  %408 = bitcast i32 %407 to float
>  %409 = fmul float %391, %408
>  %410 = fmul float %392, %408
>  %411 = fmul float %393, %408
>  %412 = fmul float %409, 0x3FE53ABD40000000
>  %413 = fmul float %410, 0x3FE53ABD40000000
>  %414 = fmul float %411, 0x3FE53ABD40000000
>  %415 = fadd float %375, %412
>  %416 = fadd float %376, %413
>  %417 = fadd float %377, %414
>  %418 = fsub float -0.000000e+00, %58
>  %419 = fadd float %379, %418
>  %420 = fsub float -0.000000e+00, %59
>  %421 = fadd float %381, %420
>  %422 = fsub float -0.000000e+00, %62
>  %423 = fadd float %383, %422
>  %424 = fsub float -0.000000e+00, %63
>  %425 = fadd float %385, %424
>  %426 = bitcast float %419 to i32
>  %427 = bitcast float %421 to i32
>  %428 = insertelement <2 x i32> undef, i32 %426, i32 0
>  %429 = insertelement <2 x i32> %428, i32 %427, i32 1
>  %430 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %429, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %431 = extractelement <4 x float> %430, i32 0
>  %432 = extractelement <4 x float> %430, i32 1
>  %433 = extractelement <4 x float> %430, i32 2
>  %434 = bitcast float %423 to i32
>  %435 = bitcast float %425 to i32
>  %436 = insertelement <2 x i32> undef, i32 %434, i32 0
>  %437 = insertelement <2 x i32> %436, i32 %435, i32 1
>  %438 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %437, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %439 = extractelement <4 x float> %438, i32 0
>  %440 = call float @fabs(float %439)
>  %441 = fcmp uge float %440, %24
>  %442 = select i1 %441, float 1.000000e+00, float 0.000000e+00
>  %443 = fsub float -0.000000e+00, %442
>  %444 = fptosi float %443 to i32
>  %445 = bitcast i32 %444 to float
>  %446 = bitcast float %445 to i32
>  %447 = and i32 %446, 1065353216
>  %448 = bitcast i32 %447 to float
>  %449 = fmul float %431, %448
>  %450 = fmul float %432, %448
>  %451 = fmul float %433, %448
>  %452 = fmul float %449, 0x3FE42B00A0000000
>  %453 = fmul float %450, 0x3FE42B00A0000000
>  %454 = fmul float %451, 0x3FE42B00A0000000
>  %455 = fadd float %415, %452
>  %456 = fadd float %416, %453
>  %457 = fadd float %417, %454
>  %458 = fsub float -0.000000e+00, %58
>  %459 = fadd float %419, %458
>  %460 = fsub float -0.000000e+00, %59
>  %461 = fadd float %421, %460
>  %462 = fsub float -0.000000e+00, %62
>  %463 = fadd float %423, %462
>  %464 = fsub float -0.000000e+00, %63
>  %465 = fadd float %425, %464
>  %466 = bitcast float %459 to i32
>  %467 = bitcast float %461 to i32
>  %468 = insertelement <2 x i32> undef, i32 %466, i32 0
>  %469 = insertelement <2 x i32> %468, i32 %467, i32 1
>  %470 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %469, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %471 = extractelement <4 x float> %470, i32 0
>  %472 = extractelement <4 x float> %470, i32 1
>  %473 = extractelement <4 x float> %470, i32 2
>  %474 = bitcast float %463 to i32
>  %475 = bitcast float %465 to i32
>  %476 = insertelement <2 x i32> undef, i32 %474, i32 0
>  %477 = insertelement <2 x i32> %476, i32 %475, i32 1
>  %478 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %477, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %479 = extractelement <4 x float> %478, i32 0
>  %480 = call float @fabs(float %479)
>  %481 = fcmp uge float %480, %24
>  %482 = select i1 %481, float 1.000000e+00, float 0.000000e+00
>  %483 = fsub float -0.000000e+00, %482
>  %484 = fptosi float %483 to i32
>  %485 = bitcast i32 %484 to float
>  %486 = bitcast float %485 to i32
>  %487 = and i32 %486, 1065353216
>  %488 = bitcast i32 %487 to float
>  %489 = fmul float %471, %488
>  %490 = fmul float %472, %488
>  %491 = fmul float %473, %488
>  %492 = fmul float %489, 0x3FE328DA20000000
>  %493 = fmul float %490, 0x3FE328DA20000000
>  %494 = fmul float %491, 0x3FE328DA20000000
>  %495 = fadd float %455, %492
>  %496 = fadd float %456, %493
>  %497 = fadd float %457, %494
>  %498 = fsub float -0.000000e+00, %58
>  %499 = fadd float %459, %498
>  %500 = fsub float -0.000000e+00, %59
>  %501 = fadd float %461, %500
>  %502 = fsub float -0.000000e+00, %62
>  %503 = fadd float %463, %502
>  %504 = fsub float -0.000000e+00, %63
>  %505 = fadd float %465, %504
>  %506 = bitcast float %499 to i32
>  %507 = bitcast float %501 to i32
>  %508 = insertelement <2 x i32> undef, i32 %506, i32 0
>  %509 = insertelement <2 x i32> %508, i32 %507, i32 1
>  %510 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %509, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %511 = extractelement <4 x float> %510, i32 0
>  %512 = extractelement <4 x float> %510, i32 1
>  %513 = extractelement <4 x float> %510, i32 2
>  %514 = bitcast float %503 to i32
>  %515 = bitcast float %505 to i32
>  %516 = insertelement <2 x i32> undef, i32 %514, i32 0
>  %517 = insertelement <2 x i32> %516, i32 %515, i32 1
>  %518 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %517, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %519 = extractelement <4 x float> %518, i32 0
>  %520 = call float @fabs(float %519)
>  %521 = fcmp uge float %520, %24
>  %522 = select i1 %521, float 1.000000e+00, float 0.000000e+00
>  %523 = fsub float -0.000000e+00, %522
>  %524 = fptosi float %523 to i32
>  %525 = bitcast i32 %524 to float
>  %526 = bitcast float %525 to i32
>  %527 = and i32 %526, 1065353216
>  %528 = bitcast i32 %527 to float
>  %529 = fmul float %511, %528
>  %530 = fmul float %512, %528
>  %531 = fmul float %513, %528
>  %532 = fmul float %529, 0x3FE2339C00000000
>  %533 = fmul float %530, 0x3FE2339C00000000
>  %534 = fmul float %531, 0x3FE2339C00000000
>  %535 = fadd float %495, %532
>  %536 = fadd float %496, %533
>  %537 = fadd float %497, %534
>  %538 = fsub float -0.000000e+00, %58
>  %539 = fadd float %499, %538
>  %540 = fsub float -0.000000e+00, %59
>  %541 = fadd float %501, %540
>  %542 = fsub float -0.000000e+00, %62
>  %543 = fadd float %503, %542
>  %544 = fsub float -0.000000e+00, %63
>  %545 = fadd float %505, %544
>  %546 = bitcast float %539 to i32
>  %547 = bitcast float %541 to i32
>  %548 = insertelement <2 x i32> undef, i32 %546, i32 0
>  %549 = insertelement <2 x i32> %548, i32 %547, i32 1
>  %550 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %549, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %551 = extractelement <4 x float> %550, i32 0
>  %552 = extractelement <4 x float> %550, i32 1
>  %553 = extractelement <4 x float> %550, i32 2
>  %554 = bitcast float %543 to i32
>  %555 = bitcast float %545 to i32
>  %556 = insertelement <2 x i32> undef, i32 %554, i32 0
>  %557 = insertelement <2 x i32> %556, i32 %555, i32 1
>  %558 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %557, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %559 = extractelement <4 x float> %558, i32 0
>  %560 = call float @fabs(float %559)
>  %561 = fcmp uge float %560, %24
>  %562 = select i1 %561, float 1.000000e+00, float 0.000000e+00
>  %563 = fsub float -0.000000e+00, %562
>  %564 = fptosi float %563 to i32
>  %565 = bitcast i32 %564 to float
>  %566 = bitcast float %565 to i32
>  %567 = and i32 %566, 1065353216
>  %568 = bitcast i32 %567 to float
>  %569 = fmul float %551, %568
>  %570 = fmul float %552, %568
>  %571 = fmul float %553, %568
>  %572 = fmul float %569, 0x3FE14AA100000000
>  %573 = fmul float %570, 0x3FE14AA100000000
>  %574 = fmul float %571, 0x3FE14AA100000000
>  %575 = fadd float %535, %572
>  %576 = fadd float %536, %573
>  %577 = fadd float %537, %574
>  %578 = fsub float -0.000000e+00, %58
>  %579 = fadd float %539, %578
>  %580 = fsub float -0.000000e+00, %59
>  %581 = fadd float %541, %580
>  %582 = fsub float -0.000000e+00, %62
>  %583 = fadd float %543, %582
>  %584 = fsub float -0.000000e+00, %63
>  %585 = fadd float %545, %584
>  %586 = bitcast float %579 to i32
>  %587 = bitcast float %581 to i32
>  %588 = insertelement <2 x i32> undef, i32 %586, i32 0
>  %589 = insertelement <2 x i32> %588, i32 %587, i32 1
>  %590 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %589, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %591 = extractelement <4 x float> %590, i32 0
>  %592 = extractelement <4 x float> %590, i32 1
>  %593 = extractelement <4 x float> %590, i32 2
>  %594 = bitcast float %583 to i32
>  %595 = bitcast float %585 to i32
>  %596 = insertelement <2 x i32> undef, i32 %594, i32 0
>  %597 = insertelement <2 x i32> %596, i32 %595, i32 1
>  %598 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %597, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %599 = extractelement <4 x float> %598, i32 0
>  %600 = call float @fabs(float %599)
>  %601 = fcmp uge float %600, %24
>  %602 = select i1 %601, float 1.000000e+00, float 0.000000e+00
>  %603 = fsub float -0.000000e+00, %602
>  %604 = fptosi float %603 to i32
>  %605 = bitcast i32 %604 to float
>  %606 = bitcast float %605 to i32
>  %607 = and i32 %606, 1065353216
>  %608 = bitcast i32 %607 to float
>  %609 = fmul float %591, %608
>  %610 = fmul float %592, %608
>  %611 = fmul float %593, %608
>  %612 = fmul float %609, 0x3FE06D4C20000000
>  %613 = fmul float %610, 0x3FE06D4C20000000
>  %614 = fmul float %611, 0x3FE06D4C20000000
>  %615 = fadd float %575, %612
>  %616 = fadd float %576, %613
>  %617 = fadd float %577, %614
>  %618 = fsub float -0.000000e+00, %58
>  %619 = fadd float %579, %618
>  %620 = fsub float -0.000000e+00, %59
>  %621 = fadd float %581, %620
>  %622 = fsub float -0.000000e+00, %62
>  %623 = fadd float %583, %622
>  %624 = fsub float -0.000000e+00, %63
>  %625 = fadd float %585, %624
>  %626 = bitcast float %619 to i32
>  %627 = bitcast float %621 to i32
>  %628 = insertelement <2 x i32> undef, i32 %626, i32 0
>  %629 = insertelement <2 x i32> %628, i32 %627, i32 1
>  %630 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %629, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %631 = extractelement <4 x float> %630, i32 0
>  %632 = extractelement <4 x float> %630, i32 1
>  %633 = extractelement <4 x float> %630, i32 2
>  %634 = bitcast float %623 to i32
>  %635 = bitcast float %625 to i32
>  %636 = insertelement <2 x i32> undef, i32 %634, i32 0
>  %637 = insertelement <2 x i32> %636, i32 %635, i32 1
>  %638 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %637, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %639 = extractelement <4 x float> %638, i32 0
>  %640 = call float @fabs(float %639)
>  %641 = fcmp uge float %640, %24
>  %642 = select i1 %641, float 1.000000e+00, float 0.000000e+00
>  %643 = fsub float -0.000000e+00, %642
>  %644 = fptosi float %643 to i32
>  %645 = bitcast i32 %644 to float
>  %646 = bitcast float %645 to i32
>  %647 = and i32 %646, 1065353216
>  %648 = bitcast i32 %647 to float
>  %649 = fmul float %631, %648
>  %650 = fmul float %632, %648
>  %651 = fmul float %633, %648
>  %652 = fmul float %649, 0x3FDF3610A0000000
>  %653 = fmul float %650, 0x3FDF3610A0000000
>  %654 = fmul float %651, 0x3FDF3610A0000000
>  %655 = fadd float %615, %652
>  %656 = fadd float %616, %653
>  %657 = fadd float %617, %654
>  %658 = fsub float -0.000000e+00, %58
>  %659 = fadd float %619, %658
>  %660 = fsub float -0.000000e+00, %59
>  %661 = fadd float %621, %660
>  %662 = fsub float -0.000000e+00, %62
>  %663 = fadd float %623, %662
>  %664 = fsub float -0.000000e+00, %63
>  %665 = fadd float %625, %664
>  %666 = bitcast float %659 to i32
>  %667 = bitcast float %661 to i32
>  %668 = insertelement <2 x i32> undef, i32 %666, i32 0
>  %669 = insertelement <2 x i32> %668, i32 %667, i32 1
>  %670 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %669, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %671 = extractelement <4 x float> %670, i32 0
>  %672 = extractelement <4 x float> %670, i32 1
>  %673 = extractelement <4 x float> %670, i32 2
>  %674 = bitcast float %663 to i32
>  %675 = bitcast float %665 to i32
>  %676 = insertelement <2 x i32> undef, i32 %674, i32 0
>  %677 = insertelement <2 x i32> %676, i32 %675, i32 1
>  %678 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %677, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %679 = extractelement <4 x float> %678, i32 0
>  %680 = call float @fabs(float %679)
>  %681 = fcmp uge float %680, %24
>  %682 = select i1 %681, float 1.000000e+00, float 0.000000e+00
>  %683 = fsub float -0.000000e+00, %682
>  %684 = fptosi float %683 to i32
>  %685 = bitcast i32 %684 to float
>  %686 = bitcast float %685 to i32
>  %687 = and i32 %686, 1065353216
>  %688 = bitcast i32 %687 to float
>  %689 = fmul float %671, %688
>  %690 = fmul float %672, %688
>  %691 = fmul float %673, %688
>  %692 = fmul float %689, 0x3FDDA68FC0000000
>  %693 = fmul float %690, 0x3FDDA68FC0000000
>  %694 = fmul float %691, 0x3FDDA68FC0000000
>  %695 = fadd float %655, %692
>  %696 = fadd float %656, %693
>  %697 = fadd float %657, %694
>  %698 = fsub float -0.000000e+00, %58
>  %699 = fadd float %659, %698
>  %700 = fsub float -0.000000e+00, %59
>  %701 = fadd float %661, %700
>  %702 = fsub float -0.000000e+00, %62
>  %703 = fadd float %663, %702
>  %704 = fsub float -0.000000e+00, %63
>  %705 = fadd float %665, %704
>  %706 = bitcast float %699 to i32
>  %707 = bitcast float %701 to i32
>  %708 = insertelement <2 x i32> undef, i32 %706, i32 0
>  %709 = insertelement <2 x i32> %708, i32 %707, i32 1
>  %710 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %709, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %711 = extractelement <4 x float> %710, i32 0
>  %712 = extractelement <4 x float> %710, i32 1
>  %713 = extractelement <4 x float> %710, i32 2
>  %714 = bitcast float %703 to i32
>  %715 = bitcast float %705 to i32
>  %716 = insertelement <2 x i32> undef, i32 %714, i32 0
>  %717 = insertelement <2 x i32> %716, i32 %715, i32 1
>  %718 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %717, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %719 = extractelement <4 x float> %718, i32 0
>  %720 = call float @fabs(float %719)
>  %721 = fcmp uge float %720, %24
>  %722 = select i1 %721, float 1.000000e+00, float 0.000000e+00
>  %723 = fsub float -0.000000e+00, %722
>  %724 = fptosi float %723 to i32
>  %725 = bitcast i32 %724 to float
>  %726 = bitcast float %725 to i32
>  %727 = and i32 %726, 1065353216
>  %728 = bitcast i32 %727 to float
>  %729 = fmul float %711, %728
>  %730 = fmul float %712, %728
>  %731 = fmul float %713, %728
>  %732 = fmul float %729, 0x3FDC2B0880000000
>  %733 = fmul float %730, 0x3FDC2B0880000000
>  %734 = fmul float %731, 0x3FDC2B0880000000
>  %735 = fadd float %695, %732
>  %736 = fadd float %696, %733
>  %737 = fadd float %697, %734
>  %738 = fsub float -0.000000e+00, %58
>  %739 = fadd float %699, %738
>  %740 = fsub float -0.000000e+00, %59
>  %741 = fadd float %701, %740
>  %742 = fsub float -0.000000e+00, %62
>  %743 = fadd float %703, %742
>  %744 = fsub float -0.000000e+00, %63
>  %745 = fadd float %705, %744
>  %746 = bitcast float %739 to i32
>  %747 = bitcast float %741 to i32
>  %748 = insertelement <2 x i32> undef, i32 %746, i32 0
>  %749 = insertelement <2 x i32> %748, i32 %747, i32 1
>  %750 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %749, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %751 = extractelement <4 x float> %750, i32 0
>  %752 = extractelement <4 x float> %750, i32 1
>  %753 = extractelement <4 x float> %750, i32 2
>  %754 = bitcast float %743 to i32
>  %755 = bitcast float %745 to i32
>  %756 = insertelement <2 x i32> undef, i32 %754, i32 0
>  %757 = insertelement <2 x i32> %756, i32 %755, i32 1
>  %758 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %757, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %759 = extractelement <4 x float> %758, i32 0
>  %760 = call float @fabs(float %759)
>  %761 = fcmp uge float %760, %24
>  %762 = select i1 %761, float 1.000000e+00, float 0.000000e+00
>  %763 = fsub float -0.000000e+00, %762
>  %764 = fptosi float %763 to i32
>  %765 = bitcast i32 %764 to float
>  %766 = bitcast float %765 to i32
>  %767 = and i32 %766, 1065353216
>  %768 = bitcast i32 %767 to float
>  %769 = fmul float %751, %768
>  %770 = fmul float %752, %768
>  %771 = fmul float %753, %768
>  %772 = fmul float %769, 0x3FDAC27B40000000
>  %773 = fmul float %770, 0x3FDAC27B40000000
>  %774 = fmul float %771, 0x3FDAC27B40000000
>  %775 = fadd float %735, %772
>  %776 = fadd float %736, %773
>  %777 = fadd float %737, %774
>  %778 = fsub float -0.000000e+00, %58
>  %779 = fadd float %739, %778
>  %780 = fsub float -0.000000e+00, %59
>  %781 = fadd float %741, %780
>  %782 = fsub float -0.000000e+00, %62
>  %783 = fadd float %743, %782
>  %784 = fsub float -0.000000e+00, %63
>  %785 = fadd float %745, %784
>  %786 = bitcast float %779 to i32
>  %787 = bitcast float %781 to i32
>  %788 = insertelement <2 x i32> undef, i32 %786, i32 0
>  %789 = insertelement <2 x i32> %788, i32 %787, i32 1
>  %790 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %789, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %791 = extractelement <4 x float> %790, i32 0
>  %792 = extractelement <4 x float> %790, i32 1
>  %793 = extractelement <4 x float> %790, i32 2
>  %794 = bitcast float %783 to i32
>  %795 = bitcast float %785 to i32
>  %796 = insertelement <2 x i32> undef, i32 %794, i32 0
>  %797 = insertelement <2 x i32> %796, i32 %795, i32 1
>  %798 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %797, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %799 = extractelement <4 x float> %798, i32 0
>  %800 = call float @fabs(float %799)
>  %801 = fcmp uge float %800, %24
>  %802 = select i1 %801, float 1.000000e+00, float 0.000000e+00
>  %803 = fsub float -0.000000e+00, %802
>  %804 = fptosi float %803 to i32
>  %805 = bitcast i32 %804 to float
>  %806 = bitcast float %805 to i32
>  %807 = and i32 %806, 1065353216
>  %808 = bitcast i32 %807 to float
>  %809 = fmul float %791, %808
>  %810 = fmul float %792, %808
>  %811 = fmul float %793, %808
>  %812 = fmul float %809, 0x3FD96BF520000000
>  %813 = fmul float %810, 0x3FD96BF520000000
>  %814 = fmul float %811, 0x3FD96BF520000000
>  %815 = fadd float %775, %812
>  %816 = fadd float %776, %813
>  %817 = fadd float %777, %814
>  %818 = fsub float -0.000000e+00, %58
>  %819 = fadd float %779, %818
>  %820 = fsub float -0.000000e+00, %59
>  %821 = fadd float %781, %820
>  %822 = fsub float -0.000000e+00, %62
>  %823 = fadd float %783, %822
>  %824 = fsub float -0.000000e+00, %63
>  %825 = fadd float %785, %824
>  %826 = bitcast float %819 to i32
>  %827 = bitcast float %821 to i32
>  %828 = insertelement <2 x i32> undef, i32 %826, i32 0
>  %829 = insertelement <2 x i32> %828, i32 %827, i32 1
>  %830 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %829, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %831 = extractelement <4 x float> %830, i32 0
>  %832 = extractelement <4 x float> %830, i32 1
>  %833 = extractelement <4 x float> %830, i32 2
>  %834 = bitcast float %823 to i32
>  %835 = bitcast float %825 to i32
>  %836 = insertelement <2 x i32> undef, i32 %834, i32 0
>  %837 = insertelement <2 x i32> %836, i32 %835, i32 1
>  %838 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %837, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %839 = extractelement <4 x float> %838, i32 0
>  %840 = call float @fabs(float %839)
>  %841 = fcmp uge float %840, %24
>  %842 = select i1 %841, float 1.000000e+00, float 0.000000e+00
>  %843 = fsub float -0.000000e+00, %842
>  %844 = fptosi float %843 to i32
>  %845 = bitcast i32 %844 to float
>  %846 = bitcast float %845 to i32
>  %847 = and i32 %846, 1065353216
>  %848 = bitcast i32 %847 to float
>  %849 = fmul float %831, %848
>  %850 = fmul float %832, %848
>  %851 = fmul float %833, %848
>  %852 = fmul float %849, 0x3FD8268F40000000
>  %853 = fmul float %850, 0x3FD8268F40000000
>  %854 = fmul float %851, 0x3FD8268F40000000
>  %855 = fadd float %815, %852
>  %856 = fadd float %816, %853
>  %857 = fadd float %817, %854
>  %858 = fsub float -0.000000e+00, %58
>  %859 = fadd float %819, %858
>  %860 = fsub float -0.000000e+00, %59
>  %861 = fadd float %821, %860
>  %862 = fsub float -0.000000e+00, %62
>  %863 = fadd float %823, %862
>  %864 = fsub float -0.000000e+00, %63
>  %865 = fadd float %825, %864
>  %866 = bitcast float %859 to i32
>  %867 = bitcast float %861 to i32
>  %868 = insertelement <2 x i32> undef, i32 %866, i32 0
>  %869 = insertelement <2 x i32> %868, i32 %867, i32 1
>  %870 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %869, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %871 = extractelement <4 x float> %870, i32 0
>  %872 = extractelement <4 x float> %870, i32 1
>  %873 = extractelement <4 x float> %870, i32 2
>  %874 = bitcast float %863 to i32
>  %875 = bitcast float %865 to i32
>  %876 = insertelement <2 x i32> undef, i32 %874, i32 0
>  %877 = insertelement <2 x i32> %876, i32 %875, i32 1
>  %878 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %877, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %879 = extractelement <4 x float> %878, i32 0
>  %880 = call float @fabs(float %879)
>  %881 = fcmp uge float %880, %24
>  %882 = select i1 %881, float 1.000000e+00, float 0.000000e+00
>  %883 = fsub float -0.000000e+00, %882
>  %884 = fptosi float %883 to i32
>  %885 = bitcast i32 %884 to float
>  %886 = bitcast float %885 to i32
>  %887 = and i32 %886, 1065353216
>  %888 = bitcast i32 %887 to float
>  %889 = fmul float %871, %888
>  %890 = fmul float %872, %888
>  %891 = fmul float %873, %888
>  %892 = fmul float %889, 0x3FD6F16E80000000
>  %893 = fmul float %890, 0x3FD6F16E80000000
>  %894 = fmul float %891, 0x3FD6F16E80000000
>  %895 = fadd float %855, %892
>  %896 = fadd float %856, %893
>  %897 = fadd float %857, %894
>  %898 = fsub float -0.000000e+00, %58
>  %899 = fadd float %859, %898
>  %900 = fsub float -0.000000e+00, %59
>  %901 = fadd float %861, %900
>  %902 = fsub float -0.000000e+00, %62
>  %903 = fadd float %863, %902
>  %904 = fsub float -0.000000e+00, %63
>  %905 = fadd float %865, %904
>  %906 = bitcast float %899 to i32
>  %907 = bitcast float %901 to i32
>  %908 = insertelement <2 x i32> undef, i32 %906, i32 0
>  %909 = insertelement <2 x i32> %908, i32 %907, i32 1
>  %910 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %909, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %911 = extractelement <4 x float> %910, i32 0
>  %912 = extractelement <4 x float> %910, i32 1
>  %913 = extractelement <4 x float> %910, i32 2
>  %914 = bitcast float %903 to i32
>  %915 = bitcast float %905 to i32
>  %916 = insertelement <2 x i32> undef, i32 %914, i32 0
>  %917 = insertelement <2 x i32> %916, i32 %915, i32 1
>  %918 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %917, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %919 = extractelement <4 x float> %918, i32 0
>  %920 = call float @fabs(float %919)
>  %921 = fcmp uge float %920, %24
>  %922 = select i1 %921, float 1.000000e+00, float 0.000000e+00
>  %923 = fsub float -0.000000e+00, %922
>  %924 = fptosi float %923 to i32
>  %925 = bitcast i32 %924 to float
>  %926 = bitcast float %925 to i32
>  %927 = and i32 %926, 1065353216
>  %928 = bitcast i32 %927 to float
>  %929 = fmul float %911, %928
>  %930 = fmul float %912, %928
>  %931 = fmul float %913, %928
>  %932 = fmul float %929, 0x3FD5CBC280000000
>  %933 = fmul float %930, 0x3FD5CBC280000000
>  %934 = fmul float %931, 0x3FD5CBC280000000
>  %935 = fadd float %895, %932
>  %936 = fadd float %896, %933
>  %937 = fadd float %897, %934
>  %938 = fsub float -0.000000e+00, %58
>  %939 = fadd float %899, %938
>  %940 = fsub float -0.000000e+00, %59
>  %941 = fadd float %901, %940
>  %942 = fsub float -0.000000e+00, %62
>  %943 = fadd float %903, %942
>  %944 = fsub float -0.000000e+00, %63
>  %945 = fadd float %905, %944
>  %946 = bitcast float %939 to i32
>  %947 = bitcast float %941 to i32
>  %948 = insertelement <2 x i32> undef, i32 %946, i32 0
>  %949 = insertelement <2 x i32> %948, i32 %947, i32 1
>  %950 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %949, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %951 = extractelement <4 x float> %950, i32 0
>  %952 = extractelement <4 x float> %950, i32 1
>  %953 = extractelement <4 x float> %950, i32 2
>  %954 = bitcast float %943 to i32
>  %955 = bitcast float %945 to i32
>  %956 = insertelement <2 x i32> undef, i32 %954, i32 0
>  %957 = insertelement <2 x i32> %956, i32 %955, i32 1
>  %958 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %957, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %959 = extractelement <4 x float> %958, i32 0
>  %960 = call float @fabs(float %959)
>  %961 = fcmp uge float %960, %24
>  %962 = select i1 %961, float 1.000000e+00, float 0.000000e+00
>  %963 = fsub float -0.000000e+00, %962
>  %964 = fptosi float %963 to i32
>  %965 = bitcast i32 %964 to float
>  %966 = bitcast float %965 to i32
>  %967 = and i32 %966, 1065353216
>  %968 = bitcast i32 %967 to float
>  %969 = fmul float %951, %968
>  %970 = fmul float %952, %968
>  %971 = fmul float %953, %968
>  %972 = fmul float %969, 0x3FD4B4C580000000
>  %973 = fmul float %970, 0x3FD4B4C580000000
>  %974 = fmul float %971, 0x3FD4B4C580000000
>  %975 = fadd float %935, %972
>  %976 = fadd float %936, %973
>  %977 = fadd float %937, %974
>  %978 = fsub float -0.000000e+00, %58
>  %979 = fadd float %939, %978
>  %980 = fsub float -0.000000e+00, %59
>  %981 = fadd float %941, %980
>  %982 = fsub float -0.000000e+00, %62
>  %983 = fadd float %943, %982
>  %984 = fsub float -0.000000e+00, %63
>  %985 = fadd float %945, %984
>  %986 = bitcast float %979 to i32
>  %987 = bitcast float %981 to i32
>  %988 = insertelement <2 x i32> undef, i32 %986, i32 0
>  %989 = insertelement <2 x i32> %988, i32 %987, i32 1
>  %990 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %989, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %991 = extractelement <4 x float> %990, i32 0
>  %992 = extractelement <4 x float> %990, i32 1
>  %993 = extractelement <4 x float> %990, i32 2
>  %994 = bitcast float %983 to i32
>  %995 = bitcast float %985 to i32
>  %996 = insertelement <2 x i32> undef, i32 %994, i32 0
>  %997 = insertelement <2 x i32> %996, i32 %995, i32 1
>  %998 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %997, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %999 = extractelement <4 x float> %998, i32 0
>  %1000 = call float @fabs(float %999)
>  %1001 = fcmp uge float %1000, %24
>  %1002 = select i1 %1001, float 1.000000e+00, float 0.000000e+00
>  %1003 = fsub float -0.000000e+00, %1002
>  %1004 = fptosi float %1003 to i32
>  %1005 = bitcast i32 %1004 to float
>  %1006 = bitcast float %1005 to i32
>  %1007 = and i32 %1006, 1065353216
>  %1008 = bitcast i32 %1007 to float
>  %1009 = fmul float %991, %1008
>  %1010 = fmul float %992, %1008
>  %1011 = fmul float %993, %1008
>  %1012 = fmul float %1009, 0x3FD3ABBBA0000000
>  %1013 = fmul float %1010, 0x3FD3ABBBA0000000
>  %1014 = fmul float %1011, 0x3FD3ABBBA0000000
>  %1015 = fadd float %975, %1012
>  %1016 = fadd float %976, %1013
>  %1017 = fadd float %977, %1014
>  %1018 = fsub float -0.000000e+00, %58
>  %1019 = fadd float %979, %1018
>  %1020 = fsub float -0.000000e+00, %59
>  %1021 = fadd float %981, %1020
>  %1022 = fsub float -0.000000e+00, %62
>  %1023 = fadd float %983, %1022
>  %1024 = fsub float -0.000000e+00, %63
>  %1025 = fadd float %985, %1024
>  %1026 = bitcast float %1019 to i32
>  %1027 = bitcast float %1021 to i32
>  %1028 = insertelement <2 x i32> undef, i32 %1026, i32 0
>  %1029 = insertelement <2 x i32> %1028, i32 %1027, i32 1
>  %1030 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1029, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1031 = extractelement <4 x float> %1030, i32 0
>  %1032 = extractelement <4 x float> %1030, i32 1
>  %1033 = extractelement <4 x float> %1030, i32 2
>  %1034 = bitcast float %1023 to i32
>  %1035 = bitcast float %1025 to i32
>  %1036 = insertelement <2 x i32> undef, i32 %1034, i32 0
>  %1037 = insertelement <2 x i32> %1036, i32 %1035, i32 1
>  %1038 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1037, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1039 = extractelement <4 x float> %1038, i32 0
>  %1040 = call float @fabs(float %1039)
>  %1041 = fcmp uge float %1040, %24
>  %1042 = select i1 %1041, float 1.000000e+00, float 0.000000e+00
>  %1043 = fsub float -0.000000e+00, %1042
>  %1044 = fptosi float %1043 to i32
>  %1045 = bitcast i32 %1044 to float
>  %1046 = bitcast float %1045 to i32
>  %1047 = and i32 %1046, 1065353216
>  %1048 = bitcast i32 %1047 to float
>  %1049 = fmul float %1031, %1048
>  %1050 = fmul float %1032, %1048
>  %1051 = fmul float %1033, %1048
>  %1052 = fmul float %1049, 0x3FD2AFF240000000
>  %1053 = fmul float %1050, 0x3FD2AFF240000000
>  %1054 = fmul float %1051, 0x3FD2AFF240000000
>  %1055 = fadd float %1015, %1052
>  %1056 = fadd float %1016, %1053
>  %1057 = fadd float %1017, %1054
>  %1058 = fsub float -0.000000e+00, %58
>  %1059 = fadd float %1019, %1058
>  %1060 = fsub float -0.000000e+00, %59
>  %1061 = fadd float %1021, %1060
>  %1062 = fsub float -0.000000e+00, %62
>  %1063 = fadd float %1023, %1062
>  %1064 = fsub float -0.000000e+00, %63
>  %1065 = fadd float %1025, %1064
>  %1066 = bitcast float %1059 to i32
>  %1067 = bitcast float %1061 to i32
>  %1068 = insertelement <2 x i32> undef, i32 %1066, i32 0
>  %1069 = insertelement <2 x i32> %1068, i32 %1067, i32 1
>  %1070 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1069, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1071 = extractelement <4 x float> %1070, i32 0
>  %1072 = extractelement <4 x float> %1070, i32 1
>  %1073 = extractelement <4 x float> %1070, i32 2
>  %1074 = bitcast float %1063 to i32
>  %1075 = bitcast float %1065 to i32
>  %1076 = insertelement <2 x i32> undef, i32 %1074, i32 0
>  %1077 = insertelement <2 x i32> %1076, i32 %1075, i32 1
>  %1078 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1077, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1079 = extractelement <4 x float> %1078, i32 0
>  %1080 = call float @fabs(float %1079)
>  %1081 = fcmp uge float %1080, %24
>  %1082 = select i1 %1081, float 1.000000e+00, float 0.000000e+00
>  %1083 = fsub float -0.000000e+00, %1082
>  %1084 = fptosi float %1083 to i32
>  %1085 = bitcast i32 %1084 to float
>  %1086 = bitcast float %1085 to i32
>  %1087 = and i32 %1086, 1065353216
>  %1088 = bitcast i32 %1087 to float
>  %1089 = fmul float %1071, %1088
>  %1090 = fmul float %1072, %1088
>  %1091 = fmul float %1073, %1088
>  %1092 = fmul float %1089, 0x3FD1C0BFC0000000
>  %1093 = fmul float %1090, 0x3FD1C0BFC0000000
>  %1094 = fmul float %1091, 0x3FD1C0BFC0000000
>  %1095 = fadd float %1055, %1092
>  %1096 = fadd float %1056, %1093
>  %1097 = fadd float %1057, %1094
>  %1098 = fsub float -0.000000e+00, %58
>  %1099 = fadd float %1059, %1098
>  %1100 = fsub float -0.000000e+00, %59
>  %1101 = fadd float %1061, %1100
>  %1102 = fsub float -0.000000e+00, %62
>  %1103 = fadd float %1063, %1102
>  %1104 = fsub float -0.000000e+00, %63
>  %1105 = fadd float %1065, %1104
>  %1106 = bitcast float %1099 to i32
>  %1107 = bitcast float %1101 to i32
>  %1108 = insertelement <2 x i32> undef, i32 %1106, i32 0
>  %1109 = insertelement <2 x i32> %1108, i32 %1107, i32 1
>  %1110 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1109, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1111 = extractelement <4 x float> %1110, i32 0
>  %1112 = extractelement <4 x float> %1110, i32 1
>  %1113 = extractelement <4 x float> %1110, i32 2
>  %1114 = bitcast float %1103 to i32
>  %1115 = bitcast float %1105 to i32
>  %1116 = insertelement <2 x i32> undef, i32 %1114, i32 0
>  %1117 = insertelement <2 x i32> %1116, i32 %1115, i32 1
>  %1118 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1117, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1119 = extractelement <4 x float> %1118, i32 0
>  %1120 = call float @fabs(float %1119)
>  %1121 = fcmp uge float %1120, %24
>  %1122 = select i1 %1121, float 1.000000e+00, float 0.000000e+00
>  %1123 = fsub float -0.000000e+00, %1122
>  %1124 = fptosi float %1123 to i32
>  %1125 = bitcast i32 %1124 to float
>  %1126 = bitcast float %1125 to i32
>  %1127 = and i32 %1126, 1065353216
>  %1128 = bitcast i32 %1127 to float
>  %1129 = fmul float %1111, %1128
>  %1130 = fmul float %1112, %1128
>  %1131 = fmul float %1113, %1128
>  %1132 = fmul float %1129, 0x3FD0DD8300000000
>  %1133 = fmul float %1130, 0x3FD0DD8300000000
>  %1134 = fmul float %1131, 0x3FD0DD8300000000
>  %1135 = fadd float %1095, %1132
>  %1136 = fadd float %1096, %1133
>  %1137 = fadd float %1097, %1134
>  %1138 = fsub float -0.000000e+00, %58
>  %1139 = fadd float %1099, %1138
>  %1140 = fsub float -0.000000e+00, %59
>  %1141 = fadd float %1101, %1140
>  %1142 = fsub float -0.000000e+00, %62
>  %1143 = fadd float %1103, %1142
>  %1144 = fsub float -0.000000e+00, %63
>  %1145 = fadd float %1105, %1144
>  %1146 = bitcast float %1139 to i32
>  %1147 = bitcast float %1141 to i32
>  %1148 = insertelement <2 x i32> undef, i32 %1146, i32 0
>  %1149 = insertelement <2 x i32> %1148, i32 %1147, i32 1
>  %1150 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1149, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1151 = extractelement <4 x float> %1150, i32 0
>  %1152 = extractelement <4 x float> %1150, i32 1
>  %1153 = extractelement <4 x float> %1150, i32 2
>  %1154 = bitcast float %1143 to i32
>  %1155 = bitcast float %1145 to i32
>  %1156 = insertelement <2 x i32> undef, i32 %1154, i32 0
>  %1157 = insertelement <2 x i32> %1156, i32 %1155, i32 1
>  %1158 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1157, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1159 = extractelement <4 x float> %1158, i32 0
>  %1160 = call float @fabs(float %1159)
>  %1161 = fcmp uge float %1160, %24
>  %1162 = select i1 %1161, float 1.000000e+00, float 0.000000e+00
>  %1163 = fsub float -0.000000e+00, %1162
>  %1164 = fptosi float %1163 to i32
>  %1165 = bitcast i32 %1164 to float
>  %1166 = bitcast float %1165 to i32
>  %1167 = and i32 %1166, 1065353216
>  %1168 = bitcast i32 %1167 to float
>  %1169 = fmul float %1151, %1168
>  %1170 = fmul float %1152, %1168
>  %1171 = fmul float %1153, %1168
>  %1172 = fmul float %1169, 0x3FD005A2E0000000
>  %1173 = fmul float %1170, 0x3FD005A2E0000000
>  %1174 = fmul float %1171, 0x3FD005A2E0000000
>  %1175 = fadd float %1135, %1172
>  %1176 = fadd float %1136, %1173
>  %1177 = fadd float %1137, %1174
>  %1178 = fsub float -0.000000e+00, %58
>  %1179 = fadd float %1139, %1178
>  %1180 = fsub float -0.000000e+00, %59
>  %1181 = fadd float %1141, %1180
>  %1182 = fsub float -0.000000e+00, %62
>  %1183 = fadd float %1143, %1182
>  %1184 = fsub float -0.000000e+00, %63
>  %1185 = fadd float %1145, %1184
>  %1186 = bitcast float %1179 to i32
>  %1187 = bitcast float %1181 to i32
>  %1188 = insertelement <2 x i32> undef, i32 %1186, i32 0
>  %1189 = insertelement <2 x i32> %1188, i32 %1187, i32 1
>  %1190 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1189, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1191 = extractelement <4 x float> %1190, i32 0
>  %1192 = extractelement <4 x float> %1190, i32 1
>  %1193 = extractelement <4 x float> %1190, i32 2
>  %1194 = bitcast float %1183 to i32
>  %1195 = bitcast float %1185 to i32
>  %1196 = insertelement <2 x i32> undef, i32 %1194, i32 0
>  %1197 = insertelement <2 x i32> %1196, i32 %1195, i32 1
>  %1198 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1197, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1199 = extractelement <4 x float> %1198, i32 0
>  %1200 = call float @fabs(float %1199)
>  %1201 = fcmp uge float %1200, %24
>  %1202 = select i1 %1201, float 1.000000e+00, float 0.000000e+00
>  %1203 = fsub float -0.000000e+00, %1202
>  %1204 = fptosi float %1203 to i32
>  %1205 = bitcast i32 %1204 to float
>  %1206 = bitcast float %1205 to i32
>  %1207 = and i32 %1206, 1065353216
>  %1208 = bitcast i32 %1207 to float
>  %1209 = fmul float %1191, %1208
>  %1210 = fmul float %1192, %1208
>  %1211 = fmul float %1193, %1208
>  %1212 = fmul float %1209, 0x3FCE711BE0000000
>  %1213 = fmul float %1210, 0x3FCE711BE0000000
>  %1214 = fmul float %1211, 0x3FCE711BE0000000
>  %1215 = fadd float %1175, %1212
>  %1216 = fadd float %1176, %1213
>  %1217 = fadd float %1177, %1214
>  %1218 = fsub float -0.000000e+00, %58
>  %1219 = fadd float %1179, %1218
>  %1220 = fsub float -0.000000e+00, %59
>  %1221 = fadd float %1181, %1220
>  %1222 = fsub float -0.000000e+00, %62
>  %1223 = fadd float %1183, %1222
>  %1224 = fsub float -0.000000e+00, %63
>  %1225 = fadd float %1185, %1224
>  %1226 = bitcast float %1219 to i32
>  %1227 = bitcast float %1221 to i32
>  %1228 = insertelement <2 x i32> undef, i32 %1226, i32 0
>  %1229 = insertelement <2 x i32> %1228, i32 %1227, i32 1
>  %1230 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1229, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1231 = extractelement <4 x float> %1230, i32 0
>  %1232 = extractelement <4 x float> %1230, i32 1
>  %1233 = extractelement <4 x float> %1230, i32 2
>  %1234 = bitcast float %1223 to i32
>  %1235 = bitcast float %1225 to i32
>  %1236 = insertelement <2 x i32> undef, i32 %1234, i32 0
>  %1237 = insertelement <2 x i32> %1236, i32 %1235, i32 1
>  %1238 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1237, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1239 = extractelement <4 x float> %1238, i32 0
>  %1240 = call float @fabs(float %1239)
>  %1241 = fcmp uge float %1240, %24
>  %1242 = select i1 %1241, float 1.000000e+00, float 0.000000e+00
>  %1243 = fsub float -0.000000e+00, %1242
>  %1244 = fptosi float %1243 to i32
>  %1245 = bitcast i32 %1244 to float
>  %1246 = bitcast float %1245 to i32
>  %1247 = and i32 %1246, 1065353216
>  %1248 = bitcast i32 %1247 to float
>  %1249 = fmul float %1231, %1248
>  %1250 = fmul float %1232, %1248
>  %1251 = fmul float %1233, %1248
>  %1252 = fmul float %1249, 0x3FCCEB7400000000
>  %1253 = fmul float %1250, 0x3FCCEB7400000000
>  %1254 = fmul float %1251, 0x3FCCEB7400000000
>  %1255 = fadd float %1215, %1252
>  %1256 = fadd float %1216, %1253
>  %1257 = fadd float %1217, %1254
>  %1258 = fsub float -0.000000e+00, %58
>  %1259 = fadd float %1219, %1258
>  %1260 = fsub float -0.000000e+00, %59
>  %1261 = fadd float %1221, %1260
>  %1262 = fsub float -0.000000e+00, %62
>  %1263 = fadd float %1223, %1262
>  %1264 = fsub float -0.000000e+00, %63
>  %1265 = fadd float %1225, %1264
>  %1266 = bitcast float %1259 to i32
>  %1267 = bitcast float %1261 to i32
>  %1268 = insertelement <2 x i32> undef, i32 %1266, i32 0
>  %1269 = insertelement <2 x i32> %1268, i32 %1267, i32 1
>  %1270 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1269, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1271 = extractelement <4 x float> %1270, i32 0
>  %1272 = extractelement <4 x float> %1270, i32 1
>  %1273 = extractelement <4 x float> %1270, i32 2
>  %1274 = bitcast float %1263 to i32
>  %1275 = bitcast float %1265 to i32
>  %1276 = insertelement <2 x i32> undef, i32 %1274, i32 0
>  %1277 = insertelement <2 x i32> %1276, i32 %1275, i32 1
>  %1278 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1277, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1279 = extractelement <4 x float> %1278, i32 0
>  %1280 = call float @fabs(float %1279)
>  %1281 = fcmp uge float %1280, %24
>  %1282 = select i1 %1281, float 1.000000e+00, float 0.000000e+00
>  %1283 = fsub float -0.000000e+00, %1282
>  %1284 = fptosi float %1283 to i32
>  %1285 = bitcast i32 %1284 to float
>  %1286 = bitcast float %1285 to i32
>  %1287 = and i32 %1286, 1065353216
>  %1288 = bitcast i32 %1287 to float
>  %1289 = fmul float %1271, %1288
>  %1290 = fmul float %1272, %1288
>  %1291 = fmul float %1273, %1288
>  %1292 = fmul float %1289, 0x3FCB7947C0000000
>  %1293 = fmul float %1290, 0x3FCB7947C0000000
>  %1294 = fmul float %1291, 0x3FCB7947C0000000
>  %1295 = fadd float %1255, %1292
>  %1296 = fadd float %1256, %1293
>  %1297 = fadd float %1257, %1294
>  %1298 = fsub float -0.000000e+00, %58
>  %1299 = fadd float %1259, %1298
>  %1300 = fsub float -0.000000e+00, %59
>  %1301 = fadd float %1261, %1300
>  %1302 = fsub float -0.000000e+00, %62
>  %1303 = fadd float %1263, %1302
>  %1304 = fsub float -0.000000e+00, %63
>  %1305 = fadd float %1265, %1304
>  %1306 = bitcast float %1299 to i32
>  %1307 = bitcast float %1301 to i32
>  %1308 = insertelement <2 x i32> undef, i32 %1306, i32 0
>  %1309 = insertelement <2 x i32> %1308, i32 %1307, i32 1
>  %1310 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1309, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1311 = extractelement <4 x float> %1310, i32 0
>  %1312 = extractelement <4 x float> %1310, i32 1
>  %1313 = extractelement <4 x float> %1310, i32 2
>  %1314 = bitcast float %1303 to i32
>  %1315 = bitcast float %1305 to i32
>  %1316 = insertelement <2 x i32> undef, i32 %1314, i32 0
>  %1317 = insertelement <2 x i32> %1316, i32 %1315, i32 1
>  %1318 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1317, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1319 = extractelement <4 x float> %1318, i32 0
>  %1320 = call float @fabs(float %1319)
>  %1321 = fcmp uge float %1320, %24
>  %1322 = select i1 %1321, float 1.000000e+00, float 0.000000e+00
>  %1323 = fsub float -0.000000e+00, %1322
>  %1324 = fptosi float %1323 to i32
>  %1325 = bitcast i32 %1324 to float
>  %1326 = bitcast float %1325 to i32
>  %1327 = and i32 %1326, 1065353216
>  %1328 = bitcast i32 %1327 to float
>  %1329 = fmul float %1311, %1328
>  %1330 = fmul float %1312, %1328
>  %1331 = fmul float %1313, %1328
>  %1332 = fmul float %1329, 0x3FCA199DC0000000
>  %1333 = fmul float %1330, 0x3FCA199DC0000000
>  %1334 = fmul float %1331, 0x3FCA199DC0000000
>  %1335 = fadd float %1295, %1332
>  %1336 = fadd float %1296, %1333
>  %1337 = fadd float %1297, %1334
>  %1338 = fsub float -0.000000e+00, %58
>  %1339 = fadd float %1299, %1338
>  %1340 = fsub float -0.000000e+00, %59
>  %1341 = fadd float %1301, %1340
>  %1342 = fsub float -0.000000e+00, %62
>  %1343 = fadd float %1303, %1342
>  %1344 = fsub float -0.000000e+00, %63
>  %1345 = fadd float %1305, %1344
>  %1346 = bitcast float %1339 to i32
>  %1347 = bitcast float %1341 to i32
>  %1348 = insertelement <2 x i32> undef, i32 %1346, i32 0
>  %1349 = insertelement <2 x i32> %1348, i32 %1347, i32 1
>  %1350 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1349, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1351 = extractelement <4 x float> %1350, i32 0
>  %1352 = extractelement <4 x float> %1350, i32 1
>  %1353 = extractelement <4 x float> %1350, i32 2
>  %1354 = bitcast float %1343 to i32
>  %1355 = bitcast float %1345 to i32
>  %1356 = insertelement <2 x i32> undef, i32 %1354, i32 0
>  %1357 = insertelement <2 x i32> %1356, i32 %1355, i32 1
>  %1358 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1357, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1359 = extractelement <4 x float> %1358, i32 0
>  %1360 = call float @fabs(float %1359)
>  %1361 = fcmp uge float %1360, %24
>  %1362 = select i1 %1361, float 1.000000e+00, float 0.000000e+00
>  %1363 = fsub float -0.000000e+00, %1362
>  %1364 = fptosi float %1363 to i32
>  %1365 = bitcast i32 %1364 to float
>  %1366 = bitcast float %1365 to i32
>  %1367 = and i32 %1366, 1065353216
>  %1368 = bitcast i32 %1367 to float
>  %1369 = fmul float %1351, %1368
>  %1370 = fmul float %1352, %1368
>  %1371 = fmul float %1353, %1368
>  %1372 = fmul float %1369, 0x3FC8CB8900000000
>  %1373 = fmul float %1370, 0x3FC8CB8900000000
>  %1374 = fmul float %1371, 0x3FC8CB8900000000
>  %1375 = fadd float %1335, %1372
>  %1376 = fadd float %1336, %1373
>  %1377 = fadd float %1337, %1374
>  %1378 = fsub float -0.000000e+00, %58
>  %1379 = fadd float %1339, %1378
>  %1380 = fsub float -0.000000e+00, %59
>  %1381 = fadd float %1341, %1380
>  %1382 = fsub float -0.000000e+00, %62
>  %1383 = fadd float %1343, %1382
>  %1384 = fsub float -0.000000e+00, %63
>  %1385 = fadd float %1345, %1384
>  %1386 = bitcast float %1379 to i32
>  %1387 = bitcast float %1381 to i32
>  %1388 = insertelement <2 x i32> undef, i32 %1386, i32 0
>  %1389 = insertelement <2 x i32> %1388, i32 %1387, i32 1
>  %1390 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1389, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1391 = extractelement <4 x float> %1390, i32 0
>  %1392 = extractelement <4 x float> %1390, i32 1
>  %1393 = extractelement <4 x float> %1390, i32 2
>  %1394 = bitcast float %1383 to i32
>  %1395 = bitcast float %1385 to i32
>  %1396 = insertelement <2 x i32> undef, i32 %1394, i32 0
>  %1397 = insertelement <2 x i32> %1396, i32 %1395, i32 1
>  %1398 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1397, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1399 = extractelement <4 x float> %1398, i32 0
>  %1400 = call float @fabs(float %1399)
>  %1401 = fcmp uge float %1400, %24
>  %1402 = select i1 %1401, float 1.000000e+00, float 0.000000e+00
>  %1403 = fsub float -0.000000e+00, %1402
>  %1404 = fptosi float %1403 to i32
>  %1405 = bitcast i32 %1404 to float
>  %1406 = bitcast float %1405 to i32
>  %1407 = and i32 %1406, 1065353216
>  %1408 = bitcast i32 %1407 to float
>  %1409 = fmul float %1391, %1408
>  %1410 = fmul float %1392, %1408
>  %1411 = fmul float %1393, %1408
>  %1412 = fmul float %1409, 0x3FC78E2880000000
>  %1413 = fmul float %1410, 0x3FC78E2880000000
>  %1414 = fmul float %1411, 0x3FC78E2880000000
>  %1415 = fadd float %1375, %1412
>  %1416 = fadd float %1376, %1413
>  %1417 = fadd float %1377, %1414
>  %1418 = fsub float -0.000000e+00, %58
>  %1419 = fadd float %1379, %1418
>  %1420 = fsub float -0.000000e+00, %59
>  %1421 = fadd float %1381, %1420
>  %1422 = fsub float -0.000000e+00, %62
>  %1423 = fadd float %1383, %1422
>  %1424 = fsub float -0.000000e+00, %63
>  %1425 = fadd float %1385, %1424
>  %1426 = bitcast float %1419 to i32
>  %1427 = bitcast float %1421 to i32
>  %1428 = insertelement <2 x i32> undef, i32 %1426, i32 0
>  %1429 = insertelement <2 x i32> %1428, i32 %1427, i32 1
>  %1430 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1429, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1431 = extractelement <4 x float> %1430, i32 0
>  %1432 = extractelement <4 x float> %1430, i32 1
>  %1433 = extractelement <4 x float> %1430, i32 2
>  %1434 = bitcast float %1423 to i32
>  %1435 = bitcast float %1425 to i32
>  %1436 = insertelement <2 x i32> undef, i32 %1434, i32 0
>  %1437 = insertelement <2 x i32> %1436, i32 %1435, i32 1
>  %1438 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1437, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1439 = extractelement <4 x float> %1438, i32 0
>  %1440 = call float @fabs(float %1439)
>  %1441 = fcmp uge float %1440, %24
>  %1442 = select i1 %1441, float 1.000000e+00, float 0.000000e+00
>  %1443 = fsub float -0.000000e+00, %1442
>  %1444 = fptosi float %1443 to i32
>  %1445 = bitcast i32 %1444 to float
>  %1446 = bitcast float %1445 to i32
>  %1447 = and i32 %1446, 1065353216
>  %1448 = bitcast i32 %1447 to float
>  %1449 = fmul float %1431, %1448
>  %1450 = fmul float %1432, %1448
>  %1451 = fmul float %1433, %1448
>  %1452 = fmul float %1449, 0x3FC660A680000000
>  %1453 = fmul float %1450, 0x3FC660A680000000
>  %1454 = fmul float %1451, 0x3FC660A680000000
>  %1455 = fadd float %1415, %1452
>  %1456 = fadd float %1416, %1453
>  %1457 = fadd float %1417, %1454
>  %1458 = fsub float -0.000000e+00, %58
>  %1459 = fadd float %1419, %1458
>  %1460 = fsub float -0.000000e+00, %59
>  %1461 = fadd float %1421, %1460
>  %1462 = fsub float -0.000000e+00, %62
>  %1463 = fadd float %1423, %1462
>  %1464 = fsub float -0.000000e+00, %63
>  %1465 = fadd float %1425, %1464
>  %1466 = bitcast float %1459 to i32
>  %1467 = bitcast float %1461 to i32
>  %1468 = insertelement <2 x i32> undef, i32 %1466, i32 0
>  %1469 = insertelement <2 x i32> %1468, i32 %1467, i32 1
>  %1470 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1469, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1471 = extractelement <4 x float> %1470, i32 0
>  %1472 = extractelement <4 x float> %1470, i32 1
>  %1473 = extractelement <4 x float> %1470, i32 2
>  %1474 = bitcast float %1463 to i32
>  %1475 = bitcast float %1465 to i32
>  %1476 = insertelement <2 x i32> undef, i32 %1474, i32 0
>  %1477 = insertelement <2 x i32> %1476, i32 %1475, i32 1
>  %1478 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1477, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1479 = extractelement <4 x float> %1478, i32 0
>  %1480 = call float @fabs(float %1479)
>  %1481 = fcmp uge float %1480, %24
>  %1482 = select i1 %1481, float 1.000000e+00, float 0.000000e+00
>  %1483 = fsub float -0.000000e+00, %1482
>  %1484 = fptosi float %1483 to i32
>  %1485 = bitcast i32 %1484 to float
>  %1486 = bitcast float %1485 to i32
>  %1487 = and i32 %1486, 1065353216
>  %1488 = bitcast i32 %1487 to float
>  %1489 = fmul float %1471, %1488
>  %1490 = fmul float %1472, %1488
>  %1491 = fmul float %1473, %1488
>  %1492 = fmul float %1489, 0x3FC54237C0000000
>  %1493 = fmul float %1490, 0x3FC54237C0000000
>  %1494 = fmul float %1491, 0x3FC54237C0000000
>  %1495 = fadd float %1455, %1492
>  %1496 = fadd float %1456, %1493
>  %1497 = fadd float %1457, %1494
>  %1498 = fsub float -0.000000e+00, %58
>  %1499 = fadd float %1459, %1498
>  %1500 = fsub float -0.000000e+00, %59
>  %1501 = fadd float %1461, %1500
>  %1502 = fsub float -0.000000e+00, %62
>  %1503 = fadd float %1463, %1502
>  %1504 = fsub float -0.000000e+00, %63
>  %1505 = fadd float %1465, %1504
>  %1506 = bitcast float %1499 to i32
>  %1507 = bitcast float %1501 to i32
>  %1508 = insertelement <2 x i32> undef, i32 %1506, i32 0
>  %1509 = insertelement <2 x i32> %1508, i32 %1507, i32 1
>  %1510 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1509, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1511 = extractelement <4 x float> %1510, i32 0
>  %1512 = extractelement <4 x float> %1510, i32 1
>  %1513 = extractelement <4 x float> %1510, i32 2
>  %1514 = bitcast float %1503 to i32
>  %1515 = bitcast float %1505 to i32
>  %1516 = insertelement <2 x i32> undef, i32 %1514, i32 0
>  %1517 = insertelement <2 x i32> %1516, i32 %1515, i32 1
>  %1518 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1517, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1519 = extractelement <4 x float> %1518, i32 0
>  %1520 = call float @fabs(float %1519)
>  %1521 = fcmp uge float %1520, %24
>  %1522 = select i1 %1521, float 1.000000e+00, float 0.000000e+00
>  %1523 = fsub float -0.000000e+00, %1522
>  %1524 = fptosi float %1523 to i32
>  %1525 = bitcast i32 %1524 to float
>  %1526 = bitcast float %1525 to i32
>  %1527 = and i32 %1526, 1065353216
>  %1528 = bitcast i32 %1527 to float
>  %1529 = fmul float %1511, %1528
>  %1530 = fmul float %1512, %1528
>  %1531 = fmul float %1513, %1528
>  %1532 = fmul float %1529, 0x3FC4321B60000000
>  %1533 = fmul float %1530, 0x3FC4321B60000000
>  %1534 = fmul float %1531, 0x3FC4321B60000000
>  %1535 = fadd float %1495, %1532
>  %1536 = fadd float %1496, %1533
>  %1537 = fadd float %1497, %1534
>  %1538 = fsub float -0.000000e+00, %58
>  %1539 = fadd float %1499, %1538
>  %1540 = fsub float -0.000000e+00, %59
>  %1541 = fadd float %1501, %1540
>  %1542 = fsub float -0.000000e+00, %62
>  %1543 = fadd float %1503, %1542
>  %1544 = fsub float -0.000000e+00, %63
>  %1545 = fadd float %1505, %1544
>  %1546 = bitcast float %1539 to i32
>  %1547 = bitcast float %1541 to i32
>  %1548 = insertelement <2 x i32> undef, i32 %1546, i32 0
>  %1549 = insertelement <2 x i32> %1548, i32 %1547, i32 1
>  %1550 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1549, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1551 = extractelement <4 x float> %1550, i32 0
>  %1552 = extractelement <4 x float> %1550, i32 1
>  %1553 = extractelement <4 x float> %1550, i32 2
>  %1554 = bitcast float %1543 to i32
>  %1555 = bitcast float %1545 to i32
>  %1556 = insertelement <2 x i32> undef, i32 %1554, i32 0
>  %1557 = insertelement <2 x i32> %1556, i32 %1555, i32 1
>  %1558 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1557, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1559 = extractelement <4 x float> %1558, i32 0
>  %1560 = call float @fabs(float %1559)
>  %1561 = fcmp uge float %1560, %24
>  %1562 = select i1 %1561, float 1.000000e+00, float 0.000000e+00
>  %1563 = fsub float -0.000000e+00, %1562
>  %1564 = fptosi float %1563 to i32
>  %1565 = bitcast i32 %1564 to float
>  %1566 = bitcast float %1565 to i32
>  %1567 = and i32 %1566, 1065353216
>  %1568 = bitcast i32 %1567 to float
>  %1569 = fmul float %1551, %1568
>  %1570 = fmul float %1552, %1568
>  %1571 = fmul float %1553, %1568
>  %1572 = fmul float %1569, 0x3FC32F9A00000000
>  %1573 = fmul float %1570, 0x3FC32F9A00000000
>  %1574 = fmul float %1571, 0x3FC32F9A00000000
>  %1575 = fadd float %1535, %1572
>  %1576 = fadd float %1536, %1573
>  %1577 = fadd float %1537, %1574
>  %1578 = fsub float -0.000000e+00, %58
>  %1579 = fadd float %1539, %1578
>  %1580 = fsub float -0.000000e+00, %59
>  %1581 = fadd float %1541, %1580
>  %1582 = fsub float -0.000000e+00, %62
>  %1583 = fadd float %1543, %1582
>  %1584 = fsub float -0.000000e+00, %63
>  %1585 = fadd float %1545, %1584
>  %1586 = bitcast float %1579 to i32
>  %1587 = bitcast float %1581 to i32
>  %1588 = insertelement <2 x i32> undef, i32 %1586, i32 0
>  %1589 = insertelement <2 x i32> %1588, i32 %1587, i32 1
>  %1590 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1589, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1591 = extractelement <4 x float> %1590, i32 0
>  %1592 = extractelement <4 x float> %1590, i32 1
>  %1593 = extractelement <4 x float> %1590, i32 2
>  %1594 = bitcast float %1583 to i32
>  %1595 = bitcast float %1585 to i32
>  %1596 = insertelement <2 x i32> undef, i32 %1594, i32 0
>  %1597 = insertelement <2 x i32> %1596, i32 %1595, i32 1
>  %1598 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1597, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1599 = extractelement <4 x float> %1598, i32 0
>  %1600 = call float @fabs(float %1599)
>  %1601 = fcmp uge float %1600, %24
>  %1602 = select i1 %1601, float 1.000000e+00, float 0.000000e+00
>  %1603 = fsub float -0.000000e+00, %1602
>  %1604 = fptosi float %1603 to i32
>  %1605 = bitcast i32 %1604 to float
>  %1606 = bitcast float %1605 to i32
>  %1607 = and i32 %1606, 1065353216
>  %1608 = bitcast i32 %1607 to float
>  %1609 = fmul float %1591, %1608
>  %1610 = fmul float %1592, %1608
>  %1611 = fmul float %1593, %1608
>  %1612 = fmul float %1609, 0x3FC23A0580000000
>  %1613 = fmul float %1610, 0x3FC23A0580000000
>  %1614 = fmul float %1611, 0x3FC23A0580000000
>  %1615 = fadd float %1575, %1612
>  %1616 = fadd float %1576, %1613
>  %1617 = fadd float %1577, %1614
>  %1618 = fsub float -0.000000e+00, %58
>  %1619 = fadd float %1579, %1618
>  %1620 = fsub float -0.000000e+00, %59
>  %1621 = fadd float %1581, %1620
>  %1622 = fsub float -0.000000e+00, %62
>  %1623 = fadd float %1583, %1622
>  %1624 = fsub float -0.000000e+00, %63
>  %1625 = fadd float %1585, %1624
>  %1626 = bitcast float %1619 to i32
>  %1627 = bitcast float %1621 to i32
>  %1628 = insertelement <2 x i32> undef, i32 %1626, i32 0
>  %1629 = insertelement <2 x i32> %1628, i32 %1627, i32 1
>  %1630 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1629, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1631 = extractelement <4 x float> %1630, i32 0
>  %1632 = extractelement <4 x float> %1630, i32 1
>  %1633 = extractelement <4 x float> %1630, i32 2
>  %1634 = bitcast float %1623 to i32
>  %1635 = bitcast float %1625 to i32
>  %1636 = insertelement <2 x i32> undef, i32 %1634, i32 0
>  %1637 = insertelement <2 x i32> %1636, i32 %1635, i32 1
>  %1638 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1637, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1639 = extractelement <4 x float> %1638, i32 0
>  %1640 = call float @fabs(float %1639)
>  %1641 = fcmp uge float %1640, %24
>  %1642 = select i1 %1641, float 1.000000e+00, float 0.000000e+00
>  %1643 = fsub float -0.000000e+00, %1642
>  %1644 = fptosi float %1643 to i32
>  %1645 = bitcast i32 %1644 to float
>  %1646 = bitcast float %1645 to i32
>  %1647 = and i32 %1646, 1065353216
>  %1648 = bitcast i32 %1647 to float
>  %1649 = fmul float %1631, %1648
>  %1650 = fmul float %1632, %1648
>  %1651 = fmul float %1633, %1648
>  %1652 = fmul float %1649, 0x3FC150B860000000
>  %1653 = fmul float %1650, 0x3FC150B860000000
>  %1654 = fmul float %1651, 0x3FC150B860000000
>  %1655 = fadd float %1615, %1652
>  %1656 = fadd float %1616, %1653
>  %1657 = fadd float %1617, %1654
>  %1658 = fsub float -0.000000e+00, %58
>  %1659 = fadd float %1619, %1658
>  %1660 = fsub float -0.000000e+00, %59
>  %1661 = fadd float %1621, %1660
>  %1662 = fsub float -0.000000e+00, %62
>  %1663 = fadd float %1623, %1662
>  %1664 = fsub float -0.000000e+00, %63
>  %1665 = fadd float %1625, %1664
>  %1666 = bitcast float %1659 to i32
>  %1667 = bitcast float %1661 to i32
>  %1668 = insertelement <2 x i32> undef, i32 %1666, i32 0
>  %1669 = insertelement <2 x i32> %1668, i32 %1667, i32 1
>  %1670 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1669, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1671 = extractelement <4 x float> %1670, i32 0
>  %1672 = extractelement <4 x float> %1670, i32 1
>  %1673 = extractelement <4 x float> %1670, i32 2
>  %1674 = bitcast float %1663 to i32
>  %1675 = bitcast float %1665 to i32
>  %1676 = insertelement <2 x i32> undef, i32 %1674, i32 0
>  %1677 = insertelement <2 x i32> %1676, i32 %1675, i32 1
>  %1678 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1677, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1679 = extractelement <4 x float> %1678, i32 0
>  %1680 = call float @fabs(float %1679)
>  %1681 = fcmp uge float %1680, %24
>  %1682 = select i1 %1681, float 1.000000e+00, float 0.000000e+00
>  %1683 = fsub float -0.000000e+00, %1682
>  %1684 = fptosi float %1683 to i32
>  %1685 = bitcast i32 %1684 to float
>  %1686 = bitcast float %1685 to i32
>  %1687 = and i32 %1686, 1065353216
>  %1688 = bitcast i32 %1687 to float
>  %1689 = fmul float %1671, %1688
>  %1690 = fmul float %1672, %1688
>  %1691 = fmul float %1673, %1688
>  %1692 = fmul float %1689, 0x3FC0731580000000
>  %1693 = fmul float %1690, 0x3FC0731580000000
>  %1694 = fmul float %1691, 0x3FC0731580000000
>  %1695 = fadd float %1655, %1692
>  %1696 = fadd float %1656, %1693
>  %1697 = fadd float %1657, %1694
>  %1698 = fsub float -0.000000e+00, %58
>  %1699 = fadd float %1659, %1698
>  %1700 = fsub float -0.000000e+00, %59
>  %1701 = fadd float %1661, %1700
>  %1702 = fsub float -0.000000e+00, %62
>  %1703 = fadd float %1663, %1702
>  %1704 = fsub float -0.000000e+00, %63
>  %1705 = fadd float %1665, %1704
>  %1706 = bitcast float %1699 to i32
>  %1707 = bitcast float %1701 to i32
>  %1708 = insertelement <2 x i32> undef, i32 %1706, i32 0
>  %1709 = insertelement <2 x i32> %1708, i32 %1707, i32 1
>  %1710 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1709, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1711 = extractelement <4 x float> %1710, i32 0
>  %1712 = extractelement <4 x float> %1710, i32 1
>  %1713 = extractelement <4 x float> %1710, i32 2
>  %1714 = bitcast float %1703 to i32
>  %1715 = bitcast float %1705 to i32
>  %1716 = insertelement <2 x i32> undef, i32 %1714, i32 0
>  %1717 = insertelement <2 x i32> %1716, i32 %1715, i32 1
>  %1718 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1717, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1719 = extractelement <4 x float> %1718, i32 0
>  %1720 = call float @fabs(float %1719)
>  %1721 = fcmp uge float %1720, %24
>  %1722 = select i1 %1721, float 1.000000e+00, float 0.000000e+00
>  %1723 = fsub float -0.000000e+00, %1722
>  %1724 = fptosi float %1723 to i32
>  %1725 = bitcast i32 %1724 to float
>  %1726 = bitcast float %1725 to i32
>  %1727 = and i32 %1726, 1065353216
>  %1728 = bitcast i32 %1727 to float
>  %1729 = fmul float %1711, %1728
>  %1730 = fmul float %1712, %1728
>  %1731 = fmul float %1713, %1728
>  %1732 = fmul float %1729, 0x3FBF410F40000000
>  %1733 = fmul float %1730, 0x3FBF410F40000000
>  %1734 = fmul float %1731, 0x3FBF410F40000000
>  %1735 = fadd float %1695, %1732
>  %1736 = fadd float %1696, %1733
>  %1737 = fadd float %1697, %1734
>  %1738 = fsub float -0.000000e+00, %58
>  %1739 = fadd float %1699, %1738
>  %1740 = fsub float -0.000000e+00, %59
>  %1741 = fadd float %1701, %1740
>  %1742 = fsub float -0.000000e+00, %62
>  %1743 = fadd float %1703, %1742
>  %1744 = fsub float -0.000000e+00, %63
>  %1745 = fadd float %1705, %1744
>  %1746 = bitcast float %1739 to i32
>  %1747 = bitcast float %1741 to i32
>  %1748 = insertelement <2 x i32> undef, i32 %1746, i32 0
>  %1749 = insertelement <2 x i32> %1748, i32 %1747, i32 1
>  %1750 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1749, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1751 = extractelement <4 x float> %1750, i32 0
>  %1752 = extractelement <4 x float> %1750, i32 1
>  %1753 = extractelement <4 x float> %1750, i32 2
>  %1754 = bitcast float %1743 to i32
>  %1755 = bitcast float %1745 to i32
>  %1756 = insertelement <2 x i32> undef, i32 %1754, i32 0
>  %1757 = insertelement <2 x i32> %1756, i32 %1755, i32 1
>  %1758 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1757, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1759 = extractelement <4 x float> %1758, i32 0
>  %1760 = call float @fabs(float %1759)
>  %1761 = fcmp uge float %1760, %24
>  %1762 = select i1 %1761, float 1.000000e+00, float 0.000000e+00
>  %1763 = fsub float -0.000000e+00, %1762
>  %1764 = fptosi float %1763 to i32
>  %1765 = bitcast i32 %1764 to float
>  %1766 = bitcast float %1765 to i32
>  %1767 = and i32 %1766, 1065353216
>  %1768 = bitcast i32 %1767 to float
>  %1769 = fmul float %1751, %1768
>  %1770 = fmul float %1752, %1768
>  %1771 = fmul float %1753, %1768
>  %1772 = fmul float %1769, 0x3FBDB101A0000000
>  %1773 = fmul float %1770, 0x3FBDB101A0000000
>  %1774 = fmul float %1771, 0x3FBDB101A0000000
>  %1775 = fadd float %1735, %1772
>  %1776 = fadd float %1736, %1773
>  %1777 = fadd float %1737, %1774
>  %1778 = fsub float -0.000000e+00, %58
>  %1779 = fadd float %1739, %1778
>  %1780 = fsub float -0.000000e+00, %59
>  %1781 = fadd float %1741, %1780
>  %1782 = fsub float -0.000000e+00, %62
>  %1783 = fadd float %1743, %1782
>  %1784 = fsub float -0.000000e+00, %63
>  %1785 = fadd float %1745, %1784
>  %1786 = bitcast float %1779 to i32
>  %1787 = bitcast float %1781 to i32
>  %1788 = insertelement <2 x i32> undef, i32 %1786, i32 0
>  %1789 = insertelement <2 x i32> %1788, i32 %1787, i32 1
>  %1790 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1789, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1791 = extractelement <4 x float> %1790, i32 0
>  %1792 = extractelement <4 x float> %1790, i32 1
>  %1793 = extractelement <4 x float> %1790, i32 2
>  %1794 = bitcast float %1783 to i32
>  %1795 = bitcast float %1785 to i32
>  %1796 = insertelement <2 x i32> undef, i32 %1794, i32 0
>  %1797 = insertelement <2 x i32> %1796, i32 %1795, i32 1
>  %1798 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1797, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1799 = extractelement <4 x float> %1798, i32 0
>  %1800 = call float @fabs(float %1799)
>  %1801 = fcmp uge float %1800, %24
>  %1802 = select i1 %1801, float 1.000000e+00, float 0.000000e+00
>  %1803 = fsub float -0.000000e+00, %1802
>  %1804 = fptosi float %1803 to i32
>  %1805 = bitcast i32 %1804 to float
>  %1806 = bitcast float %1805 to i32
>  %1807 = and i32 %1806, 1065353216
>  %1808 = bitcast i32 %1807 to float
>  %1809 = fmul float %1791, %1808
>  %1810 = fmul float %1792, %1808
>  %1811 = fmul float %1793, %1808
>  %1812 = fmul float %1809, 0x3FBC34F4C0000000
>  %1813 = fmul float %1810, 0x3FBC34F4C0000000
>  %1814 = fmul float %1811, 0x3FBC34F4C0000000
>  %1815 = fadd float %1775, %1812
>  %1816 = fadd float %1776, %1813
>  %1817 = fadd float %1777, %1814
>  %1818 = fsub float -0.000000e+00, %58
>  %1819 = fadd float %1779, %1818
>  %1820 = fsub float -0.000000e+00, %59
>  %1821 = fadd float %1781, %1820
>  %1822 = fsub float -0.000000e+00, %62
>  %1823 = fadd float %1783, %1822
>  %1824 = fsub float -0.000000e+00, %63
>  %1825 = fadd float %1785, %1824
>  %1826 = bitcast float %1819 to i32
>  %1827 = bitcast float %1821 to i32
>  %1828 = insertelement <2 x i32> undef, i32 %1826, i32 0
>  %1829 = insertelement <2 x i32> %1828, i32 %1827, i32 1
>  %1830 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1829, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1831 = extractelement <4 x float> %1830, i32 0
>  %1832 = extractelement <4 x float> %1830, i32 1
>  %1833 = extractelement <4 x float> %1830, i32 2
>  %1834 = bitcast float %1823 to i32
>  %1835 = bitcast float %1825 to i32
>  %1836 = insertelement <2 x i32> undef, i32 %1834, i32 0
>  %1837 = insertelement <2 x i32> %1836, i32 %1835, i32 1
>  %1838 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1837, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1839 = extractelement <4 x float> %1838, i32 0
>  %1840 = call float @fabs(float %1839)
>  %1841 = fcmp uge float %1840, %24
>  %1842 = select i1 %1841, float 1.000000e+00, float 0.000000e+00
>  %1843 = fsub float -0.000000e+00, %1842
>  %1844 = fptosi float %1843 to i32
>  %1845 = bitcast i32 %1844 to float
>  %1846 = bitcast float %1845 to i32
>  %1847 = and i32 %1846, 1065353216
>  %1848 = bitcast i32 %1847 to float
>  %1849 = fmul float %1831, %1848
>  %1850 = fmul float %1832, %1848
>  %1851 = fmul float %1833, %1848
>  %1852 = fmul float %1849, 0x3FBACBE880000000
>  %1853 = fmul float %1850, 0x3FBACBE880000000
>  %1854 = fmul float %1851, 0x3FBACBE880000000
>  %1855 = fadd float %1815, %1852
>  %1856 = fadd float %1816, %1853
>  %1857 = fadd float %1817, %1854
>  %1858 = fsub float -0.000000e+00, %58
>  %1859 = fadd float %1819, %1858
>  %1860 = fsub float -0.000000e+00, %59
>  %1861 = fadd float %1821, %1860
>  %1862 = fsub float -0.000000e+00, %62
>  %1863 = fadd float %1823, %1862
>  %1864 = fsub float -0.000000e+00, %63
>  %1865 = fadd float %1825, %1864
>  %1866 = bitcast float %1859 to i32
>  %1867 = bitcast float %1861 to i32
>  %1868 = insertelement <2 x i32> undef, i32 %1866, i32 0
>  %1869 = insertelement <2 x i32> %1868, i32 %1867, i32 1
>  %1870 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1869, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1871 = extractelement <4 x float> %1870, i32 0
>  %1872 = extractelement <4 x float> %1870, i32 1
>  %1873 = extractelement <4 x float> %1870, i32 2
>  %1874 = bitcast float %1863 to i32
>  %1875 = bitcast float %1865 to i32
>  %1876 = insertelement <2 x i32> undef, i32 %1874, i32 0
>  %1877 = insertelement <2 x i32> %1876, i32 %1875, i32 1
>  %1878 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1877, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1879 = extractelement <4 x float> %1878, i32 0
>  %1880 = call float @fabs(float %1879)
>  %1881 = fcmp uge float %1880, %24
>  %1882 = select i1 %1881, float 1.000000e+00, float 0.000000e+00
>  %1883 = fsub float -0.000000e+00, %1882
>  %1884 = fptosi float %1883 to i32
>  %1885 = bitcast i32 %1884 to float
>  %1886 = bitcast float %1885 to i32
>  %1887 = and i32 %1886, 1065353216
>  %1888 = bitcast i32 %1887 to float
>  %1889 = fmul float %1871, %1888
>  %1890 = fmul float %1872, %1888
>  %1891 = fmul float %1873, %1888
>  %1892 = fmul float %1889, 0x3FB974E9A0000000
>  %1893 = fmul float %1890, 0x3FB974E9A0000000
>  %1894 = fmul float %1891, 0x3FB974E9A0000000
>  %1895 = fadd float %1855, %1892
>  %1896 = fadd float %1856, %1893
>  %1897 = fadd float %1857, %1894
>  %1898 = fsub float -0.000000e+00, %58
>  %1899 = fadd float %1859, %1898
>  %1900 = fsub float -0.000000e+00, %59
>  %1901 = fadd float %1861, %1900
>  %1902 = fsub float -0.000000e+00, %62
>  %1903 = fadd float %1863, %1902
>  %1904 = fsub float -0.000000e+00, %63
>  %1905 = fadd float %1865, %1904
>  %1906 = bitcast float %1899 to i32
>  %1907 = bitcast float %1901 to i32
>  %1908 = insertelement <2 x i32> undef, i32 %1906, i32 0
>  %1909 = insertelement <2 x i32> %1908, i32 %1907, i32 1
>  %1910 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1909, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1911 = extractelement <4 x float> %1910, i32 0
>  %1912 = extractelement <4 x float> %1910, i32 1
>  %1913 = extractelement <4 x float> %1910, i32 2
>  %1914 = bitcast float %1903 to i32
>  %1915 = bitcast float %1905 to i32
>  %1916 = insertelement <2 x i32> undef, i32 %1914, i32 0
>  %1917 = insertelement <2 x i32> %1916, i32 %1915, i32 1
>  %1918 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1917, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1919 = extractelement <4 x float> %1918, i32 0
>  %1920 = call float @fabs(float %1919)
>  %1921 = fcmp uge float %1920, %24
>  %1922 = select i1 %1921, float 1.000000e+00, float 0.000000e+00
>  %1923 = fsub float -0.000000e+00, %1922
>  %1924 = fptosi float %1923 to i32
>  %1925 = bitcast i32 %1924 to float
>  %1926 = bitcast float %1925 to i32
>  %1927 = and i32 %1926, 1065353216
>  %1928 = bitcast i32 %1927 to float
>  %1929 = fmul float %1911, %1928
>  %1930 = fmul float %1912, %1928
>  %1931 = fmul float %1913, %1928
>  %1932 = fmul float %1929, 0x3FB82F1120000000
>  %1933 = fmul float %1930, 0x3FB82F1120000000
>  %1934 = fmul float %1931, 0x3FB82F1120000000
>  %1935 = fadd float %1895, %1932
>  %1936 = fadd float %1896, %1933
>  %1937 = fadd float %1897, %1934
>  %1938 = fsub float -0.000000e+00, %58
>  %1939 = fadd float %1899, %1938
>  %1940 = fsub float -0.000000e+00, %59
>  %1941 = fadd float %1901, %1940
>  %1942 = fsub float -0.000000e+00, %62
>  %1943 = fadd float %1903, %1942
>  %1944 = fsub float -0.000000e+00, %63
>  %1945 = fadd float %1905, %1944
>  %1946 = bitcast float %1939 to i32
>  %1947 = bitcast float %1941 to i32
>  %1948 = insertelement <2 x i32> undef, i32 %1946, i32 0
>  %1949 = insertelement <2 x i32> %1948, i32 %1947, i32 1
>  %1950 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1949, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1951 = extractelement <4 x float> %1950, i32 0
>  %1952 = extractelement <4 x float> %1950, i32 1
>  %1953 = extractelement <4 x float> %1950, i32 2
>  %1954 = bitcast float %1943 to i32
>  %1955 = bitcast float %1945 to i32
>  %1956 = insertelement <2 x i32> undef, i32 %1954, i32 0
>  %1957 = insertelement <2 x i32> %1956, i32 %1955, i32 1
>  %1958 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1957, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1959 = extractelement <4 x float> %1958, i32 0
>  %1960 = call float @fabs(float %1959)
>  %1961 = fcmp uge float %1960, %24
>  %1962 = select i1 %1961, float 1.000000e+00, float 0.000000e+00
>  %1963 = fsub float -0.000000e+00, %1962
>  %1964 = fptosi float %1963 to i32
>  %1965 = bitcast i32 %1964 to float
>  %1966 = bitcast float %1965 to i32
>  %1967 = and i32 %1966, 1065353216
>  %1968 = bitcast i32 %1967 to float
>  %1969 = fmul float %1951, %1968
>  %1970 = fmul float %1952, %1968
>  %1971 = fmul float %1953, %1968
>  %1972 = fmul float %1969, 0x3FB6F98380000000
>  %1973 = fmul float %1970, 0x3FB6F98380000000
>  %1974 = fmul float %1971, 0x3FB6F98380000000
>  %1975 = fadd float %1935, %1972
>  %1976 = fadd float %1936, %1973
>  %1977 = fadd float %1937, %1974
>  %1978 = fsub float -0.000000e+00, %58
>  %1979 = fadd float %1939, %1978
>  %1980 = fsub float -0.000000e+00, %59
>  %1981 = fadd float %1941, %1980
>  %1982 = fsub float -0.000000e+00, %62
>  %1983 = fadd float %1943, %1982
>  %1984 = fsub float -0.000000e+00, %63
>  %1985 = fadd float %1945, %1984
>  %1986 = bitcast float %1979 to i32
>  %1987 = bitcast float %1981 to i32
>  %1988 = insertelement <2 x i32> undef, i32 %1986, i32 0
>  %1989 = insertelement <2 x i32> %1988, i32 %1987, i32 1
>  %1990 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1989, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %1991 = extractelement <4 x float> %1990, i32 0
>  %1992 = extractelement <4 x float> %1990, i32 1
>  %1993 = extractelement <4 x float> %1990, i32 2
>  %1994 = bitcast float %1983 to i32
>  %1995 = bitcast float %1985 to i32
>  %1996 = insertelement <2 x i32> undef, i32 %1994, i32 0
>  %1997 = insertelement <2 x i32> %1996, i32 %1995, i32 1
>  %1998 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1997, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %1999 = extractelement <4 x float> %1998, i32 0
>  %2000 = call float @fabs(float %1999)
>  %2001 = fcmp uge float %2000, %24
>  %2002 = select i1 %2001, float 1.000000e+00, float 0.000000e+00
>  %2003 = fsub float -0.000000e+00, %2002
>  %2004 = fptosi float %2003 to i32
>  %2005 = bitcast i32 %2004 to float
>  %2006 = bitcast float %2005 to i32
>  %2007 = and i32 %2006, 1065353216
>  %2008 = bitcast i32 %2007 to float
>  %2009 = fmul float %1991, %2008
>  %2010 = fmul float %1992, %2008
>  %2011 = fmul float %1993, %2008
>  %2012 = fmul float %2009, 0x3FB5D37020000000
>  %2013 = fmul float %2010, 0x3FB5D37020000000
>  %2014 = fmul float %2011, 0x3FB5D37020000000
>  %2015 = fadd float %1975, %2012
>  %2016 = fadd float %1976, %2013
>  %2017 = fadd float %1977, %2014
>  %2018 = fsub float -0.000000e+00, %58
>  %2019 = fadd float %1979, %2018
>  %2020 = fsub float -0.000000e+00, %59
>  %2021 = fadd float %1981, %2020
>  %2022 = fsub float -0.000000e+00, %62
>  %2023 = fadd float %1983, %2022
>  %2024 = fsub float -0.000000e+00, %63
>  %2025 = fadd float %1985, %2024
>  %2026 = bitcast float %2019 to i32
>  %2027 = bitcast float %2021 to i32
>  %2028 = insertelement <2 x i32> undef, i32 %2026, i32 0
>  %2029 = insertelement <2 x i32> %2028, i32 %2027, i32 1
>  %2030 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %2029, <32 x i8> %34, <16 x i8> %36, i32 2)
>  %2031 = extractelement <4 x float> %2030, i32 0
>  %2032 = extractelement <4 x float> %2030, i32 1
>  %2033 = extractelement <4 x float> %2030, i32 2
>  %2034 = bitcast float %2023 to i32
>  %2035 = bitcast float %2025 to i32
>  %2036 = insertelement <2 x i32> undef, i32 %2034, i32 0
>  %2037 = insertelement <2 x i32> %2036, i32 %2035, i32 1
>  %2038 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %2037, <32 x i8> %38, <16 x i8> %40, i32 2)
>  %2039 = extractelement <4 x float> %2038, i32 0
>  %2040 = call float @fabs(float %2039)
>  %2041 = fcmp uge float %2040, %24
>  %2042 = select i1 %2041, float 1.000000e+00, float 0.000000e+00
>  %2043 = fsub float -0.000000e+00, %2042
>  %2044 = fptosi float %2043 to i32
>  %2045 = bitcast i32 %2044 to float
>  %2046 = bitcast float %2045 to i32
>  %2047 = and i32 %2046, 1065353216
>  %2048 = bitcast i32 %2047 to float
>  %2049 = fmul float %2031, %2048
>  %2050 = fmul float %2032, %2048
>  %2051 = fmul float %2033, %2048
>  %2052 = fmul float %2049, 0x3FB4BC10E0000000
>  %2053 = fmul float %2050, 0x3FB4BC10E0000000
>  %2054 = fmul float %2051, 0x3FB4BC10E0000000
>  %2055 = fadd float %2015, %2052
>  %2056 = fadd float %2016, %2053
>  %2057 = fadd float %2017, %2054
>  %2058 = fmul float %2055, %29
>  %2059 = fmul float %2056, %30
>  %2060 = fmul float %2057, %31
>  %2061 = call i32 @llvm.SI.packf16(float %2058, float %2059)
>  %2062 = bitcast i32 %2061 to float
>  %2063 = call i32 @llvm.SI.packf16(float %2060, float 0.000000e+00)
>  %2064 = bitcast i32 %2063 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %2062, float %2064, float %2062, float %2064)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readonly
>declare float @llvm.sin.f32(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.fraction.(float) #3
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #4
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readonly }
>attributes #3 = { readnone }
>attributes #4 = { readonly }
>
>!0 = metadata !{metadata !"const", null, i32 1}
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>bf8c0770
>d20601b9
>020101b9
>d00c0006
>020009b9
>d20000b9
>0019e480
>d20600b9
>220101b9
>7f7211b9
>377372f2
>118173b7
>7f7402ff
>3e2190db
>d28200c2
>06f775c0
>098253bc
>098055bb
>f0800700
>0064bbc0
>09885bbf
>098663be
>f0800100
>0006bec3
>bf8c0770
>d20601be
>020101be
>d00c0006
>020009be
>d20000be
>0019e480
>d20600be
>220101be
>7f7c11be
>377d7cf2
>118b7dbc
>7f7e02ff
>3e197cd0
>d28200c7
>070b7fc5
>098c53c1
>098a55c0
>f0800700
>0064c0c5
>09925bc4
>099063c3
>f0800100
>0006c3c8
>bf8c0770
>d20601c3
>020101c3
>d00c0006
>020009c3
>d20000c3
>0019e480
>d20600c3
>220101c3
>7f8611c3
>378786f2
>119587c1
>7f8802ff
>3e11d02c
>d28200cc
>071f89ca
>099653c6
>099455c5
>f0800700
>0064c5ca
>099c5bc9
>099a63c8
>f0800100
>0006c8cd
>bf8c0770
>d20601c8
>020101c8
>d00c0006
>020009c8
>d20000c8
>0019e480
>d20600c8
>220101c8
>7f9011c8
>379190f2
>119f91c6
>7f9202ff
>3e0a85c3
>d28200d1
>073393cf
>09a053cb
>099e55ca
>f0800700
>0064cacf
>09a65bce
>09a463cd
>f0800100
>0006cdd2
>bf8c0770
>d20601cd
>020101cd
>d00c0006
>020009cd
>d20000cd
>0019e480
>d20600cd
>220101cd
>7f9a11cd
>379b9af2
>11a99bcb
>7f9c02ff
>3e0398ac
>d28200d6
>07479dd4
>09aa53d0
>09a855cf
>f0800700
>0064cfd4
>09b05bd3
>09ae63d2
>f0800100
>0006d2d7
>bf8c0770
>d20601d2
>020101d2
>d00c0006
>020009d2
>d20000d2
>0019e480
>d20600d2
>220101d2
>7fa411d2
>37a5a4f2
>11b3a5d0
>7fa602ff
>3dfa087a
>d28200db
>075ba7d9
>09b453d5
>09b255d4
>f0800700
>0064d4d9
>09ba5bd8
>09b863d7
>f0800100
>0006d7dc
>bf8c0770
>d20601d7
>020101d7
>d00c0006
>020009d7
>d20000d7
>0019e480
>d20600d7
>220101d7
>7fae11d7
>37afaef2
>11bdafd5
>7fb002ff
>3ded880d
>d28200e0
>076fb1de
>09be53da
>09bc55d9
>f0800700
>0064d9de
>09c45bdd
>09c263dc
>f0800100
>0006dce1
>bf8c0770
>d20601dc
>020101dc
>d00c0006
>020009dc
>d20000dc
>0019e480
>d20600dc
>220101dc
>7fb811dc
>37b9b8f2
>11c7b9da
>7fba02ff
>3de1a7a6
>d28200e5
>0783bbe3
>09c853df
>09c655de
>f0800700
>0064dee3
>09ce5be2
>09cc63e1
>f0800100
>0006e1e6
>bf8c0770
>d20601e1
>020101e1
>d00c0006
>020009e1
>d20000e1
>0019e480
>d20600e1
>220101e1
>7fc211e1
>37c3c2f2
>11d1c3df
>7fc402ff
>3dd65f44
>d28200ea
>0797c5e8
>09d253e4
>09d055e3
>f0800700
>0064e3e8
>09d85be7
>09d663e6
>f0800100
>0006e6eb
>bf8c0770
>d20601e6
>020101e6
>d00c0006
>020009e6
>d20000e6
>0019e480
>d20600e6
>220101e6
>7fcc11e6
>37cdccf2
>11dbcde4
>7fce02ff
>3dcba74d
>d28200ef
>07abcfed
>09dc53e9
>09da55e8
>f0800700
>0064e8ed
>09e25bec
>09e063eb
>f0800100
>0006ebf0
>bf8c0770
>d20601eb
>020101eb
>d00c0006
>020009eb
>d20000eb
>0019e480
>d20600eb
>220101eb
>7fd611eb
>37d7d6f2
>11e5d7e9
>7fd802ff
>3dc17889
>d28200f4
>07bfd9f2
>09e653ee
>09e455ed
>f0800700
>0064edf2
>09ec5bf1
>09ea63f0
>f0800100
>0006f0f5
>bf8c0770
>d20601f0
>020101f0
>d00c0006
>020009f0
>d20000f0
>0019e480
>d20600f0
>220101f0
>7fe011f0
>37e1e0f2
>11efe1ee
>7fe202ff
>3db7cc1c
>d28200f9
>07d3e3f7
>09f053f3
>09ee55f2
>f0800700
>0064f2f7
>09f65bf6
>09f463f5
>f0800100
>0006f5fa
>bf8c0770
>d20601f5
>020101f5
>d00c0006
>020009f5
>d20000f5
>0019e480
>d20600f5
>220101f5
>7fea11f5
>37ebeaf2
>11f9ebf3
>7fec02ff
>3dae9b81
>d28200fc
>07e7edfc
>09fc53f8
>09fa55f7
>f0800700
>0064f7fd
>08545bfb
>085263fa
>f0800100
>00062929
>bf8c0770
>d2060129
>02010129
>d00c0000
>02000929
>d2000029
>0001e480
>d2060029
>22010129
>7e521129
>365252f2
>105a53f8
>7e5402ff
>3da5e087
>d282002d
>07f2552d
>c2000909
>bf8c007f
>105a5a00
>10620700
>106262ff
>3f733333
>d2820031
>04c60f04
>11f41708
>d2820031
>04c619fa
>11f4210d
>d2820031
>04c623fa
>11f42b12
>d2820031
>04c62dfa
>11f43517
>d2820031
>04c637fa
>11f43f1c
>d2820031
>04c641fa
>11f44921
>d2820031
>04c64bfa
>11f45726
>d2820031
>04c659fa
>11f4652e
>d2820031
>04c667fa
>11f46f34
>d2820031
>04c671fa
>11f47939
>d2820031
>04c67bfa
>11f4833e
>d2820031
>04c685fa
>11f48d43
>d2820031
>04c68ffa
>11f49748
>d2820031
>04c699fa
>11f4a14d
>d2820031
>04c6a3fa
>11f4ab52
>d2820031
>04c6adfa
>11f4b557
>d2820031
>04c6b7fa
>11f4bf5c
>d2820031
>04c6c1fa
>11f4c961
>d2820031
>04c6cbfa
>11f4d366
>d2820031
>04c6d5fa
>11f4dd6b
>d2820031
>04c6dffa
>11f4e770
>d2820031
>04c6e9fa
>11f4f175
>d2820031
>04c6f3fa
>11f4fb7a
>d2820031
>04c6fdfa
>11f5057f
>d2820031
>04c707fa
>11f50f84
>d2820031
>04c711fa
>11f51989
>d2820031
>04c71bfa
>11f5238e
>d2820031
>04c725fa
>11f52d93
>d2820031
>04c72ffa
>11f53798
>d2820031
>04c739fa
>11f5419d
>d2820031
>04c743fa
>11f54ba2
>d2820031
>04c74dfa
>11f555a7
>d2820031
>04c757fa
>11f55fac
>d2820031
>04c761fa
>11f569b1
>d2820031
>04c76bfa
>11f573b6
>d2820031
>04c775fa
>11f57dbb
>d2820031
>04c77ffa
>11f587c0
>d2820031
>04c789fa
>11f591c5
>d2820031
>04c793fa
>11f59bca
>d2820031
>04c79dfa
>11f5a5cf
>d2820031
>04c7a7fa
>11f5afd4
>d2820031
>04c7b1fa
>11f5b9d9
>d2820031
>04c7bbfa
>11f5c3de
>d2820031
>04c7c5fa
>11f5cde3
>d2820031
>04c7cffa
>11f5d7e8
>d2820031
>04c7d9fa
>11f5e1ed
>d2820031
>04c7e3fa
>11f5ebf2
>d2820031
>04c7edfa
>11f453f7
>d2820031
>04c655fa
>c2000908
>bf8c007f
>10626200
>5e5a5b31
>10000702
>100000ff
>3f733333
>d2820000
>04020f06
>1002170a
>d2820000
>04021901
>1002210f
>d2820000
>04022301
>10022b14
>d2820000
>04022d01
>10023519
>d2820000
>04023701
>10023f1e
>d2820000
>04024101
>10024923
>d2820000
>04024b01
>10025728
>d2820000
>04025901
>10026530
>d2820000
>04026701
>10026f36
>d2820000
>04027101
>1002793b
>d2820000
>04027b01
>10028340
>d2820000
>04028501
>10028d45
>d2820000
>04028f01
>1002974a
>d2820000
>04029901
>1002a14f
>d2820000
>0402a301
>1002ab54
>d2820000
>0402ad01
>1002b559
>d2820000
>0402b701
>1002bf5e
>d2820000
>0402c101
>1002c963
>d2820000
>0402cb01
>1002d368
>d2820000
>0402d501
>1002dd6d
>d2820000
>0402df01
>1002e772
>d2820000
>0402e901
>1002f177
>d2820000
>0402f301
>1002fb7c
>d2820000
>0402fd01
>10030581
>d2820000
>04030701
>10030f86
>d2820000
>04031101
>1003198b
>d2820000
>04031b01
>10032390
>d2820000
>04032501
>10032d95
>d2820000
>04032f01
>1003379a
>d2820000
>04033901
>1003419f
>d2820000
>04034301
>10034ba4
>d2820000
>04034d01
>100355a9
>d2820000
>04035701
>10035fae
>d2820000
>04036101
>100369b3
>d2820000
>04036b01
>100373b8
>d2820000
>04037501
>10037dbd
>d2820000
>04037f01
>100387c2
>d2820000
>04038901
>100391c7
>d2820000
>04039301
>10039bcc
>d2820000
>04039d01
>1003a5d1
>d2820000
>0403a701
>1003afd6
>d2820000
>0403b101
>1003b9db
>d2820000
>0403bb01
>1003c3e0
>d2820000
>0403c501
>1003cde5
>d2820000
>0403cf01
>1003d7ea
>d2820000
>0403d901
>1003e1ef
>d2820000
>0403e301
>1003ebf4
>d2820000
>0403ed01
>100253f9
>d2820000
>04025501
>c200090a
>bf8c007f
>10000000
>d25e0000
>02010100
>f8001c0f
>002d002d
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[0], CONST[0], TEMP[0]
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
>  %26 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
>  %30 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %31 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %32 = bitcast float %30 to i32
>  %33 = bitcast float %31 to i32
>  %34 = insertelement <2 x i32> undef, i32 %32, i32 0
>  %35 = insertelement <2 x i32> %34, i32 %33, i32 1
>  %36 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %35, <32 x i8> %27, <16 x i8> %29, i32 2)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = fmul float %22, %37
>  %42 = fmul float %23, %38
>  %43 = fmul float %24, %39
>  %44 = fmul float %25, %40
>  %45 = call i32 @llvm.SI.packf16(float %41, float %42)
>  %46 = bitcast i32 %45 to float
>  %47 = call i32 @llvm.SI.packf16(float %43, float %44)
>  %48 = bitcast i32 %47 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %46, float %48, float %46, float %48)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c80c0100
>c80d0101
>c8080000
>c8090001
>c0840300
>c0c60500
>bf8c007f
>f0800f00
>00430002
>c0800100
>bf8c0070
>c2020103
>bf8c007f
>10080604
>c2020102
>bf8c007f
>100a0404
>5e080905
>c2020101
>bf8c007f
>100a0204
>c2000100
>bf8c007f
>10000000
>5e000b00
>f8001c0f
>04000400
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[19], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..2]
>DCL TEMP[0..21], LOCAL
>IMM[0] FLT32 {    0.0000,     0.2990,     0.5870,     0.1140}
>IMM[1] FLT32 {    0.0000,     1.0000,    -1.0000,     0.0833}
>IMM[2] FLT32 {    0.1660,    -2.0000,     2.0000,     0.0833}
>IMM[3] FLT32 {    0.5000,     3.0000,     0.2500,     1.5000}
>IMM[4] FLT32 {    4.0000,     8.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[0].xyxx
>  1: MOV TEMP[1].xy, IN[0].xyyy
>  2: MOV TEMP[1].w, IMM[0].xxxx
>  3: TXL TEMP[1], TEMP[1], SAMP[0], 2D
>  4: DP3 TEMP[2].x, TEMP[1].xyzz, IMM[0].yzww
>  5: MAD TEMP[3].xy, IMM[1].xyyy, CONST[0].xyyy, IN[0].xyyy
>  6: MOV TEMP[3].xy, TEMP[3].xyyy
>  7: MOV TEMP[3].w, IMM[0].xxxx
>  8: TXL TEMP[3].xyz, TEMP[3], SAMP[0], 2D
>  9: DP3 TEMP[3].x, TEMP[3].xyzz, IMM[0].yzww
> 10: MOV TEMP[4].x, TEMP[3].xxxx
> 11: MAD TEMP[5].xy, IMM[1].yxxx, CONST[0].xyyy, IN[0].xyyy
> 12: MOV TEMP[5].xy, TEMP[5].xyyy
> 13: MOV TEMP[5].w, IMM[0].xxxx
> 14: TXL TEMP[5].xyz, TEMP[5], SAMP[0], 2D
> 15: DP3 TEMP[5].x, TEMP[5].xyzz, IMM[0].yzww
> 16: MAD TEMP[6].xy, IMM[1].xzzz, CONST[0].xyyy, IN[0].xyyy
> 17: MOV TEMP[6].xy, TEMP[6].xyyy
> 18: MOV TEMP[6].w, IMM[0].xxxx
> 19: TXL TEMP[6].xyz, TEMP[6], SAMP[0], 2D
> 20: DP3 TEMP[6].x, TEMP[6].xyzz, IMM[0].yzww
> 21: MOV TEMP[7].x, TEMP[6].xxxx
> 22: MAD TEMP[8].xy, IMM[1].zxxx, CONST[0].xyyy, IN[0].xyyy
> 23: MOV TEMP[8].xy, TEMP[8].xyyy
> 24: MOV TEMP[8].w, IMM[0].xxxx
> 25: TXL TEMP[8].xyz, TEMP[8], SAMP[0], 2D
> 26: DP3 TEMP[8].x, TEMP[8].xyzz, IMM[0].yzww
> 27: MAX TEMP[9].x, TEMP[6].xxxx, TEMP[8].xxxx
> 28: MAX TEMP[10].x, TEMP[3].xxxx, TEMP[2].xxxx
> 29: MAX TEMP[10].x, TEMP[5].xxxx, TEMP[10].xxxx
> 30: MAX TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
> 31: MIN TEMP[10].x, TEMP[6].xxxx, TEMP[8].xxxx
> 32: MIN TEMP[11].x, TEMP[3].xxxx, TEMP[2].xxxx
> 33: MIN TEMP[11].x, TEMP[5].xxxx, TEMP[11].xxxx
> 34: MIN TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
> 35: ADD TEMP[10].x, TEMP[9].xxxx, -TEMP[10].xxxx
> 36: MUL TEMP[9].x, TEMP[9].xxxx, IMM[2].xxxx
> 37: MAX TEMP[9].x, IMM[1].wwww, TEMP[9].xxxx
> 38: SLT TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx
> 39: F2I TEMP[9].x, -TEMP[9]
> 40: UIF TEMP[9].xxxx :0
> 41:   MOV TEMP[1], TEMP[1]
> 42: ELSE :0
> 43:   MAD TEMP[9].xy, IMM[1].zzzz, CONST[0].xyyy, IN[0].xyyy
> 44:   MOV TEMP[9].xy, TEMP[9].xyyy
> 45:   MOV TEMP[9].w, IMM[0].xxxx
> 46:   TXL TEMP[9].xyz, TEMP[9], SAMP[0], 2D
> 47:   DP3 TEMP[9].x, TEMP[9].xyzz, IMM[0].yzww
> 48:   ADD TEMP[11].xy, IN[0].xyyy, CONST[0].xyyy
> 49:   MOV TEMP[11].xy, TEMP[11].xyyy
> 50:   MOV TEMP[11].w, IMM[0].xxxx
> 51:   TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
> 52:   DP3 TEMP[11].x, TEMP[11].xyzz, IMM[0].yzww
> 53:   MAD TEMP[12].xy, IMM[1].yzzz, CONST[0].xyyy, IN[0].xyyy
> 54:   MOV TEMP[12].xy, TEMP[12].xyyy
> 55:   MOV TEMP[12].w, IMM[0].xxxx
> 56:   TXL TEMP[12].xyz, TEMP[12], SAMP[0], 2D
> 57:   DP3 TEMP[12].x, TEMP[12].xyzz, IMM[0].yzww
> 58:   MAD TEMP[13].xy, IMM[1].zyyy, CONST[0].xyyy, IN[0].xyyy
> 59:   MOV TEMP[13].xy, TEMP[13].xyyy
> 60:   MOV TEMP[13].w, IMM[0].xxxx
> 61:   TXL TEMP[13].xyz, TEMP[13], SAMP[0], 2D
> 62:   DP3 TEMP[13].x, TEMP[13].xyzz, IMM[0].yzww
> 63:   ADD TEMP[14].x, TEMP[6].xxxx, TEMP[3].xxxx
> 64:   ADD TEMP[15].x, TEMP[8].xxxx, TEMP[5].xxxx
> 65:   RCP TEMP[10].x, TEMP[10].xxxx
> 66:   ADD TEMP[16].x, TEMP[12].xxxx, TEMP[11].xxxx
> 67:   ADD TEMP[17].x, TEMP[9].xxxx, TEMP[13].xxxx
> 68:   MOV TEMP[18].x, CONST[0].xxxx
> 69:   MAD TEMP[19].x, IMM[2].yyyy, TEMP[8].xxxx, TEMP[17].xxxx
> 70:   ABS TEMP[19].x, TEMP[19].xxxx
> 71:   MAD TEMP[20].x, IMM[2].yyyy, TEMP[2].xxxx, TEMP[14].xxxx
> 72:   ABS TEMP[20].x, TEMP[20].xxxx
> 73:   MAD TEMP[21].x, IMM[2].yyyy, TEMP[5].xxxx, TEMP[16].xxxx
> 74:   ABS TEMP[21].x, TEMP[21].xxxx
> 75:   MAD TEMP[20].x, TEMP[20].xxxx, IMM[2].zzzz, TEMP[21].xxxx
> 76:   ADD TEMP[19].x, TEMP[19].xxxx, TEMP[20].xxxx
> 77:   ADD TEMP[11].x, TEMP[13].xxxx, TEMP[11].xxxx
> 78:   MAD TEMP[3].x, IMM[2].yyyy, TEMP[3].xxxx, TEMP[11].xxxx
> 79:   ABS TEMP[3].x, TEMP[3].xxxx
> 80:   MAD TEMP[11].x, IMM[2].yyyy, TEMP[2].xxxx, TEMP[15].xxxx
> 81:   ABS TEMP[11].x, TEMP[11].xxxx
> 82:   ADD TEMP[9].x, TEMP[9].xxxx, TEMP[12].xxxx
> 83:   MAD TEMP[6].x, IMM[2].yyyy, TEMP[6].xxxx, TEMP[9].xxxx
> 84:   ABS TEMP[6].x, TEMP[6].xxxx
> 85:   MAD TEMP[6].x, TEMP[11].xxxx, IMM[2].zzzz, TEMP[6].xxxx
> 86:   ADD TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
> 87:   SGE TEMP[3].x, TEMP[19].xxxx, TEMP[3].xxxx
> 88:   F2I TEMP[3].x, -TEMP[3]
> 89:   ADD TEMP[6].x, TEMP[14].xxxx, TEMP[15].xxxx
> 90:   ADD TEMP[9].x, TEMP[17].xxxx, TEMP[16].xxxx
> 91:   MAD TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz, TEMP[9].xxxx
> 92:   NOT TEMP[9].x, TEMP[3].xxxx
> 93:   UIF TEMP[9].xxxx :0
> 94:     MOV TEMP[7].x, TEMP[8].xxxx
> 95:   ENDIF
> 96:   NOT TEMP[8].x, TEMP[3].xxxx
> 97:   UIF TEMP[8].xxxx :0
> 98:     MOV TEMP[4].x, TEMP[5].xxxx
> 99:   ENDIF
>100:   UIF TEMP[3].xxxx :0
>101:     MOV TEMP[18].x, CONST[0].yyyy
>102:   ENDIF
>103:   MAD TEMP[5].x, TEMP[6].xxxx, IMM[2].wwww, -TEMP[2].xxxx
>104:   ADD TEMP[6].x, TEMP[7].xxxx, -TEMP[2].xxxx
>105:   ADD TEMP[8].x, TEMP[4].xxxx, -TEMP[2].xxxx
>106:   ADD TEMP[7].x, TEMP[7].xxxx, TEMP[2].xxxx
>107:   ADD TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx
>108:   ABS TEMP[9].x, TEMP[6].xxxx
>109:   ABS TEMP[11].x, TEMP[8].xxxx
>110:   SGE TEMP[9].x, TEMP[9].xxxx, TEMP[11].xxxx
>111:   F2I TEMP[9].x, -TEMP[9]
>112:   ABS TEMP[6].x, TEMP[6].xxxx
>113:   ABS TEMP[8].x, TEMP[8].xxxx
>114:   MAX TEMP[6].x, TEMP[6].xxxx, TEMP[8].xxxx
>115:   UIF TEMP[9].xxxx :0
>116:     MOV TEMP[18].x, -TEMP[18].xxxx
>117:   ENDIF
>118:   ABS TEMP[5].x, TEMP[5].xxxx
>119:   MUL_SAT TEMP[5].x, TEMP[5].xxxx, TEMP[10].xxxx
>120:   MOV TEMP[8].xy, IN[0].xyxx
>121:   NOT TEMP[10].x, TEMP[3].xxxx
>122:   UIF TEMP[10].xxxx :0
>123:     MOV TEMP[10].x, IMM[0].xxxx
>124:   ELSE :0
>125:     MOV TEMP[10].x, CONST[0].xxxx
>126:   ENDIF
>127:   MOV TEMP[10].x, TEMP[10].xxxx
>128:   UIF TEMP[3].xxxx :0
>129:     MOV TEMP[11].x, IMM[0].xxxx
>130:   ELSE :0
>131:     MOV TEMP[11].x, CONST[0].yyyy
>132:   ENDIF
>133:   MOV TEMP[10].y, TEMP[11].xxxx
>134:   NOT TEMP[11].x, TEMP[3].xxxx
>135:   UIF TEMP[11].xxxx :0
>136:     MAD TEMP[8].x, TEMP[18].xxxx, IMM[3].xxxx, IN[0].xxxx
>137:   ENDIF
>138:   UIF TEMP[3].xxxx :0
>139:     MAD TEMP[11].x, TEMP[18].xxxx, IMM[3].xxxx, IN[0].yyyy
>140:     MOV TEMP[8].y, TEMP[11].xxxx
>141:   ENDIF
>142:   ADD TEMP[11].xy, TEMP[8].xyyy, -TEMP[10].xyyy
>143:   MOV TEMP[12].xy, TEMP[11].xyxx
>144:   ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
>145:   MAD TEMP[13].x, IMM[2].yyyy, TEMP[5].xxxx, IMM[3].yyyy
>146:   MOV TEMP[14].xy, TEMP[11].xyyy
>147:   MOV TEMP[14].w, IMM[0].xxxx
>148:   TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>149:   DP3 TEMP[14].x, TEMP[14].xyzz, IMM[0].yzww
>150:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
>151:   MOV TEMP[15].xy, TEMP[8].xyyy
>152:   MOV TEMP[15].w, IMM[0].xxxx
>153:   TXL TEMP[15].xyz, TEMP[15], SAMP[0], 2D
>154:   DP3 TEMP[15].x, TEMP[15].xyzz, IMM[0].yzww
>155:   NOT TEMP[9].x, TEMP[9].xxxx
>156:   UIF TEMP[9].xxxx :0
>157:     MOV TEMP[7].x, TEMP[4].xxxx
>158:   ENDIF
>159:   MUL TEMP[6].x, TEMP[6].xxxx, IMM[3].zzzz
>160:   MUL TEMP[5].x, TEMP[13].xxxx, TEMP[5].xxxx
>161:   MUL TEMP[9].x, TEMP[7].xxxx, IMM[3].xxxx
>162:   ADD TEMP[9].x, TEMP[2].xxxx, -TEMP[9].xxxx
>163:   SLT TEMP[9].x, TEMP[9].xxxx, IMM[0].xxxx
>164:   F2I TEMP[9].x, -TEMP[9]
>165:   MUL TEMP[13].x, TEMP[7].xxxx, IMM[3].xxxx
>166:   ADD TEMP[13].x, TEMP[14].xxxx, -TEMP[13].xxxx
>167:   MOV TEMP[2].x, TEMP[13].xxxx
>168:   MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>169:   ADD TEMP[4].x, TEMP[15].xxxx, -TEMP[14].xxxx
>170:   ABS TEMP[13].x, TEMP[13].xxxx
>171:   SGE TEMP[13].x, TEMP[13].xxxx, TEMP[6].xxxx
>172:   F2I TEMP[13].x, -TEMP[13]
>173:   ABS TEMP[14].x, TEMP[4].xxxx
>174:   SGE TEMP[14].x, TEMP[14].xxxx, TEMP[6].xxxx
>175:   F2I TEMP[14].x, -TEMP[14]
>176:   NOT TEMP[15].x, TEMP[13].xxxx
>177:   UIF TEMP[15].xxxx :0
>178:     ADD TEMP[12].xy, TEMP[11].xyyy, -TEMP[10].xyyy
>179:   ENDIF
>180:   NOT TEMP[11].x, TEMP[13].xxxx
>181:   NOT TEMP[15].x, TEMP[14].xxxx
>182:   OR TEMP[11].x, TEMP[11].xxxx, TEMP[15].xxxx
>183:   NOT TEMP[15].x, TEMP[14].xxxx
>184:   UIF TEMP[15].xxxx :0
>185:     ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
>186:   ENDIF
>187:   UIF TEMP[11].xxxx :0
>188:     NOT TEMP[11].x, TEMP[13].xxxx
>189:     UIF TEMP[11].xxxx :0
>190:       MOV TEMP[11].xy, TEMP[12].xyyy
>191:       MOV TEMP[11].w, IMM[0].xxxx
>192:       TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
>193:       DP3 TEMP[2].x, TEMP[11].xyzz, IMM[0].yzww
>194:     ENDIF
>195:     NOT TEMP[11].x, TEMP[14].xxxx
>196:     UIF TEMP[11].xxxx :0
>197:       MOV TEMP[11].xy, TEMP[8].xyyy
>198:       MOV TEMP[11].w, IMM[0].xxxx
>199:       TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
>200:       DP3 TEMP[4].x, TEMP[11].xyzz, IMM[0].yzww
>201:     ENDIF
>202:     NOT TEMP[11].x, TEMP[13].xxxx
>203:     UIF TEMP[11].xxxx :0
>204:       MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>205:       ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[11].xxxx
>206:     ENDIF
>207:     NOT TEMP[11].x, TEMP[14].xxxx
>208:     UIF TEMP[11].xxxx :0
>209:       MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>210:       ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>211:     ENDIF
>212:     ABS TEMP[11].x, TEMP[2].xxxx
>213:     SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>214:     F2I TEMP[13].x, -TEMP[11]
>215:     ABS TEMP[11].x, TEMP[4].xxxx
>216:     SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>217:     F2I TEMP[11].x, -TEMP[11]
>218:     NOT TEMP[14].x, TEMP[13].xxxx
>219:     UIF TEMP[14].xxxx :0
>220:       ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[10].xyyy
>221:     ENDIF
>222:     NOT TEMP[14].x, TEMP[13].xxxx
>223:     NOT TEMP[15].x, TEMP[11].xxxx
>224:     OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>225:     NOT TEMP[15].x, TEMP[11].xxxx
>226:     UIF TEMP[15].xxxx :0
>227:       ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
>228:     ENDIF
>229:     UIF TEMP[14].xxxx :0
>230:       NOT TEMP[14].x, TEMP[13].xxxx
>231:       UIF TEMP[14].xxxx :0
>232:         MOV TEMP[14].xy, TEMP[12].xyyy
>233:         MOV TEMP[14].w, IMM[0].xxxx
>234:         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>235:         DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>236:       ENDIF
>237:       NOT TEMP[14].x, TEMP[11].xxxx
>238:       UIF TEMP[14].xxxx :0
>239:         MOV TEMP[14].xy, TEMP[8].xyyy
>240:         MOV TEMP[14].w, IMM[0].xxxx
>241:         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>242:         DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>243:       ENDIF
>244:       NOT TEMP[14].x, TEMP[13].xxxx
>245:       UIF TEMP[14].xxxx :0
>246:         MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>247:         ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>248:       ENDIF
>249:       NOT TEMP[11].x, TEMP[11].xxxx
>250:       UIF TEMP[11].xxxx :0
>251:         MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>252:         ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>253:       ENDIF
>254:       ABS TEMP[11].x, TEMP[2].xxxx
>255:       SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>256:       F2I TEMP[13].x, -TEMP[11]
>257:       ABS TEMP[11].x, TEMP[4].xxxx
>258:       SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>259:       F2I TEMP[11].x, -TEMP[11]
>260:       NOT TEMP[14].x, TEMP[13].xxxx
>261:       UIF TEMP[14].xxxx :0
>262:         ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[10].xyyy
>263:       ENDIF
>264:       NOT TEMP[14].x, TEMP[13].xxxx
>265:       NOT TEMP[15].x, TEMP[11].xxxx
>266:       OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>267:       NOT TEMP[15].x, TEMP[11].xxxx
>268:       UIF TEMP[15].xxxx :0
>269:         ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
>270:       ENDIF
>271:       UIF TEMP[14].xxxx :0
>272:         NOT TEMP[14].x, TEMP[13].xxxx
>273:         UIF TEMP[14].xxxx :0
>274:           MOV TEMP[14].xy, TEMP[12].xyyy
>275:           MOV TEMP[14].w, IMM[0].xxxx
>276:           TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>277:           DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>278:         ENDIF
>279:         NOT TEMP[14].x, TEMP[11].xxxx
>280:         UIF TEMP[14].xxxx :0
>281:           MOV TEMP[14].xy, TEMP[8].xyyy
>282:           MOV TEMP[14].w, IMM[0].xxxx
>283:           TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>284:           DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>285:         ENDIF
>286:         NOT TEMP[14].x, TEMP[13].xxxx
>287:         UIF TEMP[14].xxxx :0
>288:           MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>289:           ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>290:         ENDIF
>291:         NOT TEMP[11].x, TEMP[11].xxxx
>292:         UIF TEMP[11].xxxx :0
>293:           MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>294:           ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>295:         ENDIF
>296:         ABS TEMP[11].x, TEMP[2].xxxx
>297:         SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>298:         F2I TEMP[13].x, -TEMP[11]
>299:         ABS TEMP[11].x, TEMP[4].xxxx
>300:         SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>301:         F2I TEMP[11].x, -TEMP[11]
>302:         NOT TEMP[14].x, TEMP[13].xxxx
>303:         UIF TEMP[14].xxxx :0
>304:           ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[10].xyyy
>305:         ENDIF
>306:         NOT TEMP[14].x, TEMP[13].xxxx
>307:         NOT TEMP[15].x, TEMP[11].xxxx
>308:         OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>309:         NOT TEMP[15].x, TEMP[11].xxxx
>310:         UIF TEMP[15].xxxx :0
>311:           ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
>312:         ENDIF
>313:         UIF TEMP[14].xxxx :0
>314:           NOT TEMP[14].x, TEMP[13].xxxx
>315:           UIF TEMP[14].xxxx :0
>316:             MOV TEMP[14].xy, TEMP[12].xyyy
>317:             MOV TEMP[14].w, IMM[0].xxxx
>318:             TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>319:             DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>320:           ENDIF
>321:           NOT TEMP[14].x, TEMP[11].xxxx
>322:           UIF TEMP[14].xxxx :0
>323:             MOV TEMP[14].xy, TEMP[8].xyyy
>324:             MOV TEMP[14].w, IMM[0].xxxx
>325:             TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>326:             DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>327:           ENDIF
>328:           NOT TEMP[14].x, TEMP[13].xxxx
>329:           UIF TEMP[14].xxxx :0
>330:             MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>331:             ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>332:           ENDIF
>333:           NOT TEMP[11].x, TEMP[11].xxxx
>334:           UIF TEMP[11].xxxx :0
>335:             MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>336:             ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>337:           ENDIF
>338:           ABS TEMP[11].x, TEMP[2].xxxx
>339:           SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>340:           F2I TEMP[13].x, -TEMP[11]
>341:           ABS TEMP[11].x, TEMP[4].xxxx
>342:           SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>343:           F2I TEMP[11].x, -TEMP[11]
>344:           NOT TEMP[14].x, TEMP[13].xxxx
>345:           UIF TEMP[14].xxxx :0
>346:             MUL TEMP[14].xy, TEMP[10].xyyy, IMM[3].wwww
>347:             ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>348:           ENDIF
>349:           NOT TEMP[14].x, TEMP[13].xxxx
>350:           NOT TEMP[15].x, TEMP[11].xxxx
>351:           OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>352:           NOT TEMP[15].x, TEMP[11].xxxx
>353:           UIF TEMP[15].xxxx :0
>354:             MAD TEMP[8].xy, TEMP[10].xyyy, IMM[3].wwww, TEMP[8].xyyy
>355:           ENDIF
>356:           UIF TEMP[14].xxxx :0
>357:             NOT TEMP[14].x, TEMP[13].xxxx
>358:             UIF TEMP[14].xxxx :0
>359:               MOV TEMP[14].xy, TEMP[12].xyyy
>360:               MOV TEMP[14].w, IMM[0].xxxx
>361:               TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>362:               DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>363:             ENDIF
>364:             NOT TEMP[14].x, TEMP[11].xxxx
>365:             UIF TEMP[14].xxxx :0
>366:               MOV TEMP[14].xy, TEMP[8].xyyy
>367:               MOV TEMP[14].w, IMM[0].xxxx
>368:               TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>369:               DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>370:             ENDIF
>371:             NOT TEMP[14].x, TEMP[13].xxxx
>372:             UIF TEMP[14].xxxx :0
>373:               MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>374:               ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>375:             ENDIF
>376:             NOT TEMP[11].x, TEMP[11].xxxx
>377:             UIF TEMP[11].xxxx :0
>378:               MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>379:               ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>380:             ENDIF
>381:             ABS TEMP[11].x, TEMP[2].xxxx
>382:             SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>383:             F2I TEMP[13].x, -TEMP[11]
>384:             ABS TEMP[11].x, TEMP[4].xxxx
>385:             SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>386:             F2I TEMP[11].x, -TEMP[11]
>387:             NOT TEMP[14].x, TEMP[13].xxxx
>388:             UIF TEMP[14].xxxx :0
>389:               MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
>390:               ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>391:             ENDIF
>392:             NOT TEMP[14].x, TEMP[13].xxxx
>393:             NOT TEMP[15].x, TEMP[11].xxxx
>394:             OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>395:             NOT TEMP[15].x, TEMP[11].xxxx
>396:             UIF TEMP[15].xxxx :0
>397:               MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
>398:             ENDIF
>399:             UIF TEMP[14].xxxx :0
>400:               NOT TEMP[14].x, TEMP[13].xxxx
>401:               UIF TEMP[14].xxxx :0
>402:                 MOV TEMP[14].xy, TEMP[12].xyyy
>403:                 MOV TEMP[14].w, IMM[0].xxxx
>404:                 TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>405:                 DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>406:               ENDIF
>407:               NOT TEMP[14].x, TEMP[11].xxxx
>408:               UIF TEMP[14].xxxx :0
>409:                 MOV TEMP[14].xy, TEMP[8].xyyy
>410:                 MOV TEMP[14].w, IMM[0].xxxx
>411:                 TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>412:                 DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>413:               ENDIF
>414:               NOT TEMP[14].x, TEMP[13].xxxx
>415:               UIF TEMP[14].xxxx :0
>416:                 MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>417:                 ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>418:               ENDIF
>419:               NOT TEMP[11].x, TEMP[11].xxxx
>420:               UIF TEMP[11].xxxx :0
>421:                 MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>422:                 ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>423:               ENDIF
>424:               ABS TEMP[11].x, TEMP[2].xxxx
>425:               SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>426:               F2I TEMP[13].x, -TEMP[11]
>427:               ABS TEMP[11].x, TEMP[4].xxxx
>428:               SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>429:               F2I TEMP[11].x, -TEMP[11]
>430:               NOT TEMP[14].x, TEMP[13].xxxx
>431:               UIF TEMP[14].xxxx :0
>432:                 MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
>433:                 ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>434:               ENDIF
>435:               NOT TEMP[14].x, TEMP[13].xxxx
>436:               NOT TEMP[15].x, TEMP[11].xxxx
>437:               OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>438:               NOT TEMP[15].x, TEMP[11].xxxx
>439:               UIF TEMP[15].xxxx :0
>440:                 MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
>441:               ENDIF
>442:               UIF TEMP[14].xxxx :0
>443:                 NOT TEMP[14].x, TEMP[13].xxxx
>444:                 UIF TEMP[14].xxxx :0
>445:                   MOV TEMP[14].xy, TEMP[12].xyyy
>446:                   MOV TEMP[14].w, IMM[0].xxxx
>447:                   TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>448:                   DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>449:                 ENDIF
>450:                 NOT TEMP[14].x, TEMP[11].xxxx
>451:                 UIF TEMP[14].xxxx :0
>452:                   MOV TEMP[14].xy, TEMP[8].xyyy
>453:                   MOV TEMP[14].w, IMM[0].xxxx
>454:                   TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>455:                   DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>456:                 ENDIF
>457:                 NOT TEMP[14].x, TEMP[13].xxxx
>458:                 UIF TEMP[14].xxxx :0
>459:                   MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>460:                   ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>461:                 ENDIF
>462:                 NOT TEMP[11].x, TEMP[11].xxxx
>463:                 UIF TEMP[11].xxxx :0
>464:                   MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>465:                   ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>466:                 ENDIF
>467:                 ABS TEMP[11].x, TEMP[2].xxxx
>468:                 SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>469:                 F2I TEMP[13].x, -TEMP[11]
>470:                 ABS TEMP[11].x, TEMP[4].xxxx
>471:                 SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>472:                 F2I TEMP[11].x, -TEMP[11]
>473:                 NOT TEMP[14].x, TEMP[13].xxxx
>474:                 UIF TEMP[14].xxxx :0
>475:                   MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
>476:                   ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>477:                 ENDIF
>478:                 NOT TEMP[14].x, TEMP[13].xxxx
>479:                 NOT TEMP[15].x, TEMP[11].xxxx
>480:                 OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>481:                 NOT TEMP[15].x, TEMP[11].xxxx
>482:                 UIF TEMP[15].xxxx :0
>483:                   MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
>484:                 ENDIF
>485:                 UIF TEMP[14].xxxx :0
>486:                   NOT TEMP[14].x, TEMP[13].xxxx
>487:                   UIF TEMP[14].xxxx :0
>488:                     MOV TEMP[14].xy, TEMP[12].xyyy
>489:                     MOV TEMP[14].w, IMM[0].xxxx
>490:                     TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>491:                     DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>492:                   ENDIF
>493:                   NOT TEMP[14].x, TEMP[11].xxxx
>494:                   UIF TEMP[14].xxxx :0
>495:                     MOV TEMP[14].xy, TEMP[8].xyyy
>496:                     MOV TEMP[14].w, IMM[0].xxxx
>497:                     TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>498:                     DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>499:                   ENDIF
>500:                   NOT TEMP[14].x, TEMP[13].xxxx
>501:                   UIF TEMP[14].xxxx :0
>502:                     MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>503:                     ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>504:                   ENDIF
>505:                   NOT TEMP[11].x, TEMP[11].xxxx
>506:                   UIF TEMP[11].xxxx :0
>507:                     MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>508:                     ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>509:                   ENDIF
>510:                   ABS TEMP[11].x, TEMP[2].xxxx
>511:                   SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>512:                   F2I TEMP[13].x, -TEMP[11]
>513:                   ABS TEMP[11].x, TEMP[4].xxxx
>514:                   SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>515:                   F2I TEMP[11].x, -TEMP[11]
>516:                   NOT TEMP[14].x, TEMP[13].xxxx
>517:                   UIF TEMP[14].xxxx :0
>518:                     MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
>519:                     ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>520:                   ENDIF
>521:                   NOT TEMP[14].x, TEMP[13].xxxx
>522:                   NOT TEMP[15].x, TEMP[11].xxxx
>523:                   OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>524:                   NOT TEMP[15].x, TEMP[11].xxxx
>525:                   UIF TEMP[15].xxxx :0
>526:                     MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
>527:                   ENDIF
>528:                   UIF TEMP[14].xxxx :0
>529:                     NOT TEMP[14].x, TEMP[13].xxxx
>530:                     UIF TEMP[14].xxxx :0
>531:                       MOV TEMP[14].xy, TEMP[12].xyyy
>532:                       MOV TEMP[14].w, IMM[0].xxxx
>533:                       TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>534:                       DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>535:                     ENDIF
>536:                     NOT TEMP[14].x, TEMP[11].xxxx
>537:                     UIF TEMP[14].xxxx :0
>538:                       MOV TEMP[14].xy, TEMP[8].xyyy
>539:                       MOV TEMP[14].w, IMM[0].xxxx
>540:                       TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>541:                       DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>542:                     ENDIF
>543:                     NOT TEMP[14].x, TEMP[13].xxxx
>544:                     UIF TEMP[14].xxxx :0
>545:                       MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>546:                       ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>547:                     ENDIF
>548:                     NOT TEMP[11].x, TEMP[11].xxxx
>549:                     UIF TEMP[11].xxxx :0
>550:                       MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
>551:                       ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
>552:                     ENDIF
>553:                     ABS TEMP[11].x, TEMP[2].xxxx
>554:                     SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>555:                     F2I TEMP[13].x, -TEMP[11]
>556:                     ABS TEMP[11].x, TEMP[4].xxxx
>557:                     SGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
>558:                     F2I TEMP[11].x, -TEMP[11]
>559:                     NOT TEMP[14].x, TEMP[13].xxxx
>560:                     UIF TEMP[14].xxxx :0
>561:                       MUL TEMP[14].xy, TEMP[10].xyyy, IMM[4].xxxx
>562:                       ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
>563:                     ENDIF
>564:                     NOT TEMP[14].x, TEMP[13].xxxx
>565:                     NOT TEMP[15].x, TEMP[11].xxxx
>566:                     OR TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx
>567:                     NOT TEMP[15].x, TEMP[11].xxxx
>568:                     UIF TEMP[15].xxxx :0
>569:                       MAD TEMP[8].xy, TEMP[10].xyyy, IMM[4].xxxx, TEMP[8].xyyy
>570:                     ENDIF
>571:                     UIF TEMP[14].xxxx :0
>572:                       NOT TEMP[14].x, TEMP[13].xxxx
>573:                       UIF TEMP[14].xxxx :0
>574:                         MOV TEMP[14].xy, TEMP[12].xyyy
>575:                         MOV TEMP[14].w, IMM[0].xxxx
>576:                         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>577:                         DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
>578:                       ENDIF
>579:                       NOT TEMP[14].x, TEMP[11].xxxx
>580:                       UIF TEMP[14].xxxx :0
>581:                         MOV TEMP[14].xy, TEMP[8].xyyy
>582:                         MOV TEMP[14].w, IMM[0].xxxx
>583:                         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
>584:                         DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
>585:                       ENDIF
>586:                       NOT TEMP[14].x, TEMP[13].xxxx
>587:                       UIF TEMP[14].xxxx :0
>588:                         MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
>589:                         ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
>590:                       ENDIF
>591:                       NOT TEMP[11].x, TEMP[11].xxxx
>592:                       UIF TEMP[11].xxxx :0
>593:                         MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].xxxx
>594:                         ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx
>595:                       ENDIF
>596:                       ABS TEMP[7].x, TEMP[2].xxxx
>597:                       SGE TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx
>598:                       F2I TEMP[13].x, -TEMP[7]
>599:                       ABS TEMP[7].x, TEMP[4].xxxx
>600:                       SGE TEMP[6].x, TEMP[7].xxxx, TEMP[6].xxxx
>601:                       F2I TEMP[6].x, -TEMP[6]
>602:                       NOT TEMP[7].x, TEMP[13].xxxx
>603:                       UIF TEMP[7].xxxx :0
>604:                         MUL TEMP[7].xy, TEMP[10].xyyy, IMM[4].yyyy
>605:                         ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[7].xyyy
>606:                       ENDIF
>607:                       NOT TEMP[6].x, TEMP[6].xxxx
>608:                       UIF TEMP[6].xxxx :0
>609:                         MAD TEMP[8].xy, TEMP[10].xyyy, IMM[4].yyyy, TEMP[8].xyyy
>610:                       ENDIF
>611:                     ENDIF
>612:                   ENDIF
>613:                 ENDIF
>614:               ENDIF
>615:             ENDIF
>616:           ENDIF
>617:         ENDIF
>618:       ENDIF
>619:     ENDIF
>620:   ENDIF
>621:   ADD TEMP[6].x, IN[0].xxxx, -TEMP[12].xxxx
>622:   ADD TEMP[7].x, TEMP[8].xxxx, -IN[0].xxxx
>623:   NOT TEMP[10].x, TEMP[3].xxxx
>624:   UIF TEMP[10].xxxx :0
>625:     ADD TEMP[6].x, IN[0].yyyy, -TEMP[12].yyyy
>626:   ENDIF
>627:   NOT TEMP[10].x, TEMP[3].xxxx
>628:   UIF TEMP[10].xxxx :0
>629:     ADD TEMP[7].x, TEMP[8].yyyy, -IN[0].yyyy
>630:   ENDIF
>631:   SLT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
>632:   F2I TEMP[2].x, -TEMP[2]
>633:   USNE TEMP[2].x, TEMP[2].xxxx, TEMP[9].xxxx
>634:   SLT TEMP[4].x, TEMP[4].xxxx, IMM[0].xxxx
>635:   F2I TEMP[4].x, -TEMP[4]
>636:   USNE TEMP[4].x, TEMP[4].xxxx, TEMP[9].xxxx
>637:   ADD TEMP[8].x, TEMP[7].xxxx, TEMP[6].xxxx
>638:   RCP TEMP[8].x, TEMP[8].xxxx
>639:   MIN TEMP[9].x, TEMP[6].xxxx, TEMP[7].xxxx
>640:   SLT TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
>641:   F2I TEMP[6].x, -TEMP[6]
>642:   UIF TEMP[6].xxxx :0
>643:     MOV TEMP[2].x, TEMP[2].xxxx
>644:   ELSE :0
>645:     MOV TEMP[2].x, TEMP[4].xxxx
>646:   ENDIF
>647:   MAD TEMP[4].x, TEMP[9].xxxx, -TEMP[8].xxxx, IMM[3].xxxx
>648:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
>649:   MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].zzzz
>650:   UIF TEMP[2].xxxx :0
>651:     MOV TEMP[2].x, TEMP[4].xxxx
>652:   ELSE :0
>653:     MOV TEMP[2].x, IMM[0].xxxx
>654:   ENDIF
>655:   MAX TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
>656:   NOT TEMP[4].x, TEMP[3].xxxx
>657:   UIF TEMP[4].xxxx :0
>658:     MAD TEMP[0].x, TEMP[2].xxxx, TEMP[18].xxxx, IN[0].xxxx
>659:   ENDIF
>660:   UIF TEMP[3].xxxx :0
>661:     MAD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx, IN[0].yyyy
>662:     MOV TEMP[0].y, TEMP[2].xxxx
>663:   ENDIF
>664:   MOV TEMP[0].xy, TEMP[0].xyyy
>665:   MOV TEMP[0].w, IMM[0].xxxx
>666:   TXL TEMP[0], TEMP[0], SAMP[0], 2D
>667:   MOV TEMP[1], TEMP[0]
>668: ENDIF
>669: MOV OUT[0], TEMP[1]
>670: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
>  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
>  %24 = getelementptr <32 x i8> addrspace(2)* %2, i32 0
>  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
>  %26 = getelementptr <16 x i8> addrspace(2)* %1, i32 0
>  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
>  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5)
>  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5)
>  %30 = bitcast float %28 to i32
>  %31 = bitcast float %29 to i32
>  %32 = bitcast float 0.000000e+00 to i32
>  %33 = insertelement <4 x i32> undef, i32 %30, i32 0
>  %34 = insertelement <4 x i32> %33, i32 %31, i32 1
>  %35 = insertelement <4 x i32> %34, i32 %32, i32 2
>  %36 = insertelement <4 x i32> %35, i32 undef, i32 3
>  %37 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %36, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %38, 0x3FD322D0E0000000
>  %43 = fmul float %39, 0x3FE2C8B440000000
>  %44 = fadd float %43, %42
>  %45 = fmul float %40, 0x3FBD2F1AA0000000
>  %46 = fadd float %44, %45
>  %47 = fmul float 0.000000e+00, %22
>  %48 = fadd float %47, %28
>  %49 = fmul float 1.000000e+00, %23
>  %50 = fadd float %49, %29
>  %51 = bitcast float %48 to i32
>  %52 = bitcast float %50 to i32
>  %53 = bitcast float 0.000000e+00 to i32
>  %54 = insertelement <4 x i32> undef, i32 %51, i32 0
>  %55 = insertelement <4 x i32> %54, i32 %52, i32 1
>  %56 = insertelement <4 x i32> %55, i32 %53, i32 2
>  %57 = insertelement <4 x i32> %56, i32 undef, i32 3
>  %58 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %57, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = fmul float %59, 0x3FD322D0E0000000
>  %63 = fmul float %60, 0x3FE2C8B440000000
>  %64 = fadd float %63, %62
>  %65 = fmul float %61, 0x3FBD2F1AA0000000
>  %66 = fadd float %64, %65
>  %67 = fmul float 1.000000e+00, %22
>  %68 = fadd float %67, %28
>  %69 = fmul float 0.000000e+00, %23
>  %70 = fadd float %69, %29
>  %71 = bitcast float %68 to i32
>  %72 = bitcast float %70 to i32
>  %73 = bitcast float 0.000000e+00 to i32
>  %74 = insertelement <4 x i32> undef, i32 %71, i32 0
>  %75 = insertelement <4 x i32> %74, i32 %72, i32 1
>  %76 = insertelement <4 x i32> %75, i32 %73, i32 2
>  %77 = insertelement <4 x i32> %76, i32 undef, i32 3
>  %78 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %77, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %79 = extractelement <4 x float> %78, i32 0
>  %80 = extractelement <4 x float> %78, i32 1
>  %81 = extractelement <4 x float> %78, i32 2
>  %82 = fmul float %79, 0x3FD322D0E0000000
>  %83 = fmul float %80, 0x3FE2C8B440000000
>  %84 = fadd float %83, %82
>  %85 = fmul float %81, 0x3FBD2F1AA0000000
>  %86 = fadd float %84, %85
>  %87 = fmul float 0.000000e+00, %22
>  %88 = fadd float %87, %28
>  %89 = fmul float -1.000000e+00, %23
>  %90 = fadd float %89, %29
>  %91 = bitcast float %88 to i32
>  %92 = bitcast float %90 to i32
>  %93 = bitcast float 0.000000e+00 to i32
>  %94 = insertelement <4 x i32> undef, i32 %91, i32 0
>  %95 = insertelement <4 x i32> %94, i32 %92, i32 1
>  %96 = insertelement <4 x i32> %95, i32 %93, i32 2
>  %97 = insertelement <4 x i32> %96, i32 undef, i32 3
>  %98 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %97, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %99 = extractelement <4 x float> %98, i32 0
>  %100 = extractelement <4 x float> %98, i32 1
>  %101 = extractelement <4 x float> %98, i32 2
>  %102 = fmul float %99, 0x3FD322D0E0000000
>  %103 = fmul float %100, 0x3FE2C8B440000000
>  %104 = fadd float %103, %102
>  %105 = fmul float %101, 0x3FBD2F1AA0000000
>  %106 = fadd float %104, %105
>  %107 = fmul float -1.000000e+00, %22
>  %108 = fadd float %107, %28
>  %109 = fmul float 0.000000e+00, %23
>  %110 = fadd float %109, %29
>  %111 = bitcast float %108 to i32
>  %112 = bitcast float %110 to i32
>  %113 = bitcast float 0.000000e+00 to i32
>  %114 = insertelement <4 x i32> undef, i32 %111, i32 0
>  %115 = insertelement <4 x i32> %114, i32 %112, i32 1
>  %116 = insertelement <4 x i32> %115, i32 %113, i32 2
>  %117 = insertelement <4 x i32> %116, i32 undef, i32 3
>  %118 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %117, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %119 = extractelement <4 x float> %118, i32 0
>  %120 = extractelement <4 x float> %118, i32 1
>  %121 = extractelement <4 x float> %118, i32 2
>  %122 = fmul float %119, 0x3FD322D0E0000000
>  %123 = fmul float %120, 0x3FE2C8B440000000
>  %124 = fadd float %123, %122
>  %125 = fmul float %121, 0x3FBD2F1AA0000000
>  %126 = fadd float %124, %125
>  %127 = fcmp uge float %106, %126
>  %128 = select i1 %127, float %106, float %126
>  %129 = fcmp uge float %66, %46
>  %130 = select i1 %129, float %66, float %46
>  %131 = fcmp uge float %86, %130
>  %132 = select i1 %131, float %86, float %130
>  %133 = fcmp uge float %128, %132
>  %134 = select i1 %133, float %128, float %132
>  %135 = fcmp uge float %106, %126
>  %136 = select i1 %135, float %126, float %106
>  %137 = fcmp uge float %66, %46
>  %138 = select i1 %137, float %46, float %66
>  %139 = fcmp uge float %86, %138
>  %140 = select i1 %139, float %138, float %86
>  %141 = fcmp uge float %136, %140
>  %142 = select i1 %141, float %140, float %136
>  %143 = fsub float -0.000000e+00, %142
>  %144 = fadd float %134, %143
>  %145 = fmul float %134, 0x3FC53F7CE0000000
>  %146 = fcmp uge float 0x3FB5532620000000, %145
>  %147 = select i1 %146, float 0x3FB5532620000000, float %145
>  %148 = fcmp ult float %144, %147
>  %149 = select i1 %148, float 1.000000e+00, float 0.000000e+00
>  %150 = fsub float -0.000000e+00, %149
>  %151 = fptosi float %150 to i32
>  %152 = bitcast i32 %151 to float
>  %153 = bitcast float %152 to i32
>  %154 = icmp ne i32 %153, 0
>  br i1 %154, label %ENDIF, label %ELSE
>
>ELSE:                                             ; preds = %main_body
>  %155 = fmul float -1.000000e+00, %22
>  %156 = fadd float %155, %28
>  %157 = fmul float -1.000000e+00, %23
>  %158 = fadd float %157, %29
>  %159 = bitcast float %156 to i32
>  %160 = bitcast float %158 to i32
>  %161 = bitcast float 0.000000e+00 to i32
>  %162 = insertelement <4 x i32> undef, i32 %159, i32 0
>  %163 = insertelement <4 x i32> %162, i32 %160, i32 1
>  %164 = insertelement <4 x i32> %163, i32 %161, i32 2
>  %165 = insertelement <4 x i32> %164, i32 undef, i32 3
>  %166 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %165, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %167 = extractelement <4 x float> %166, i32 0
>  %168 = extractelement <4 x float> %166, i32 1
>  %169 = extractelement <4 x float> %166, i32 2
>  %170 = fmul float %167, 0x3FD322D0E0000000
>  %171 = fmul float %168, 0x3FE2C8B440000000
>  %172 = fadd float %171, %170
>  %173 = fmul float %169, 0x3FBD2F1AA0000000
>  %174 = fadd float %172, %173
>  %175 = fadd float %28, %22
>  %176 = fadd float %29, %23
>  %177 = bitcast float %175 to i32
>  %178 = bitcast float %176 to i32
>  %179 = bitcast float 0.000000e+00 to i32
>  %180 = insertelement <4 x i32> undef, i32 %177, i32 0
>  %181 = insertelement <4 x i32> %180, i32 %178, i32 1
>  %182 = insertelement <4 x i32> %181, i32 %179, i32 2
>  %183 = insertelement <4 x i32> %182, i32 undef, i32 3
>  %184 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %183, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %185 = extractelement <4 x float> %184, i32 0
>  %186 = extractelement <4 x float> %184, i32 1
>  %187 = extractelement <4 x float> %184, i32 2
>  %188 = fmul float %185, 0x3FD322D0E0000000
>  %189 = fmul float %186, 0x3FE2C8B440000000
>  %190 = fadd float %189, %188
>  %191 = fmul float %187, 0x3FBD2F1AA0000000
>  %192 = fadd float %190, %191
>  %193 = fmul float 1.000000e+00, %22
>  %194 = fadd float %193, %28
>  %195 = fmul float -1.000000e+00, %23
>  %196 = fadd float %195, %29
>  %197 = bitcast float %194 to i32
>  %198 = bitcast float %196 to i32
>  %199 = bitcast float 0.000000e+00 to i32
>  %200 = insertelement <4 x i32> undef, i32 %197, i32 0
>  %201 = insertelement <4 x i32> %200, i32 %198, i32 1
>  %202 = insertelement <4 x i32> %201, i32 %199, i32 2
>  %203 = insertelement <4 x i32> %202, i32 undef, i32 3
>  %204 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %203, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %205 = extractelement <4 x float> %204, i32 0
>  %206 = extractelement <4 x float> %204, i32 1
>  %207 = extractelement <4 x float> %204, i32 2
>  %208 = fmul float %205, 0x3FD322D0E0000000
>  %209 = fmul float %206, 0x3FE2C8B440000000
>  %210 = fadd float %209, %208
>  %211 = fmul float %207, 0x3FBD2F1AA0000000
>  %212 = fadd float %210, %211
>  %213 = fmul float -1.000000e+00, %22
>  %214 = fadd float %213, %28
>  %215 = fmul float 1.000000e+00, %23
>  %216 = fadd float %215, %29
>  %217 = bitcast float %214 to i32
>  %218 = bitcast float %216 to i32
>  %219 = bitcast float 0.000000e+00 to i32
>  %220 = insertelement <4 x i32> undef, i32 %217, i32 0
>  %221 = insertelement <4 x i32> %220, i32 %218, i32 1
>  %222 = insertelement <4 x i32> %221, i32 %219, i32 2
>  %223 = insertelement <4 x i32> %222, i32 undef, i32 3
>  %224 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %223, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %225 = extractelement <4 x float> %224, i32 0
>  %226 = extractelement <4 x float> %224, i32 1
>  %227 = extractelement <4 x float> %224, i32 2
>  %228 = fmul float %225, 0x3FD322D0E0000000
>  %229 = fmul float %226, 0x3FE2C8B440000000
>  %230 = fadd float %229, %228
>  %231 = fmul float %227, 0x3FBD2F1AA0000000
>  %232 = fadd float %230, %231
>  %233 = fadd float %106, %66
>  %234 = fadd float %126, %86
>  %235 = fdiv float 1.000000e+00, %144
>  %236 = fadd float %212, %192
>  %237 = fadd float %174, %232
>  %238 = fmul float -2.000000e+00, %126
>  %239 = fadd float %238, %237
>  %240 = call float @fabs(float %239)
>  %241 = fmul float -2.000000e+00, %46
>  %242 = fadd float %241, %233
>  %243 = call float @fabs(float %242)
>  %244 = fmul float -2.000000e+00, %86
>  %245 = fadd float %244, %236
>  %246 = call float @fabs(float %245)
>  %247 = fmul float %243, 2.000000e+00
>  %248 = fadd float %247, %246
>  %249 = fadd float %240, %248
>  %250 = fadd float %232, %192
>  %251 = fmul float -2.000000e+00, %66
>  %252 = fadd float %251, %250
>  %253 = call float @fabs(float %252)
>  %254 = fmul float -2.000000e+00, %46
>  %255 = fadd float %254, %234
>  %256 = call float @fabs(float %255)
>  %257 = fadd float %174, %212
>  %258 = fmul float -2.000000e+00, %106
>  %259 = fadd float %258, %257
>  %260 = call float @fabs(float %259)
>  %261 = fmul float %256, 2.000000e+00
>  %262 = fadd float %261, %260
>  %263 = fadd float %253, %262
>  %264 = fcmp uge float %249, %263
>  %265 = select i1 %264, float 1.000000e+00, float 0.000000e+00
>  %266 = fsub float -0.000000e+00, %265
>  %267 = fptosi float %266 to i32
>  %268 = bitcast i32 %267 to float
>  %269 = fadd float %233, %234
>  %270 = fadd float %237, %236
>  %271 = fmul float %269, 2.000000e+00
>  %272 = fadd float %271, %270
>  %273 = bitcast float %268 to i32
>  %274 = xor i32 %273, -1
>  %275 = bitcast i32 %274 to float
>  %276 = bitcast float %275 to i32
>  %277 = icmp ne i32 %276, 0
>  %. = select i1 %277, float %126, float %106
>  %278 = bitcast float %268 to i32
>  %279 = xor i32 %278, -1
>  %280 = bitcast i32 %279 to float
>  %281 = bitcast float %280 to i32
>  %282 = icmp ne i32 %281, 0
>  %temp16.0 = select i1 %282, float %86, float %66
>  %283 = bitcast float %268 to i32
>  %284 = icmp ne i32 %283, 0
>  %.349 = select i1 %284, float %23, float %22
>  %285 = fsub float -0.000000e+00, %46
>  %286 = fmul float %272, 0x3FB5555560000000
>  %287 = fadd float %286, %285
>  %288 = fsub float -0.000000e+00, %46
>  %289 = fadd float %., %288
>  %290 = fsub float -0.000000e+00, %46
>  %291 = fadd float %temp16.0, %290
>  %292 = fadd float %., %46
>  %293 = fadd float %temp16.0, %46
>  %294 = call float @fabs(float %289)
>  %295 = call float @fabs(float %291)
>  %296 = fcmp uge float %294, %295
>  %297 = select i1 %296, float 1.000000e+00, float 0.000000e+00
>  %298 = fsub float -0.000000e+00, %297
>  %299 = fptosi float %298 to i32
>  %300 = bitcast i32 %299 to float
>  %301 = call float @fabs(float %289)
>  %302 = call float @fabs(float %291)
>  %303 = fcmp uge float %301, %302
>  %304 = select i1 %303, float %301, float %302
>  %305 = bitcast float %300 to i32
>  %306 = icmp ne i32 %305, 0
>  br i1 %306, label %IF98, label %ENDIF97
>
>ENDIF:                                            ; preds = %main_body, %ENDIF346
>  %temp7.0 = phi float [ %1510, %ENDIF346 ], [ %41, %main_body ]
>  %temp6.0 = phi float [ %1509, %ENDIF346 ], [ %40, %main_body ]
>  %temp5.0 = phi float [ %1508, %ENDIF346 ], [ %39, %main_body ]
>  %temp4.0 = phi float [ %1507, %ENDIF346 ], [ %38, %main_body ]
>  %307 = call i32 @llvm.SI.packf16(float %temp4.0, float %temp5.0)
>  %308 = bitcast i32 %307 to float
>  %309 = call i32 @llvm.SI.packf16(float %temp6.0, float %temp7.0)
>  %310 = bitcast i32 %309 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %308, float %310, float %308, float %310)
>  ret void
>
>IF98:                                             ; preds = %ELSE
>  %311 = fsub float -0.000000e+00, %.349
>  br label %ENDIF97
>
>ENDIF97:                                          ; preds = %ELSE, %IF98
>  %temp72.1 = phi float [ %311, %IF98 ], [ %.349, %ELSE ]
>  %312 = call float @fabs(float %287)
>  %313 = fmul float %312, %235
>  %314 = call float @llvm.AMDIL.clamp.(float %313, float 0.000000e+00, float 1.000000e+00)
>  %315 = bitcast float %268 to i32
>  %316 = xor i32 %315, -1
>  %317 = bitcast i32 %316 to float
>  %318 = bitcast float %317 to i32
>  %319 = icmp ne i32 %318, 0
>  %.350 = select i1 %319, float 0.000000e+00, float %22
>  %320 = bitcast float %268 to i32
>  %321 = icmp ne i32 %320, 0
>  %temp44.0 = select i1 %321, float 0.000000e+00, float %23
>  %322 = bitcast float %268 to i32
>  %323 = xor i32 %322, -1
>  %324 = bitcast i32 %323 to float
>  %325 = bitcast float %324 to i32
>  %326 = icmp ne i32 %325, 0
>  br i1 %326, label %IF107, label %ENDIF106
>
>IF107:                                            ; preds = %ENDIF97
>  %327 = fmul float %temp72.1, 5.000000e-01
>  %328 = fadd float %327, %28
>  br label %ENDIF106
>
>ENDIF106:                                         ; preds = %ENDIF97, %IF107
>  %temp32.0 = phi float [ %328, %IF107 ], [ %28, %ENDIF97 ]
>  %329 = bitcast float %268 to i32
>  %330 = icmp ne i32 %329, 0
>  br i1 %330, label %IF110, label %ENDIF109
>
>IF110:                                            ; preds = %ENDIF106
>  %331 = fmul float %temp72.1, 5.000000e-01
>  %332 = fadd float %331, %29
>  br label %ENDIF109
>
>ENDIF109:                                         ; preds = %ENDIF106, %IF110
>  %temp33.0 = phi float [ %332, %IF110 ], [ %29, %ENDIF106 ]
>  %333 = fsub float -0.000000e+00, %.350
>  %334 = fadd float %temp32.0, %333
>  %335 = fsub float -0.000000e+00, %temp44.0
>  %336 = fadd float %temp33.0, %335
>  %337 = fadd float %temp32.0, %.350
>  %338 = fadd float %temp33.0, %temp44.0
>  %339 = fmul float -2.000000e+00, %314
>  %340 = fadd float %339, 3.000000e+00
>  %341 = bitcast float %334 to i32
>  %342 = bitcast float %336 to i32
>  %343 = bitcast float 0.000000e+00 to i32
>  %344 = insertelement <4 x i32> undef, i32 %341, i32 0
>  %345 = insertelement <4 x i32> %344, i32 %342, i32 1
>  %346 = insertelement <4 x i32> %345, i32 %343, i32 2
>  %347 = insertelement <4 x i32> %346, i32 undef, i32 3
>  %348 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %347, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %349 = extractelement <4 x float> %348, i32 0
>  %350 = extractelement <4 x float> %348, i32 1
>  %351 = extractelement <4 x float> %348, i32 2
>  %352 = fmul float %349, 0x3FD322D0E0000000
>  %353 = fmul float %350, 0x3FE2C8B440000000
>  %354 = fadd float %353, %352
>  %355 = fmul float %351, 0x3FBD2F1AA0000000
>  %356 = fadd float %354, %355
>  %357 = fmul float %314, %314
>  %358 = bitcast float %337 to i32
>  %359 = bitcast float %338 to i32
>  %360 = bitcast float 0.000000e+00 to i32
>  %361 = insertelement <4 x i32> undef, i32 %358, i32 0
>  %362 = insertelement <4 x i32> %361, i32 %359, i32 1
>  %363 = insertelement <4 x i32> %362, i32 %360, i32 2
>  %364 = insertelement <4 x i32> %363, i32 undef, i32 3
>  %365 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %364, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %366 = extractelement <4 x float> %365, i32 0
>  %367 = extractelement <4 x float> %365, i32 1
>  %368 = extractelement <4 x float> %365, i32 2
>  %369 = fmul float %366, 0x3FD322D0E0000000
>  %370 = fmul float %367, 0x3FE2C8B440000000
>  %371 = fadd float %370, %369
>  %372 = fmul float %368, 0x3FBD2F1AA0000000
>  %373 = fadd float %371, %372
>  %374 = bitcast float %300 to i32
>  %375 = xor i32 %374, -1
>  %376 = bitcast i32 %375 to float
>  %377 = bitcast float %376 to i32
>  %378 = icmp ne i32 %377, 0
>  %.351 = select i1 %378, float %293, float %292
>  %379 = fmul float %304, 2.500000e-01
>  %380 = fmul float %340, %357
>  %381 = fmul float %.351, 5.000000e-01
>  %382 = fsub float -0.000000e+00, %381
>  %383 = fadd float %46, %382
>  %384 = fcmp ult float %383, 0.000000e+00
>  %385 = select i1 %384, float 1.000000e+00, float 0.000000e+00
>  %386 = fsub float -0.000000e+00, %385
>  %387 = fptosi float %386 to i32
>  %388 = bitcast i32 %387 to float
>  %389 = fmul float %.351, 5.000000e-01
>  %390 = fsub float -0.000000e+00, %389
>  %391 = fadd float %356, %390
>  %392 = fmul float %.351, 5.000000e-01
>  %393 = fsub float -0.000000e+00, %392
>  %394 = fadd float %373, %393
>  %395 = call float @fabs(float %391)
>  %396 = fcmp uge float %395, %379
>  %397 = select i1 %396, float 1.000000e+00, float 0.000000e+00
>  %398 = fsub float -0.000000e+00, %397
>  %399 = fptosi float %398 to i32
>  %400 = bitcast i32 %399 to float
>  %401 = call float @fabs(float %394)
>  %402 = fcmp uge float %401, %379
>  %403 = select i1 %402, float 1.000000e+00, float 0.000000e+00
>  %404 = fsub float -0.000000e+00, %403
>  %405 = fptosi float %404 to i32
>  %406 = bitcast i32 %405 to float
>  %407 = bitcast float %400 to i32
>  %408 = xor i32 %407, -1
>  %409 = bitcast i32 %408 to float
>  %410 = bitcast float %409 to i32
>  %411 = icmp ne i32 %410, 0
>  br i1 %411, label %IF116, label %ENDIF115
>
>IF116:                                            ; preds = %ENDIF109
>  %412 = fadd float %334, %333
>  %413 = fsub float -0.000000e+00, %temp44.0
>  %414 = fadd float %336, %413
>  br label %ENDIF115
>
>ENDIF115:                                         ; preds = %ENDIF109, %IF116
>  %temp48.0 = phi float [ %412, %IF116 ], [ %334, %ENDIF109 ]
>  %temp49.0 = phi float [ %414, %IF116 ], [ %336, %ENDIF109 ]
>  %415 = bitcast float %400 to i32
>  %416 = xor i32 %415, -1
>  %417 = bitcast i32 %416 to float
>  %418 = bitcast float %406 to i32
>  %419 = xor i32 %418, -1
>  %420 = bitcast i32 %419 to float
>  %421 = bitcast float %417 to i32
>  %422 = bitcast float %420 to i32
>  %423 = or i32 %421, %422
>  %424 = bitcast i32 %423 to float
>  %425 = bitcast float %406 to i32
>  %426 = xor i32 %425, -1
>  %427 = bitcast i32 %426 to float
>  %428 = bitcast float %427 to i32
>  %429 = icmp ne i32 %428, 0
>  br i1 %429, label %IF119, label %ENDIF118
>
>IF119:                                            ; preds = %ENDIF115
>  %430 = fadd float %337, %.350
>  %431 = fadd float %338, %temp44.0
>  br label %ENDIF118
>
>ENDIF118:                                         ; preds = %ENDIF115, %IF119
>  %temp33.1 = phi float [ %431, %IF119 ], [ %338, %ENDIF115 ]
>  %temp32.1 = phi float [ %430, %IF119 ], [ %337, %ENDIF115 ]
>  %432 = bitcast float %424 to i32
>  %433 = icmp ne i32 %432, 0
>  br i1 %433, label %IF122, label %ENDIF121
>
>IF122:                                            ; preds = %ENDIF118
>  %434 = bitcast float %400 to i32
>  %435 = xor i32 %434, -1
>  %436 = bitcast i32 %435 to float
>  %437 = bitcast float %436 to i32
>  %438 = icmp ne i32 %437, 0
>  br i1 %438, label %IF125, label %ENDIF124
>
>ENDIF121:                                         ; preds = %IF329, %ENDIF325, %ENDIF307, %ENDIF286, %ENDIF265, %ENDIF244, %ENDIF223, %ENDIF202, %ENDIF181, %ENDIF160, %ENDIF139, %ENDIF118
>  %temp33.2 = phi float [ %temp33.1, %ENDIF118 ], [ %temp33.3, %ENDIF139 ], [ %temp33.5, %ENDIF160 ], [ %temp33.7, %ENDIF181 ], [ %temp33.9, %ENDIF202 ], [ %temp33.11, %ENDIF223 ], [ %temp33.13, %ENDIF244 ], [ %temp33.15, %ENDIF265 ], [ %temp33.17, %ENDIF286 ], [ %temp33.19, %ENDIF307 ], [ %1438, %IF329 ], [ %temp33.19, %ENDIF325 ]
>  %temp32.2 = phi float [ %temp32.1, %ENDIF118 ], [ %temp32.3, %ENDIF139 ], [ %temp32.5, %ENDIF160 ], [ %temp32.7, %ENDIF181 ], [ %temp32.9, %ENDIF202 ], [ %temp32.11, %ENDIF223 ], [ %temp32.13, %ENDIF244 ], [ %temp32.15, %ENDIF265 ], [ %temp32.17, %ENDIF286 ], [ %temp32.19, %ENDIF307 ], [ %1436, %IF329 ], [ %temp32.19, %ENDIF325 ]
>  %temp48.1 = phi float [ %temp48.0, %ENDIF118 ], [ %temp48.2, %ENDIF139 ], [ %temp48.4, %ENDIF160 ], [ %temp48.6, %ENDIF181 ], [ %temp48.8, %ENDIF202 ], [ %temp48.10, %ENDIF223 ], [ %temp48.12, %ENDIF244 ], [ %temp48.14, %ENDIF265 ], [ %temp48.16, %ENDIF286 ], [ %temp48.18, %ENDIF307 ], [ %temp48.20, %ENDIF325 ], [ %temp48.20, %IF329 ]
>  %temp49.1 = phi float [ %temp49.0, %ENDIF118 ], [ %temp49.2, %ENDIF139 ], [ %temp49.4, %ENDIF160 ], [ %temp49.6, %ENDIF181 ], [ %temp49.8, %ENDIF202 ], [ %temp49.10, %ENDIF223 ], [ %temp49.12, %ENDIF244 ], [ %temp49.14, %ENDIF265 ], [ %temp49.16, %ENDIF286 ], [ %temp49.18, %ENDIF307 ], [ %temp49.20, %ENDIF325 ], [ %temp49.20, %IF329 ]
>  %temp16.1 = phi float [ %394, %ENDIF118 ], [ %temp16.3, %ENDIF139 ], [ %temp16.6, %ENDIF160 ], [ %temp16.9, %ENDIF181 ], [ %temp16.12, %ENDIF202 ], [ %temp16.15, %ENDIF223 ], [ %temp16.18, %ENDIF244 ], [ %temp16.21, %ENDIF265 ], [ %temp16.24, %ENDIF286 ], [ %temp16.27, %ENDIF307 ], [ %temp16.30, %ENDIF325 ], [ %temp16.30, %IF329 ]
>  %temp8.0 = phi float [ %391, %ENDIF118 ], [ %temp8.2, %ENDIF139 ], [ %temp8.5, %ENDIF160 ], [ %temp8.8, %ENDIF181 ], [ %temp8.11, %ENDIF202 ], [ %temp8.14, %ENDIF223 ], [ %temp8.17, %ENDIF244 ], [ %temp8.20, %ENDIF265 ], [ %temp8.23, %ENDIF286 ], [ %temp8.26, %ENDIF307 ], [ %temp8.29, %ENDIF325 ], [ %temp8.29, %IF329 ]
>  %439 = fsub float -0.000000e+00, %temp48.1
>  %440 = fadd float %28, %439
>  %441 = fsub float -0.000000e+00, %28
>  %442 = fadd float %temp32.2, %441
>  %443 = bitcast float %268 to i32
>  %444 = xor i32 %443, -1
>  %445 = bitcast i32 %444 to float
>  %446 = bitcast float %445 to i32
>  %447 = icmp ne i32 %446, 0
>  br i1 %447, label %IF332, label %ENDIF331
>
>IF125:                                            ; preds = %IF122
>  %448 = bitcast float %temp48.0 to i32
>  %449 = bitcast float %temp49.0 to i32
>  %450 = bitcast float 0.000000e+00 to i32
>  %451 = insertelement <4 x i32> undef, i32 %448, i32 0
>  %452 = insertelement <4 x i32> %451, i32 %449, i32 1
>  %453 = insertelement <4 x i32> %452, i32 %450, i32 2
>  %454 = insertelement <4 x i32> %453, i32 undef, i32 3
>  %455 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %454, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %456 = extractelement <4 x float> %455, i32 0
>  %457 = extractelement <4 x float> %455, i32 1
>  %458 = extractelement <4 x float> %455, i32 2
>  %459 = fmul float %456, 0x3FD322D0E0000000
>  %460 = fmul float %457, 0x3FE2C8B440000000
>  %461 = fadd float %460, %459
>  %462 = fmul float %458, 0x3FBD2F1AA0000000
>  %463 = fadd float %461, %462
>  br label %ENDIF124
>
>ENDIF124:                                         ; preds = %IF122, %IF125
>  %temp8.1 = phi float [ %463, %IF125 ], [ %391, %IF122 ]
>  %464 = bitcast float %406 to i32
>  %465 = xor i32 %464, -1
>  %466 = bitcast i32 %465 to float
>  %467 = bitcast float %466 to i32
>  %468 = icmp ne i32 %467, 0
>  br i1 %468, label %IF128, label %ENDIF127
>
>IF128:                                            ; preds = %ENDIF124
>  %469 = bitcast float %temp32.1 to i32
>  %470 = bitcast float %temp33.1 to i32
>  %471 = bitcast float 0.000000e+00 to i32
>  %472 = insertelement <4 x i32> undef, i32 %469, i32 0
>  %473 = insertelement <4 x i32> %472, i32 %470, i32 1
>  %474 = insertelement <4 x i32> %473, i32 %471, i32 2
>  %475 = insertelement <4 x i32> %474, i32 undef, i32 3
>  %476 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %475, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %477 = extractelement <4 x float> %476, i32 0
>  %478 = extractelement <4 x float> %476, i32 1
>  %479 = extractelement <4 x float> %476, i32 2
>  %480 = fmul float %477, 0x3FD322D0E0000000
>  %481 = fmul float %478, 0x3FE2C8B440000000
>  %482 = fadd float %481, %480
>  %483 = fmul float %479, 0x3FBD2F1AA0000000
>  %484 = fadd float %482, %483
>  br label %ENDIF127
>
>ENDIF127:                                         ; preds = %ENDIF124, %IF128
>  %temp16.2 = phi float [ %484, %IF128 ], [ %394, %ENDIF124 ]
>  %485 = bitcast float %400 to i32
>  %486 = xor i32 %485, -1
>  %487 = bitcast i32 %486 to float
>  %488 = bitcast float %487 to i32
>  %489 = icmp ne i32 %488, 0
>  br i1 %489, label %IF131, label %ENDIF130
>
>IF131:                                            ; preds = %ENDIF127
>  %490 = fmul float %.351, 5.000000e-01
>  %491 = fsub float -0.000000e+00, %490
>  %492 = fadd float %temp8.1, %491
>  br label %ENDIF130
>
>ENDIF130:                                         ; preds = %ENDIF127, %IF131
>  %temp8.2 = phi float [ %492, %IF131 ], [ %temp8.1, %ENDIF127 ]
>  %493 = bitcast float %406 to i32
>  %494 = xor i32 %493, -1
>  %495 = bitcast i32 %494 to float
>  %496 = bitcast float %495 to i32
>  %497 = icmp ne i32 %496, 0
>  br i1 %497, label %IF134, label %ENDIF133
>
>IF134:                                            ; preds = %ENDIF130
>  %498 = fmul float %.351, 5.000000e-01
>  %499 = fsub float -0.000000e+00, %498
>  %500 = fadd float %temp16.2, %499
>  br label %ENDIF133
>
>ENDIF133:                                         ; preds = %ENDIF130, %IF134
>  %temp16.3 = phi float [ %500, %IF134 ], [ %temp16.2, %ENDIF130 ]
>  %501 = call float @fabs(float %temp8.2)
>  %502 = fcmp uge float %501, %379
>  %503 = select i1 %502, float 1.000000e+00, float 0.000000e+00
>  %504 = fsub float -0.000000e+00, %503
>  %505 = fptosi float %504 to i32
>  %506 = bitcast i32 %505 to float
>  %507 = call float @fabs(float %temp16.3)
>  %508 = fcmp uge float %507, %379
>  %509 = select i1 %508, float 1.000000e+00, float 0.000000e+00
>  %510 = fsub float -0.000000e+00, %509
>  %511 = fptosi float %510 to i32
>  %512 = bitcast i32 %511 to float
>  %513 = bitcast float %506 to i32
>  %514 = xor i32 %513, -1
>  %515 = bitcast i32 %514 to float
>  %516 = bitcast float %515 to i32
>  %517 = icmp ne i32 %516, 0
>  br i1 %517, label %IF137, label %ENDIF136
>
>IF137:                                            ; preds = %ENDIF133
>  %518 = fsub float -0.000000e+00, %.350
>  %519 = fadd float %temp48.0, %518
>  %520 = fsub float -0.000000e+00, %temp44.0
>  %521 = fadd float %temp49.0, %520
>  br label %ENDIF136
>
>ENDIF136:                                         ; preds = %ENDIF133, %IF137
>  %temp48.2 = phi float [ %519, %IF137 ], [ %temp48.0, %ENDIF133 ]
>  %temp49.2 = phi float [ %521, %IF137 ], [ %temp49.0, %ENDIF133 ]
>  %522 = bitcast float %506 to i32
>  %523 = xor i32 %522, -1
>  %524 = bitcast i32 %523 to float
>  %525 = bitcast float %512 to i32
>  %526 = xor i32 %525, -1
>  %527 = bitcast i32 %526 to float
>  %528 = bitcast float %524 to i32
>  %529 = bitcast float %527 to i32
>  %530 = or i32 %528, %529
>  %531 = bitcast i32 %530 to float
>  %532 = bitcast float %512 to i32
>  %533 = xor i32 %532, -1
>  %534 = bitcast i32 %533 to float
>  %535 = bitcast float %534 to i32
>  %536 = icmp ne i32 %535, 0
>  br i1 %536, label %IF140, label %ENDIF139
>
>IF140:                                            ; preds = %ENDIF136
>  %537 = fadd float %temp32.1, %.350
>  %538 = fadd float %temp33.1, %temp44.0
>  br label %ENDIF139
>
>ENDIF139:                                         ; preds = %ENDIF136, %IF140
>  %temp33.3 = phi float [ %538, %IF140 ], [ %temp33.1, %ENDIF136 ]
>  %temp32.3 = phi float [ %537, %IF140 ], [ %temp32.1, %ENDIF136 ]
>  %539 = bitcast float %531 to i32
>  %540 = icmp ne i32 %539, 0
>  br i1 %540, label %IF143, label %ENDIF121
>
>IF143:                                            ; preds = %ENDIF139
>  %541 = bitcast float %506 to i32
>  %542 = xor i32 %541, -1
>  %543 = bitcast i32 %542 to float
>  %544 = bitcast float %543 to i32
>  %545 = icmp ne i32 %544, 0
>  br i1 %545, label %IF146, label %ENDIF145
>
>IF146:                                            ; preds = %IF143
>  %546 = bitcast float %temp48.2 to i32
>  %547 = bitcast float %temp49.2 to i32
>  %548 = bitcast float 0.000000e+00 to i32
>  %549 = insertelement <4 x i32> undef, i32 %546, i32 0
>  %550 = insertelement <4 x i32> %549, i32 %547, i32 1
>  %551 = insertelement <4 x i32> %550, i32 %548, i32 2
>  %552 = insertelement <4 x i32> %551, i32 undef, i32 3
>  %553 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %552, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %554 = extractelement <4 x float> %553, i32 0
>  %555 = extractelement <4 x float> %553, i32 1
>  %556 = extractelement <4 x float> %553, i32 2
>  %557 = fmul float %554, 0x3FD322D0E0000000
>  %558 = fmul float %555, 0x3FE2C8B440000000
>  %559 = fadd float %558, %557
>  %560 = fmul float %556, 0x3FBD2F1AA0000000
>  %561 = fadd float %559, %560
>  br label %ENDIF145
>
>ENDIF145:                                         ; preds = %IF143, %IF146
>  %temp8.4 = phi float [ %561, %IF146 ], [ %temp8.2, %IF143 ]
>  %562 = bitcast float %512 to i32
>  %563 = xor i32 %562, -1
>  %564 = bitcast i32 %563 to float
>  %565 = bitcast float %564 to i32
>  %566 = icmp ne i32 %565, 0
>  br i1 %566, label %IF149, label %ENDIF148
>
>IF149:                                            ; preds = %ENDIF145
>  %567 = bitcast float %temp32.3 to i32
>  %568 = bitcast float %temp33.3 to i32
>  %569 = bitcast float 0.000000e+00 to i32
>  %570 = insertelement <4 x i32> undef, i32 %567, i32 0
>  %571 = insertelement <4 x i32> %570, i32 %568, i32 1
>  %572 = insertelement <4 x i32> %571, i32 %569, i32 2
>  %573 = insertelement <4 x i32> %572, i32 undef, i32 3
>  %574 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %573, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %575 = extractelement <4 x float> %574, i32 0
>  %576 = extractelement <4 x float> %574, i32 1
>  %577 = extractelement <4 x float> %574, i32 2
>  %578 = fmul float %575, 0x3FD322D0E0000000
>  %579 = fmul float %576, 0x3FE2C8B440000000
>  %580 = fadd float %579, %578
>  %581 = fmul float %577, 0x3FBD2F1AA0000000
>  %582 = fadd float %580, %581
>  br label %ENDIF148
>
>ENDIF148:                                         ; preds = %ENDIF145, %IF149
>  %temp16.5 = phi float [ %582, %IF149 ], [ %temp16.3, %ENDIF145 ]
>  %583 = bitcast float %506 to i32
>  %584 = xor i32 %583, -1
>  %585 = bitcast i32 %584 to float
>  %586 = bitcast float %585 to i32
>  %587 = icmp ne i32 %586, 0
>  br i1 %587, label %IF152, label %ENDIF151
>
>IF152:                                            ; preds = %ENDIF148
>  %588 = fmul float %.351, 5.000000e-01
>  %589 = fsub float -0.000000e+00, %588
>  %590 = fadd float %temp8.4, %589
>  br label %ENDIF151
>
>ENDIF151:                                         ; preds = %ENDIF148, %IF152
>  %temp8.5 = phi float [ %590, %IF152 ], [ %temp8.4, %ENDIF148 ]
>  %591 = bitcast float %512 to i32
>  %592 = xor i32 %591, -1
>  %593 = bitcast i32 %592 to float
>  %594 = bitcast float %593 to i32
>  %595 = icmp ne i32 %594, 0
>  br i1 %595, label %IF155, label %ENDIF154
>
>IF155:                                            ; preds = %ENDIF151
>  %596 = fmul float %.351, 5.000000e-01
>  %597 = fsub float -0.000000e+00, %596
>  %598 = fadd float %temp16.5, %597
>  br label %ENDIF154
>
>ENDIF154:                                         ; preds = %ENDIF151, %IF155
>  %temp16.6 = phi float [ %598, %IF155 ], [ %temp16.5, %ENDIF151 ]
>  %599 = call float @fabs(float %temp8.5)
>  %600 = fcmp uge float %599, %379
>  %601 = select i1 %600, float 1.000000e+00, float 0.000000e+00
>  %602 = fsub float -0.000000e+00, %601
>  %603 = fptosi float %602 to i32
>  %604 = bitcast i32 %603 to float
>  %605 = call float @fabs(float %temp16.6)
>  %606 = fcmp uge float %605, %379
>  %607 = select i1 %606, float 1.000000e+00, float 0.000000e+00
>  %608 = fsub float -0.000000e+00, %607
>  %609 = fptosi float %608 to i32
>  %610 = bitcast i32 %609 to float
>  %611 = bitcast float %604 to i32
>  %612 = xor i32 %611, -1
>  %613 = bitcast i32 %612 to float
>  %614 = bitcast float %613 to i32
>  %615 = icmp ne i32 %614, 0
>  br i1 %615, label %IF158, label %ENDIF157
>
>IF158:                                            ; preds = %ENDIF154
>  %616 = fsub float -0.000000e+00, %.350
>  %617 = fadd float %temp48.2, %616
>  %618 = fsub float -0.000000e+00, %temp44.0
>  %619 = fadd float %temp49.2, %618
>  br label %ENDIF157
>
>ENDIF157:                                         ; preds = %ENDIF154, %IF158
>  %temp48.4 = phi float [ %617, %IF158 ], [ %temp48.2, %ENDIF154 ]
>  %temp49.4 = phi float [ %619, %IF158 ], [ %temp49.2, %ENDIF154 ]
>  %620 = bitcast float %604 to i32
>  %621 = xor i32 %620, -1
>  %622 = bitcast i32 %621 to float
>  %623 = bitcast float %610 to i32
>  %624 = xor i32 %623, -1
>  %625 = bitcast i32 %624 to float
>  %626 = bitcast float %622 to i32
>  %627 = bitcast float %625 to i32
>  %628 = or i32 %626, %627
>  %629 = bitcast i32 %628 to float
>  %630 = bitcast float %610 to i32
>  %631 = xor i32 %630, -1
>  %632 = bitcast i32 %631 to float
>  %633 = bitcast float %632 to i32
>  %634 = icmp ne i32 %633, 0
>  br i1 %634, label %IF161, label %ENDIF160
>
>IF161:                                            ; preds = %ENDIF157
>  %635 = fadd float %temp32.3, %.350
>  %636 = fadd float %temp33.3, %temp44.0
>  br label %ENDIF160
>
>ENDIF160:                                         ; preds = %ENDIF157, %IF161
>  %temp33.5 = phi float [ %636, %IF161 ], [ %temp33.3, %ENDIF157 ]
>  %temp32.5 = phi float [ %635, %IF161 ], [ %temp32.3, %ENDIF157 ]
>  %637 = bitcast float %629 to i32
>  %638 = icmp ne i32 %637, 0
>  br i1 %638, label %IF164, label %ENDIF121
>
>IF164:                                            ; preds = %ENDIF160
>  %639 = bitcast float %604 to i32
>  %640 = xor i32 %639, -1
>  %641 = bitcast i32 %640 to float
>  %642 = bitcast float %641 to i32
>  %643 = icmp ne i32 %642, 0
>  br i1 %643, label %IF167, label %ENDIF166
>
>IF167:                                            ; preds = %IF164
>  %644 = bitcast float %temp48.4 to i32
>  %645 = bitcast float %temp49.4 to i32
>  %646 = bitcast float 0.000000e+00 to i32
>  %647 = insertelement <4 x i32> undef, i32 %644, i32 0
>  %648 = insertelement <4 x i32> %647, i32 %645, i32 1
>  %649 = insertelement <4 x i32> %648, i32 %646, i32 2
>  %650 = insertelement <4 x i32> %649, i32 undef, i32 3
>  %651 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %650, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %652 = extractelement <4 x float> %651, i32 0
>  %653 = extractelement <4 x float> %651, i32 1
>  %654 = extractelement <4 x float> %651, i32 2
>  %655 = fmul float %652, 0x3FD322D0E0000000
>  %656 = fmul float %653, 0x3FE2C8B440000000
>  %657 = fadd float %656, %655
>  %658 = fmul float %654, 0x3FBD2F1AA0000000
>  %659 = fadd float %657, %658
>  br label %ENDIF166
>
>ENDIF166:                                         ; preds = %IF164, %IF167
>  %temp8.7 = phi float [ %659, %IF167 ], [ %temp8.5, %IF164 ]
>  %660 = bitcast float %610 to i32
>  %661 = xor i32 %660, -1
>  %662 = bitcast i32 %661 to float
>  %663 = bitcast float %662 to i32
>  %664 = icmp ne i32 %663, 0
>  br i1 %664, label %IF170, label %ENDIF169
>
>IF170:                                            ; preds = %ENDIF166
>  %665 = bitcast float %temp32.5 to i32
>  %666 = bitcast float %temp33.5 to i32
>  %667 = bitcast float 0.000000e+00 to i32
>  %668 = insertelement <4 x i32> undef, i32 %665, i32 0
>  %669 = insertelement <4 x i32> %668, i32 %666, i32 1
>  %670 = insertelement <4 x i32> %669, i32 %667, i32 2
>  %671 = insertelement <4 x i32> %670, i32 undef, i32 3
>  %672 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %671, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %673 = extractelement <4 x float> %672, i32 0
>  %674 = extractelement <4 x float> %672, i32 1
>  %675 = extractelement <4 x float> %672, i32 2
>  %676 = fmul float %673, 0x3FD322D0E0000000
>  %677 = fmul float %674, 0x3FE2C8B440000000
>  %678 = fadd float %677, %676
>  %679 = fmul float %675, 0x3FBD2F1AA0000000
>  %680 = fadd float %678, %679
>  br label %ENDIF169
>
>ENDIF169:                                         ; preds = %ENDIF166, %IF170
>  %temp16.8 = phi float [ %680, %IF170 ], [ %temp16.6, %ENDIF166 ]
>  %681 = bitcast float %604 to i32
>  %682 = xor i32 %681, -1
>  %683 = bitcast i32 %682 to float
>  %684 = bitcast float %683 to i32
>  %685 = icmp ne i32 %684, 0
>  br i1 %685, label %IF173, label %ENDIF172
>
>IF173:                                            ; preds = %ENDIF169
>  %686 = fmul float %.351, 5.000000e-01
>  %687 = fsub float -0.000000e+00, %686
>  %688 = fadd float %temp8.7, %687
>  br label %ENDIF172
>
>ENDIF172:                                         ; preds = %ENDIF169, %IF173
>  %temp8.8 = phi float [ %688, %IF173 ], [ %temp8.7, %ENDIF169 ]
>  %689 = bitcast float %610 to i32
>  %690 = xor i32 %689, -1
>  %691 = bitcast i32 %690 to float
>  %692 = bitcast float %691 to i32
>  %693 = icmp ne i32 %692, 0
>  br i1 %693, label %IF176, label %ENDIF175
>
>IF176:                                            ; preds = %ENDIF172
>  %694 = fmul float %.351, 5.000000e-01
>  %695 = fsub float -0.000000e+00, %694
>  %696 = fadd float %temp16.8, %695
>  br label %ENDIF175
>
>ENDIF175:                                         ; preds = %ENDIF172, %IF176
>  %temp16.9 = phi float [ %696, %IF176 ], [ %temp16.8, %ENDIF172 ]
>  %697 = call float @fabs(float %temp8.8)
>  %698 = fcmp uge float %697, %379
>  %699 = select i1 %698, float 1.000000e+00, float 0.000000e+00
>  %700 = fsub float -0.000000e+00, %699
>  %701 = fptosi float %700 to i32
>  %702 = bitcast i32 %701 to float
>  %703 = call float @fabs(float %temp16.9)
>  %704 = fcmp uge float %703, %379
>  %705 = select i1 %704, float 1.000000e+00, float 0.000000e+00
>  %706 = fsub float -0.000000e+00, %705
>  %707 = fptosi float %706 to i32
>  %708 = bitcast i32 %707 to float
>  %709 = bitcast float %702 to i32
>  %710 = xor i32 %709, -1
>  %711 = bitcast i32 %710 to float
>  %712 = bitcast float %711 to i32
>  %713 = icmp ne i32 %712, 0
>  br i1 %713, label %IF179, label %ENDIF178
>
>IF179:                                            ; preds = %ENDIF175
>  %714 = fsub float -0.000000e+00, %.350
>  %715 = fadd float %temp48.4, %714
>  %716 = fsub float -0.000000e+00, %temp44.0
>  %717 = fadd float %temp49.4, %716
>  br label %ENDIF178
>
>ENDIF178:                                         ; preds = %ENDIF175, %IF179
>  %temp48.6 = phi float [ %715, %IF179 ], [ %temp48.4, %ENDIF175 ]
>  %temp49.6 = phi float [ %717, %IF179 ], [ %temp49.4, %ENDIF175 ]
>  %718 = bitcast float %702 to i32
>  %719 = xor i32 %718, -1
>  %720 = bitcast i32 %719 to float
>  %721 = bitcast float %708 to i32
>  %722 = xor i32 %721, -1
>  %723 = bitcast i32 %722 to float
>  %724 = bitcast float %720 to i32
>  %725 = bitcast float %723 to i32
>  %726 = or i32 %724, %725
>  %727 = bitcast i32 %726 to float
>  %728 = bitcast float %708 to i32
>  %729 = xor i32 %728, -1
>  %730 = bitcast i32 %729 to float
>  %731 = bitcast float %730 to i32
>  %732 = icmp ne i32 %731, 0
>  br i1 %732, label %IF182, label %ENDIF181
>
>IF182:                                            ; preds = %ENDIF178
>  %733 = fadd float %temp32.5, %.350
>  %734 = fadd float %temp33.5, %temp44.0
>  br label %ENDIF181
>
>ENDIF181:                                         ; preds = %ENDIF178, %IF182
>  %temp33.7 = phi float [ %734, %IF182 ], [ %temp33.5, %ENDIF178 ]
>  %temp32.7 = phi float [ %733, %IF182 ], [ %temp32.5, %ENDIF178 ]
>  %735 = bitcast float %727 to i32
>  %736 = icmp ne i32 %735, 0
>  br i1 %736, label %IF185, label %ENDIF121
>
>IF185:                                            ; preds = %ENDIF181
>  %737 = bitcast float %702 to i32
>  %738 = xor i32 %737, -1
>  %739 = bitcast i32 %738 to float
>  %740 = bitcast float %739 to i32
>  %741 = icmp ne i32 %740, 0
>  br i1 %741, label %IF188, label %ENDIF187
>
>IF188:                                            ; preds = %IF185
>  %742 = bitcast float %temp48.6 to i32
>  %743 = bitcast float %temp49.6 to i32
>  %744 = bitcast float 0.000000e+00 to i32
>  %745 = insertelement <4 x i32> undef, i32 %742, i32 0
>  %746 = insertelement <4 x i32> %745, i32 %743, i32 1
>  %747 = insertelement <4 x i32> %746, i32 %744, i32 2
>  %748 = insertelement <4 x i32> %747, i32 undef, i32 3
>  %749 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %748, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %750 = extractelement <4 x float> %749, i32 0
>  %751 = extractelement <4 x float> %749, i32 1
>  %752 = extractelement <4 x float> %749, i32 2
>  %753 = fmul float %750, 0x3FD322D0E0000000
>  %754 = fmul float %751, 0x3FE2C8B440000000
>  %755 = fadd float %754, %753
>  %756 = fmul float %752, 0x3FBD2F1AA0000000
>  %757 = fadd float %755, %756
>  br label %ENDIF187
>
>ENDIF187:                                         ; preds = %IF185, %IF188
>  %temp8.10 = phi float [ %757, %IF188 ], [ %temp8.8, %IF185 ]
>  %758 = bitcast float %708 to i32
>  %759 = xor i32 %758, -1
>  %760 = bitcast i32 %759 to float
>  %761 = bitcast float %760 to i32
>  %762 = icmp ne i32 %761, 0
>  br i1 %762, label %IF191, label %ENDIF190
>
>IF191:                                            ; preds = %ENDIF187
>  %763 = bitcast float %temp32.7 to i32
>  %764 = bitcast float %temp33.7 to i32
>  %765 = bitcast float 0.000000e+00 to i32
>  %766 = insertelement <4 x i32> undef, i32 %763, i32 0
>  %767 = insertelement <4 x i32> %766, i32 %764, i32 1
>  %768 = insertelement <4 x i32> %767, i32 %765, i32 2
>  %769 = insertelement <4 x i32> %768, i32 undef, i32 3
>  %770 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %769, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %771 = extractelement <4 x float> %770, i32 0
>  %772 = extractelement <4 x float> %770, i32 1
>  %773 = extractelement <4 x float> %770, i32 2
>  %774 = fmul float %771, 0x3FD322D0E0000000
>  %775 = fmul float %772, 0x3FE2C8B440000000
>  %776 = fadd float %775, %774
>  %777 = fmul float %773, 0x3FBD2F1AA0000000
>  %778 = fadd float %776, %777
>  br label %ENDIF190
>
>ENDIF190:                                         ; preds = %ENDIF187, %IF191
>  %temp16.11 = phi float [ %778, %IF191 ], [ %temp16.9, %ENDIF187 ]
>  %779 = bitcast float %702 to i32
>  %780 = xor i32 %779, -1
>  %781 = bitcast i32 %780 to float
>  %782 = bitcast float %781 to i32
>  %783 = icmp ne i32 %782, 0
>  br i1 %783, label %IF194, label %ENDIF193
>
>IF194:                                            ; preds = %ENDIF190
>  %784 = fmul float %.351, 5.000000e-01
>  %785 = fsub float -0.000000e+00, %784
>  %786 = fadd float %temp8.10, %785
>  br label %ENDIF193
>
>ENDIF193:                                         ; preds = %ENDIF190, %IF194
>  %temp8.11 = phi float [ %786, %IF194 ], [ %temp8.10, %ENDIF190 ]
>  %787 = bitcast float %708 to i32
>  %788 = xor i32 %787, -1
>  %789 = bitcast i32 %788 to float
>  %790 = bitcast float %789 to i32
>  %791 = icmp ne i32 %790, 0
>  br i1 %791, label %IF197, label %ENDIF196
>
>IF197:                                            ; preds = %ENDIF193
>  %792 = fmul float %.351, 5.000000e-01
>  %793 = fsub float -0.000000e+00, %792
>  %794 = fadd float %temp16.11, %793
>  br label %ENDIF196
>
>ENDIF196:                                         ; preds = %ENDIF193, %IF197
>  %temp16.12 = phi float [ %794, %IF197 ], [ %temp16.11, %ENDIF193 ]
>  %795 = call float @fabs(float %temp8.11)
>  %796 = fcmp uge float %795, %379
>  %797 = select i1 %796, float 1.000000e+00, float 0.000000e+00
>  %798 = fsub float -0.000000e+00, %797
>  %799 = fptosi float %798 to i32
>  %800 = bitcast i32 %799 to float
>  %801 = call float @fabs(float %temp16.12)
>  %802 = fcmp uge float %801, %379
>  %803 = select i1 %802, float 1.000000e+00, float 0.000000e+00
>  %804 = fsub float -0.000000e+00, %803
>  %805 = fptosi float %804 to i32
>  %806 = bitcast i32 %805 to float
>  %807 = bitcast float %800 to i32
>  %808 = xor i32 %807, -1
>  %809 = bitcast i32 %808 to float
>  %810 = bitcast float %809 to i32
>  %811 = icmp ne i32 %810, 0
>  br i1 %811, label %IF200, label %ENDIF199
>
>IF200:                                            ; preds = %ENDIF196
>  %812 = fmul float %.350, 1.500000e+00
>  %813 = fmul float %temp44.0, 1.500000e+00
>  %814 = fsub float -0.000000e+00, %812
>  %815 = fadd float %temp48.6, %814
>  %816 = fsub float -0.000000e+00, %813
>  %817 = fadd float %temp49.6, %816
>  br label %ENDIF199
>
>ENDIF199:                                         ; preds = %ENDIF196, %IF200
>  %temp48.8 = phi float [ %815, %IF200 ], [ %temp48.6, %ENDIF196 ]
>  %temp49.8 = phi float [ %817, %IF200 ], [ %temp49.6, %ENDIF196 ]
>  %818 = bitcast float %800 to i32
>  %819 = xor i32 %818, -1
>  %820 = bitcast i32 %819 to float
>  %821 = bitcast float %806 to i32
>  %822 = xor i32 %821, -1
>  %823 = bitcast i32 %822 to float
>  %824 = bitcast float %820 to i32
>  %825 = bitcast float %823 to i32
>  %826 = or i32 %824, %825
>  %827 = bitcast i32 %826 to float
>  %828 = bitcast float %806 to i32
>  %829 = xor i32 %828, -1
>  %830 = bitcast i32 %829 to float
>  %831 = bitcast float %830 to i32
>  %832 = icmp ne i32 %831, 0
>  br i1 %832, label %IF203, label %ENDIF202
>
>IF203:                                            ; preds = %ENDIF199
>  %833 = fmul float %.350, 1.500000e+00
>  %834 = fadd float %833, %temp32.7
>  %835 = fmul float %temp44.0, 1.500000e+00
>  %836 = fadd float %835, %temp33.7
>  br label %ENDIF202
>
>ENDIF202:                                         ; preds = %ENDIF199, %IF203
>  %temp33.9 = phi float [ %836, %IF203 ], [ %temp33.7, %ENDIF199 ]
>  %temp32.9 = phi float [ %834, %IF203 ], [ %temp32.7, %ENDIF199 ]
>  %837 = bitcast float %827 to i32
>  %838 = icmp ne i32 %837, 0
>  br i1 %838, label %IF206, label %ENDIF121
>
>IF206:                                            ; preds = %ENDIF202
>  %839 = bitcast float %800 to i32
>  %840 = xor i32 %839, -1
>  %841 = bitcast i32 %840 to float
>  %842 = bitcast float %841 to i32
>  %843 = icmp ne i32 %842, 0
>  br i1 %843, label %IF209, label %ENDIF208
>
>IF209:                                            ; preds = %IF206
>  %844 = bitcast float %temp48.8 to i32
>  %845 = bitcast float %temp49.8 to i32
>  %846 = bitcast float 0.000000e+00 to i32
>  %847 = insertelement <4 x i32> undef, i32 %844, i32 0
>  %848 = insertelement <4 x i32> %847, i32 %845, i32 1
>  %849 = insertelement <4 x i32> %848, i32 %846, i32 2
>  %850 = insertelement <4 x i32> %849, i32 undef, i32 3
>  %851 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %850, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %852 = extractelement <4 x float> %851, i32 0
>  %853 = extractelement <4 x float> %851, i32 1
>  %854 = extractelement <4 x float> %851, i32 2
>  %855 = fmul float %852, 0x3FD322D0E0000000
>  %856 = fmul float %853, 0x3FE2C8B440000000
>  %857 = fadd float %856, %855
>  %858 = fmul float %854, 0x3FBD2F1AA0000000
>  %859 = fadd float %857, %858
>  br label %ENDIF208
>
>ENDIF208:                                         ; preds = %IF206, %IF209
>  %temp8.13 = phi float [ %859, %IF209 ], [ %temp8.11, %IF206 ]
>  %860 = bitcast float %806 to i32
>  %861 = xor i32 %860, -1
>  %862 = bitcast i32 %861 to float
>  %863 = bitcast float %862 to i32
>  %864 = icmp ne i32 %863, 0
>  br i1 %864, label %IF212, label %ENDIF211
>
>IF212:                                            ; preds = %ENDIF208
>  %865 = bitcast float %temp32.9 to i32
>  %866 = bitcast float %temp33.9 to i32
>  %867 = bitcast float 0.000000e+00 to i32
>  %868 = insertelement <4 x i32> undef, i32 %865, i32 0
>  %869 = insertelement <4 x i32> %868, i32 %866, i32 1
>  %870 = insertelement <4 x i32> %869, i32 %867, i32 2
>  %871 = insertelement <4 x i32> %870, i32 undef, i32 3
>  %872 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %871, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %873 = extractelement <4 x float> %872, i32 0
>  %874 = extractelement <4 x float> %872, i32 1
>  %875 = extractelement <4 x float> %872, i32 2
>  %876 = fmul float %873, 0x3FD322D0E0000000
>  %877 = fmul float %874, 0x3FE2C8B440000000
>  %878 = fadd float %877, %876
>  %879 = fmul float %875, 0x3FBD2F1AA0000000
>  %880 = fadd float %878, %879
>  br label %ENDIF211
>
>ENDIF211:                                         ; preds = %ENDIF208, %IF212
>  %temp16.14 = phi float [ %880, %IF212 ], [ %temp16.12, %ENDIF208 ]
>  %881 = bitcast float %800 to i32
>  %882 = xor i32 %881, -1
>  %883 = bitcast i32 %882 to float
>  %884 = bitcast float %883 to i32
>  %885 = icmp ne i32 %884, 0
>  br i1 %885, label %IF215, label %ENDIF214
>
>IF215:                                            ; preds = %ENDIF211
>  %886 = fmul float %.351, 5.000000e-01
>  %887 = fsub float -0.000000e+00, %886
>  %888 = fadd float %temp8.13, %887
>  br label %ENDIF214
>
>ENDIF214:                                         ; preds = %ENDIF211, %IF215
>  %temp8.14 = phi float [ %888, %IF215 ], [ %temp8.13, %ENDIF211 ]
>  %889 = bitcast float %806 to i32
>  %890 = xor i32 %889, -1
>  %891 = bitcast i32 %890 to float
>  %892 = bitcast float %891 to i32
>  %893 = icmp ne i32 %892, 0
>  br i1 %893, label %IF218, label %ENDIF217
>
>IF218:                                            ; preds = %ENDIF214
>  %894 = fmul float %.351, 5.000000e-01
>  %895 = fsub float -0.000000e+00, %894
>  %896 = fadd float %temp16.14, %895
>  br label %ENDIF217
>
>ENDIF217:                                         ; preds = %ENDIF214, %IF218
>  %temp16.15 = phi float [ %896, %IF218 ], [ %temp16.14, %ENDIF214 ]
>  %897 = call float @fabs(float %temp8.14)
>  %898 = fcmp uge float %897, %379
>  %899 = select i1 %898, float 1.000000e+00, float 0.000000e+00
>  %900 = fsub float -0.000000e+00, %899
>  %901 = fptosi float %900 to i32
>  %902 = bitcast i32 %901 to float
>  %903 = call float @fabs(float %temp16.15)
>  %904 = fcmp uge float %903, %379
>  %905 = select i1 %904, float 1.000000e+00, float 0.000000e+00
>  %906 = fsub float -0.000000e+00, %905
>  %907 = fptosi float %906 to i32
>  %908 = bitcast i32 %907 to float
>  %909 = bitcast float %902 to i32
>  %910 = xor i32 %909, -1
>  %911 = bitcast i32 %910 to float
>  %912 = bitcast float %911 to i32
>  %913 = icmp ne i32 %912, 0
>  br i1 %913, label %IF221, label %ENDIF220
>
>IF221:                                            ; preds = %ENDIF217
>  %914 = fmul float %.350, 2.000000e+00
>  %915 = fmul float %temp44.0, 2.000000e+00
>  %916 = fsub float -0.000000e+00, %914
>  %917 = fadd float %temp48.8, %916
>  %918 = fsub float -0.000000e+00, %915
>  %919 = fadd float %temp49.8, %918
>  br label %ENDIF220
>
>ENDIF220:                                         ; preds = %ENDIF217, %IF221
>  %temp48.10 = phi float [ %917, %IF221 ], [ %temp48.8, %ENDIF217 ]
>  %temp49.10 = phi float [ %919, %IF221 ], [ %temp49.8, %ENDIF217 ]
>  %920 = bitcast float %902 to i32
>  %921 = xor i32 %920, -1
>  %922 = bitcast i32 %921 to float
>  %923 = bitcast float %908 to i32
>  %924 = xor i32 %923, -1
>  %925 = bitcast i32 %924 to float
>  %926 = bitcast float %922 to i32
>  %927 = bitcast float %925 to i32
>  %928 = or i32 %926, %927
>  %929 = bitcast i32 %928 to float
>  %930 = bitcast float %908 to i32
>  %931 = xor i32 %930, -1
>  %932 = bitcast i32 %931 to float
>  %933 = bitcast float %932 to i32
>  %934 = icmp ne i32 %933, 0
>  br i1 %934, label %IF224, label %ENDIF223
>
>IF224:                                            ; preds = %ENDIF220
>  %935 = fmul float %.350, 2.000000e+00
>  %936 = fadd float %935, %temp32.9
>  %937 = fmul float %temp44.0, 2.000000e+00
>  %938 = fadd float %937, %temp33.9
>  br label %ENDIF223
>
>ENDIF223:                                         ; preds = %ENDIF220, %IF224
>  %temp33.11 = phi float [ %938, %IF224 ], [ %temp33.9, %ENDIF220 ]
>  %temp32.11 = phi float [ %936, %IF224 ], [ %temp32.9, %ENDIF220 ]
>  %939 = bitcast float %929 to i32
>  %940 = icmp ne i32 %939, 0
>  br i1 %940, label %IF227, label %ENDIF121
>
>IF227:                                            ; preds = %ENDIF223
>  %941 = bitcast float %902 to i32
>  %942 = xor i32 %941, -1
>  %943 = bitcast i32 %942 to float
>  %944 = bitcast float %943 to i32
>  %945 = icmp ne i32 %944, 0
>  br i1 %945, label %IF230, label %ENDIF229
>
>IF230:                                            ; preds = %IF227
>  %946 = bitcast float %temp48.10 to i32
>  %947 = bitcast float %temp49.10 to i32
>  %948 = bitcast float 0.000000e+00 to i32
>  %949 = insertelement <4 x i32> undef, i32 %946, i32 0
>  %950 = insertelement <4 x i32> %949, i32 %947, i32 1
>  %951 = insertelement <4 x i32> %950, i32 %948, i32 2
>  %952 = insertelement <4 x i32> %951, i32 undef, i32 3
>  %953 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %952, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %954 = extractelement <4 x float> %953, i32 0
>  %955 = extractelement <4 x float> %953, i32 1
>  %956 = extractelement <4 x float> %953, i32 2
>  %957 = fmul float %954, 0x3FD322D0E0000000
>  %958 = fmul float %955, 0x3FE2C8B440000000
>  %959 = fadd float %958, %957
>  %960 = fmul float %956, 0x3FBD2F1AA0000000
>  %961 = fadd float %959, %960
>  br label %ENDIF229
>
>ENDIF229:                                         ; preds = %IF227, %IF230
>  %temp8.16 = phi float [ %961, %IF230 ], [ %temp8.14, %IF227 ]
>  %962 = bitcast float %908 to i32
>  %963 = xor i32 %962, -1
>  %964 = bitcast i32 %963 to float
>  %965 = bitcast float %964 to i32
>  %966 = icmp ne i32 %965, 0
>  br i1 %966, label %IF233, label %ENDIF232
>
>IF233:                                            ; preds = %ENDIF229
>  %967 = bitcast float %temp32.11 to i32
>  %968 = bitcast float %temp33.11 to i32
>  %969 = bitcast float 0.000000e+00 to i32
>  %970 = insertelement <4 x i32> undef, i32 %967, i32 0
>  %971 = insertelement <4 x i32> %970, i32 %968, i32 1
>  %972 = insertelement <4 x i32> %971, i32 %969, i32 2
>  %973 = insertelement <4 x i32> %972, i32 undef, i32 3
>  %974 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %973, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %975 = extractelement <4 x float> %974, i32 0
>  %976 = extractelement <4 x float> %974, i32 1
>  %977 = extractelement <4 x float> %974, i32 2
>  %978 = fmul float %975, 0x3FD322D0E0000000
>  %979 = fmul float %976, 0x3FE2C8B440000000
>  %980 = fadd float %979, %978
>  %981 = fmul float %977, 0x3FBD2F1AA0000000
>  %982 = fadd float %980, %981
>  br label %ENDIF232
>
>ENDIF232:                                         ; preds = %ENDIF229, %IF233
>  %temp16.17 = phi float [ %982, %IF233 ], [ %temp16.15, %ENDIF229 ]
>  %983 = bitcast float %902 to i32
>  %984 = xor i32 %983, -1
>  %985 = bitcast i32 %984 to float
>  %986 = bitcast float %985 to i32
>  %987 = icmp ne i32 %986, 0
>  br i1 %987, label %IF236, label %ENDIF235
>
>IF236:                                            ; preds = %ENDIF232
>  %988 = fmul float %.351, 5.000000e-01
>  %989 = fsub float -0.000000e+00, %988
>  %990 = fadd float %temp8.16, %989
>  br label %ENDIF235
>
>ENDIF235:                                         ; preds = %ENDIF232, %IF236
>  %temp8.17 = phi float [ %990, %IF236 ], [ %temp8.16, %ENDIF232 ]
>  %991 = bitcast float %908 to i32
>  %992 = xor i32 %991, -1
>  %993 = bitcast i32 %992 to float
>  %994 = bitcast float %993 to i32
>  %995 = icmp ne i32 %994, 0
>  br i1 %995, label %IF239, label %ENDIF238
>
>IF239:                                            ; preds = %ENDIF235
>  %996 = fmul float %.351, 5.000000e-01
>  %997 = fsub float -0.000000e+00, %996
>  %998 = fadd float %temp16.17, %997
>  br label %ENDIF238
>
>ENDIF238:                                         ; preds = %ENDIF235, %IF239
>  %temp16.18 = phi float [ %998, %IF239 ], [ %temp16.17, %ENDIF235 ]
>  %999 = call float @fabs(float %temp8.17)
>  %1000 = fcmp uge float %999, %379
>  %1001 = select i1 %1000, float 1.000000e+00, float 0.000000e+00
>  %1002 = fsub float -0.000000e+00, %1001
>  %1003 = fptosi float %1002 to i32
>  %1004 = bitcast i32 %1003 to float
>  %1005 = call float @fabs(float %temp16.18)
>  %1006 = fcmp uge float %1005, %379
>  %1007 = select i1 %1006, float 1.000000e+00, float 0.000000e+00
>  %1008 = fsub float -0.000000e+00, %1007
>  %1009 = fptosi float %1008 to i32
>  %1010 = bitcast i32 %1009 to float
>  %1011 = bitcast float %1004 to i32
>  %1012 = xor i32 %1011, -1
>  %1013 = bitcast i32 %1012 to float
>  %1014 = bitcast float %1013 to i32
>  %1015 = icmp ne i32 %1014, 0
>  br i1 %1015, label %IF242, label %ENDIF241
>
>IF242:                                            ; preds = %ENDIF238
>  %1016 = fmul float %.350, 2.000000e+00
>  %1017 = fmul float %temp44.0, 2.000000e+00
>  %1018 = fsub float -0.000000e+00, %1016
>  %1019 = fadd float %temp48.10, %1018
>  %1020 = fsub float -0.000000e+00, %1017
>  %1021 = fadd float %temp49.10, %1020
>  br label %ENDIF241
>
>ENDIF241:                                         ; preds = %ENDIF238, %IF242
>  %temp48.12 = phi float [ %1019, %IF242 ], [ %temp48.10, %ENDIF238 ]
>  %temp49.12 = phi float [ %1021, %IF242 ], [ %temp49.10, %ENDIF238 ]
>  %1022 = bitcast float %1004 to i32
>  %1023 = xor i32 %1022, -1
>  %1024 = bitcast i32 %1023 to float
>  %1025 = bitcast float %1010 to i32
>  %1026 = xor i32 %1025, -1
>  %1027 = bitcast i32 %1026 to float
>  %1028 = bitcast float %1024 to i32
>  %1029 = bitcast float %1027 to i32
>  %1030 = or i32 %1028, %1029
>  %1031 = bitcast i32 %1030 to float
>  %1032 = bitcast float %1010 to i32
>  %1033 = xor i32 %1032, -1
>  %1034 = bitcast i32 %1033 to float
>  %1035 = bitcast float %1034 to i32
>  %1036 = icmp ne i32 %1035, 0
>  br i1 %1036, label %IF245, label %ENDIF244
>
>IF245:                                            ; preds = %ENDIF241
>  %1037 = fmul float %.350, 2.000000e+00
>  %1038 = fadd float %1037, %temp32.11
>  %1039 = fmul float %temp44.0, 2.000000e+00
>  %1040 = fadd float %1039, %temp33.11
>  br label %ENDIF244
>
>ENDIF244:                                         ; preds = %ENDIF241, %IF245
>  %temp33.13 = phi float [ %1040, %IF245 ], [ %temp33.11, %ENDIF241 ]
>  %temp32.13 = phi float [ %1038, %IF245 ], [ %temp32.11, %ENDIF241 ]
>  %1041 = bitcast float %1031 to i32
>  %1042 = icmp ne i32 %1041, 0
>  br i1 %1042, label %IF248, label %ENDIF121
>
>IF248:                                            ; preds = %ENDIF244
>  %1043 = bitcast float %1004 to i32
>  %1044 = xor i32 %1043, -1
>  %1045 = bitcast i32 %1044 to float
>  %1046 = bitcast float %1045 to i32
>  %1047 = icmp ne i32 %1046, 0
>  br i1 %1047, label %IF251, label %ENDIF250
>
>IF251:                                            ; preds = %IF248
>  %1048 = bitcast float %temp48.12 to i32
>  %1049 = bitcast float %temp49.12 to i32
>  %1050 = bitcast float 0.000000e+00 to i32
>  %1051 = insertelement <4 x i32> undef, i32 %1048, i32 0
>  %1052 = insertelement <4 x i32> %1051, i32 %1049, i32 1
>  %1053 = insertelement <4 x i32> %1052, i32 %1050, i32 2
>  %1054 = insertelement <4 x i32> %1053, i32 undef, i32 3
>  %1055 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1054, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1056 = extractelement <4 x float> %1055, i32 0
>  %1057 = extractelement <4 x float> %1055, i32 1
>  %1058 = extractelement <4 x float> %1055, i32 2
>  %1059 = fmul float %1056, 0x3FD322D0E0000000
>  %1060 = fmul float %1057, 0x3FE2C8B440000000
>  %1061 = fadd float %1060, %1059
>  %1062 = fmul float %1058, 0x3FBD2F1AA0000000
>  %1063 = fadd float %1061, %1062
>  br label %ENDIF250
>
>ENDIF250:                                         ; preds = %IF248, %IF251
>  %temp8.19 = phi float [ %1063, %IF251 ], [ %temp8.17, %IF248 ]
>  %1064 = bitcast float %1010 to i32
>  %1065 = xor i32 %1064, -1
>  %1066 = bitcast i32 %1065 to float
>  %1067 = bitcast float %1066 to i32
>  %1068 = icmp ne i32 %1067, 0
>  br i1 %1068, label %IF254, label %ENDIF253
>
>IF254:                                            ; preds = %ENDIF250
>  %1069 = bitcast float %temp32.13 to i32
>  %1070 = bitcast float %temp33.13 to i32
>  %1071 = bitcast float 0.000000e+00 to i32
>  %1072 = insertelement <4 x i32> undef, i32 %1069, i32 0
>  %1073 = insertelement <4 x i32> %1072, i32 %1070, i32 1
>  %1074 = insertelement <4 x i32> %1073, i32 %1071, i32 2
>  %1075 = insertelement <4 x i32> %1074, i32 undef, i32 3
>  %1076 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1075, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1077 = extractelement <4 x float> %1076, i32 0
>  %1078 = extractelement <4 x float> %1076, i32 1
>  %1079 = extractelement <4 x float> %1076, i32 2
>  %1080 = fmul float %1077, 0x3FD322D0E0000000
>  %1081 = fmul float %1078, 0x3FE2C8B440000000
>  %1082 = fadd float %1081, %1080
>  %1083 = fmul float %1079, 0x3FBD2F1AA0000000
>  %1084 = fadd float %1082, %1083
>  br label %ENDIF253
>
>ENDIF253:                                         ; preds = %ENDIF250, %IF254
>  %temp16.20 = phi float [ %1084, %IF254 ], [ %temp16.18, %ENDIF250 ]
>  %1085 = bitcast float %1004 to i32
>  %1086 = xor i32 %1085, -1
>  %1087 = bitcast i32 %1086 to float
>  %1088 = bitcast float %1087 to i32
>  %1089 = icmp ne i32 %1088, 0
>  br i1 %1089, label %IF257, label %ENDIF256
>
>IF257:                                            ; preds = %ENDIF253
>  %1090 = fmul float %.351, 5.000000e-01
>  %1091 = fsub float -0.000000e+00, %1090
>  %1092 = fadd float %temp8.19, %1091
>  br label %ENDIF256
>
>ENDIF256:                                         ; preds = %ENDIF253, %IF257
>  %temp8.20 = phi float [ %1092, %IF257 ], [ %temp8.19, %ENDIF253 ]
>  %1093 = bitcast float %1010 to i32
>  %1094 = xor i32 %1093, -1
>  %1095 = bitcast i32 %1094 to float
>  %1096 = bitcast float %1095 to i32
>  %1097 = icmp ne i32 %1096, 0
>  br i1 %1097, label %IF260, label %ENDIF259
>
>IF260:                                            ; preds = %ENDIF256
>  %1098 = fmul float %.351, 5.000000e-01
>  %1099 = fsub float -0.000000e+00, %1098
>  %1100 = fadd float %temp16.20, %1099
>  br label %ENDIF259
>
>ENDIF259:                                         ; preds = %ENDIF256, %IF260
>  %temp16.21 = phi float [ %1100, %IF260 ], [ %temp16.20, %ENDIF256 ]
>  %1101 = call float @fabs(float %temp8.20)
>  %1102 = fcmp uge float %1101, %379
>  %1103 = select i1 %1102, float 1.000000e+00, float 0.000000e+00
>  %1104 = fsub float -0.000000e+00, %1103
>  %1105 = fptosi float %1104 to i32
>  %1106 = bitcast i32 %1105 to float
>  %1107 = call float @fabs(float %temp16.21)
>  %1108 = fcmp uge float %1107, %379
>  %1109 = select i1 %1108, float 1.000000e+00, float 0.000000e+00
>  %1110 = fsub float -0.000000e+00, %1109
>  %1111 = fptosi float %1110 to i32
>  %1112 = bitcast i32 %1111 to float
>  %1113 = bitcast float %1106 to i32
>  %1114 = xor i32 %1113, -1
>  %1115 = bitcast i32 %1114 to float
>  %1116 = bitcast float %1115 to i32
>  %1117 = icmp ne i32 %1116, 0
>  br i1 %1117, label %IF263, label %ENDIF262
>
>IF263:                                            ; preds = %ENDIF259
>  %1118 = fmul float %.350, 2.000000e+00
>  %1119 = fmul float %temp44.0, 2.000000e+00
>  %1120 = fsub float -0.000000e+00, %1118
>  %1121 = fadd float %temp48.12, %1120
>  %1122 = fsub float -0.000000e+00, %1119
>  %1123 = fadd float %temp49.12, %1122
>  br label %ENDIF262
>
>ENDIF262:                                         ; preds = %ENDIF259, %IF263
>  %temp48.14 = phi float [ %1121, %IF263 ], [ %temp48.12, %ENDIF259 ]
>  %temp49.14 = phi float [ %1123, %IF263 ], [ %temp49.12, %ENDIF259 ]
>  %1124 = bitcast float %1106 to i32
>  %1125 = xor i32 %1124, -1
>  %1126 = bitcast i32 %1125 to float
>  %1127 = bitcast float %1112 to i32
>  %1128 = xor i32 %1127, -1
>  %1129 = bitcast i32 %1128 to float
>  %1130 = bitcast float %1126 to i32
>  %1131 = bitcast float %1129 to i32
>  %1132 = or i32 %1130, %1131
>  %1133 = bitcast i32 %1132 to float
>  %1134 = bitcast float %1112 to i32
>  %1135 = xor i32 %1134, -1
>  %1136 = bitcast i32 %1135 to float
>  %1137 = bitcast float %1136 to i32
>  %1138 = icmp ne i32 %1137, 0
>  br i1 %1138, label %IF266, label %ENDIF265
>
>IF266:                                            ; preds = %ENDIF262
>  %1139 = fmul float %.350, 2.000000e+00
>  %1140 = fadd float %1139, %temp32.13
>  %1141 = fmul float %temp44.0, 2.000000e+00
>  %1142 = fadd float %1141, %temp33.13
>  br label %ENDIF265
>
>ENDIF265:                                         ; preds = %ENDIF262, %IF266
>  %temp33.15 = phi float [ %1142, %IF266 ], [ %temp33.13, %ENDIF262 ]
>  %temp32.15 = phi float [ %1140, %IF266 ], [ %temp32.13, %ENDIF262 ]
>  %1143 = bitcast float %1133 to i32
>  %1144 = icmp ne i32 %1143, 0
>  br i1 %1144, label %IF269, label %ENDIF121
>
>IF269:                                            ; preds = %ENDIF265
>  %1145 = bitcast float %1106 to i32
>  %1146 = xor i32 %1145, -1
>  %1147 = bitcast i32 %1146 to float
>  %1148 = bitcast float %1147 to i32
>  %1149 = icmp ne i32 %1148, 0
>  br i1 %1149, label %IF272, label %ENDIF271
>
>IF272:                                            ; preds = %IF269
>  %1150 = bitcast float %temp48.14 to i32
>  %1151 = bitcast float %temp49.14 to i32
>  %1152 = bitcast float 0.000000e+00 to i32
>  %1153 = insertelement <4 x i32> undef, i32 %1150, i32 0
>  %1154 = insertelement <4 x i32> %1153, i32 %1151, i32 1
>  %1155 = insertelement <4 x i32> %1154, i32 %1152, i32 2
>  %1156 = insertelement <4 x i32> %1155, i32 undef, i32 3
>  %1157 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1156, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1158 = extractelement <4 x float> %1157, i32 0
>  %1159 = extractelement <4 x float> %1157, i32 1
>  %1160 = extractelement <4 x float> %1157, i32 2
>  %1161 = fmul float %1158, 0x3FD322D0E0000000
>  %1162 = fmul float %1159, 0x3FE2C8B440000000
>  %1163 = fadd float %1162, %1161
>  %1164 = fmul float %1160, 0x3FBD2F1AA0000000
>  %1165 = fadd float %1163, %1164
>  br label %ENDIF271
>
>ENDIF271:                                         ; preds = %IF269, %IF272
>  %temp8.22 = phi float [ %1165, %IF272 ], [ %temp8.20, %IF269 ]
>  %1166 = bitcast float %1112 to i32
>  %1167 = xor i32 %1166, -1
>  %1168 = bitcast i32 %1167 to float
>  %1169 = bitcast float %1168 to i32
>  %1170 = icmp ne i32 %1169, 0
>  br i1 %1170, label %IF275, label %ENDIF274
>
>IF275:                                            ; preds = %ENDIF271
>  %1171 = bitcast float %temp32.15 to i32
>  %1172 = bitcast float %temp33.15 to i32
>  %1173 = bitcast float 0.000000e+00 to i32
>  %1174 = insertelement <4 x i32> undef, i32 %1171, i32 0
>  %1175 = insertelement <4 x i32> %1174, i32 %1172, i32 1
>  %1176 = insertelement <4 x i32> %1175, i32 %1173, i32 2
>  %1177 = insertelement <4 x i32> %1176, i32 undef, i32 3
>  %1178 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1177, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1179 = extractelement <4 x float> %1178, i32 0
>  %1180 = extractelement <4 x float> %1178, i32 1
>  %1181 = extractelement <4 x float> %1178, i32 2
>  %1182 = fmul float %1179, 0x3FD322D0E0000000
>  %1183 = fmul float %1180, 0x3FE2C8B440000000
>  %1184 = fadd float %1183, %1182
>  %1185 = fmul float %1181, 0x3FBD2F1AA0000000
>  %1186 = fadd float %1184, %1185
>  br label %ENDIF274
>
>ENDIF274:                                         ; preds = %ENDIF271, %IF275
>  %temp16.23 = phi float [ %1186, %IF275 ], [ %temp16.21, %ENDIF271 ]
>  %1187 = bitcast float %1106 to i32
>  %1188 = xor i32 %1187, -1
>  %1189 = bitcast i32 %1188 to float
>  %1190 = bitcast float %1189 to i32
>  %1191 = icmp ne i32 %1190, 0
>  br i1 %1191, label %IF278, label %ENDIF277
>
>IF278:                                            ; preds = %ENDIF274
>  %1192 = fmul float %.351, 5.000000e-01
>  %1193 = fsub float -0.000000e+00, %1192
>  %1194 = fadd float %temp8.22, %1193
>  br label %ENDIF277
>
>ENDIF277:                                         ; preds = %ENDIF274, %IF278
>  %temp8.23 = phi float [ %1194, %IF278 ], [ %temp8.22, %ENDIF274 ]
>  %1195 = bitcast float %1112 to i32
>  %1196 = xor i32 %1195, -1
>  %1197 = bitcast i32 %1196 to float
>  %1198 = bitcast float %1197 to i32
>  %1199 = icmp ne i32 %1198, 0
>  br i1 %1199, label %IF281, label %ENDIF280
>
>IF281:                                            ; preds = %ENDIF277
>  %1200 = fmul float %.351, 5.000000e-01
>  %1201 = fsub float -0.000000e+00, %1200
>  %1202 = fadd float %temp16.23, %1201
>  br label %ENDIF280
>
>ENDIF280:                                         ; preds = %ENDIF277, %IF281
>  %temp16.24 = phi float [ %1202, %IF281 ], [ %temp16.23, %ENDIF277 ]
>  %1203 = call float @fabs(float %temp8.23)
>  %1204 = fcmp uge float %1203, %379
>  %1205 = select i1 %1204, float 1.000000e+00, float 0.000000e+00
>  %1206 = fsub float -0.000000e+00, %1205
>  %1207 = fptosi float %1206 to i32
>  %1208 = bitcast i32 %1207 to float
>  %1209 = call float @fabs(float %temp16.24)
>  %1210 = fcmp uge float %1209, %379
>  %1211 = select i1 %1210, float 1.000000e+00, float 0.000000e+00
>  %1212 = fsub float -0.000000e+00, %1211
>  %1213 = fptosi float %1212 to i32
>  %1214 = bitcast i32 %1213 to float
>  %1215 = bitcast float %1208 to i32
>  %1216 = xor i32 %1215, -1
>  %1217 = bitcast i32 %1216 to float
>  %1218 = bitcast float %1217 to i32
>  %1219 = icmp ne i32 %1218, 0
>  br i1 %1219, label %IF284, label %ENDIF283
>
>IF284:                                            ; preds = %ENDIF280
>  %1220 = fmul float %.350, 2.000000e+00
>  %1221 = fmul float %temp44.0, 2.000000e+00
>  %1222 = fsub float -0.000000e+00, %1220
>  %1223 = fadd float %temp48.14, %1222
>  %1224 = fsub float -0.000000e+00, %1221
>  %1225 = fadd float %temp49.14, %1224
>  br label %ENDIF283
>
>ENDIF283:                                         ; preds = %ENDIF280, %IF284
>  %temp48.16 = phi float [ %1223, %IF284 ], [ %temp48.14, %ENDIF280 ]
>  %temp49.16 = phi float [ %1225, %IF284 ], [ %temp49.14, %ENDIF280 ]
>  %1226 = bitcast float %1208 to i32
>  %1227 = xor i32 %1226, -1
>  %1228 = bitcast i32 %1227 to float
>  %1229 = bitcast float %1214 to i32
>  %1230 = xor i32 %1229, -1
>  %1231 = bitcast i32 %1230 to float
>  %1232 = bitcast float %1228 to i32
>  %1233 = bitcast float %1231 to i32
>  %1234 = or i32 %1232, %1233
>  %1235 = bitcast i32 %1234 to float
>  %1236 = bitcast float %1214 to i32
>  %1237 = xor i32 %1236, -1
>  %1238 = bitcast i32 %1237 to float
>  %1239 = bitcast float %1238 to i32
>  %1240 = icmp ne i32 %1239, 0
>  br i1 %1240, label %IF287, label %ENDIF286
>
>IF287:                                            ; preds = %ENDIF283
>  %1241 = fmul float %.350, 2.000000e+00
>  %1242 = fadd float %1241, %temp32.15
>  %1243 = fmul float %temp44.0, 2.000000e+00
>  %1244 = fadd float %1243, %temp33.15
>  br label %ENDIF286
>
>ENDIF286:                                         ; preds = %ENDIF283, %IF287
>  %temp33.17 = phi float [ %1244, %IF287 ], [ %temp33.15, %ENDIF283 ]
>  %temp32.17 = phi float [ %1242, %IF287 ], [ %temp32.15, %ENDIF283 ]
>  %1245 = bitcast float %1235 to i32
>  %1246 = icmp ne i32 %1245, 0
>  br i1 %1246, label %IF290, label %ENDIF121
>
>IF290:                                            ; preds = %ENDIF286
>  %1247 = bitcast float %1208 to i32
>  %1248 = xor i32 %1247, -1
>  %1249 = bitcast i32 %1248 to float
>  %1250 = bitcast float %1249 to i32
>  %1251 = icmp ne i32 %1250, 0
>  br i1 %1251, label %IF293, label %ENDIF292
>
>IF293:                                            ; preds = %IF290
>  %1252 = bitcast float %temp48.16 to i32
>  %1253 = bitcast float %temp49.16 to i32
>  %1254 = bitcast float 0.000000e+00 to i32
>  %1255 = insertelement <4 x i32> undef, i32 %1252, i32 0
>  %1256 = insertelement <4 x i32> %1255, i32 %1253, i32 1
>  %1257 = insertelement <4 x i32> %1256, i32 %1254, i32 2
>  %1258 = insertelement <4 x i32> %1257, i32 undef, i32 3
>  %1259 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1258, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1260 = extractelement <4 x float> %1259, i32 0
>  %1261 = extractelement <4 x float> %1259, i32 1
>  %1262 = extractelement <4 x float> %1259, i32 2
>  %1263 = fmul float %1260, 0x3FD322D0E0000000
>  %1264 = fmul float %1261, 0x3FE2C8B440000000
>  %1265 = fadd float %1264, %1263
>  %1266 = fmul float %1262, 0x3FBD2F1AA0000000
>  %1267 = fadd float %1265, %1266
>  br label %ENDIF292
>
>ENDIF292:                                         ; preds = %IF290, %IF293
>  %temp8.25 = phi float [ %1267, %IF293 ], [ %temp8.23, %IF290 ]
>  %1268 = bitcast float %1214 to i32
>  %1269 = xor i32 %1268, -1
>  %1270 = bitcast i32 %1269 to float
>  %1271 = bitcast float %1270 to i32
>  %1272 = icmp ne i32 %1271, 0
>  br i1 %1272, label %IF296, label %ENDIF295
>
>IF296:                                            ; preds = %ENDIF292
>  %1273 = bitcast float %temp32.17 to i32
>  %1274 = bitcast float %temp33.17 to i32
>  %1275 = bitcast float 0.000000e+00 to i32
>  %1276 = insertelement <4 x i32> undef, i32 %1273, i32 0
>  %1277 = insertelement <4 x i32> %1276, i32 %1274, i32 1
>  %1278 = insertelement <4 x i32> %1277, i32 %1275, i32 2
>  %1279 = insertelement <4 x i32> %1278, i32 undef, i32 3
>  %1280 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1279, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1281 = extractelement <4 x float> %1280, i32 0
>  %1282 = extractelement <4 x float> %1280, i32 1
>  %1283 = extractelement <4 x float> %1280, i32 2
>  %1284 = fmul float %1281, 0x3FD322D0E0000000
>  %1285 = fmul float %1282, 0x3FE2C8B440000000
>  %1286 = fadd float %1285, %1284
>  %1287 = fmul float %1283, 0x3FBD2F1AA0000000
>  %1288 = fadd float %1286, %1287
>  br label %ENDIF295
>
>ENDIF295:                                         ; preds = %ENDIF292, %IF296
>  %temp16.26 = phi float [ %1288, %IF296 ], [ %temp16.24, %ENDIF292 ]
>  %1289 = bitcast float %1208 to i32
>  %1290 = xor i32 %1289, -1
>  %1291 = bitcast i32 %1290 to float
>  %1292 = bitcast float %1291 to i32
>  %1293 = icmp ne i32 %1292, 0
>  br i1 %1293, label %IF299, label %ENDIF298
>
>IF299:                                            ; preds = %ENDIF295
>  %1294 = fmul float %.351, 5.000000e-01
>  %1295 = fsub float -0.000000e+00, %1294
>  %1296 = fadd float %temp8.25, %1295
>  br label %ENDIF298
>
>ENDIF298:                                         ; preds = %ENDIF295, %IF299
>  %temp8.26 = phi float [ %1296, %IF299 ], [ %temp8.25, %ENDIF295 ]
>  %1297 = bitcast float %1214 to i32
>  %1298 = xor i32 %1297, -1
>  %1299 = bitcast i32 %1298 to float
>  %1300 = bitcast float %1299 to i32
>  %1301 = icmp ne i32 %1300, 0
>  br i1 %1301, label %IF302, label %ENDIF301
>
>IF302:                                            ; preds = %ENDIF298
>  %1302 = fmul float %.351, 5.000000e-01
>  %1303 = fsub float -0.000000e+00, %1302
>  %1304 = fadd float %temp16.26, %1303
>  br label %ENDIF301
>
>ENDIF301:                                         ; preds = %ENDIF298, %IF302
>  %temp16.27 = phi float [ %1304, %IF302 ], [ %temp16.26, %ENDIF298 ]
>  %1305 = call float @fabs(float %temp8.26)
>  %1306 = fcmp uge float %1305, %379
>  %1307 = select i1 %1306, float 1.000000e+00, float 0.000000e+00
>  %1308 = fsub float -0.000000e+00, %1307
>  %1309 = fptosi float %1308 to i32
>  %1310 = bitcast i32 %1309 to float
>  %1311 = call float @fabs(float %temp16.27)
>  %1312 = fcmp uge float %1311, %379
>  %1313 = select i1 %1312, float 1.000000e+00, float 0.000000e+00
>  %1314 = fsub float -0.000000e+00, %1313
>  %1315 = fptosi float %1314 to i32
>  %1316 = bitcast i32 %1315 to float
>  %1317 = bitcast float %1310 to i32
>  %1318 = xor i32 %1317, -1
>  %1319 = bitcast i32 %1318 to float
>  %1320 = bitcast float %1319 to i32
>  %1321 = icmp ne i32 %1320, 0
>  br i1 %1321, label %IF305, label %ENDIF304
>
>IF305:                                            ; preds = %ENDIF301
>  %1322 = fmul float %.350, 4.000000e+00
>  %1323 = fmul float %temp44.0, 4.000000e+00
>  %1324 = fsub float -0.000000e+00, %1322
>  %1325 = fadd float %temp48.16, %1324
>  %1326 = fsub float -0.000000e+00, %1323
>  %1327 = fadd float %temp49.16, %1326
>  br label %ENDIF304
>
>ENDIF304:                                         ; preds = %ENDIF301, %IF305
>  %temp48.18 = phi float [ %1325, %IF305 ], [ %temp48.16, %ENDIF301 ]
>  %temp49.18 = phi float [ %1327, %IF305 ], [ %temp49.16, %ENDIF301 ]
>  %1328 = bitcast float %1310 to i32
>  %1329 = xor i32 %1328, -1
>  %1330 = bitcast i32 %1329 to float
>  %1331 = bitcast float %1316 to i32
>  %1332 = xor i32 %1331, -1
>  %1333 = bitcast i32 %1332 to float
>  %1334 = bitcast float %1330 to i32
>  %1335 = bitcast float %1333 to i32
>  %1336 = or i32 %1334, %1335
>  %1337 = bitcast i32 %1336 to float
>  %1338 = bitcast float %1316 to i32
>  %1339 = xor i32 %1338, -1
>  %1340 = bitcast i32 %1339 to float
>  %1341 = bitcast float %1340 to i32
>  %1342 = icmp ne i32 %1341, 0
>  br i1 %1342, label %IF308, label %ENDIF307
>
>IF308:                                            ; preds = %ENDIF304
>  %1343 = fmul float %.350, 4.000000e+00
>  %1344 = fadd float %1343, %temp32.17
>  %1345 = fmul float %temp44.0, 4.000000e+00
>  %1346 = fadd float %1345, %temp33.17
>  br label %ENDIF307
>
>ENDIF307:                                         ; preds = %ENDIF304, %IF308
>  %temp33.19 = phi float [ %1346, %IF308 ], [ %temp33.17, %ENDIF304 ]
>  %temp32.19 = phi float [ %1344, %IF308 ], [ %temp32.17, %ENDIF304 ]
>  %1347 = bitcast float %1337 to i32
>  %1348 = icmp ne i32 %1347, 0
>  br i1 %1348, label %IF311, label %ENDIF121
>
>IF311:                                            ; preds = %ENDIF307
>  %1349 = bitcast float %1310 to i32
>  %1350 = xor i32 %1349, -1
>  %1351 = bitcast i32 %1350 to float
>  %1352 = bitcast float %1351 to i32
>  %1353 = icmp ne i32 %1352, 0
>  br i1 %1353, label %IF314, label %ENDIF313
>
>IF314:                                            ; preds = %IF311
>  %1354 = bitcast float %temp48.18 to i32
>  %1355 = bitcast float %temp49.18 to i32
>  %1356 = bitcast float 0.000000e+00 to i32
>  %1357 = insertelement <4 x i32> undef, i32 %1354, i32 0
>  %1358 = insertelement <4 x i32> %1357, i32 %1355, i32 1
>  %1359 = insertelement <4 x i32> %1358, i32 %1356, i32 2
>  %1360 = insertelement <4 x i32> %1359, i32 undef, i32 3
>  %1361 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1360, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1362 = extractelement <4 x float> %1361, i32 0
>  %1363 = extractelement <4 x float> %1361, i32 1
>  %1364 = extractelement <4 x float> %1361, i32 2
>  %1365 = fmul float %1362, 0x3FD322D0E0000000
>  %1366 = fmul float %1363, 0x3FE2C8B440000000
>  %1367 = fadd float %1366, %1365
>  %1368 = fmul float %1364, 0x3FBD2F1AA0000000
>  %1369 = fadd float %1367, %1368
>  br label %ENDIF313
>
>ENDIF313:                                         ; preds = %IF311, %IF314
>  %temp8.28 = phi float [ %1369, %IF314 ], [ %temp8.26, %IF311 ]
>  %1370 = bitcast float %1316 to i32
>  %1371 = xor i32 %1370, -1
>  %1372 = bitcast i32 %1371 to float
>  %1373 = bitcast float %1372 to i32
>  %1374 = icmp ne i32 %1373, 0
>  br i1 %1374, label %IF317, label %ENDIF316
>
>IF317:                                            ; preds = %ENDIF313
>  %1375 = bitcast float %temp32.19 to i32
>  %1376 = bitcast float %temp33.19 to i32
>  %1377 = bitcast float 0.000000e+00 to i32
>  %1378 = insertelement <4 x i32> undef, i32 %1375, i32 0
>  %1379 = insertelement <4 x i32> %1378, i32 %1376, i32 1
>  %1380 = insertelement <4 x i32> %1379, i32 %1377, i32 2
>  %1381 = insertelement <4 x i32> %1380, i32 undef, i32 3
>  %1382 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1381, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1383 = extractelement <4 x float> %1382, i32 0
>  %1384 = extractelement <4 x float> %1382, i32 1
>  %1385 = extractelement <4 x float> %1382, i32 2
>  %1386 = fmul float %1383, 0x3FD322D0E0000000
>  %1387 = fmul float %1384, 0x3FE2C8B440000000
>  %1388 = fadd float %1387, %1386
>  %1389 = fmul float %1385, 0x3FBD2F1AA0000000
>  %1390 = fadd float %1388, %1389
>  br label %ENDIF316
>
>ENDIF316:                                         ; preds = %ENDIF313, %IF317
>  %temp16.29 = phi float [ %1390, %IF317 ], [ %temp16.27, %ENDIF313 ]
>  %1391 = bitcast float %1310 to i32
>  %1392 = xor i32 %1391, -1
>  %1393 = bitcast i32 %1392 to float
>  %1394 = bitcast float %1393 to i32
>  %1395 = icmp ne i32 %1394, 0
>  br i1 %1395, label %IF320, label %ENDIF319
>
>IF320:                                            ; preds = %ENDIF316
>  %1396 = fmul float %.351, 5.000000e-01
>  %1397 = fsub float -0.000000e+00, %1396
>  %1398 = fadd float %temp8.28, %1397
>  br label %ENDIF319
>
>ENDIF319:                                         ; preds = %ENDIF316, %IF320
>  %temp8.29 = phi float [ %1398, %IF320 ], [ %temp8.28, %ENDIF316 ]
>  %1399 = bitcast float %1316 to i32
>  %1400 = xor i32 %1399, -1
>  %1401 = bitcast i32 %1400 to float
>  %1402 = bitcast float %1401 to i32
>  %1403 = icmp ne i32 %1402, 0
>  br i1 %1403, label %IF323, label %ENDIF322
>
>IF323:                                            ; preds = %ENDIF319
>  %1404 = fmul float %.351, 5.000000e-01
>  %1405 = fsub float -0.000000e+00, %1404
>  %1406 = fadd float %temp16.29, %1405
>  br label %ENDIF322
>
>ENDIF322:                                         ; preds = %ENDIF319, %IF323
>  %temp16.30 = phi float [ %1406, %IF323 ], [ %temp16.29, %ENDIF319 ]
>  %1407 = call float @fabs(float %temp8.29)
>  %1408 = fcmp uge float %1407, %379
>  %1409 = select i1 %1408, float 1.000000e+00, float 0.000000e+00
>  %1410 = fsub float -0.000000e+00, %1409
>  %1411 = fptosi float %1410 to i32
>  %1412 = bitcast i32 %1411 to float
>  %1413 = call float @fabs(float %temp16.30)
>  %1414 = fcmp uge float %1413, %379
>  %1415 = select i1 %1414, float 1.000000e+00, float 0.000000e+00
>  %1416 = fsub float -0.000000e+00, %1415
>  %1417 = fptosi float %1416 to i32
>  %1418 = bitcast i32 %1417 to float
>  %1419 = bitcast float %1412 to i32
>  %1420 = xor i32 %1419, -1
>  %1421 = bitcast i32 %1420 to float
>  %1422 = bitcast float %1421 to i32
>  %1423 = icmp ne i32 %1422, 0
>  br i1 %1423, label %IF326, label %ENDIF325
>
>IF326:                                            ; preds = %ENDIF322
>  %1424 = fmul float %.350, 8.000000e+00
>  %1425 = fmul float %temp44.0, 8.000000e+00
>  %1426 = fsub float -0.000000e+00, %1424
>  %1427 = fadd float %temp48.18, %1426
>  %1428 = fsub float -0.000000e+00, %1425
>  %1429 = fadd float %temp49.18, %1428
>  br label %ENDIF325
>
>ENDIF325:                                         ; preds = %ENDIF322, %IF326
>  %temp48.20 = phi float [ %1427, %IF326 ], [ %temp48.18, %ENDIF322 ]
>  %temp49.20 = phi float [ %1429, %IF326 ], [ %temp49.18, %ENDIF322 ]
>  %1430 = bitcast float %1418 to i32
>  %1431 = xor i32 %1430, -1
>  %1432 = bitcast i32 %1431 to float
>  %1433 = bitcast float %1432 to i32
>  %1434 = icmp ne i32 %1433, 0
>  br i1 %1434, label %IF329, label %ENDIF121
>
>IF329:                                            ; preds = %ENDIF325
>  %1435 = fmul float %.350, 8.000000e+00
>  %1436 = fadd float %1435, %temp32.19
>  %1437 = fmul float %temp44.0, 8.000000e+00
>  %1438 = fadd float %1437, %temp33.19
>  br label %ENDIF121
>
>IF332:                                            ; preds = %ENDIF121
>  %1439 = fsub float -0.000000e+00, %temp49.1
>  %1440 = fadd float %29, %1439
>  br label %ENDIF331
>
>ENDIF331:                                         ; preds = %ENDIF121, %IF332
>  %temp24.0 = phi float [ %1440, %IF332 ], [ %440, %ENDIF121 ]
>  %1441 = bitcast float %268 to i32
>  %1442 = xor i32 %1441, -1
>  %1443 = bitcast i32 %1442 to float
>  %1444 = bitcast float %1443 to i32
>  %1445 = icmp ne i32 %1444, 0
>  br i1 %1445, label %IF335, label %ENDIF334
>
>IF335:                                            ; preds = %ENDIF331
>  %1446 = fsub float -0.000000e+00, %29
>  %1447 = fadd float %temp33.2, %1446
>  br label %ENDIF334
>
>ENDIF334:                                         ; preds = %ENDIF331, %IF335
>  %temp28.2 = phi float [ %1447, %IF335 ], [ %442, %ENDIF331 ]
>  %1448 = fcmp ult float %temp8.0, 0.000000e+00
>  %1449 = select i1 %1448, float 1.000000e+00, float 0.000000e+00
>  %1450 = fsub float -0.000000e+00, %1449
>  %1451 = fptosi float %1450 to i32
>  %1452 = bitcast i32 %1451 to float
>  %1453 = bitcast float %1452 to i32
>  %1454 = bitcast float %388 to i32
>  %1455 = icmp ne i32 %1453, %1454
>  %1456 = sext i1 %1455 to i32
>  %1457 = bitcast i32 %1456 to float
>  %1458 = fcmp ult float %temp16.1, 0.000000e+00
>  %1459 = select i1 %1458, float 1.000000e+00, float 0.000000e+00
>  %1460 = fsub float -0.000000e+00, %1459
>  %1461 = fptosi float %1460 to i32
>  %1462 = bitcast i32 %1461 to float
>  %1463 = bitcast float %1462 to i32
>  %1464 = bitcast float %388 to i32
>  %1465 = icmp ne i32 %1463, %1464
>  %1466 = sext i1 %1465 to i32
>  %1467 = bitcast i32 %1466 to float
>  %1468 = fadd float %temp28.2, %temp24.0
>  %1469 = fdiv float 1.000000e+00, %1468
>  %1470 = fcmp uge float %temp24.0, %temp28.2
>  %1471 = select i1 %1470, float %temp28.2, float %temp24.0
>  %1472 = fcmp ult float %temp24.0, %temp28.2
>  %1473 = select i1 %1472, float 1.000000e+00, float 0.000000e+00
>  %1474 = fsub float -0.000000e+00, %1473
>  %1475 = fptosi float %1474 to i32
>  %1476 = bitcast i32 %1475 to float
>  %1477 = bitcast float %1476 to i32
>  %1478 = icmp ne i32 %1477, 0
>  %.352 = select i1 %1478, float %1457, float %1467
>  %1479 = fsub float -0.000000e+00, %1469
>  %1480 = fmul float %1471, %1479
>  %1481 = fadd float %1480, 5.000000e-01
>  %1482 = fmul float %380, %380
>  %1483 = fmul float %1482, 2.500000e-01
>  %1484 = bitcast float %.352 to i32
>  %1485 = icmp ne i32 %1484, 0
>  %temp8.31 = select i1 %1485, float %1481, float 0.000000e+00
>  %1486 = fcmp uge float %temp8.31, %1483
>  %1487 = select i1 %1486, float %temp8.31, float %1483
>  %1488 = bitcast float %268 to i32
>  %1489 = xor i32 %1488, -1
>  %1490 = bitcast i32 %1489 to float
>  %1491 = bitcast float %1490 to i32
>  %1492 = icmp ne i32 %1491, 0
>  br i1 %1492, label %IF344, label %ENDIF343
>
>IF344:                                            ; preds = %ENDIF334
>  %1493 = fmul float %1487, %temp72.1
>  %1494 = fadd float %1493, %28
>  br label %ENDIF343
>
>ENDIF343:                                         ; preds = %ENDIF334, %IF344
>  %temp.0 = phi float [ %1494, %IF344 ], [ %28, %ENDIF334 ]
>  %1495 = bitcast float %268 to i32
>  %1496 = icmp ne i32 %1495, 0
>  br i1 %1496, label %IF347, label %ENDIF346
>
>IF347:                                            ; preds = %ENDIF343
>  %1497 = fmul float %1487, %temp72.1
>  %1498 = fadd float %1497, %29
>  br label %ENDIF346
>
>ENDIF346:                                         ; preds = %ENDIF343, %IF347
>  %temp1.0 = phi float [ %1498, %IF347 ], [ %29, %ENDIF343 ]
>  %1499 = bitcast float %temp.0 to i32
>  %1500 = bitcast float %temp1.0 to i32
>  %1501 = bitcast float 0.000000e+00 to i32
>  %1502 = insertelement <4 x i32> undef, i32 %1499, i32 0
>  %1503 = insertelement <4 x i32> %1502, i32 %1500, i32 1
>  %1504 = insertelement <4 x i32> %1503, i32 %1501, i32 2
>  %1505 = insertelement <4 x i32> %1504, i32 undef, i32 3
>  %1506 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1505, <32 x i8> %25, <16 x i8> %27, i32 2)
>  %1507 = extractelement <4 x float> %1506, i32 0
>  %1508 = extractelement <4 x float> %1506, i32 1
>  %1509 = extractelement <4 x float> %1506, i32 2
>  %1510 = extractelement <4 x float> %1506, i32 3
>  br label %ENDIF
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: readonly
>declare float @fabs(float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #3
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readonly }
>attributes #3 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>befe0a7e
>befc0306
>c8080100
>c8090101
>c80c0000
>c80d0001
>7e080302
>7e0a0280
>c0840300
>c0c60500
>bf8c007f
>f0900f00
>00430e03
>bf8c0770
>10021cff
>3e991687
>7e0002ff
>3f1645a2
>d2820001
>0406010f
>7e1202ff
>3de978d5
>d282000b
>04061310
>c0820100
>bf8c007f
>c2010501
>bf8c007f
>06260402
>c2018500
>bf8c007f
>d2820012
>040d0003
>7e280305
>f0900700
>00431612
>bf8c0770
>10022cff
>3e991687
>d2820001
>04060117
>d2820001
>04061318
>d00c0000
>02021701
>d2000008
>0002030b
>d2820017
>04090002
>062c0603
>7e300305
>f0900700
>00431a16
>bf8c0770
>100e34ff
>3e991687
>d2820007
>041e011b
>d2820007
>041e131c
>d00c0004
>02021107
>d200000a
>00120f08
>0a2c0603
>7e300305
>f0900700
>00431616
>bf8c0770
>10102cff
>3e991687
>d2820008
>04220117
>d2820008
>04221318
>0a260402
>7e280305
>f0900700
>00431212
>bf8c0770
>101824ff
>3e991687
>d2820000
>04320113
>d282000d
>04021314
>d00c0004
>0202110d
>d2000000
>00121b08
>d00c0006
>02021500
>d2000000
>001a010a
>101200ff
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>3a322ec1
>3a3430c1
>3832331a
>d10a001e
>02018317
>be9e241e
>899e1e7e
>06342311
>0610111a
>06342512
>060e0f1a
>88fe1e7e
>d10a001e
>02010119
>be9e241e
>899e1e7e
>bf8800d5
>d10a0020
>02018318
>bea02420
>89a0207e
>bf880013
>7e280280
>7e32030d
>7e34030e
>7e36030f
>7e380310
>7e360314
>f0900700
>00431919
>bf8c0770
>102832ff
>3e991687
>7e3802ff
>3f1645a2
>d2820014
>0452391a
>7e3802ff
>3de978d5
>d2820014
>0452391b
>88fe207e
>d10a0020
>02018317
>bea02420
>89a0207e
>bf880013
>7e260280
>7e320307
>7e340308
>7e360309
>7e38030a
>7e360313
>f0900700
>00431919
>bf8c0770
>102632ff
>3e991687
>7e3802ff
>3f1645a2
>d2820013
>044e391a
>7e3802ff
>3de978d5
>d2820013
>044e391b
>88fe207e
>d10a0020
>02018318
>bea02420
>89a0207e
>d2820014
>0451e316
>88fe207e
>d10a0020
>02018317
>bea02420
>89a0207e
>d2820013
>044de316
>88fe207e
>d2060117
>02010113
>d00c0020
>02022b17
>d2000017
>0081e480
>d2060017
>22010117
>7e2e1117
>d2060118
>02010114
>d00c0020
>02022b18
>d2000018
>0081e480
>d2060018
>22010118
>7e301118
>d10a0020
>02018318
>bea02420
>89a0207e
>103222f6
>081c330e
>103224f6
>081a330d
>88fe207e
>3a322ec1
>3a3430c1
>3832331a
>d10a0020
>02018317
>bea02420
>89a0207e
>d2820008
>0421ed11
>d2820007
>041ded12
>88fe207e
>d10a0020
>02010119
>bea02420
>89a0207e
>bf880068
>d10a0022
>02018318
>bea22422
>89a2227e
>bf880013
>7e280280
>7e32030d
>7e34030e
>7e36030f
>7e380310
>7e360314
>f0900700
>00431919
>bf8c0770
>102832ff
>3e991687
>7e3802ff
>3f1645a2
>d2820014
>0452391a
>7e3802ff
>3de978d5
>d2820014
>0452391b
>88fe227e
>d10a0022
>02018317
>bea22422
>89a2227e
>bf880013
>7e260280
>7e320307
>7e340308
>7e360309
>7e38030a
>7e360313
>f0900700
>00431919
>bf8c0770
>102632ff
>3e991687
>7e3802ff
>3f1645a2
>d2820013
>044e391a
>7e3802ff
>3de978d5
>d2820013
>044e391b
>88fe227e
>d10a0022
>02018318
>bea22422
>89a2227e
>d2820014
>0451e316
>88fe227e
>d10a0022
>02018317
>bea22422
>89a2227e
>d2820013
>044de316
>88fe227e
>d2060116
>02010113
>d00c0022
>02022b16
>d2000016
>0089e480
>d2060016
>22010116
>7e2c1116
>d2060117
>02010114
>d00c0022
>02022b17
>d2000015
>0089e480
>d2060015
>22010115
>7e2a1115
>d10a0022
>02018315
>bea22422
>89a2227e
>102a22ff
>41000000
>081c2b0e
>102a24ff
>41000000
>081a2b0d
>88fe227e
>d10a0022
>02018316
>bea22422
>89a2227e
>7e2a02ff
>41000000
>d2820008
>04222b11
>d2820007
>041e2b12
>88fe227e
>88fe207e
>88fe1e7e
>88fe1c7e
>88fe1a7e
>88fe187e
>88fe167e
>88fe147e
>88fe067e
>88fe047e
>88fe027e
>08220707
>08241b03
>d10a0002
>02018300
>be822402
>8982027e
>08241d02
>88fe027e
>d10a0002
>02018300
>be822402
>8982027e
>08220508
>88fe027e
>d0020002
>02022312
>d2000007
>0009e480
>d2060007
>22010107
>7e0e1107
>d10a0002
>02010107
>d0020004
>02010114
>d2000007
>0011e480
>d2060007
>22010107
>7e0e1107
>d10a0004
>02021907
>d2000007
>00118280
>d0020004
>02010113
>d2000008
>0011e480
>d2060008
>22010108
>7e101108
>d10a0004
>02021908
>d2000008
>00118280
>d2000007
>000a0f08
>d10a0002
>02010107
>d00c0004
>02022312
>d2000007
>00122312
>06102511
>7e105508
>100e1107
>080e0ef0
>d2000007
>000a0e80
>1010170b
>101010ff
>3e800000
>d00c0002
>02021107
>d2000007
>000a0f08
>d10a0002
>02018300
>be822402
>8982027e
>d2820003
>040e0307
>88fe027e
>d10a0002
>02010100
>be822402
>8982027e
>d2820002
>040a0307
>88fe027e
>7e080302
>7e0a0280
>f0900f00
>00430e03
>bf8c0770
>88fe007e
>5e002310
>5e021f0e
>f8001c0f
>00010001
>bf810000
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[19]
>DCL CONST[0..1]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].yyxy
>  1: MOV TEMP[0].xy, IN[0].xyxx
>  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
>  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
>  4: MOV TEMP[1].zw, TEMP[2].yyxy
>  5: MOV OUT[1], TEMP[1]
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %9 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
>  %10 = load <16 x i8> addrspace(2)* %9, !tbaa !0
>  %11 = call float @llvm.SI.load.const(<16 x i8> %10, i32 0)
>  %12 = call float @llvm.SI.load.const(<16 x i8> %10, i32 4)
>  %13 = call float @llvm.SI.load.const(<16 x i8> %10, i32 8)
>  %14 = call float @llvm.SI.load.const(<16 x i8> %10, i32 12)
>  %15 = call float @llvm.SI.load.const(<16 x i8> %10, i32 16)
>  %16 = call float @llvm.SI.load.const(<16 x i8> %10, i32 20)
>  %17 = call float @llvm.SI.load.const(<16 x i8> %10, i32 24)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %10, i32 28)
>  %19 = getelementptr <16 x i8> addrspace(2)* %3, i32 0
>  %20 = load <16 x i8> addrspace(2)* %19, !tbaa !0
>  %21 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %5)
>  %22 = extractelement <4 x float> %21, i32 0
>  %23 = extractelement <4 x float> %21, i32 1
>  %24 = extractelement <4 x float> %21, i32 2
>  %25 = extractelement <4 x float> %21, i32 3
>  %26 = fmul float %24, %11
>  %27 = fadd float %26, %13
>  %28 = fmul float %25, %12
>  %29 = fadd float %28, %14
>  %30 = fmul float %24, %15
>  %31 = fadd float %30, %17
>  %32 = fmul float %25, %16
>  %33 = fadd float %32, %18
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %27, float %29, float %31, float %33)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %22, float %23, float 0.000000e+00, float 1.000000e+00)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>SI CODE:
>c0820700
>bf8c007f
>e00c2000
>80010000
>c0800100
>bf8c0070
>c2020105
>c2028107
>bf8c007f
>7e080205
>d2820004
>04100903
>c2020104
>c2028106
>bf8c007f
>7e0a0205
>d2820005
>04140902
>c2020101
>c2028103
>bf8c007f
>7e0c0205
>d2820006
>04180903
>c2020100
>c2000102
>bf8c007f
>7e0e0200
>d2820007
>041c0902
>f800020f
>04050607
>bf8c070f
>7e0802f2
>7e0a0280
>f80008cf
>04050100
>bf810000
>radeon: Failed to allocate virtual address for buffer:
>radeon:    size      : 65536 bytes
>radeon:    alignment : 4096 bytes
>radeon:    domains   : 2
>radeon:    va        : 0x0000000001782000
>radeon: Failed to allocate virtual address for buffer:
>radeon:    size      : 65536 bytes
>radeon:    alignment : 4096 bytes
>radeon:    domains   : 2
>radeon:    va        : 0x0000000001782000
>radeon: The kernel rejected CS, see dmesg for more information.
>Game removed: AppID 41070 "Serious Sam 3: BFE", ProcID 2241 
>/home/behem0th/Steam/steam.sh: line 704:  2026 ÐÐ°Ð²ÐµÑÑÐµÐ½Ð¾      $STEAM_DEBUGGER "$STEAMROOT/$PLATFORM/$STEAMEXE" "$@"

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Attachments on bug 67111: 82721 | 82722 | 82723

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