Attachment 82766 Details for Bug 67030 – fix hdmi port clock limits on haswell

[patch] fix hdmi port clock limits on haswell

0001-drm-i915-fix-hdmi-portclock-limits-on-Haswell.patch (text/plain), 2.85 KB, created by Daniel Vetter on 2013-07-21 11:03:31 UTC

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Creator: Daniel Vetter

Created: 2013-07-21 11:03:31 UTC

Size: 2.85 KB

patch

obsolete

>From 5c1f7c4dee1c3522798f9c8118dc67b6eabe8038 Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Sun, 21 Jul 2013 13:00:06 +0200
>Subject: [PATCH] drm/i915: fix hdmi portclock limits on Haswell
>
>In
>
>commit 325b9d048810f7689ec644595061c0b700e64bce
>Author: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date:   Fri Apr 19 11:24:33 2013 +0200
>
>    drm/i915: fixup 12bpc hdmi dotclock handling
>
>I've errornously claimed that we don't yet support the hdmi 1.4
>dotclocks > 225 MHz on Haswell. But a bug report and a closer look at
>the wrpll table showed that we've supported port clocks up to 300MHz.
>
>With the new code to dynamically compute wrpll limits we should have
>no issues going up to the full 340 MHz range of hdmi 1.4, so let's
>just use that to fix this regression. That'll allow 4k over hdmi for
>free!
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67048
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67030
>Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>---
> drivers/gpu/drm/i915/i915_dma.c   | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>index 5c0663f..ed32c43 100644
>--- a/drivers/gpu/drm/i915/i915_dma.c
>+++ b/drivers/gpu/drm/i915/i915_dma.c
>@@ -1593,8 +1593,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> 	intel_detect_pch(dev);
> 
> 	intel_irq_init(dev);
>-	intel_gt_init(dev);
> 	intel_gt_reset(dev);
>+	intel_gt_init(dev);
> 
> 	/* Try to make sure MCHBAR is enabled before poking at it */
> 	intel_setup_mchbar(dev);
>diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>index 98df2a0..29b6028 100644
>--- a/drivers/gpu/drm/i915/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/intel_hdmi.c
>@@ -806,6 +806,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> 	struct drm_device *dev = encoder->base.dev;
> 	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
> 	int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
>+	int portclock_limit = IS_HASWELL(dev) ? 340000 : 225000;
> 	int desired_bpp;
> 
> 	if (intel_hdmi->color_range_auto) {
>@@ -829,7 +830,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> 	 * outputs. We also need to check that the higher clock still fits
> 	 * within limits.
> 	 */
>-	if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
>+	if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
> 	    && HAS_PCH_SPLIT(dev)) {
> 		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
> 		desired_bpp = 12*3;
>@@ -846,7 +847,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> 		pipe_config->pipe_bpp = desired_bpp;
> 	}
> 
>-	if (adjusted_mode->clock > 225000) {
>+	if (adjusted_mode->clock > portclock_limit) {
> 		DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
> 		return false;
> 	}
>-- 
>1.8.3.2
>

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Attachments on bug 67030: 82577 | 82766 | 82769 | 82796 | 82800 | 82805 | 82809 | 83302 | 83338 | 83387 | 83745 | 83746 | 83761 | 90869 | 92647

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