Attachment 82845 Details for Bug 66808 – possible fix

[patch] possible fix

0001-drm-i915-update-last_vblank-when-disabling-the-power.patch (text/plain), 1.97 KB, created by Paulo Zanoni on 2013-07-22 21:57:14 UTC

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Creator: Paulo Zanoni

Created: 2013-07-22 21:57:14 UTC

Size: 1.97 KB

patch

obsolete

>From 8bc3fdad98d61bccf7919dd479176102940eda64 Mon Sep 17 00:00:00 2001
>From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Date: Mon, 22 Jul 2013 18:30:18 -0300
>Subject: [PATCH] drm/i915: update last_vblank when disabling the power well
>
>The DRM layer keeps track of our vblanks and it assumes our vblank
>counters only go back to zero when they overflows. The problem is that
>when we disable the power well our counters also go to zero, but it
>doesn't mean they did overflow. So on this patch we grab the lock and
>update last_vblank so the DRM layer won't think our counters
>overflowed.
>
>This patch fixes the following intel-gpu-tools test:
>./kms_flip --run-subtest blocking-absolute-wf_vblank
>
>Regression introduced by the following commit:
>
>commit bf51d5e2cda5d36d98e4b46ac7fca9461e512c41
>Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Date:   Wed Jul 3 17:12:13 2013 -0300
>    drm/i915: switch disable_power_well default value to 1
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66808
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>---
> drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 7643b16..d401783 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -5060,8 +5060,21 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
> 		}
> 	} else {
> 		if (enable_requested) {
>+			unsigned long irqflags;
>+			enum pipe p;
>+
> 			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
>+			POSTING_READ(HSW_PWR_WELL_DRIVER);
> 			DRM_DEBUG_KMS("Requesting to disable the power well\n");
>+
>+			/* After this, the registers on the pipes that are part
>+			 * of the power well will become zero, so we have to
>+			 * adjust our counters according to that. */
>+			spin_lock_irqsave(&dev->vbl_lock, irqflags);
>+			for_each_pipe(p)
>+				if (p != PIPE_A)
>+					dev->last_vblank[p] = 0;
>+			spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
> 		}
> 	}
> }
>-- 
>1.8.1.2
>

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