Attachment 82900 Details for Bug 67243 – dmesg

dmesg

e6510dmesg0724.txt (text/plain), 208.71 KB, created by lu hua on 2013-07-24 06:27:42 UTC

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Creator: lu hua

Created: 2013-07-24 06:27:42 UTC

Size: 208.71 KB

patch

obsolete

>[   31.848565] netpoll: netconsole: local port 6665
>[   31.848661] netpoll: netconsole: local IPv4 address 0.0.0.0
>[   31.848717] netpoll: netconsole: interface 'em1'
>[   31.848763] netpoll: netconsole: remote port 6666
>[   31.848815] netpoll: netconsole: remote IPv4 address 10.239.47.38
>[   31.848872] netpoll: netconsole: remote ethernet address 00:13:20:fb:6a:c9
>[   31.848930] netpoll: netconsole: local IP 10.239.47.26
>[   31.849009] console [netcon0] enabled
>[   31.849040] netconsole: network logging started
>[   31.857369] netpoll: netconsole: local port 6665
>[   31.857476] netpoll: netconsole: local IPv4 address 0.0.0.0
>[   31.857565] netpoll: netconsole: interface 'em1'
>[   31.857614] netpoll: netconsole: remote port 6666
>[   31.857660] netpoll: netconsole: remote IPv4 address 10.239.47.38
>[   31.857712] netpoll: netconsole: remote ethernet address 00:13:20:fb:6a:c9
>[   31.857765] netpoll: netconsole: local IP 10.239.47.26
>[   31.857834] console [netcon0] enabled
>[   31.857865] netconsole: network logging started
>[   48.727628] [drm:i915_driver_open], 
>[   48.727800] [drm:intel_crtc_cursor_set], cursor off
>[   48.727896] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[   48.728039] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   48.728177] [drm:intel_crtc_cursor_set], cursor off
>[   48.728318] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[   48.728417] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   48.728567] [drm:i915_driver_open], 
>[   48.728943] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.728965] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.728984] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.728991] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.729002] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   48.729009] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[   48.729015] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   48.729028] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   48.729265] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[   48.729437] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[   48.729444] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   48.729458] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[   48.729465] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[   48.729469] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   48.729474] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   48.729484] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[   48.729493] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.729499] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[   48.729562] [drm:drm_mode_addfb2], [FB:32]
>[   48.729571] [drm:drm_mode_addfb2], [FB:33]
>[   48.729576] [drm:drm_mode_setcrtc], [CRTC:3]
>[   48.729581] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   48.729585] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   48.729591] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   48.729596] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   48.729601] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   48.729606] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   48.729611] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   48.729614] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   48.729683] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[   48.729717] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   48.729741] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   48.729761] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[   48.729788] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   48.729798] [drm:intel_dump_pipe_config], requested mode:
>[   48.729803] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   48.729811] [drm:intel_dump_pipe_config], adjusted mode:
>[   48.729815] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   48.729823] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   48.729830] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   48.729835] [drm:intel_dump_pipe_config], ips: 0
>[   48.729841] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   48.729846] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[   48.729852] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   48.729861] [drm:ironlake_edp_backlight_off], 
>[   48.931092] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   48.931101] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   48.931106] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   49.810437] [drm:intel_dp_link_down], 
>[   49.862467] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   49.913692] [drm:intel_update_fbc], no output, disabling
>[   49.920692] [drm:ironlake_update_plane], Writing base 00450000 00000000 0 0 2752
>[   49.920708] [drm:intel_update_fbc], no output, disabling
>[   49.920717] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   49.920726] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   49.920731] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   49.921240] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 4
>[   49.921247] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4
>[   49.921255] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4
>[   49.921265] [drm:ironlake_edp_pll_on], 
>[   49.973533] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   50.025564] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   50.025576] [drm:intel_update_fbc], fbc set to per-chip default
>[   50.025580] [drm:intel_update_fbc], fbc disabled per module param
>[   50.025586] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   50.025593] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   50.025600] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   50.025612] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   50.025618] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   50.327180] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   50.327779] [drm:intel_dp_start_link_train], clock recovery OK
>[   50.327784] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   50.327788] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   50.327793] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   50.327803] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   50.327808] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[   50.668894] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   50.668905] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   50.719922] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   50.720814] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   50.720968] [drm:ironlake_edp_backlight_on], 
>[   50.761963] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   50.771965] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   50.771988] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   50.771997] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   50.772005] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   50.772014] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   50.772023] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   50.772033] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   50.772042] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   50.772051] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   50.772060] [drm:check_crtc_state], [CRTC:3]
>[   50.772074] [drm:check_crtc_state], [CRTC:5]
>[   50.772082] [drm:check_shared_dpll_state], PCH DPLL A
>[   50.772093] [drm:check_shared_dpll_state], PCH DPLL B
>[   50.787628] [drm:intel_update_fbc], fbc set to per-chip default
>[   50.787640] [drm:intel_update_fbc], fbc disabled per module param
>[   59.150464] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   59.150484] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   59.150489] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   59.150494] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   59.150500] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   59.150506] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   59.150519] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   59.150526] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   59.150534] [drm:ironlake_edp_backlight_off], 
>[   59.351555] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   59.351564] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   59.351570] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   60.222858] [drm:intel_dp_link_down], 
>[   60.274886] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   60.326120] [drm:intel_update_fbc], no output, disabling
>[   60.326147] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   60.326154] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   60.326160] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   60.326166] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   60.326172] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   60.326178] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   60.326183] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   60.326189] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   60.326195] [drm:check_crtc_state], [CRTC:3]
>[   60.326200] [drm:check_crtc_state], [CRTC:5]
>[   60.326205] [drm:check_shared_dpll_state], PCH DPLL A
>[   60.326212] [drm:check_shared_dpll_state], PCH DPLL B
>[   60.328210] [drm:drm_mode_addfb2], could not create framebuffer
>[   60.328292] [drm:drm_mode_addfb2], [FB:32]
>[   60.328308] [drm:drm_mode_addfb2], [FB:33]
>[   60.328387] [drm:drm_mode_setcrtc], [CRTC:3]
>[   60.328396] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   60.328401] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   60.328409] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   60.328414] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   60.328419] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   60.328425] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   60.328431] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   60.328438] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   60.328444] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[   60.328450] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   60.328457] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   60.328463] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   60.328470] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   60.328476] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   60.328481] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   60.328486] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[   60.328491] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.328498] [drm:intel_dump_pipe_config], requested mode:
>[   60.328503] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   60.328511] [drm:intel_dump_pipe_config], adjusted mode:
>[   60.328516] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   60.328524] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   60.328530] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   60.328535] [drm:intel_dump_pipe_config], ips: 0
>[   60.339779] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[   60.339799] [drm:intel_update_fbc], no output, disabling
>[   60.339810] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   60.339817] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   60.339824] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   60.340338] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[   60.340348] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[   60.340355] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[   60.340365] [drm:ironlake_edp_pll_on], 
>[   60.391954] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   60.443987] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   60.443998] [drm:intel_update_fbc], fbc set to per-chip default
>[   60.444003] [drm:intel_update_fbc], fbc disabled per module param
>[   60.444009] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   60.444016] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   60.444022] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   60.444034] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   60.444040] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   60.745603] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   60.746202] [drm:intel_dp_start_link_train], clock recovery OK
>[   60.746206] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   60.746211] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   60.746216] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   60.746225] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   60.746231] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[   61.087315] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   61.087328] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   61.138345] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   61.139236] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   61.139392] [drm:ironlake_edp_backlight_on], 
>[   61.180413] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   61.190465] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   61.190491] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   61.190500] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   61.190507] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   61.190514] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   61.190521] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   61.190529] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   61.190536] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   61.190543] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   61.190550] [drm:check_crtc_state], [CRTC:3]
>[   61.190563] [drm:check_crtc_state], [CRTC:5]
>[   61.190569] [drm:check_shared_dpll_state], PCH DPLL A
>[   61.190578] [drm:check_shared_dpll_state], PCH DPLL B
>[   61.205995] [drm:intel_update_fbc], fbc set to per-chip default
>[   61.206004] [drm:intel_update_fbc], fbc disabled per module param
>[   68.353305] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   68.353325] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   68.353331] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   68.353336] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   68.353341] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   68.353348] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   68.353364] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   68.353369] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   68.353375] [drm:ironlake_edp_backlight_off], 
>[   68.554139] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   68.554149] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   68.554154] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   69.423541] [drm:intel_dp_link_down], 
>[   69.475556] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   69.526809] [drm:intel_update_fbc], no output, disabling
>[   69.526836] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   69.526844] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   69.526850] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   69.526856] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   69.526862] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   69.526868] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   69.526874] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   69.526880] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   69.526885] [drm:check_crtc_state], [CRTC:3]
>[   69.526890] [drm:check_crtc_state], [CRTC:5]
>[   69.526895] [drm:check_shared_dpll_state], PCH DPLL A
>[   69.526903] [drm:check_shared_dpll_state], PCH DPLL B
>[   69.530898] [drm:drm_mode_addfb2], [FB:32]
>[   69.530912] [drm:drm_mode_addfb2], [FB:33]
>[   69.530920] [drm:drm_mode_setcrtc], [CRTC:3]
>[   69.530927] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   69.530933] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   69.530941] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   69.530946] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   69.530951] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   69.530957] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   69.531035] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   69.531043] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   69.531048] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[   69.531054] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   69.531061] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   69.531068] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   69.531074] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[   69.531080] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   69.531144] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   69.531148] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[   69.531154] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   69.531161] [drm:intel_dump_pipe_config], requested mode:
>[   69.531165] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   69.531174] [drm:intel_dump_pipe_config], adjusted mode:
>[   69.531178] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   69.531186] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   69.531192] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   69.531198] [drm:intel_dump_pipe_config], ips: 0
>[   69.542536] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[   69.542555] [drm:intel_update_fbc], no output, disabling
>[   69.542566] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   69.542574] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   69.542580] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   69.543088] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[   69.543096] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[   69.543104] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[   69.543114] [drm:ironlake_edp_pll_on], 
>[   69.594626] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   69.646658] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   69.646670] [drm:intel_update_fbc], fbc set to per-chip default
>[   69.646674] [drm:intel_update_fbc], fbc disabled per module param
>[   69.646680] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   69.646687] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   69.646693] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   69.646705] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   69.646711] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   69.948286] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   69.948883] [drm:intel_dp_start_link_train], clock recovery OK
>[   69.948888] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   69.948892] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   69.948897] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   69.948907] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   69.948912] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[   70.290061] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   70.290078] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   70.341091] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   70.342045] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   70.342207] [drm:ironlake_edp_backlight_on], 
>[   70.383128] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   70.393128] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   70.393155] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   70.393163] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   70.393170] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   70.393177] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   70.393184] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   70.393192] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   70.393199] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   70.393206] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   70.393213] [drm:check_crtc_state], [CRTC:3]
>[   70.393226] [drm:check_crtc_state], [CRTC:5]
>[   70.393232] [drm:check_shared_dpll_state], PCH DPLL A
>[   70.393242] [drm:check_shared_dpll_state], PCH DPLL B
>[   70.408868] [drm:intel_update_fbc], fbc set to per-chip default
>[   70.408880] [drm:intel_update_fbc], fbc disabled per module param
>[   78.375885] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   78.375904] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   78.375909] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   78.375914] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   78.375920] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   78.375927] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   78.375939] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   78.375946] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   78.375954] [drm:ironlake_edp_backlight_off], 
>[   78.577372] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   78.577382] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   78.577387] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   79.443701] [drm:intel_dp_link_down], 
>[   79.495732] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   79.546970] [drm:intel_update_fbc], no output, disabling
>[   79.546996] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   79.547003] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   79.547009] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   79.547014] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   79.547020] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   79.547026] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   79.547032] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   79.547038] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   79.547043] [drm:check_crtc_state], [CRTC:3]
>[   79.547049] [drm:check_crtc_state], [CRTC:5]
>[   79.547054] [drm:check_shared_dpll_state], PCH DPLL A
>[   79.547061] [drm:check_shared_dpll_state], PCH DPLL B
>[   79.551042] [drm:drm_mode_addfb2], [FB:32]
>[   79.551064] [drm:drm_mode_addfb2], [FB:33]
>[   79.551076] [drm:drm_mode_setcrtc], [CRTC:3]
>[   79.551087] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   79.551095] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   79.551106] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   79.551114] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   79.551126] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   79.551130] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   79.551134] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   79.551138] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   79.551141] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[   79.551145] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   79.551154] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   79.551161] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   79.551167] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   79.551173] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   79.551179] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   79.551184] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[   79.551189] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   79.551304] [drm:intel_dump_pipe_config], requested mode:
>[   79.551309] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   79.551317] [drm:intel_dump_pipe_config], adjusted mode:
>[   79.551322] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   79.551329] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   79.551336] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   79.551341] [drm:intel_dump_pipe_config], ips: 0
>[   79.562633] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[   79.562654] [drm:intel_update_fbc], no output, disabling
>[   79.562665] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   79.562673] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   79.562678] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   79.563188] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[   79.563197] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[   79.563205] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[   79.563216] [drm:ironlake_edp_pll_on], 
>[   79.614796] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   79.666833] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   79.666845] [drm:intel_update_fbc], fbc set to per-chip default
>[   79.666850] [drm:intel_update_fbc], fbc disabled per module param
>[   79.666855] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   79.666863] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   79.666870] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   79.666881] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   79.666888] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   79.968454] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   79.969055] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   79.969644] [drm:intel_dp_start_link_train], clock recovery OK
>[   79.969648] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   79.969652] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   79.969657] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   79.969666] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   79.969672] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[   80.310235] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   80.310252] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   80.361262] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   80.362216] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   80.362374] [drm:ironlake_edp_backlight_on], 
>[   80.403224] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   80.413302] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   80.413330] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   80.413338] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   80.413345] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   80.413352] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   80.413360] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   80.413367] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   80.413373] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   80.413381] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   80.413388] [drm:check_crtc_state], [CRTC:3]
>[   80.413401] [drm:check_crtc_state], [CRTC:5]
>[   80.413407] [drm:check_shared_dpll_state], PCH DPLL A
>[   80.413417] [drm:check_shared_dpll_state], PCH DPLL B
>[   80.428973] [drm:intel_update_fbc], fbc set to per-chip default
>[   80.428983] [drm:intel_update_fbc], fbc disabled per module param
>[   87.576011] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   87.576030] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   87.576035] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   87.576041] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   87.576046] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   87.576053] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   87.576065] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   87.576072] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   87.576080] [drm:ironlake_edp_backlight_off], 
>[   87.776997] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   87.777006] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   87.777012] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   88.647373] [drm:intel_dp_link_down], 
>[   88.699404] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   88.750642] [drm:intel_update_fbc], no output, disabling
>[   88.750668] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   88.750676] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   88.750681] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   88.750687] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   88.750693] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   88.750699] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   88.750705] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   88.750711] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   88.750717] [drm:check_crtc_state], [CRTC:3]
>[   88.750723] [drm:check_crtc_state], [CRTC:5]
>[   88.750727] [drm:check_shared_dpll_state], PCH DPLL A
>[   88.750735] [drm:check_shared_dpll_state], PCH DPLL B
>[   88.754768] [drm:drm_mode_addfb2], [FB:32]
>[   88.754784] [drm:drm_mode_addfb2], [FB:33]
>[   88.754792] [drm:drm_mode_setcrtc], [CRTC:3]
>[   88.754800] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   88.754806] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   88.754813] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   88.754819] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[   88.754824] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[   88.754832] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   88.754906] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   88.754912] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   88.754918] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   88.754932] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   88.754940] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   88.754947] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   88.754954] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   88.754960] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   88.754966] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[   88.754972] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   88.754978] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   88.754983] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[   88.754989] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   88.754996] [drm:intel_dump_pipe_config], requested mode:
>[   88.755000] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   88.755008] [drm:intel_dump_pipe_config], adjusted mode:
>[   88.755013] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   88.755022] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   88.755028] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   88.755033] [drm:intel_dump_pipe_config], ips: 0
>[   88.762253] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 2752
>[   88.762268] [drm:intel_update_fbc], no output, disabling
>[   88.762278] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   88.762285] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   88.762291] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   88.762799] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 4
>[   88.762804] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4
>[   88.762809] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4
>[   88.762816] [drm:ironlake_edp_pll_on], 
>[   88.814472] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   88.866556] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   88.866567] [drm:intel_update_fbc], fbc set to per-chip default
>[   88.866572] [drm:intel_update_fbc], fbc disabled per module param
>[   88.866578] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   88.866585] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   88.866592] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   88.866604] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   88.866611] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   89.168116] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   89.168717] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   89.169308] [drm:intel_dp_start_link_train], clock recovery OK
>[   89.169312] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   89.169316] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   89.169322] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   89.169331] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   89.169336] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 9000000a control abcd0009
>[   89.509911] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   89.509929] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   89.560943] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   89.561864] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   89.562019] [drm:ironlake_edp_backlight_on], 
>[   89.602934] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   89.612979] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   89.613002] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   89.613010] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   89.613017] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   89.613025] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   89.613033] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   89.613040] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   89.613048] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   89.613055] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   89.613064] [drm:check_crtc_state], [CRTC:3]
>[   89.613077] [drm:check_crtc_state], [CRTC:5]
>[   89.613083] [drm:check_shared_dpll_state], PCH DPLL A
>[   89.613092] [drm:check_shared_dpll_state], PCH DPLL B
>[   89.628691] [drm:intel_update_fbc], fbc set to per-chip default
>[   89.628703] [drm:intel_update_fbc], fbc disabled per module param
>[   90.263072] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[   97.938361] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[   97.938379] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[   97.938385] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   97.938393] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   97.938398] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   97.938405] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   97.938417] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   97.938424] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[   97.938432] [drm:ironlake_edp_backlight_off], 
>[   98.139427] [drm:ironlake_edp_panel_off], Turn eDP power off
>[   98.139437] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[   98.139444] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[   98.929711] [drm:intel_dp_link_down], 
>[   98.981742] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   99.032977] [drm:intel_update_fbc], no output, disabling
>[   99.032996] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   99.033001] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   99.033004] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   99.033008] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   99.033012] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   99.033016] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   99.033020] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   99.033024] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   99.033028] [drm:check_crtc_state], [CRTC:3]
>[   99.033031] [drm:check_crtc_state], [CRTC:5]
>[   99.033034] [drm:check_shared_dpll_state], PCH DPLL A
>[   99.033040] [drm:check_shared_dpll_state], PCH DPLL B
>[   99.034475] [drm:drm_mode_addfb2], could not create framebuffer
>[   99.034509] [drm:drm_mode_addfb2], [FB:32]
>[   99.034515] [drm:drm_mode_addfb2], [FB:33]
>[   99.034583] [drm:drm_mode_setcrtc], [CRTC:3]
>[   99.034587] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[   99.034590] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[   99.034594] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[   99.034596] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[   99.034599] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[   99.034602] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[   99.034606] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   99.034609] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[   99.034612] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[   99.034616] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[   99.034620] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[   99.034623] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[   99.034630] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[   99.034633] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[   99.034636] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[   99.034639] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[   99.034641] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   99.034644] [drm:intel_dump_pipe_config], requested mode:
>[   99.034647] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   99.034650] [drm:intel_dump_pipe_config], adjusted mode:
>[   99.034652] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[   99.034656] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   99.034659] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[   99.034770] [drm:intel_dump_pipe_config], ips: 0
>[   99.044268] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[   99.044282] [drm:intel_update_fbc], no output, disabling
>[   99.044290] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[   99.044294] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[   99.044297] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[   99.044803] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[   99.044809] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[   99.044813] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[   99.044820] [drm:ironlake_edp_pll_on], 
>[   99.096810] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   99.148845] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[   99.148859] [drm:intel_update_fbc], fbc set to per-chip default
>[   99.148864] [drm:intel_update_fbc], fbc disabled per module param
>[   99.148871] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[   99.148879] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   99.148887] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[   99.148901] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   99.148908] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[   99.450496] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   99.451093] [drm:intel_dp_start_link_train], clock recovery OK
>[   99.451098] [drm:ironlake_edp_panel_on], Turn eDP power on
>[   99.451102] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[   99.451108] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[   99.451117] [drm:ironlake_wait_panel_on], Wait for panel power on
>[   99.451122] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[   99.792179] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[   99.792195] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   99.843212] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[   99.844122] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[   99.844275] [drm:ironlake_edp_backlight_on], 
>[   99.844974] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[   99.885311] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[   99.895242] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[   99.895269] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[   99.895278] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[   99.895287] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[   99.895296] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[   99.895305] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[   99.895314] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[   99.895322] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[   99.895332] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[   99.895341] [drm:check_crtc_state], [CRTC:3]
>[   99.895356] [drm:check_crtc_state], [CRTC:5]
>[   99.895363] [drm:check_shared_dpll_state], PCH DPLL A
>[   99.895374] [drm:check_shared_dpll_state], PCH DPLL B
>[   99.910881] [drm:intel_update_fbc], fbc set to per-chip default
>[   99.910891] [drm:intel_update_fbc], fbc disabled per module param
>[  108.059536] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  108.059559] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  108.059564] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  108.059569] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  108.059575] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  108.059582] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  108.059594] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  108.059601] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  108.059609] [drm:ironlake_edp_backlight_off], 
>[  108.260669] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  108.260679] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  108.260686] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
>[  109.145006] [drm:intel_dp_link_down], 
>[  109.197038] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  109.248274] [drm:intel_update_fbc], no output, disabling
>[  109.248294] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  109.248298] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  109.248301] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  109.248305] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  109.248309] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  109.248313] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  109.248316] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  109.248320] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  109.248324] [drm:check_crtc_state], [CRTC:3]
>[  109.248328] [drm:check_crtc_state], [CRTC:5]
>[  109.248331] [drm:check_shared_dpll_state], PCH DPLL A
>[  109.248337] [drm:check_shared_dpll_state], PCH DPLL B
>[  109.251044] [drm:drm_mode_addfb2], [FB:32]
>[  109.251052] [drm:drm_mode_addfb2], [FB:33]
>[  109.251056] [drm:drm_mode_setcrtc], [CRTC:3]
>[  109.251061] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  109.251064] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  109.251068] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  109.251071] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  109.251133] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  109.251137] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  109.251145] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  109.251149] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  109.251152] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  109.251155] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  109.251162] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  109.251165] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  109.251168] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  109.251171] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  109.251174] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  109.251176] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  109.251179] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  109.251182] [drm:intel_dump_pipe_config], requested mode:
>[  109.251185] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  109.251189] [drm:intel_dump_pipe_config], adjusted mode:
>[  109.251191] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  109.251195] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  109.251198] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  109.251200] [drm:intel_dump_pipe_config], ips: 0
>[  109.260582] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[  109.260595] [drm:intel_update_fbc], no output, disabling
>[  109.260602] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  109.260606] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  109.260609] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  109.261115] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  109.261120] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  109.261124] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  109.261130] [drm:ironlake_edp_pll_on], 
>[  109.313110] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  109.365142] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  109.365156] [drm:intel_update_fbc], fbc set to per-chip default
>[  109.365162] [drm:intel_update_fbc], fbc disabled per module param
>[  109.365169] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  109.365177] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  109.365184] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  109.365197] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  109.365205] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  109.666756] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  109.667355] [drm:intel_dp_start_link_train], clock recovery OK
>[  109.667360] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  109.667364] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  109.667370] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  109.667379] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  109.667384] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  110.008476] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  110.008496] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  110.059510] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  110.060474] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  110.060628] [drm:ironlake_edp_backlight_on], 
>[  110.061324] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  110.101602] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  110.111607] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  110.111634] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  110.111643] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  110.111650] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  110.111657] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  110.111664] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  110.111671] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  110.111679] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  110.111686] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  110.111693] [drm:check_crtc_state], [CRTC:3]
>[  110.111706] [drm:check_crtc_state], [CRTC:5]
>[  110.111712] [drm:check_shared_dpll_state], PCH DPLL A
>[  110.111721] [drm:check_shared_dpll_state], PCH DPLL B
>[  110.127297] [drm:intel_update_fbc], fbc set to per-chip default
>[  110.127308] [drm:intel_update_fbc], fbc disabled per module param
>[  119.095392] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  119.095411] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  119.095417] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  119.095422] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  119.095427] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  119.095434] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  119.095449] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  119.095455] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  119.095461] [drm:ironlake_edp_backlight_off], 
>[  119.296453] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  119.296462] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  119.296468] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  120.128712] [drm:intel_dp_link_down], 
>[  120.180742] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  120.231969] [drm:intel_update_fbc], no output, disabling
>[  120.231988] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  120.231994] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  120.231998] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  120.232002] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  120.232007] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  120.232011] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  120.232016] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  120.232021] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  120.232026] [drm:check_crtc_state], [CRTC:3]
>[  120.232030] [drm:check_crtc_state], [CRTC:5]
>[  120.232034] [drm:check_shared_dpll_state], PCH DPLL A
>[  120.232041] [drm:check_shared_dpll_state], PCH DPLL B
>[  120.234618] [drm:drm_mode_addfb2], [FB:32]
>[  120.234626] [drm:drm_mode_addfb2], [FB:33]
>[  120.234630] [drm:drm_mode_setcrtc], [CRTC:3]
>[  120.234634] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  120.234637] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  120.234641] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  120.234644] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  120.234647] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  120.234710] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  120.234718] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  120.234722] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  120.234725] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  120.234728] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  120.234732] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  120.234738] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  120.234741] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  120.234744] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  120.234747] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  120.234749] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  120.234752] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  120.234755] [drm:intel_dump_pipe_config], requested mode:
>[  120.234758] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  120.234783] [drm:intel_dump_pipe_config], adjusted mode:
>[  120.234791] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  120.234802] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  120.234812] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  120.234816] [drm:intel_dump_pipe_config], ips: 0
>[  120.244480] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[  120.244493] [drm:intel_update_fbc], no output, disabling
>[  120.244500] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  120.244504] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  120.244507] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  120.245013] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  120.245018] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  120.245022] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  120.245028] [drm:ironlake_edp_pll_on], 
>[  120.296886] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  120.348908] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  120.348919] [drm:intel_update_fbc], fbc set to per-chip default
>[  120.348924] [drm:intel_update_fbc], fbc disabled per module param
>[  120.348930] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  120.348938] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  120.348944] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  120.348956] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  120.348962] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  120.650517] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  120.651116] [drm:intel_dp_start_link_train], clock recovery OK
>[  120.651120] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  120.651125] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  120.651130] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  120.651139] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  120.651145] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  120.992311] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  120.992328] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  121.043340] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  121.044300] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  121.044461] [drm:ironlake_edp_backlight_on], 
>[  121.085298] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  121.095378] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  121.095403] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  121.095412] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  121.095418] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  121.095426] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  121.095434] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  121.095441] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  121.095449] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  121.095456] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  121.095463] [drm:check_crtc_state], [CRTC:3]
>[  121.095477] [drm:check_crtc_state], [CRTC:5]
>[  121.095483] [drm:check_shared_dpll_state], PCH DPLL A
>[  121.095493] [drm:check_shared_dpll_state], PCH DPLL B
>[  121.111059] [drm:intel_update_fbc], fbc set to per-chip default
>[  121.111067] [drm:intel_update_fbc], fbc disabled per module param
>[  123.255085] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  128.257795] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  128.257814] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  128.257819] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  128.257824] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  128.257829] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  128.257836] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  128.257850] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  128.257855] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  128.257861] [drm:ironlake_edp_backlight_off], 
>[  128.459103] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  128.459113] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  128.459118] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  129.345458] [drm:intel_dp_link_down], 
>[  129.397489] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  129.448726] [drm:intel_update_fbc], no output, disabling
>[  129.448753] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  129.448759] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  129.448765] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  129.448771] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  129.448777] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  129.448783] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  129.448789] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  129.448796] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  129.448801] [drm:check_crtc_state], [CRTC:3]
>[  129.448807] [drm:check_crtc_state], [CRTC:5]
>[  129.448811] [drm:check_shared_dpll_state], PCH DPLL A
>[  129.448819] [drm:check_shared_dpll_state], PCH DPLL B
>[  129.452763] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  129.452777] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  129.452787] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  129.452794] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  129.452800] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  129.452808] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  129.452815] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  129.452828] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  129.452835] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  129.753923] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  129.754099] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  129.754106] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  129.754120] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  129.754126] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  129.754130] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  129.754136] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  129.754144] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  129.754153] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  129.754158] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  129.754205] [drm:drm_mode_addfb2], [FB:32]
>[  129.754213] [drm:drm_mode_addfb2], [FB:33]
>[  129.754217] [drm:drm_mode_setcrtc], [CRTC:5]
>[  129.754222] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  129.754226] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  129.754231] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  129.754297] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  129.754301] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  129.754306] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  129.754311] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  129.754315] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  129.754318] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  129.754329] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  129.754334] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  129.754338] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  129.754343] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  129.754347] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  129.754351] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  129.754355] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  129.754359] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  129.754362] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  129.754365] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  129.754370] [drm:intel_dump_pipe_config], requested mode:
>[  129.754373] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  129.754378] [drm:intel_dump_pipe_config], adjusted mode:
>[  129.754381] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  129.754386] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  129.754389] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  129.754393] [drm:intel_dump_pipe_config], ips: 0
>[  129.761207] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 2752
>[  129.761223] [drm:intel_update_fbc], no output, disabling
>[  129.761233] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  129.761240] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  129.761246] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  129.761755] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 4
>[  129.761768] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4
>[  129.761778] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4
>[  129.761790] [drm:ironlake_edp_pll_on], 
>[  129.813704] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  129.865741] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  129.865753] [drm:intel_update_fbc], fbc set to per-chip default
>[  129.865759] [drm:intel_update_fbc], fbc disabled per module param
>[  129.865766] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  129.865772] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  129.866168] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  129.866764] [drm:intel_dp_start_link_train], clock recovery OK
>[  129.866772] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  129.866776] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  129.866783] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  129.866791] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  129.866797] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  130.207929] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  130.207946] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  130.258958] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  130.259927] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  130.260089] [drm:ironlake_edp_backlight_on], 
>[  130.300979] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  130.311053] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  130.311076] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  130.311084] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  130.311089] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  130.311097] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  130.311103] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  130.311109] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  130.311115] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  130.311121] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  130.311127] [drm:check_crtc_state], [CRTC:3]
>[  130.311132] [drm:check_crtc_state], [CRTC:5]
>[  130.311144] [drm:check_shared_dpll_state], PCH DPLL A
>[  130.311152] [drm:check_shared_dpll_state], PCH DPLL B
>[  130.326773] [drm:intel_update_fbc], fbc set to per-chip default
>[  130.326782] [drm:intel_update_fbc], fbc disabled per module param
>[  137.635200] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  137.635221] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  137.635227] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  137.635232] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  137.635237] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  137.635245] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  137.635257] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  137.635263] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  137.635271] [drm:ironlake_edp_backlight_off], 
>[  137.835854] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  137.835864] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  137.835869] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  138.628176] [drm:intel_dp_link_down], 
>[  138.680206] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  138.732239] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  138.783479] [drm:intel_update_fbc], no output, disabling
>[  138.783504] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  138.783512] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  138.783517] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  138.783524] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  138.783530] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  138.783536] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  138.783542] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  138.783548] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  138.783554] [drm:check_crtc_state], [CRTC:3]
>[  138.783559] [drm:check_crtc_state], [CRTC:5]
>[  138.783564] [drm:check_shared_dpll_state], PCH DPLL A
>[  138.783572] [drm:check_shared_dpll_state], PCH DPLL B
>[  138.785589] [drm:drm_mode_addfb2], could not create framebuffer
>[  138.785691] [drm:drm_mode_addfb2], [FB:32]
>[  138.785701] [drm:drm_mode_addfb2], [FB:33]
>[  138.785782] [drm:drm_mode_setcrtc], [CRTC:5]
>[  138.785791] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  138.785797] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  138.785805] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  138.785810] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  138.785816] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  138.785822] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  138.785828] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  138.785835] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  138.785841] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  138.785848] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  138.785855] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  138.785862] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  138.785869] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  138.785875] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  138.785881] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  138.785886] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  138.785891] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  138.785898] [drm:intel_dump_pipe_config], requested mode:
>[  138.785903] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  138.785912] [drm:intel_dump_pipe_config], adjusted mode:
>[  138.785917] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  138.785924] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  138.785930] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  138.785936] [drm:intel_dump_pipe_config], ips: 0
>[  138.796974] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504
>[  138.796994] [drm:intel_update_fbc], no output, disabling
>[  138.797005] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  138.797013] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  138.797019] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  138.797529] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6
>[  138.797539] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  138.797547] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  138.797557] [drm:ironlake_edp_pll_on], 
>[  138.849310] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  138.901346] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  138.901358] [drm:intel_update_fbc], fbc set to per-chip default
>[  138.901363] [drm:intel_update_fbc], fbc disabled per module param
>[  138.901369] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  138.901377] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  138.901384] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  138.901395] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  138.901401] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  139.202962] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  139.203558] [drm:intel_dp_start_link_train], clock recovery OK
>[  139.203563] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  139.203567] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  139.203573] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  139.203582] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  139.203587] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  139.544681] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  139.544700] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  139.595713] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  139.596681] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  139.596858] [drm:ironlake_edp_backlight_on], 
>[  139.637742] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  139.647734] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  139.647751] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  139.647757] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  139.647761] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  139.647766] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  139.647772] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  139.647776] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  139.647781] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  139.647786] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  139.647791] [drm:check_crtc_state], [CRTC:3]
>[  139.647795] [drm:check_crtc_state], [CRTC:5]
>[  139.647805] [drm:check_shared_dpll_state], PCH DPLL A
>[  139.647812] [drm:check_shared_dpll_state], PCH DPLL B
>[  139.663441] [drm:intel_update_fbc], fbc set to per-chip default
>[  139.663451] [drm:intel_update_fbc], fbc disabled per module param
>[  146.728654] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  146.728672] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  146.728678] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  146.728682] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  146.728688] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  146.728695] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  146.728707] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  146.728714] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  146.728723] [drm:ironlake_edp_backlight_off], 
>[  146.929484] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  146.929494] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  146.929499] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  147.730789] [drm:intel_dp_link_down], 
>[  147.782794] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  147.834825] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  147.886089] [drm:intel_update_fbc], no output, disabling
>[  147.886109] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  147.886114] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  147.886117] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  147.886121] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  147.886125] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  147.886129] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  147.886132] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  147.886136] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  147.886140] [drm:check_crtc_state], [CRTC:3]
>[  147.886143] [drm:check_crtc_state], [CRTC:5]
>[  147.886146] [drm:check_shared_dpll_state], PCH DPLL A
>[  147.886153] [drm:check_shared_dpll_state], PCH DPLL B
>[  147.888882] [drm:drm_mode_addfb2], [FB:32]
>[  147.888891] [drm:drm_mode_addfb2], [FB:33]
>[  147.888895] [drm:drm_mode_setcrtc], [CRTC:5]
>[  147.888899] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  147.888901] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  147.888905] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  147.888908] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  147.888911] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  147.888974] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  147.888982] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  147.888986] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  147.888989] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  147.888996] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  147.888999] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  147.889002] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  147.889004] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  147.889007] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  147.889010] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  147.889012] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  147.889015] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  147.889018] [drm:intel_dump_pipe_config], requested mode:
>[  147.889020] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  147.889024] [drm:intel_dump_pipe_config], adjusted mode:
>[  147.889026] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  147.889030] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  147.889034] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  147.889037] [drm:intel_dump_pipe_config], ips: 0
>[  147.898472] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504
>[  147.898484] [drm:intel_update_fbc], no output, disabling
>[  147.898491] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  147.898496] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  147.898498] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  147.899005] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6
>[  147.899009] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  147.899013] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  147.899019] [drm:ironlake_edp_pll_on], 
>[  147.950923] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  148.002953] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  148.002964] [drm:intel_update_fbc], fbc set to per-chip default
>[  148.002969] [drm:intel_update_fbc], fbc disabled per module param
>[  148.002975] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  148.002982] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  148.002988] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  148.003000] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  148.003006] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  148.304564] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  148.305162] [drm:intel_dp_start_link_train], clock recovery OK
>[  148.305167] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  148.305171] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  148.305176] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  148.305186] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  148.305191] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  148.646287] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  148.646306] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  148.697319] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  148.698250] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  148.698406] [drm:ironlake_edp_backlight_on], 
>[  148.739342] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  148.749422] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  148.749449] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  148.749458] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  148.749464] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  148.749472] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  148.749479] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  148.749487] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  148.749495] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  148.749502] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  148.749509] [drm:check_crtc_state], [CRTC:3]
>[  148.749516] [drm:check_crtc_state], [CRTC:5]
>[  148.749529] [drm:check_shared_dpll_state], PCH DPLL A
>[  148.749538] [drm:check_shared_dpll_state], PCH DPLL B
>[  148.765014] [drm:intel_update_fbc], fbc set to per-chip default
>[  148.765026] [drm:intel_update_fbc], fbc disabled per module param
>[  157.733219] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  157.733237] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  157.733243] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  157.733248] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  157.733253] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  157.733260] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  157.733272] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  157.733282] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  157.733288] [drm:ironlake_edp_backlight_off], 
>[  157.934278] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  157.934288] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  157.934293] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  158.732570] [drm:intel_dp_link_down], 
>[  158.784601] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  158.836629] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  158.887871] [drm:intel_update_fbc], no output, disabling
>[  158.887898] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  158.887904] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  158.887910] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  158.887916] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  158.887922] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  158.887928] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  158.887934] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  158.887940] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  158.887946] [drm:check_crtc_state], [CRTC:3]
>[  158.887951] [drm:check_crtc_state], [CRTC:5]
>[  158.887956] [drm:check_shared_dpll_state], PCH DPLL A
>[  158.887965] [drm:check_shared_dpll_state], PCH DPLL B
>[  158.891906] [drm:drm_mode_addfb2], [FB:32]
>[  158.891920] [drm:drm_mode_addfb2], [FB:33]
>[  158.891924] [drm:drm_mode_setcrtc], [CRTC:5]
>[  158.891928] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  158.891931] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  158.891935] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  158.891938] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  158.891940] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  158.891943] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  158.892010] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  158.892014] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  158.892017] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  158.892021] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  158.892027] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  158.892030] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  158.892033] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  158.892036] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  158.892039] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  158.892041] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  158.892044] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  158.892047] [drm:intel_dump_pipe_config], requested mode:
>[  158.892050] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  158.892053] [drm:intel_dump_pipe_config], adjusted mode:
>[  158.892056] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  158.892059] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  158.892062] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  158.892064] [drm:intel_dump_pipe_config], ips: 0
>[  158.902147] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 5504
>[  158.902166] [drm:intel_update_fbc], no output, disabling
>[  158.902177] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  158.902184] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  158.902190] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  158.902699] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 6, cursor: 6
>[  158.902709] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  158.902717] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  158.902728] [drm:ironlake_edp_pll_on], 
>[  158.954666] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  159.006734] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  159.006746] [drm:intel_update_fbc], fbc set to per-chip default
>[  159.006750] [drm:intel_update_fbc], fbc disabled per module param
>[  159.006756] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  159.006764] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  159.006770] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  159.006782] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  159.006788] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  159.308349] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.308947] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.309539] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.310203] [drm:intel_dp_start_link_train], clock recovery OK
>[  159.310210] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  159.310214] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  159.310219] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  159.310229] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  159.310234] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  159.651145] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  159.651164] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  159.702173] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  159.703097] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  159.703252] [drm:ironlake_edp_backlight_on], 
>[  159.744127] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  159.754203] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  159.754229] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  159.754237] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  159.754244] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  159.754252] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  159.754259] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  159.754266] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  159.754274] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  159.754281] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  159.754288] [drm:check_crtc_state], [CRTC:3]
>[  159.754294] [drm:check_crtc_state], [CRTC:5]
>[  159.754308] [drm:check_shared_dpll_state], PCH DPLL A
>[  159.754317] [drm:check_shared_dpll_state], PCH DPLL B
>[  159.769916] [drm:intel_update_fbc], fbc set to per-chip default
>[  159.769928] [drm:intel_update_fbc], fbc disabled per module param
>[  166.916939] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  166.916957] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  166.916962] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  166.916968] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  166.916974] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  166.916981] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  166.916993] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  166.917000] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  166.917008] [drm:ironlake_edp_backlight_off], 
>[  167.117973] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  167.117983] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  167.117989] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  167.921170] [drm:intel_dp_link_down], 
>[  167.973200] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.025231] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.076469] [drm:intel_update_fbc], no output, disabling
>[  168.076489] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  168.076494] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  168.076498] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  168.076503] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  168.076507] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  168.076512] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  168.076516] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  168.076521] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  168.076525] [drm:check_crtc_state], [CRTC:3]
>[  168.076529] [drm:check_crtc_state], [CRTC:5]
>[  168.076532] [drm:check_shared_dpll_state], PCH DPLL A
>[  168.076539] [drm:check_shared_dpll_state], PCH DPLL B
>[  168.079329] [drm:drm_mode_addfb2], [FB:32]
>[  168.079338] [drm:drm_mode_addfb2], [FB:33]
>[  168.079343] [drm:drm_mode_setcrtc], [CRTC:5]
>[  168.079348] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  168.079352] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  168.079419] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  168.079423] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  168.079426] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  168.079432] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  168.079437] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  168.079445] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  168.079448] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  168.079451] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  168.079455] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  168.079459] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  168.079463] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  168.079467] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  168.079470] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  168.079474] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  168.079477] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  168.079480] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  168.079483] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  168.079487] [drm:intel_dump_pipe_config], requested mode:
>[  168.079490] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  168.079494] [drm:intel_dump_pipe_config], adjusted mode:
>[  168.079497] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  168.079502] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  168.079505] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  168.079508] [drm:intel_dump_pipe_config], ips: 0
>[  168.085707] [drm:ironlake_update_plane], Writing base 028A8000 00000000 0 0 2752
>[  168.085717] [drm:intel_update_fbc], no output, disabling
>[  168.085724] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  168.085729] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  168.085732] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  168.086238] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 3, cursor: 4
>[  168.086243] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4
>[  168.086248] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4
>[  168.086276] [drm:ironlake_edp_pll_on], 
>[  168.138298] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.190330] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  168.190342] [drm:intel_update_fbc], fbc set to per-chip default
>[  168.190348] [drm:intel_update_fbc], fbc disabled per module param
>[  168.190356] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  168.190365] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  168.190374] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  168.190389] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  168.190397] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  168.491962] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  168.492560] [drm:intel_dp_start_link_train], clock recovery OK
>[  168.492564] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  168.492569] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  168.492575] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  168.492584] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  168.492590] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  168.833733] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  168.833749] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  168.884764] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  168.885667] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  168.885823] [drm:ironlake_edp_backlight_on], 
>[  168.926784] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  168.936871] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  168.936895] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  168.936903] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  168.936910] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  168.936917] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  168.936925] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  168.936932] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  168.936939] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  168.936946] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  168.936953] [drm:check_crtc_state], [CRTC:3]
>[  168.936959] [drm:check_crtc_state], [CRTC:5]
>[  168.936973] [drm:check_shared_dpll_state], PCH DPLL A
>[  168.936982] [drm:check_shared_dpll_state], PCH DPLL B
>[  168.952426] [drm:intel_update_fbc], fbc set to per-chip default
>[  168.952437] [drm:intel_update_fbc], fbc disabled per module param
>[  168.987094] [drm:ironlake_irq_handler], Pipe B FIFO underrun
>[  176.259689] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  176.259707] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  176.259713] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  176.259718] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  176.259726] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  176.259733] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  176.259745] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  176.259751] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  176.259760] [drm:ironlake_edp_backlight_off], 
>[  176.460703] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  176.460713] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  176.460719] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  177.321038] [drm:intel_dp_link_down], 
>[  177.373063] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  177.425093] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  177.476328] [drm:intel_update_fbc], no output, disabling
>[  177.476357] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  177.476365] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  177.476372] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  177.476380] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  177.476387] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  177.476395] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  177.476402] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  177.476409] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  177.476416] [drm:check_crtc_state], [CRTC:3]
>[  177.476422] [drm:check_crtc_state], [CRTC:5]
>[  177.476428] [drm:check_shared_dpll_state], PCH DPLL A
>[  177.476437] [drm:check_shared_dpll_state], PCH DPLL B
>[  177.478607] [drm:drm_mode_addfb2], could not create framebuffer
>[  177.478705] [drm:drm_mode_addfb2], [FB:32]
>[  177.478715] [drm:drm_mode_addfb2], [FB:33]
>[  177.478798] [drm:drm_mode_setcrtc], [CRTC:5]
>[  177.478806] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  177.478812] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  177.478820] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  177.478825] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  177.478886] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  177.478892] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  177.478898] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  177.478905] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  177.478911] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  177.478917] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  177.478924] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  177.478930] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  177.478936] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  177.478943] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  177.478949] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  177.478954] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  177.478959] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  177.478966] [drm:intel_dump_pipe_config], requested mode:
>[  177.478971] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  177.478980] [drm:intel_dump_pipe_config], adjusted mode:
>[  177.478984] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  177.478992] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  177.478998] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  177.479004] [drm:intel_dump_pipe_config], ips: 0
>[  177.490467] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504
>[  177.490487] [drm:intel_update_fbc], no output, disabling
>[  177.490498] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  177.490505] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  177.490511] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  177.491020] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6
>[  177.491029] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  177.491036] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  177.491047] [drm:ironlake_edp_pll_on], 
>[  177.543159] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  177.595191] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  177.595202] [drm:intel_update_fbc], fbc set to per-chip default
>[  177.595207] [drm:intel_update_fbc], fbc disabled per module param
>[  177.595213] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  177.595220] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  177.595227] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  177.595239] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  177.595245] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  177.896760] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  177.897360] [drm:intel_dp_start_link_train], clock recovery OK
>[  177.897365] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  177.897369] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  177.897375] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  177.897384] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  177.897390] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  178.238595] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  178.238612] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  178.289620] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  178.290567] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  178.290724] [drm:ironlake_edp_backlight_on], 
>[  178.331597] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  178.341594] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  178.341619] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  178.341629] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  178.341637] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  178.341646] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  178.341654] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  178.341664] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  178.341673] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  178.341683] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  178.341692] [drm:check_crtc_state], [CRTC:3]
>[  178.341700] [drm:check_crtc_state], [CRTC:5]
>[  178.341715] [drm:check_shared_dpll_state], PCH DPLL A
>[  178.341726] [drm:check_shared_dpll_state], PCH DPLL B
>[  178.357392] [drm:intel_update_fbc], fbc set to per-chip default
>[  178.357403] [drm:intel_update_fbc], fbc disabled per module param
>[  180.501413] [drm:ironlake_irq_handler], Pipe B FIFO underrun
>[  186.504914] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  186.504936] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  186.504942] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  186.504947] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  186.504953] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  186.504960] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  186.504975] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  186.504979] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  186.504985] [drm:ironlake_edp_backlight_off], 
>[  186.706010] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  186.706019] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  186.706025] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  187.509303] [drm:intel_dp_link_down], 
>[  187.561334] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  187.613366] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  187.664607] [drm:intel_update_fbc], no output, disabling
>[  187.664634] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  187.664641] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  187.664647] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  187.664653] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  187.664659] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  187.664665] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  187.664671] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  187.664677] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  187.664683] [drm:check_crtc_state], [CRTC:3]
>[  187.664688] [drm:check_crtc_state], [CRTC:5]
>[  187.664693] [drm:check_shared_dpll_state], PCH DPLL A
>[  187.664701] [drm:check_shared_dpll_state], PCH DPLL B
>[  187.668754] [drm:drm_mode_addfb2], [FB:32]
>[  187.668777] [drm:drm_mode_addfb2], [FB:33]
>[  187.668785] [drm:drm_mode_setcrtc], [CRTC:5]
>[  187.668793] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  187.668798] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  187.668806] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  187.668811] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  187.668881] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  187.668887] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  187.668901] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  187.668909] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  187.668915] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  187.668922] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  187.668929] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  187.668935] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  187.668941] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  187.668947] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  187.668953] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  187.668958] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  187.668963] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  187.668970] [drm:intel_dump_pipe_config], requested mode:
>[  187.668975] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  187.668984] [drm:intel_dump_pipe_config], adjusted mode:
>[  187.668991] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  187.669000] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  187.669006] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  187.669011] [drm:intel_dump_pipe_config], ips: 0
>[  187.680362] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504
>[  187.680381] [drm:intel_update_fbc], no output, disabling
>[  187.680392] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  187.680401] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  187.680407] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  187.680916] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6
>[  187.680924] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  187.680932] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  187.680942] [drm:ironlake_edp_pll_on], 
>[  187.732440] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  187.784471] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  187.784482] [drm:intel_update_fbc], fbc set to per-chip default
>[  187.784487] [drm:intel_update_fbc], fbc disabled per module param
>[  187.784493] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  187.784501] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  187.784508] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  187.784520] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  187.784526] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  188.086081] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  188.086676] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  188.087267] [drm:intel_dp_start_link_train], clock recovery OK
>[  188.087271] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  188.087275] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  188.087280] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  188.087290] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  188.087295] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  188.427810] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  188.427828] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  188.478843] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  188.479745] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  188.479899] [drm:ironlake_edp_backlight_on], 
>[  188.480599] [drm:ironlake_irq_handler], Pipe B FIFO underrun
>[  188.520938] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  188.530938] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  188.530964] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  188.530973] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  188.530980] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  188.530987] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  188.530995] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  188.531003] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  188.531009] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  188.531017] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  188.531025] [drm:check_crtc_state], [CRTC:3]
>[  188.531031] [drm:check_crtc_state], [CRTC:5]
>[  188.531044] [drm:check_shared_dpll_state], PCH DPLL A
>[  188.531053] [drm:check_shared_dpll_state], PCH DPLL B
>[  188.546574] [drm:intel_update_fbc], fbc set to per-chip default
>[  188.546586] [drm:intel_update_fbc], fbc disabled per module param
>[  196.079084] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  196.079104] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  196.079110] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  196.079114] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  196.079120] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  196.079127] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  196.079139] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  196.079147] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  196.079155] [drm:ironlake_edp_backlight_off], 
>[  196.279923] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  196.279932] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  196.279938] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  197.115153] [drm:intel_dp_link_down], 
>[  197.167192] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  197.219225] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  197.270466] [drm:intel_update_fbc], no output, disabling
>[  197.270495] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  197.270505] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  197.270513] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  197.270522] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  197.270532] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  197.270541] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  197.270550] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  197.270559] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  197.270568] [drm:check_crtc_state], [CRTC:3]
>[  197.270576] [drm:check_crtc_state], [CRTC:5]
>[  197.270583] [drm:check_shared_dpll_state], PCH DPLL A
>[  197.270594] [drm:check_shared_dpll_state], PCH DPLL B
>[  197.274849] [drm:drm_mode_addfb2], [FB:32]
>[  197.274864] [drm:drm_mode_addfb2], [FB:33]
>[  197.274872] [drm:drm_mode_setcrtc], [CRTC:5]
>[  197.274880] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  197.274886] [drm:intel_crtc_set_config], [CRTC:5] [FB:32] #connectors=1 (x y) (0 0)
>[  197.274894] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  197.274899] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  197.274905] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:5]
>[  197.274911] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  197.274917] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  197.274997] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  197.275003] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  197.275010] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  197.275017] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  197.275024] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  197.275030] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  197.275095] [drm:intel_dump_pipe_config], [CRTC:5][modeset] config for pipe B
>[  197.275101] [drm:intel_dump_pipe_config], cpu_transcoder: B
>[  197.275106] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  197.275112] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  197.275119] [drm:intel_dump_pipe_config], requested mode:
>[  197.275124] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  197.275132] [drm:intel_dump_pipe_config], adjusted mode:
>[  197.275137] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  197.275145] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  197.275151] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  197.275157] [drm:intel_dump_pipe_config], ips: 0
>[  197.286374] [drm:ironlake_update_plane], Writing base 038CF000 00000000 0 0 5504
>[  197.286394] [drm:intel_update_fbc], no output, disabling
>[  197.286405] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  197.286413] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  197.286419] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  197.286928] [drm:ironlake_update_wm], FIFO watermarks For pipe B - plane 4, cursor: 6
>[  197.286936] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  197.286944] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  197.286954] [drm:ironlake_edp_pll_on], 
>[  197.339360] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  197.391392] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  197.391404] [drm:intel_update_fbc], fbc set to per-chip default
>[  197.391408] [drm:intel_update_fbc], fbc disabled per module param
>[  197.391414] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  197.391421] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  197.391428] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  197.391441] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  197.391446] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  197.693016] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  197.693614] [drm:intel_dp_start_link_train], clock recovery OK
>[  197.693619] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  197.693624] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  197.693629] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  197.693638] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  197.693643] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  198.034736] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  198.034753] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  198.085826] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  198.086776] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  198.086935] [drm:ironlake_edp_backlight_on], 
>[  198.127861] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  198.137864] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  198.137890] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  198.137899] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  198.137905] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  198.137913] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  198.137921] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  198.137928] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  198.137936] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  198.137944] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  198.137952] [drm:check_crtc_state], [CRTC:3]
>[  198.137958] [drm:check_crtc_state], [CRTC:5]
>[  198.137972] [drm:check_shared_dpll_state], PCH DPLL A
>[  198.137984] [drm:check_shared_dpll_state], PCH DPLL B
>[  198.153600] [drm:intel_update_fbc], fbc set to per-chip default
>[  198.153612] [drm:intel_update_fbc], fbc disabled per module param
>[  200.221297] [drm:ironlake_irq_handler], Pipe B FIFO underrun
>[  205.218730] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  205.218746] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  205.218754] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  205.218761] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  205.218770] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  205.218779] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  205.218794] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  205.218803] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  205.218816] [drm:ironlake_edp_backlight_off], 
>[  205.419548] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  205.419558] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  205.419563] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  206.305827] [drm:intel_dp_link_down], 
>[  206.357858] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  206.409955] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  206.461190] [drm:intel_update_fbc], no output, disabling
>[  206.461210] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  206.461215] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  206.461218] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  206.461221] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  206.461225] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  206.461229] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  206.461233] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  206.461236] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  206.461240] [drm:check_crtc_state], [CRTC:3]
>[  206.461243] [drm:check_crtc_state], [CRTC:5]
>[  206.461246] [drm:check_shared_dpll_state], PCH DPLL A
>[  206.461252] [drm:check_shared_dpll_state], PCH DPLL B
>[  206.463785] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.463791] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.463796] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  206.463800] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  206.463804] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  206.463807] [drm:intel_crt_detect], CRT not detected via hotplug
>[  206.463987] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  206.464004] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.464013] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  206.464021] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  206.464387] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.464391] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  206.464394] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  206.464398] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  206.464405] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  206.464407] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  206.464411] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  206.464414] [drm:intel_crt_detect], CRT not detected via hotplug
>[  206.464578] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  206.464586] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.464591] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  206.464596] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  206.464967] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.464973] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  206.464977] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  206.464981] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  206.464990] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.464997] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.465005] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  206.465009] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  206.465016] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  206.465020] [drm:intel_crt_detect], CRT not detected via hotplug
>[  206.465195] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  206.465205] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.465211] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  206.465216] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  206.465578] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.465581] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  206.465584] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  206.465587] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  206.465591] [drm:drm_mode_getconnector], [CONNECTOR:7:?]
>[  206.465594] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1]
>[  206.465598] [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40018, result 0
>[  206.465601] [drm:intel_crt_detect], CRT not detected via hotplug
>[  206.465772] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1)
>[  206.465784] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.465789] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging
>[  206.465795] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1
>[  206.466167] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga
>[  206.466171] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0
>[  206.466173] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found]
>[  206.466176] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:7:VGA-1] disconnected
>[  206.466186] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.466190] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.466194] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  206.466197] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1]
>[  206.466361] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  206.466370] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  206.466377] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected
>[  206.466386] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  206.466392] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1]
>[  206.466563] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  206.466571] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  206.466578] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected
>[  206.466589] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.466597] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.466605] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  206.466611] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1]
>[  206.466781] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  206.466790] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  206.466796] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected
>[  206.466805] [drm:drm_mode_getconnector], [CONNECTOR:19:?]
>[  206.466811] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1]
>[  206.466987] [drm:gmbus_xfer], GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  206.466998] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpb
>[  206.467005] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:19:HDMI-A-1] disconnected
>[  206.467019] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467027] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467036] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  206.467042] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  206.467050] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected
>[  206.467057] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  206.467062] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  206.467069] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected
>[  206.467077] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467085] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467093] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  206.467098] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  206.467106] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected
>[  206.467113] [drm:drm_mode_getconnector], [CONNECTOR:21:?]
>[  206.467118] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1]
>[  206.467124] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:21:DP-1] disconnected
>[  206.467133] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467140] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467151] [drm:drm_mode_getconnector], [CONNECTOR:23:?]
>[  206.467154] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2]
>[  206.467315] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  206.467322] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  206.467326] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2] disconnected
>[  206.467333] [drm:drm_mode_getconnector], [CONNECTOR:23:?]
>[  206.467337] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2]
>[  206.467504] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  206.467509] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  206.467512] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2] disconnected
>[  206.467518] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467522] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467526] [drm:drm_mode_getconnector], [CONNECTOR:23:?]
>[  206.467529] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2]
>[  206.467701] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  206.467710] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  206.467717] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2] disconnected
>[  206.467725] [drm:drm_mode_getconnector], [CONNECTOR:23:?]
>[  206.467731] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2]
>[  206.467901] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  206.467925] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
>[  206.467944] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:23:HDMI-A-2] disconnected
>[  206.467972] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467983] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.467989] [drm:drm_mode_getconnector], [CONNECTOR:25:?]
>[  206.467993] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3]
>[  206.468160] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1)
>[  206.468165] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd
>[  206.468168] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3] disconnected
>[  206.468173] [drm:drm_mode_getconnector], [CONNECTOR:25:?]
>[  206.468176] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3]
>[  206.468344] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1)
>[  206.468354] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd
>[  206.468361] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3] disconnected
>[  206.468375] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468384] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468392] [drm:drm_mode_getconnector], [CONNECTOR:25:?]
>[  206.468398] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3]
>[  206.468568] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1)
>[  206.468578] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd
>[  206.468584] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3] disconnected
>[  206.468593] [drm:drm_mode_getconnector], [CONNECTOR:25:?]
>[  206.468599] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3]
>[  206.468770] [drm:gmbus_xfer], GMBUS [i915 gmbus dpd] NAK for addr: 0050 r(1)
>[  206.468779] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpd
>[  206.468785] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:25:HDMI-A-3] disconnected
>[  206.468796] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468804] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468812] [drm:drm_mode_getconnector], [CONNECTOR:27:?]
>[  206.468818] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2]
>[  206.468826] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2] disconnected
>[  206.468833] [drm:drm_mode_getconnector], [CONNECTOR:27:?]
>[  206.468839] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2]
>[  206.468846] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2] disconnected
>[  206.468856] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468859] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468864] [drm:drm_mode_getconnector], [CONNECTOR:27:?]
>[  206.468867] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2]
>[  206.468871] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2] disconnected
>[  206.468874] [drm:drm_mode_getconnector], [CONNECTOR:27:?]
>[  206.468877] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2]
>[  206.468880] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:DP-2] disconnected
>[  206.468884] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468888] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468892] [drm:drm_mode_getconnector], [CONNECTOR:29:?]
>[  206.468895] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3]
>[  206.468899] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3] disconnected
>[  206.468902] [drm:drm_mode_getconnector], [CONNECTOR:29:?]
>[  206.468904] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3]
>[  206.468908] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3] disconnected
>[  206.468923] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468933] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  206.468942] [drm:drm_mode_getconnector], [CONNECTOR:29:?]
>[  206.468950] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3]
>[  206.468959] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3] disconnected
>[  206.468963] [drm:drm_mode_getconnector], [CONNECTOR:29:?]
>[  206.468966] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3]
>[  206.468970] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:29:DP-3] disconnected
>[  206.468994] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  206.468996] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  206.468997] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  206.469000] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  206.469003] [drm:drm_mode_debug_printmodeline], Modeline 30:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  206.469004] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  206.469005] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  206.469006] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  206.469008] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  206.469010] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  206.469011] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  206.469013] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  206.469015] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  206.469016] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  206.469018] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  206.469020] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  206.469020] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  206.469021] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  206.469023] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  206.469024] [drm:intel_dump_pipe_config], requested mode:
>[  206.469026] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  206.469027] [drm:intel_dump_pipe_config], adjusted mode:
>[  206.469029] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  206.469030] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  206.469031] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  206.469032] [drm:intel_dump_pipe_config], ips: 0
>[  206.469053] [drm:ironlake_update_plane], Writing base 00047000 00000000 0 0 5504
>[  206.469056] [drm:intel_update_fbc], no output, disabling
>[  206.469060] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  206.469062] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  206.469063] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  206.469566] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  206.469570] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  206.469572] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  206.469576] [drm:ironlake_edp_pll_on], 
>[  206.520988] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  206.573026] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  206.573029] [drm:intel_update_fbc], fbc set to per-chip default
>[  206.573031] [drm:intel_update_fbc], fbc disabled per module param
>[  206.573034] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  206.573039] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  206.573046] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  206.573054] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  206.573058] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  206.874669] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  206.875264] [drm:intel_dp_start_link_train], clock recovery OK
>[  206.875265] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  206.875268] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  206.875273] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  206.875279] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  206.875284] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  207.216381] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  207.216389] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  207.267409] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  207.268297] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  207.268449] [drm:ironlake_edp_backlight_on], 
>[  207.269143] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  207.309449] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  207.319528] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  207.319542] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  207.319547] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  207.319550] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  207.319554] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  207.319559] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  207.319563] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  207.319567] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  207.319572] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  207.319576] [drm:check_crtc_state], [CRTC:3]
>[  207.319586] [drm:check_crtc_state], [CRTC:5]
>[  207.319588] [drm:check_shared_dpll_state], PCH DPLL A
>[  207.319595] [drm:check_shared_dpll_state], PCH DPLL B
>[  207.319602] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  207.319607] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  207.319612] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  207.319616] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  207.319636] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  207.319640] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  207.575490] [drm:i915_driver_open], 
>[  207.577820] [drm:i915_driver_open], 
>[  207.617584] [drm:intel_crtc_cursor_set], cursor off
>[  207.620855] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  207.624297] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  207.627720] [drm:intel_crtc_cursor_set], cursor off
>[  207.629576] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  207.632961] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.767992] [drm:i915_driver_open], 
>[  211.771519] [drm:intel_crtc_cursor_set], cursor off
>[  211.775006] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  211.778574] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.782120] [drm:intel_crtc_cursor_set], cursor off
>[  211.785652] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  211.788848] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.792302] [drm:i915_driver_open], 
>[  211.796008] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796025] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796042] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796051] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796060] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  211.796068] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  211.796074] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  211.796088] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  211.796299] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  211.796471] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  211.796479] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  211.796494] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  211.796501] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  211.796505] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  211.796510] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  211.796520] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  211.796530] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796535] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  211.796609] [drm:drm_mode_addfb2], [FB:32]
>[  211.796617] [drm:drm_mode_addfb2], [FB:33]
>[  211.796623] [drm:drm_mode_setcrtc], [CRTC:3]
>[  211.796628] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  211.796632] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  211.796638] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  211.796642] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  211.796713] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  211.796718] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  211.796722] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  211.796726] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  211.796730] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  211.796734] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  211.796737] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  211.796741] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  211.796744] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  211.796748] [drm:intel_dump_pipe_config], requested mode:
>[  211.796751] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  211.796756] [drm:intel_dump_pipe_config], adjusted mode:
>[  211.796759] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  211.796764] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  211.796768] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  211.796771] [drm:intel_dump_pipe_config], ips: 0
>[  211.796775] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  211.796780] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  211.796785] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  211.796792] [drm:ironlake_edp_backlight_off], 
>[  211.997554] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  211.997563] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  211.997569] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
>[  212.785888] [drm:intel_dp_link_down], 
>[  212.837919] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  212.889161] [drm:intel_update_fbc], no output, disabling
>[  212.896040] [drm:ironlake_update_plane], Writing base 00450000 00000000 0 0 2752
>[  212.896055] [drm:intel_update_fbc], no output, disabling
>[  212.896066] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  212.896074] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  212.896080] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  212.896588] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 4
>[  212.896593] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4
>[  212.896598] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4
>[  212.896604] [drm:ironlake_edp_pll_on], 
>[  212.948979] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  213.001013] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  213.001024] [drm:intel_update_fbc], fbc set to per-chip default
>[  213.001028] [drm:intel_update_fbc], fbc disabled per module param
>[  213.001034] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  213.001042] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  213.001048] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  213.001060] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  213.001066] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  213.302635] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  213.303233] [drm:intel_dp_start_link_train], clock recovery OK
>[  213.303238] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  213.303242] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  213.303247] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  213.303256] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  213.303261] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  213.644416] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  213.644433] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  213.695445] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  213.696395] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  213.696551] [drm:ironlake_edp_backlight_on], 
>[  213.737403] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  213.747413] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  213.747437] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  213.747447] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  213.747456] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  213.747465] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  213.747474] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  213.747483] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  213.747493] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  213.747502] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  213.747512] [drm:check_crtc_state], [CRTC:3]
>[  213.747527] [drm:check_crtc_state], [CRTC:5]
>[  213.747534] [drm:check_shared_dpll_state], PCH DPLL A
>[  213.747545] [drm:check_shared_dpll_state], PCH DPLL B
>[  213.763222] [drm:intel_update_fbc], fbc set to per-chip default
>[  213.763234] [drm:intel_update_fbc], fbc disabled per module param
>[  222.092872] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  222.092892] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  222.092897] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  222.092903] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  222.092909] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  222.092916] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  222.092932] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  222.092937] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  222.092943] [drm:ironlake_edp_backlight_off], 
>[  222.293909] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  222.293920] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  222.293925] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  223.098241] [drm:intel_dp_link_down], 
>[  223.150272] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  223.201509] [drm:intel_update_fbc], no output, disabling
>[  223.201535] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  223.201541] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  223.201547] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  223.201553] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  223.201559] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  223.201566] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  223.201571] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  223.201578] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  223.201584] [drm:check_crtc_state], [CRTC:3]
>[  223.201590] [drm:check_crtc_state], [CRTC:5]
>[  223.201594] [drm:check_shared_dpll_state], PCH DPLL A
>[  223.201603] [drm:check_shared_dpll_state], PCH DPLL B
>[  223.203570] [drm:drm_mode_addfb2], could not create framebuffer
>[  223.203649] [drm:drm_mode_addfb2], [FB:32]
>[  223.203661] [drm:drm_mode_addfb2], [FB:33]
>[  223.203736] [drm:drm_mode_setcrtc], [CRTC:3]
>[  223.203741] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  223.203743] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  223.203755] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  223.203760] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  223.203766] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  223.203818] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  223.203824] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  223.203831] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  223.203837] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  223.203843] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  223.203850] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  223.203856] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  223.203863] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  223.203869] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  223.203875] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  223.203880] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  223.203886] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  223.203893] [drm:intel_dump_pipe_config], requested mode:
>[  223.203898] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  223.203906] [drm:intel_dump_pipe_config], adjusted mode:
>[  223.203911] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  223.203919] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  223.203925] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  223.203931] [drm:intel_dump_pipe_config], ips: 0
>[  223.215010] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[  223.215030] [drm:intel_update_fbc], no output, disabling
>[  223.215040] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  223.215048] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  223.215054] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  223.215564] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  223.215572] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  223.215580] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  223.215591] [drm:ironlake_edp_pll_on], 
>[  223.267341] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  223.319381] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  223.319395] [drm:intel_update_fbc], fbc set to per-chip default
>[  223.319400] [drm:intel_update_fbc], fbc disabled per module param
>[  223.319407] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  223.319415] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  223.319423] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  223.319437] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  223.319445] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  223.620987] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  223.621589] [drm:intel_dp_start_link_train], clock recovery OK
>[  223.621594] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  223.621598] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  223.621603] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  223.621612] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  223.621618] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  223.962790] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  223.962809] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  224.013807] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  224.014714] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  224.014874] [drm:ironlake_edp_backlight_on], 
>[  224.055840] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  224.065841] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  224.065867] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  224.065876] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  224.065883] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  224.065890] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  224.065898] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  224.065906] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  224.065912] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  224.065921] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  224.065929] [drm:check_crtc_state], [CRTC:3]
>[  224.065943] [drm:check_crtc_state], [CRTC:5]
>[  224.065949] [drm:check_shared_dpll_state], PCH DPLL A
>[  224.065958] [drm:check_shared_dpll_state], PCH DPLL B
>[  224.081474] [drm:intel_update_fbc], fbc set to per-chip default
>[  224.081485] [drm:intel_update_fbc], fbc disabled per module param
>[  231.228433] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  231.228453] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  231.228458] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  231.228464] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  231.228469] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  231.228476] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  231.228489] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  231.228499] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  231.228507] [drm:ironlake_edp_backlight_off], 
>[  231.429593] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  231.429603] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  231.429609] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  232.282902] [drm:intel_dp_link_down], 
>[  232.334935] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  232.386170] [drm:intel_update_fbc], no output, disabling
>[  232.386197] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  232.386204] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  232.386210] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  232.386216] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  232.386222] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  232.386229] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  232.386235] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  232.386241] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  232.386246] [drm:check_crtc_state], [CRTC:3]
>[  232.386252] [drm:check_crtc_state], [CRTC:5]
>[  232.386257] [drm:check_shared_dpll_state], PCH DPLL A
>[  232.386265] [drm:check_shared_dpll_state], PCH DPLL B
>[  232.390307] [drm:drm_mode_addfb2], [FB:32]
>[  232.390322] [drm:drm_mode_addfb2], [FB:33]
>[  232.390330] [drm:drm_mode_setcrtc], [CRTC:3]
>[  232.390338] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  232.390344] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  232.390352] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  232.390358] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  232.390363] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  232.390433] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  232.390447] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  232.390455] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  232.390461] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  232.390467] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  232.390474] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  232.390481] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  232.390487] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  232.390493] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  232.390499] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  232.390504] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  232.390509] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  232.390516] [drm:intel_dump_pipe_config], requested mode:
>[  232.390521] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  232.390529] [drm:intel_dump_pipe_config], adjusted mode:
>[  232.390535] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  232.390542] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  232.390548] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  232.390555] [drm:intel_dump_pipe_config], ips: 0
>[  232.401842] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[  232.401860] [drm:intel_update_fbc], no output, disabling
>[  232.401871] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  232.401879] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  232.401884] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  232.402394] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  232.402404] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  232.402412] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  232.402422] [drm:ironlake_edp_pll_on], 
>[  232.454003] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  232.506035] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  232.506046] [drm:intel_update_fbc], fbc set to per-chip default
>[  232.506051] [drm:intel_update_fbc], fbc disabled per module param
>[  232.506057] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  232.506064] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  232.506070] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  232.506082] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  232.506088] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  232.807639] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  232.808240] [drm:intel_dp_start_link_train], clock recovery OK
>[  232.808245] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  232.808249] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  232.808255] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  232.808265] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  232.808270] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  233.149439] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  233.149456] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  233.200486] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  233.201449] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  233.201606] [drm:ironlake_edp_backlight_on], 
>[  233.242502] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  233.252506] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  233.252534] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  233.252543] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  233.252549] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  233.252558] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  233.252566] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  233.252573] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  233.252580] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  233.252588] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  233.252595] [drm:check_crtc_state], [CRTC:3]
>[  233.252609] [drm:check_crtc_state], [CRTC:5]
>[  233.252615] [drm:check_shared_dpll_state], PCH DPLL A
>[  233.252624] [drm:check_shared_dpll_state], PCH DPLL B
>[  233.268273] [drm:intel_update_fbc], fbc set to per-chip default
>[  233.268285] [drm:intel_update_fbc], fbc disabled per module param
>[  242.236290] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  242.236308] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  242.236314] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  242.236319] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  242.236325] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  242.236332] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  242.236346] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  242.236353] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  242.236361] [drm:ironlake_edp_backlight_off], 
>[  242.437368] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  242.437378] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  242.437385] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  243.269609] [drm:intel_dp_link_down], 
>[  243.321639] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  243.372879] [drm:intel_update_fbc], no output, disabling
>[  243.372907] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  243.372917] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  243.372926] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  243.372935] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  243.372944] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  243.372954] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  243.372963] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  243.372973] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  243.372981] [drm:check_crtc_state], [CRTC:3]
>[  243.372989] [drm:check_crtc_state], [CRTC:5]
>[  243.372997] [drm:check_shared_dpll_state], PCH DPLL A
>[  243.373008] [drm:check_shared_dpll_state], PCH DPLL B
>[  243.377258] [drm:drm_mode_addfb2], [FB:32]
>[  243.377274] [drm:drm_mode_addfb2], [FB:33]
>[  243.377281] [drm:drm_mode_setcrtc], [CRTC:3]
>[  243.377289] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  243.377295] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  243.377303] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  243.377309] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  243.377314] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  243.377320] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  243.377326] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  243.377406] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  243.377412] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  243.377419] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  243.377425] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  243.377432] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  243.377438] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  243.377504] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  243.377510] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  243.377515] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  243.377520] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  243.377527] [drm:intel_dump_pipe_config], requested mode:
>[  243.377532] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  243.377540] [drm:intel_dump_pipe_config], adjusted mode:
>[  243.377545] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  243.377553] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  243.377560] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  243.377565] [drm:intel_dump_pipe_config], ips: 0
>[  243.388700] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 5504
>[  243.388719] [drm:intel_update_fbc], no output, disabling
>[  243.388730] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  243.388738] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  243.388744] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  243.389252] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  243.389260] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  243.389268] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  243.389278] [drm:ironlake_edp_pll_on], 
>[  243.440775] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  243.492806] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  243.492818] [drm:intel_update_fbc], fbc set to per-chip default
>[  243.492822] [drm:intel_update_fbc], fbc disabled per module param
>[  243.492828] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  243.492835] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  243.492842] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  243.492853] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  243.492859] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  243.794425] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  243.795026] [drm:intel_dp_start_link_train], clock recovery OK
>[  243.795030] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  243.795035] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  243.795040] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  243.795050] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  243.795055] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  244.136145] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  244.136165] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  244.187177] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  244.188150] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  244.188309] [drm:ironlake_edp_backlight_on], 
>[  244.229199] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  244.239277] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  244.239304] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  244.239313] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  244.239319] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  244.239327] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  244.239334] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  244.239342] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  244.239349] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  244.239356] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  244.239363] [drm:check_crtc_state], [CRTC:3]
>[  244.239377] [drm:check_crtc_state], [CRTC:5]
>[  244.239384] [drm:check_shared_dpll_state], PCH DPLL A
>[  244.239394] [drm:check_shared_dpll_state], PCH DPLL B
>[  244.254907] [drm:intel_update_fbc], fbc set to per-chip default
>[  244.254917] [drm:intel_update_fbc], fbc disabled per module param
>[  251.401875] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  251.401894] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  251.401899] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  251.401904] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  251.401910] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  251.401921] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  251.401937] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  251.401942] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  251.401948] [drm:ironlake_edp_backlight_off], 
>[  251.602974] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  251.602984] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  251.602989] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  252.473347] [drm:intel_dp_link_down], 
>[  252.525379] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  252.576615] [drm:intel_update_fbc], no output, disabling
>[  252.576643] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  252.576650] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  252.576656] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  252.576662] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  252.576668] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  252.576674] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  252.576682] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  252.576687] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  252.576693] [drm:check_crtc_state], [CRTC:3]
>[  252.576699] [drm:check_crtc_state], [CRTC:5]
>[  252.576703] [drm:check_shared_dpll_state], PCH DPLL A
>[  252.576713] [drm:check_shared_dpll_state], PCH DPLL B
>[  252.580750] [drm:drm_mode_addfb2], [FB:32]
>[  252.580773] [drm:drm_mode_addfb2], [FB:33]
>[  252.580784] [drm:drm_mode_setcrtc], [CRTC:3]
>[  252.580795] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  252.580803] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  252.580888] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  252.580896] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  252.580901] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  252.580910] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  252.580918] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  252.580924] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  252.580930] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  252.580936] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  252.580943] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  252.580950] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  252.580957] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  252.580963] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  252.580970] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  252.580976] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  252.580982] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  252.580987] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  252.580992] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  252.580999] [drm:intel_dump_pipe_config], requested mode:
>[  252.581004] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  252.581012] [drm:intel_dump_pipe_config], adjusted mode:
>[  252.581017] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  252.581025] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  252.581031] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  252.581037] [drm:intel_dump_pipe_config], ips: 0
>[  252.587734] [drm:ironlake_update_plane], Writing base 0085A000 00000000 0 0 2752
>[  252.587748] [drm:intel_update_fbc], no output, disabling
>[  252.587758] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  252.587765] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  252.587771] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  252.588279] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 4
>[  252.588287] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4
>[  252.588295] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4
>[  252.588304] [drm:ironlake_edp_pll_on], 
>[  252.640445] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  252.692476] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  252.692488] [drm:intel_update_fbc], fbc set to per-chip default
>[  252.692493] [drm:intel_update_fbc], fbc disabled per module param
>[  252.692499] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  252.692506] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  252.692512] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  252.692524] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  252.692530] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  252.994092] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  252.994690] [drm:intel_dp_start_link_train], clock recovery OK
>[  252.994695] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  252.994699] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  252.994704] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  252.994713] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  252.994718] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  253.335880] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  253.335897] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  253.386904] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  253.387859] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  253.388017] [drm:ironlake_edp_backlight_on], 
>[  253.428946] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  253.438944] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  253.438967] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  253.438976] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  253.438982] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  253.438990] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  253.438997] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  253.439005] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  253.439012] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  253.439020] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  253.439027] [drm:check_crtc_state], [CRTC:3]
>[  253.439040] [drm:check_crtc_state], [CRTC:5]
>[  253.439046] [drm:check_shared_dpll_state], PCH DPLL A
>[  253.439055] [drm:check_shared_dpll_state], PCH DPLL B
>[  253.454622] [drm:intel_update_fbc], fbc set to per-chip default
>[  253.454634] [drm:intel_update_fbc], fbc disabled per module param
>[  255.222707] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  261.764276] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  261.764292] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  261.764298] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  261.764302] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  261.764308] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  261.764315] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  261.764329] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  261.764336] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  261.764344] [drm:ironlake_edp_backlight_off], 
>[  261.965406] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  261.965416] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  261.965421] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  262.755683] [drm:intel_dp_link_down], 
>[  262.807715] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  262.858935] [drm:intel_update_fbc], no output, disabling
>[  262.858954] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  262.858958] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  262.858961] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  262.858965] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  262.858969] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  262.858972] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  262.858976] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  262.858980] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  262.858984] [drm:check_crtc_state], [CRTC:3]
>[  262.858987] [drm:check_crtc_state], [CRTC:5]
>[  262.858990] [drm:check_shared_dpll_state], PCH DPLL A
>[  262.858996] [drm:check_shared_dpll_state], PCH DPLL B
>[  262.860434] [drm:drm_mode_addfb2], could not create framebuffer
>[  262.860468] [drm:drm_mode_addfb2], [FB:32]
>[  262.860474] [drm:drm_mode_addfb2], [FB:33]
>[  262.860541] [drm:drm_mode_setcrtc], [CRTC:3]
>[  262.860545] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  262.860548] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  262.860552] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  262.860554] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  262.860557] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  262.860560] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  262.860563] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  262.860567] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  262.860570] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  262.860573] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  262.860577] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  262.860580] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  262.860586] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  262.860589] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  262.860592] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  262.860594] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  262.860597] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  262.860601] [drm:intel_dump_pipe_config], requested mode:
>[  262.860603] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  262.860607] [drm:intel_dump_pipe_config], adjusted mode:
>[  262.860609] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  262.860613] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  262.860615] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  262.860618] [drm:intel_dump_pipe_config], ips: 0
>[  262.870144] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[  262.870157] [drm:intel_update_fbc], no output, disabling
>[  262.870164] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  262.870169] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  262.870172] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  262.870694] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  262.870702] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  262.870708] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  262.870714] [drm:ironlake_edp_pll_on], 
>[  262.922748] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  262.975866] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  262.975877] [drm:intel_update_fbc], fbc set to per-chip default
>[  262.975882] [drm:intel_update_fbc], fbc disabled per module param
>[  262.975888] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  262.975895] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  262.975901] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  262.975914] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  262.975920] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  263.277433] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  263.278031] [drm:intel_dp_start_link_train], clock recovery OK
>[  263.278036] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  263.278041] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  263.278046] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  263.278055] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  263.278060] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  263.619217] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  263.619234] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  263.670247] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  263.671199] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  263.671357] [drm:ironlake_edp_backlight_on], 
>[  263.672053] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  263.712284] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  263.722255] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  263.722282] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  263.722290] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  263.722297] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  263.722304] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  263.722312] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  263.722319] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  263.722328] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  263.722335] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  263.722342] [drm:check_crtc_state], [CRTC:3]
>[  263.722355] [drm:check_crtc_state], [CRTC:5]
>[  263.722361] [drm:check_shared_dpll_state], PCH DPLL A
>[  263.722371] [drm:check_shared_dpll_state], PCH DPLL B
>[  263.738010] [drm:intel_update_fbc], fbc set to per-chip default
>[  263.738021] [drm:intel_update_fbc], fbc disabled per module param
>[  270.803171] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  270.803191] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  270.803197] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  270.803202] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  270.803210] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  270.803217] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  270.803229] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  270.803236] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  270.803244] [drm:ironlake_edp_backlight_off], 
>[  271.003931] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  271.003940] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  271.003946] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  271.855293] [drm:intel_dp_link_down], 
>[  271.907323] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  271.958561] [drm:intel_update_fbc], no output, disabling
>[  271.958588] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  271.958595] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  271.958601] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  271.958607] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  271.958613] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  271.958619] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  271.958625] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  271.958631] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  271.958637] [drm:check_crtc_state], [CRTC:3]
>[  271.958642] [drm:check_crtc_state], [CRTC:5]
>[  271.958647] [drm:check_shared_dpll_state], PCH DPLL A
>[  271.958655] [drm:check_shared_dpll_state], PCH DPLL B
>[  271.962609] [drm:drm_mode_addfb2], [FB:32]
>[  271.962624] [drm:drm_mode_addfb2], [FB:33]
>[  271.962632] [drm:drm_mode_setcrtc], [CRTC:3]
>[  271.962640] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  271.962646] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  271.962654] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  271.962660] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  271.962665] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  271.962671] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  271.962750] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  271.962758] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  271.962764] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  271.962770] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  271.962777] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  271.962784] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  271.962790] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  271.962796] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  271.962802] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  271.962807] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  271.962813] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  271.962876] [drm:intel_dump_pipe_config], requested mode:
>[  271.962883] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  271.962894] [drm:intel_dump_pipe_config], adjusted mode:
>[  271.962901] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  271.962912] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  271.962918] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  271.962923] [drm:intel_dump_pipe_config], ips: 0
>[  271.974211] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[  271.974229] [drm:intel_update_fbc], no output, disabling
>[  271.974240] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  271.974248] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  271.974254] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  271.974764] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  271.974773] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  271.974781] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  271.974791] [drm:ironlake_edp_pll_on], 
>[  272.026393] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.078425] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  272.078436] [drm:intel_update_fbc], fbc set to per-chip default
>[  272.078441] [drm:intel_update_fbc], fbc disabled per module param
>[  272.078447] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  272.078454] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  272.078460] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  272.078474] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  272.078480] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  272.380042] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  272.380640] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  272.381229] [drm:intel_dp_start_link_train], clock recovery OK
>[  272.381233] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  272.381238] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  272.381243] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  272.381253] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  272.381258] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  272.721828] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  272.721845] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  272.772857] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  272.773825] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  272.773982] [drm:ironlake_edp_backlight_on], 
>[  272.774677] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  272.814882] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  272.824889] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  272.824914] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  272.824922] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  272.824927] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  272.824933] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  272.824940] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  272.824946] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  272.824952] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  272.824958] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  272.824964] [drm:check_crtc_state], [CRTC:3]
>[  272.824976] [drm:check_crtc_state], [CRTC:5]
>[  272.824981] [drm:check_shared_dpll_state], PCH DPLL A
>[  272.824990] [drm:check_shared_dpll_state], PCH DPLL B
>[  272.840682] [drm:intel_update_fbc], fbc set to per-chip default
>[  272.840692] [drm:intel_update_fbc], fbc disabled per module param
>[  281.810698] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  281.810718] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  281.810724] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  281.810729] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  281.810735] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  281.810741] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  281.810761] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  281.810766] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  281.810773] [drm:ironlake_edp_backlight_off], 
>[  282.011696] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  282.011706] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  282.011712] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  282.858074] [drm:intel_dp_link_down], 
>[  282.910105] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  282.961328] [drm:intel_update_fbc], no output, disabling
>[  282.961355] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  282.961362] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  282.961368] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  282.961375] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  282.961381] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  282.961386] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  282.961392] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  282.961398] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  282.961404] [drm:check_crtc_state], [CRTC:3]
>[  282.961410] [drm:check_crtc_state], [CRTC:5]
>[  282.961414] [drm:check_shared_dpll_state], PCH DPLL A
>[  282.961423] [drm:check_shared_dpll_state], PCH DPLL B
>[  282.965184] [drm:drm_mode_addfb2], [FB:32]
>[  282.965198] [drm:drm_mode_addfb2], [FB:33]
>[  282.965206] [drm:drm_mode_setcrtc], [CRTC:3]
>[  282.965214] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  282.965220] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  282.965228] [drm:intel_set_config_compute_mode_changes], crtc has no fb, full mode set
>[  282.965234] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  282.965239] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  282.965245] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  282.965324] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  282.965332] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  282.965338] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  282.965344] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  282.965351] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  282.965358] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  282.965364] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  282.965370] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  282.965376] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  282.965381] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  282.965458] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  282.965464] [drm:intel_dump_pipe_config], requested mode:
>[  282.965470] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  282.965478] [drm:intel_dump_pipe_config], adjusted mode:
>[  282.965483] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 69000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  282.965490] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  282.965497] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  282.965502] [drm:intel_dump_pipe_config], ips: 0
>[  282.976158] [drm:ironlake_update_plane], Writing base 01881000 00000000 0 0 5504
>[  282.976176] [drm:intel_update_fbc], no output, disabling
>[  282.976187] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  282.976194] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  282.976200] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  282.976710] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  282.976718] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  282.976726] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  282.976736] [drm:ironlake_edp_pll_on], 
>[  283.029174] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  283.081207] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  283.081219] [drm:intel_update_fbc], fbc set to per-chip default
>[  283.081223] [drm:intel_update_fbc], fbc disabled per module param
>[  283.081229] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  283.081237] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  283.081244] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  283.081256] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  283.081261] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  283.382811] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  283.383411] [drm:intel_dp_start_link_train], clock recovery OK
>[  283.383416] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  283.383420] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  283.383425] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  283.383435] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  283.383440] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  283.724609] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  283.724626] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  283.775639] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  283.776591] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  283.776750] [drm:ironlake_edp_backlight_on], 
>[  283.777444] [drm:ironlake_irq_handler], Pipe A FIFO underrun
>[  283.817673] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  283.827676] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  283.827703] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  283.827711] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  283.827718] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  283.827725] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  283.827733] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  283.827740] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  283.827749] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  283.827755] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  283.827763] [drm:check_crtc_state], [CRTC:3]
>[  283.827776] [drm:check_crtc_state], [CRTC:5]
>[  283.827783] [drm:check_shared_dpll_state], PCH DPLL A
>[  283.827793] [drm:check_shared_dpll_state], PCH DPLL B
>[  283.843352] [drm:intel_update_fbc], fbc set to per-chip default
>[  283.843361] [drm:intel_update_fbc], fbc disabled per module param
>[  290.985547] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  290.985566] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  290.985571] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  290.985576] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  290.985582] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  290.985592] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  290.985607] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  290.985613] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  290.985619] [drm:ironlake_edp_backlight_off], 
>[  291.186370] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  291.186380] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  291.186386] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000

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Attachments on bug 67243: 82900 | 83957 | 84898 | 84929 | 85064 | 85190 | 85229 | 85244 | 85246 | 85305

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