Attachment 84274 Details for Bug 64850 – possible fix 2/2

[patch] possible fix 2/2

0003-drm-radeon-update-line-buffer-allocation-for-dce6.patch (text/plain), 2.62 KB, created by Alex Deucher on 2013-08-19 17:14:58 UTC

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Creator: Alex Deucher

Created: 2013-08-19 17:14:58 UTC

Size: 2.62 KB

patch

obsolete

>From 78bc4707a474b5cd7a67a3ec82cbd819182d1f6b Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Mon, 19 Aug 2013 11:15:43 -0400
>Subject: [PATCH 3/4] drm/radeon: update line buffer allocation for dce6
>
>We need to allocate line buffer to each display when
>setting up the watermarks.  Failure to do so can lead
>to a blank screen.  This fixes blank screen problems
>on dce6 asics.
>
>Fixes:
>https://bugs.freedesktop.org/show_bug.cgi?id=64850
>
>Based on an initial fix from:
>Jay Cornwall <jay.cornwall@amd.com>
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>Cc: stable@vger.kernel.org
>---
> drivers/gpu/drm/radeon/si.c  | 23 +++++++++++++++++++----
> drivers/gpu/drm/radeon/sid.h |  4 ++++
> 2 files changed, 23 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
>index d5f77eb..3967cbd 100644
>--- a/drivers/gpu/drm/radeon/si.c
>+++ b/drivers/gpu/drm/radeon/si.c
>@@ -1711,7 +1711,8 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
> 				   struct drm_display_mode *mode,
> 				   struct drm_display_mode *other_mode)
> {
>-	u32 tmp;
>+	u32 tmp, buffer_alloc, i;
>+	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
> 	/*
> 	 * Line Buffer Setup
> 	 * There are 3 line buffers, each one shared by 2 display controllers.
>@@ -1726,16 +1727,30 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
> 	 * non-linked crtcs for maximum line buffer allocation.
> 	 */
> 	if (radeon_crtc->base.enabled && mode) {
>-		if (other_mode)
>+		if (other_mode) {
> 			tmp = 0; /* 1/2 */
>-		else
>+			buffer_alloc = 1;
>+		} else {
> 			tmp = 2; /* whole */
>-	} else
>+			buffer_alloc = 2;
>+		}
>+	} else {
> 		tmp = 0;
>+		buffer_alloc = 0;
>+	}
> 
> 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
> 	       DC_LB_MEMORY_CONFIG(tmp));
> 
>+	WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
>+	       DMIF_BUFFERS_ALLOCATED(buffer_alloc));
>+	for (i = 0; i < rdev->usec_timeout; i++) {
>+		if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
>+		    DMIF_BUFFERS_ALLOCATED_COMPLETED)
>+			break;
>+		udelay(1);
>+	}
>+
> 	if (radeon_crtc->base.enabled && mode) {
> 		switch (tmp) {
> 		case 0:
>diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
>index 91dae16..52d2ab6 100644
>--- a/drivers/gpu/drm/radeon/sid.h
>+++ b/drivers/gpu/drm/radeon/sid.h
>@@ -282,6 +282,10 @@
> 
> #define DMIF_ADDR_CALC  				0xC00
> 
>+#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0
>+#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
>+#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
>+
> #define	SRBM_STATUS				        0xE50
> #define		GRBM_RQ_PENDING 			(1 << 5)
> #define		VMC_BUSY 				(1 << 8)
>-- 
>1.8.3.1
>

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Attachments on bug 64850: 79637 | 79638 | 79671 | 79672 | 79737 | 84273 | 84274

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