Attachment 85305 Details for Bug 67243 – dmesg with patch comment 21

dmesg with patch comment 21

dmesg_e6510_0906.txt (text/plain), 74.64 KB, created by lu hua on 2013-09-06 05:55:00 UTC

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Creator: lu hua

Created: 2013-09-06 05:55:00 UTC

Size: 74.64 KB

patch

obsolete

>[   59.890876] console [netcon0] enabled
>[   59.890919] netconsole: network logging started
>[   59.893340] netpoll: netconsole: local port 6665
>[   59.893383] netpoll: netconsole: local IPv4 address 0.0.0.0
>[   59.893429] netpoll: netconsole: interface 'em1'
>[   59.893469] netpoll: netconsole: remote port 6666
>[   59.893509] netpoll: netconsole: remote IPv4 address 10.239.47.98
>[   59.893558] netpoll: netconsole: remote ethernet address 6c:f0:49:72:82:c6
>[   59.893616] netpoll: netconsole: local IP 10.239.47.17
>[   59.893690] console [netcon0] enabled
>[   59.893723] netconsole: network logging started
>[  380.638659] [drm:drm_stub_open], 
>[  380.638710] [drm:drm_open_helper], pid = 27312, minor = 0
>[  380.638763] [drm:i915_driver_open], 
>[  380.638800] [drm:drm_setup], 
>[  380.638835] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.638895] [drm:drm_release], open_count = 1
>[  380.638935] [drm:drm_release], pid = 27312, device = 0xe200, open_count = 1
>[  380.639127] [drm:drm_lastclose], 
>[  380.639197] [drm:intel_crtc_cursor_set], cursor off
>[  380.639294] [drm:intel_crtc_set_config], [CRTC:3] [FB:31] #connectors=1 (x y) (0 0)
>[  380.639465] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[  380.639693] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  380.639838] [drm:drm_framebuffer_reference], FB ID: 31
>[  380.639939] [drm:drm_framebuffer_unreference], FB ID: 31
>[  380.640062] [drm:intel_crtc_cursor_set], cursor off
>[  380.640157] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[  380.640259] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[  380.640468] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  380.640644] [drm:drm_framebuffer_reference], FB ID: 31
>[  380.640743] [drm:drm_framebuffer_unreference], FB ID: 31
>[  380.640845] [drm:drm_lastclose], driver lastclose completed
>[  380.640950] [drm:drm_lastclose], lastclose completed
>[  380.641079] [drm:drm_stub_open], 
>[  380.641149] [drm:drm_open_helper], pid = 27312, minor = 0
>[  380.641253] [drm:i915_driver_open], 
>[  380.644646] [drm:drm_setup], 
>[  380.648015] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.651257] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_GET_APERTURE
>[  380.654541] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.657756] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.660896] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.663609] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.666644] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.669656] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.672635] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.675618] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.678554] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GETPARAM
>[  380.681482] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  380.684390] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.684400] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.684412] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.684419] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.684435] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.684442] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.684450] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.684460] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.684474] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[  380.684481] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  380.684488] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
>[  380.684495] [drm:intel_dp_detect], [CONNECTOR:10:eDP-1]
>[  380.684501] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  380.684514] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  380.684703] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
>[  380.684873] [drm:intel_dp_probe_oui], Branch OUI: 000000
>[  380.684879] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  380.684893] [drm:drm_edid_to_eld], ELD: no CEA Extension found
>[  380.684900] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
>[  380.684904] [drm:drm_mode_debug_printmodeline], Modeline 11:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  380.684909] [drm:drm_mode_debug_printmodeline], Modeline 12:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  380.684918] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
>[  380.684922] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
>[  380.684930] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETENCODER
>[  380.684935] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.684939] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.685010] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETRESOURCES
>[  380.685015] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[8] ENCODERS[8]
>[  380.685022] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_GETCRTC
>[  380.685027] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GET_PIPE_FROM_CRTC_ID
>[  380.685074] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  380.685084] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  380.685092] [drm:drm_framebuffer_reference], FB ID: 32
>[  380.685096] [drm:drm_mode_addfb2], [FB:32]
>[  380.685100] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  380.685106] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  380.685110] [drm:drm_framebuffer_reference], FB ID: 33
>[  380.685113] [drm:drm_mode_addfb2], [FB:33]
>[  380.685118] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  380.685122] [drm:drm_mode_setcrtc], [CRTC:3]
>[  380.685190] [drm:drm_framebuffer_reference], FB ID: 32
>[  380.685194] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  380.685198] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  380.685204] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  380.685208] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  380.685213] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  380.685218] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  380.685222] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  380.685226] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  380.685230] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  380.685233] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  380.685238] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  380.685242] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  380.685245] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  380.685248] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  380.685252] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  380.685256] [drm:intel_dump_pipe_config], requested mode:
>[  380.685259] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  380.685264] [drm:intel_dump_pipe_config], adjusted mode:
>[  380.685267] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  380.685272] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  380.685275] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  380.685279] [drm:intel_dump_pipe_config], ips: 0
>[  380.685282] ironlake_crtc_disable:3457
>[  380.685289] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,60)@ 380.343725 -> 380.342485 [e 1 us, 0 rep]
>[  380.685358] ironlake_crtc_disable:3461
>[  380.685360] ironlake_crtc_disable:3465
>[  380.685363] ironlake_crtc_disable:3468
>[  380.700586] ironlake_crtc_disable:3471
>[  380.700594] ironlake_crtc_disable:3475
>[  380.700599] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  380.700608] [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
>[  380.700615] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  380.700626] [drm:ironlake_edp_backlight_off], 
>[  380.901986] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  380.901996] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  380.902001] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  381.716282] ironlake_crtc_disable:3479
>[  381.718238] ironlake_crtc_disable:3482
>[  381.718247] ironlake_crtc_disable:3485
>[  381.718253] [drm:intel_dp_link_down], 
>[  381.770313] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  381.821566] ironlake_crtc_disable:3490
>[  381.821574] ironlake_crtc_disable:3518
>[  381.821579] ironlake_crtc_disable:3522
>[  381.821584] [drm:intel_update_fbc], no output, disabling
>[  381.821589] ironlake_crtc_disable:3526
>[  381.821595] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  381.828528] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 2752
>[  381.828549] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  381.828556] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  381.828562] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  381.829071] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 4
>[  381.829078] [drm:ironlake_check_srwm], watermark 1: display plane 13, fbc lines 3, cursor 4
>[  381.829085] [drm:ironlake_check_srwm], watermark 2: display plane 39, fbc lines 3, cursor 4
>[  381.829092] [drm:ironlake_edp_pll_on], 
>[  381.881378] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  381.933410] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  381.933421] [drm:intel_update_fbc], disabled per chip default
>[  381.933427] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  381.933435] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  381.933442] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  381.933454] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  381.933460] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  382.234985] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  382.235580] [drm:intel_dp_start_link_train], clock recovery OK
>[  382.235585] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  382.235589] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  382.235595] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  382.235604] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  382.235609] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  382.576812] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  382.576829] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  382.627834] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  382.628778] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  382.628935] [drm:ironlake_edp_backlight_on], 
>[  382.669877] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  382.679875] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  382.679888] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  382.679899] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  382.679919] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  382.679927] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  382.679934] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  382.679940] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  382.679947] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  382.679954] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  382.679960] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  382.679967] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  382.679974] [drm:check_crtc_state], [CRTC:3]
>[  382.679990] [drm:check_crtc_state], [CRTC:5]
>[  382.679997] [drm:check_shared_dpll_state], PCH DPLL A
>[  382.680006] [drm:check_shared_dpll_state], PCH DPLL B
>[  382.680016] [drm:drm_framebuffer_reference], FB ID: 32
>[  382.680022] [drm:drm_framebuffer_unreference], FB ID: 31
>[  382.680027] [drm:drm_framebuffer_unreference], FB ID: 32
>[  389.684698] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  389.684711] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  389.684717] [drm:drm_framebuffer_unreference], FB ID: 0
>[  389.684723] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  389.684742] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  389.684749] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  389.684754] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  389.684760] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  389.684766] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  389.684770] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  389.684775] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  389.684781] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  389.684851] ironlake_crtc_disable:3457
>[  389.684905] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,236)@ 389.337793 -> 389.332916 [e 1 us, 0 rep]
>[  389.684914] ironlake_crtc_disable:3461
>[  389.684917] ironlake_crtc_disable:3465
>[  389.684920] ironlake_crtc_disable:3468
>[  389.696185] ironlake_crtc_disable:3471
>[  389.696193] ironlake_crtc_disable:3475
>[  389.696197] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  389.696209] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  389.696216] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  389.696224] [drm:ironlake_edp_backlight_off], 
>[  389.897530] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  389.897540] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  389.897545] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  390.722833] ironlake_crtc_disable:3479
>[  390.730838] ironlake_crtc_disable:3482
>[  390.730846] ironlake_crtc_disable:3485
>[  390.730850] [drm:intel_dp_link_down], 
>[  390.782869] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  390.834103] ironlake_crtc_disable:3490
>[  390.834111] ironlake_crtc_disable:3518
>[  390.834116] ironlake_crtc_disable:3522
>[  390.834120] [drm:intel_update_fbc], no output, disabling
>[  390.834125] ironlake_crtc_disable:3526
>[  390.834143] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  390.834148] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  390.834154] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  390.834160] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  390.834166] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  390.834172] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  390.834177] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  390.834183] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  390.834188] [drm:check_crtc_state], [CRTC:3]
>[  390.834194] [drm:check_crtc_state], [CRTC:5]
>[  390.834199] [drm:check_shared_dpll_state], PCH DPLL A
>[  390.834207] [drm:check_shared_dpll_state], PCH DPLL B
>[  390.834215] [drm:drm_framebuffer_unreference], FB ID: 0
>[  390.834220] [drm:drm_framebuffer_unreference], FB ID: 0
>[  390.834228] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  390.834609] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  390.834628] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  390.834642] [drm:intel_framebuffer_init], unsupported pixel format: RG24 little-endian (0x34324752)
>[  390.834649] [drm:drm_mode_addfb2], could not create framebuffer
>[  390.834717] [drm:drm_ioctl], ret = -22
>[  390.834735] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  390.834887] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  390.834904] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  390.834915] [drm:drm_framebuffer_reference], FB ID: 32
>[  390.834922] [drm:drm_mode_addfb2], [FB:32]
>[  390.834930] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  390.834942] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  390.834952] [drm:drm_framebuffer_reference], FB ID: 33
>[  390.834959] [drm:drm_mode_addfb2], [FB:33]
>[  390.835039] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  390.835046] [drm:drm_mode_setcrtc], [CRTC:3]
>[  390.835050] [drm:drm_framebuffer_reference], FB ID: 32
>[  390.835056] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  390.835061] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  390.835067] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  390.835072] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  390.835077] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  390.835081] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  390.835086] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  390.835091] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  390.835098] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  390.835103] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  390.835109] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  390.835115] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  390.835120] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  390.835125] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  390.835130] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  390.835136] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  390.835141] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  390.835145] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  390.835149] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  390.835155] [drm:intel_dump_pipe_config], requested mode:
>[  390.835160] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  390.835167] [drm:intel_dump_pipe_config], adjusted mode:
>[  390.835171] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  390.835186] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  390.835204] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  390.835218] [drm:intel_dump_pipe_config], ips: 0
>[  390.835233] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  390.846521] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  390.846547] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  390.846555] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  390.846561] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  390.847070] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  390.847079] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  390.847086] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  390.847094] [drm:ironlake_edp_pll_on], 
>[  390.898936] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  390.950968] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  390.950979] [drm:intel_update_fbc], disabled per chip default
>[  390.950985] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  390.950992] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  390.950999] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  390.951014] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  390.951022] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  391.252580] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  391.253177] [drm:intel_dp_start_link_train], clock recovery OK
>[  391.253182] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  391.253186] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  391.253192] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  391.253202] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  391.253207] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  391.594338] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  391.594350] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  391.645367] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  391.646263] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  391.646417] [drm:ironlake_edp_backlight_on], 
>[  391.687371] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  391.697365] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  391.697377] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  391.697390] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  391.697413] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  391.697422] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  391.697430] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  391.697439] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  391.697448] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  391.697457] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  391.697465] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  391.697475] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  391.697483] [drm:check_crtc_state], [CRTC:3]
>[  391.697500] [drm:check_crtc_state], [CRTC:5]
>[  391.697508] [drm:check_shared_dpll_state], PCH DPLL A
>[  391.697519] [drm:check_shared_dpll_state], PCH DPLL B
>[  391.697531] [drm:drm_framebuffer_reference], FB ID: 32
>[  391.697538] [drm:drm_framebuffer_unreference], FB ID: 32
>[  398.702194] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  398.702208] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  398.702214] [drm:drm_framebuffer_unreference], FB ID: 0
>[  398.702220] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  398.702239] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  398.702247] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  398.702252] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  398.702258] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  398.702264] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  398.702269] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  398.702274] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  398.702280] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  398.702286] ironlake_crtc_disable:3457
>[  398.702365] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,235)@ 398.349695 -> 398.344839 [e 1 us, 0 rep]
>[  398.702415] ironlake_crtc_disable:3461
>[  398.702419] ironlake_crtc_disable:3465
>[  398.702422] ironlake_crtc_disable:3468
>[  398.713747] ironlake_crtc_disable:3471
>[  398.713755] ironlake_crtc_disable:3475
>[  398.713759] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  398.713772] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  398.713779] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  398.713787] [drm:ironlake_edp_backlight_off], 
>[  398.915086] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  398.915096] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  398.915103] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  399.718374] ironlake_crtc_disable:3479
>[  399.730384] ironlake_crtc_disable:3482
>[  399.730392] ironlake_crtc_disable:3485
>[  399.730397] [drm:intel_dp_link_down], 
>[  399.782415] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.833586] ironlake_crtc_disable:3490
>[  399.833595] ironlake_crtc_disable:3518
>[  399.833601] ironlake_crtc_disable:3522
>[  399.833605] [drm:intel_update_fbc], no output, disabling
>[  399.833612] ironlake_crtc_disable:3526
>[  399.833630] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  399.833638] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  399.833644] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  399.833651] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  399.833658] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  399.833664] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  399.833672] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  399.833678] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  399.833684] [drm:check_crtc_state], [CRTC:3]
>[  399.833691] [drm:check_crtc_state], [CRTC:5]
>[  399.833698] [drm:check_shared_dpll_state], PCH DPLL A
>[  399.833706] [drm:check_shared_dpll_state], PCH DPLL B
>[  399.833716] [drm:drm_framebuffer_unreference], FB ID: 0
>[  399.833721] [drm:drm_framebuffer_unreference], FB ID: 0
>[  399.833731] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  399.834581] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  399.834598] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  399.834604] [drm:drm_framebuffer_reference], FB ID: 32
>[  399.834606] [drm:drm_mode_addfb2], [FB:32]
>[  399.834609] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  399.834614] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  399.834617] [drm:drm_framebuffer_reference], FB ID: 33
>[  399.834620] [drm:drm_mode_addfb2], [FB:33]
>[  399.834685] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  399.834689] [drm:drm_mode_setcrtc], [CRTC:3]
>[  399.834691] [drm:drm_framebuffer_reference], FB ID: 32
>[  399.834695] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  399.834698] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  399.834702] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  399.834705] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  399.834708] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  399.834711] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  399.834714] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  399.834719] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  399.834723] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  399.834727] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  399.834732] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  399.834736] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  399.834746] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  399.834756] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  399.834764] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  399.834769] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  399.834772] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  399.834774] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  399.834777] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  399.834780] [drm:intel_dump_pipe_config], requested mode:
>[  399.834783] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  399.834788] [drm:intel_dump_pipe_config], adjusted mode:
>[  399.834790] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  399.834794] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  399.834797] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  399.834799] [drm:intel_dump_pipe_config], ips: 0
>[  399.834803] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  399.846071] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  399.846096] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  399.846104] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  399.846109] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  399.846619] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  399.846628] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  399.846634] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  399.846642] [drm:ironlake_edp_pll_on], 
>[  399.898483] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.950449] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  399.950461] [drm:intel_update_fbc], disabled per chip default
>[  399.950469] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  399.950477] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  399.950485] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  399.950499] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  399.950506] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  400.252093] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  400.252688] [drm:intel_dp_start_link_train], clock recovery OK
>[  400.252693] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  400.252697] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  400.252703] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  400.252712] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  400.252717] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  400.593922] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  400.593941] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  400.644953] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  400.645859] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  400.646034] [drm:ironlake_edp_backlight_on], 
>[  400.686986] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  400.696984] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  400.696998] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  400.697008] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  400.697029] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  400.697036] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  400.697043] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  400.697050] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  400.697057] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  400.697063] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  400.697070] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  400.697078] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  400.697084] [drm:check_crtc_state], [CRTC:3]
>[  400.697100] [drm:check_crtc_state], [CRTC:5]
>[  400.697106] [drm:check_shared_dpll_state], PCH DPLL A
>[  400.697116] [drm:check_shared_dpll_state], PCH DPLL B
>[  400.697127] [drm:drm_framebuffer_reference], FB ID: 32
>[  400.697132] [drm:drm_framebuffer_unreference], FB ID: 32
>[  407.701790] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  407.701804] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  407.701809] [drm:drm_framebuffer_unreference], FB ID: 0
>[  407.701816] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  407.701835] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  407.701842] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  407.701847] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  407.701854] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  407.701860] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  407.701865] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  407.701869] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  407.701875] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  407.701882] ironlake_crtc_disable:3457
>[  407.701965] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,235)@ 407.343748 -> 407.338892 [e 1 us, 0 rep]
>[  407.702016] ironlake_crtc_disable:3461
>[  407.702019] ironlake_crtc_disable:3465
>[  407.702023] ironlake_crtc_disable:3468
>[  407.713302] ironlake_crtc_disable:3471
>[  407.713311] ironlake_crtc_disable:3475
>[  407.713316] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  407.713329] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  407.713338] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  407.713347] [drm:ironlake_edp_backlight_off], 
>[  407.914633] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  407.914642] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  407.914648] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  408.717926] ironlake_crtc_disable:3479
>[  408.729931] ironlake_crtc_disable:3482
>[  408.729939] ironlake_crtc_disable:3485
>[  408.729944] [drm:intel_dp_link_down], 
>[  408.781963] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  408.833195] ironlake_crtc_disable:3490
>[  408.833199] ironlake_crtc_disable:3518
>[  408.833203] ironlake_crtc_disable:3522
>[  408.833205] [drm:intel_update_fbc], no output, disabling
>[  408.833208] ironlake_crtc_disable:3526
>[  408.833222] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  408.833226] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  408.833229] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  408.833233] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  408.833237] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  408.833240] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  408.833244] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  408.833248] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  408.833251] [drm:check_crtc_state], [CRTC:3]
>[  408.833255] [drm:check_crtc_state], [CRTC:5]
>[  408.833258] [drm:check_shared_dpll_state], PCH DPLL A
>[  408.833266] [drm:check_shared_dpll_state], PCH DPLL B
>[  408.833272] [drm:drm_framebuffer_unreference], FB ID: 0
>[  408.833275] [drm:drm_framebuffer_unreference], FB ID: 0
>[  408.833280] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  408.833794] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  408.833813] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  408.833823] [drm:drm_framebuffer_reference], FB ID: 32
>[  408.833825] [drm:drm_mode_addfb2], [FB:32]
>[  408.833829] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  408.833833] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  408.833837] [drm:drm_framebuffer_reference], FB ID: 33
>[  408.833839] [drm:drm_mode_addfb2], [FB:33]
>[  408.833842] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  408.833846] [drm:drm_mode_setcrtc], [CRTC:3]
>[  408.833911] [drm:drm_framebuffer_reference], FB ID: 32
>[  408.833958] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  408.833962] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  408.833969] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  408.833979] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  408.833988] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  408.833996] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  408.834004] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  408.834010] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  408.834013] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  408.834016] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  408.834020] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  408.834023] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  408.834025] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  408.834029] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  408.834031] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  408.834034] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  408.834037] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  408.834039] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  408.834042] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  408.834045] [drm:intel_dump_pipe_config], requested mode:
>[  408.834048] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  408.834052] [drm:intel_dump_pipe_config], adjusted mode:
>[  408.834054] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  408.834058] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  408.834060] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  408.834063] [drm:intel_dump_pipe_config], ips: 0
>[  408.834067] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  408.843735] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  408.843755] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  408.843759] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  408.843762] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  408.844268] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
>[  408.844272] [drm:ironlake_check_srwm], watermark 1: display plane 24, fbc lines 3, cursor 6
>[  408.844276] [drm:ironlake_check_srwm], watermark 2: display plane 76, fbc lines 3, cursor 6
>[  408.844280] [drm:ironlake_edp_pll_on], 
>[  408.896030] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  408.948060] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  408.948072] [drm:intel_update_fbc], disabled per chip default
>[  408.948078] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  408.948086] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  408.948093] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  408.948106] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  408.948112] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  409.249676] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  409.250274] [drm:intel_dp_start_link_train], clock recovery OK
>[  409.250278] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  409.250283] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  409.250288] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  409.250298] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  409.250303] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  409.591461] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  409.591477] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  409.642490] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  409.643434] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  409.643592] [drm:ironlake_edp_backlight_on], 
>[  409.684526] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  409.694526] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  409.694537] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  409.694546] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  409.694566] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  409.694573] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  409.694579] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  409.694585] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  409.694590] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  409.694596] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  409.694602] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  409.694608] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  409.694614] [drm:check_crtc_state], [CRTC:3]
>[  409.694628] [drm:check_crtc_state], [CRTC:5]
>[  409.694634] [drm:check_shared_dpll_state], PCH DPLL A
>[  409.694643] [drm:check_shared_dpll_state], PCH DPLL B
>[  409.694652] [drm:drm_framebuffer_reference], FB ID: 32
>[  409.694657] [drm:drm_framebuffer_unreference], FB ID: 32
>[  416.699310] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  416.699327] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  416.699333] [drm:drm_framebuffer_unreference], FB ID: 0
>[  416.699342] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  416.699367] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  416.699376] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  416.699384] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  416.699391] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  416.699465] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  416.699470] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  416.699475] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  416.699527] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  416.699534] ironlake_crtc_disable:3457
>[  416.699544] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,235)@ 416.335782 -> 416.330926 [e 1 us, 0 rep]
>[  416.699552] ironlake_crtc_disable:3461
>[  416.699555] ironlake_crtc_disable:3465
>[  416.699558] ironlake_crtc_disable:3468
>[  416.710841] ironlake_crtc_disable:3471
>[  416.710849] ironlake_crtc_disable:3475
>[  416.710853] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  416.710865] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  416.710873] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  416.710881] [drm:ironlake_edp_backlight_off], 
>[  416.912178] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  416.912188] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  416.912194] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  417.726475] ironlake_crtc_disable:3479
>[  417.728472] ironlake_crtc_disable:3482
>[  417.728480] ironlake_crtc_disable:3485
>[  417.728484] [drm:intel_dp_link_down], 
>[  417.780508] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  417.831742] ironlake_crtc_disable:3490
>[  417.831747] ironlake_crtc_disable:3518
>[  417.831750] ironlake_crtc_disable:3522
>[  417.831752] [drm:intel_update_fbc], no output, disabling
>[  417.831756] ironlake_crtc_disable:3526
>[  417.831770] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  417.831774] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  417.831777] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  417.831781] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  417.831784] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  417.831788] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  417.831792] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  417.831796] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  417.831799] [drm:check_crtc_state], [CRTC:3]
>[  417.831803] [drm:check_crtc_state], [CRTC:5]
>[  417.831806] [drm:check_shared_dpll_state], PCH DPLL A
>[  417.831812] [drm:check_shared_dpll_state], PCH DPLL B
>[  417.831818] [drm:drm_framebuffer_unreference], FB ID: 0
>[  417.831821] [drm:drm_framebuffer_unreference], FB ID: 0
>[  417.831825] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  417.832327] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  417.832346] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  417.832356] [drm:drm_framebuffer_reference], FB ID: 32
>[  417.832359] [drm:drm_mode_addfb2], [FB:32]
>[  417.832362] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  417.832366] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  417.832370] [drm:drm_framebuffer_reference], FB ID: 33
>[  417.832373] [drm:drm_mode_addfb2], [FB:33]
>[  417.832438] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  417.832441] [drm:drm_mode_setcrtc], [CRTC:3]
>[  417.832444] [drm:drm_framebuffer_reference], FB ID: 32
>[  417.832451] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  417.832453] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  417.832457] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  417.832540] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set
>[  417.832561] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  417.832572] [drm:drm_mode_debug_printmodeline], Modeline 34:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  417.832582] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  417.832591] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  417.832599] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  417.832604] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  417.832607] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  417.832611] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  417.832615] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  417.832618] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  417.832622] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  417.832625] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  417.832628] [drm:intel_modeset_pipe_config], plane bpp: 18, pipe bpp: 18, dithering: 0
>[  417.832631] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  417.832634] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  417.832636] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 0
>[  417.832640] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  417.832643] [drm:intel_dump_pipe_config], requested mode:
>[  417.832645] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  417.832649] [drm:intel_dump_pipe_config], adjusted mode:
>[  417.832651] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  417.832655] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  417.832658] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  417.832661] [drm:intel_dump_pipe_config], ips: 0
>[  417.832664] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  417.838976] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 2752
>[  417.838994] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  417.838997] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  417.839000] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  417.839506] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 3, cursor: 4
>[  417.839510] [drm:ironlake_check_srwm], watermark 1: display plane 10, fbc lines 3, cursor 4
>[  417.839514] [drm:ironlake_check_srwm], watermark 2: display plane 27, fbc lines 3, cursor 4
>[  417.839518] [drm:ironlake_edp_pll_on], 
>[  417.891548] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  417.943575] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  417.943586] [drm:intel_update_fbc], disabled per chip default
>[  417.943592] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  417.943600] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  417.943608] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  417.943621] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  417.943628] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  418.245219] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  418.245815] [drm:intel_dp_start_link_train], clock recovery OK
>[  418.245819] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  418.245823] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  418.245830] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  418.245840] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  418.245845] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  418.586942] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  418.586959] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  418.637974] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  418.638932] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  418.639089] [drm:ironlake_edp_backlight_on], 
>[  418.679995] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  418.690068] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  418.690083] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  418.690093] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  418.690113] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  418.690121] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  418.690127] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  418.690135] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  418.690141] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  418.690148] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  418.690154] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  418.690160] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  418.690167] [drm:check_crtc_state], [CRTC:3]
>[  418.690182] [drm:check_crtc_state], [CRTC:5]
>[  418.690189] [drm:check_shared_dpll_state], PCH DPLL A
>[  418.690198] [drm:check_shared_dpll_state], PCH DPLL B
>[  418.690208] [drm:drm_framebuffer_reference], FB ID: 32
>[  418.690213] [drm:drm_framebuffer_unreference], FB ID: 32
>[  418.840151] [drm:ilk_display_irq_handler], Pipe A FIFO underrun
>[  425.694822] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  425.694847] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  425.694854] [drm:drm_framebuffer_unreference], FB ID: 0
>[  425.694866] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  425.694894] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  425.694900] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  425.694906] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  425.694913] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  425.694989] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  425.694995] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  425.695000] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  425.695017] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  425.695024] ironlake_crtc_disable:3457
>[  425.695034] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,235)@ 425.325728 -> 425.320872 [e 1 us, 0 rep]
>[  425.695042] ironlake_crtc_disable:3461
>[  425.695046] ironlake_crtc_disable:3465
>[  425.695049] ironlake_crtc_disable:3468
>[  425.706331] ironlake_crtc_disable:3471
>[  425.706340] ironlake_crtc_disable:3475
>[  425.706345] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  425.706359] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  425.706368] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  425.706377] [drm:ironlake_edp_backlight_off], 
>[  425.907718] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  425.907728] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  425.907734] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
>[  426.722018] ironlake_crtc_disable:3479
>[  426.724016] ironlake_crtc_disable:3482
>[  426.724024] ironlake_crtc_disable:3485
>[  426.724029] [drm:intel_dp_link_down], 
>[  426.776052] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  426.827287] ironlake_crtc_disable:3490
>[  426.827295] ironlake_crtc_disable:3518
>[  426.827301] ironlake_crtc_disable:3522
>[  426.827305] [drm:intel_update_fbc], no output, disabling
>[  426.827310] ironlake_crtc_disable:3526
>[  426.827329] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  426.827336] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  426.827341] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  426.827346] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  426.827352] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  426.827358] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  426.827364] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  426.827370] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  426.827376] [drm:check_crtc_state], [CRTC:3]
>[  426.827383] [drm:check_crtc_state], [CRTC:5]
>[  426.827388] [drm:check_shared_dpll_state], PCH DPLL A
>[  426.827396] [drm:check_shared_dpll_state], PCH DPLL B
>[  426.827405] [drm:drm_framebuffer_unreference], FB ID: 0
>[  426.827410] [drm:drm_framebuffer_unreference], FB ID: 0
>[  426.827418] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  426.827820] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  426.827835] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  426.827845] [drm:intel_framebuffer_init], unsupported pixel format: RG24 little-endian (0x34324752)
>[  426.827850] [drm:drm_mode_addfb2], could not create framebuffer
>[  426.827854] [drm:drm_ioctl], ret = -22
>[  426.827860] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  426.827899] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  426.827909] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  426.827917] [drm:drm_framebuffer_reference], FB ID: 32
>[  426.827921] [drm:drm_mode_addfb2], [FB:32]
>[  426.827994] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  426.828040] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  426.828051] [drm:drm_framebuffer_reference], FB ID: 33
>[  426.828069] [drm:drm_mode_addfb2], [FB:33]
>[  426.828084] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  426.828098] [drm:drm_mode_setcrtc], [CRTC:3]
>[  426.828112] [drm:drm_framebuffer_reference], FB ID: 32
>[  426.828121] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  426.828125] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  426.828132] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  426.828136] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  426.828141] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  426.828146] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  426.828151] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  426.828156] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  426.828162] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  426.828167] [drm:connected_sink_compute_bpp], clamping display bpp (was 24) to EDID reported max of 18
>[  426.828173] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  426.828178] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  426.828186] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  426.828190] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  426.828193] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1
>[  426.828196] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  426.828199] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  426.828201] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  426.828204] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  426.828208] [drm:intel_dump_pipe_config], requested mode:
>[  426.828210] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  426.828214] [drm:intel_dump_pipe_config], adjusted mode:
>[  426.828217] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  426.828220] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  426.828223] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  426.828226] [drm:intel_dump_pipe_config], ips: 0
>[  426.828229] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  426.839274] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  426.839300] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  426.839307] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  426.839313] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  426.839824] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  426.839831] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  426.839838] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  426.839845] [drm:ironlake_edp_pll_on], 
>[  426.892117] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  426.944149] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  426.944161] [drm:intel_update_fbc], disabled per chip default
>[  426.944167] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  426.944175] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  426.944182] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  426.944196] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  426.944202] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  427.245775] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  427.246373] [drm:intel_dp_start_link_train], clock recovery OK
>[  427.246378] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  427.246382] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  427.246388] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  427.246397] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  427.246403] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  427.587560] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  427.587579] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  427.638588] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  427.639491] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  427.639644] [drm:ironlake_edp_backlight_on], 
>[  427.640341] [drm:ilk_display_irq_handler], Pipe A FIFO underrun
>[  427.680585] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  427.690579] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  427.690592] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  427.690607] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  427.690627] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  427.690635] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  427.690642] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  427.690649] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  427.690657] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  427.690664] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  427.690671] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  427.690678] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  427.690684] [drm:check_crtc_state], [CRTC:3]
>[  427.690700] [drm:check_crtc_state], [CRTC:5]
>[  427.690707] [drm:check_shared_dpll_state], PCH DPLL A
>[  427.690716] [drm:check_shared_dpll_state], PCH DPLL B
>[  427.690731] [drm:drm_framebuffer_reference], FB ID: 32
>[  427.690736] [drm:drm_framebuffer_unreference], FB ID: 32
>[  434.695379] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  434.695392] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  434.695398] [drm:drm_framebuffer_unreference], FB ID: 0
>[  434.695405] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  434.695423] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  434.695430] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  434.695439] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  434.695445] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  434.695451] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  434.695456] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  434.695461] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  434.695467] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  434.695538] ironlake_crtc_disable:3457
>[  434.695554] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,233)@ 434.320700 -> 434.315885 [e 1 us, 0 rep]
>[  434.695564] ironlake_crtc_disable:3461
>[  434.695567] ironlake_crtc_disable:3465
>[  434.695570] ironlake_crtc_disable:3468
>[  434.708913] ironlake_crtc_disable:3471
>[  434.708923] ironlake_crtc_disable:3475
>[  434.708928] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  434.708941] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  434.708949] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
>[  434.708959] [drm:ironlake_edp_backlight_off], 
>[  434.910275] [drm:ironlake_edp_panel_off], Turn eDP power off
>[  434.910284] [drm:ironlake_wait_panel_off], Wait for panel power off time
>[  434.910290] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
>[  435.724568] ironlake_crtc_disable:3479
>[  435.740576] ironlake_crtc_disable:3482
>[  435.740584] ironlake_crtc_disable:3485
>[  435.740588] [drm:intel_dp_link_down], 
>[  435.792609] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  435.843841] ironlake_crtc_disable:3490
>[  435.843849] ironlake_crtc_disable:3518
>[  435.843854] ironlake_crtc_disable:3522
>[  435.843858] [drm:intel_update_fbc], no output, disabling
>[  435.843864] ironlake_crtc_disable:3526
>[  435.843881] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  435.843887] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  435.843892] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  435.843897] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  435.843903] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  435.843909] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  435.843915] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  435.843921] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  435.843926] [drm:check_crtc_state], [CRTC:3]
>[  435.843932] [drm:check_crtc_state], [CRTC:5]
>[  435.843937] [drm:check_shared_dpll_state], PCH DPLL A
>[  435.843945] [drm:check_shared_dpll_state], PCH DPLL B
>[  435.843953] [drm:drm_framebuffer_unreference], FB ID: 0
>[  435.843958] [drm:drm_framebuffer_unreference], FB ID: 0
>[  435.843966] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  435.844720] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  435.844735] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  435.844744] [drm:drm_framebuffer_reference], FB ID: 32
>[  435.844749] [drm:drm_mode_addfb2], [FB:32]
>[  435.844756] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, I915_GEM_CREATE
>[  435.844761] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_ADDFB2
>[  435.844764] [drm:drm_framebuffer_reference], FB ID: 33
>[  435.844767] [drm:drm_mode_addfb2], [FB:33]
>[  435.844770] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_SETCRTC
>[  435.844774] [drm:drm_mode_setcrtc], [CRTC:3]
>[  435.844776] [drm:drm_framebuffer_reference], FB ID: 32
>[  435.844842] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
>[  435.844845] [drm:intel_crtc_set_config], [CRTC:3] [FB:32] #connectors=1 (x y) (0 0)
>[  435.844849] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
>[  435.844852] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  435.844855] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  435.844858] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[  435.844861] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  435.844865] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  435.844868] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
>[  435.844879] [drm:connected_sink_compute_bpp], clamping display bpp (was 30) to EDID reported max of 18
>[  435.844891] [drm:intel_dp_compute_config], DP link computation with max lane count 1 max bw 0a pixel clock 69000KHz
>[  435.844898] [drm:intel_dp_compute_config], clamping bpp for eDP panel to BIOS-provided 18
>[  435.844901] [drm:intel_dp_compute_config], DP link bw 06 lane count 1 clock 162000 bpp 18
>[  435.844904] [drm:intel_dp_compute_config], DP link bw required 124200 available 129600
>[  435.844907] [drm:intel_modeset_pipe_config], plane bpp: 30, pipe bpp: 18, dithering: 1
>[  435.844910] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
>[  435.844913] [drm:intel_dump_pipe_config], cpu_transcoder: A
>[  435.844915] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1
>[  435.844918] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  435.844921] [drm:intel_dump_pipe_config], requested mode:
>[  435.844924] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 40 46000 1366 1398 1422 1426 768 771 775 806 0x40 0x9
>[  435.844929] [drm:intel_dump_pipe_config], adjusted mode:
>[  435.844931] [drm:drm_mode_debug_printmodeline], Modeline 0:"1366x768" 60 69000 1366 1398 1422 1426 768 771 775 806 0x48 0x9
>[  435.844935] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  435.844938] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000
>[  435.844941] [drm:intel_dump_pipe_config], ips: 0
>[  435.844944] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22
>[  435.856149] [drm:ironlake_update_plane], Writing base 0044F000 00000000 0 0 5504
>[  435.856174] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1366x768]
>[  435.856181] [drm:ironlake_set_pll_cpu_edp], eDP PLL enable for clock 162000
>[  435.856187] [drm:ironlake_set_pll_cpu_edp], 160MHz cpu eDP clock, might need ilk devA w/a
>[  435.856697] [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 4, cursor: 6
>[  435.856705] [drm:ironlake_check_srwm], watermark 1: display plane 17, fbc lines 3, cursor 6
>[  435.856712] [drm:ironlake_check_srwm], watermark 2: display plane 51, fbc lines 3, cursor 6
>[  435.856719] [drm:ironlake_edp_pll_on], 
>[  435.908681] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  435.960710] [drm:ironlake_wait_for_vblank], vblank wait timed out
>[  435.960722] [drm:intel_update_fbc], disabled per chip default
>[  435.960728] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
>[  435.960735] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  435.960743] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
>[  435.960755] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  435.960761] [drm:ironlake_edp_panel_vdd_on], eDP was not running
>[  436.262326] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  436.262922] [drm:intel_dp_start_link_train], clock recovery OK
>[  436.262927] [drm:ironlake_edp_panel_on], Turn eDP power on
>[  436.262931] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
>[  436.262936] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0008
>[  436.262946] [drm:ironlake_wait_panel_on], Wait for panel power on
>[  436.262952] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0009
>[  436.604110] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
>[  436.604126] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  436.655142] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
>[  436.656090] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
>[  436.656259] [drm:ironlake_edp_backlight_on], 
>[  436.656941] [drm:ilk_display_irq_handler], Pipe A FIFO underrun
>[  436.697178] [drm:intel_panel_actually_set_backlight], set backlight PWM = 93
>[  436.707117] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1426, vtotal 806, vdisplay 768
>[  436.707130] [drm:drm_calc_timestamping_constants], crtc 3: clock 69000 kHz framedur 16657333 linedur 20666, pixeldur 14
>[  436.707141] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
>[  436.707161] [drm:check_encoder_state], [ENCODER:8:DAC-8]
>[  436.707169] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
>[  436.707176] [drm:check_encoder_state], [ENCODER:18:TMDS-18]
>[  436.707182] [drm:check_encoder_state], [ENCODER:20:TMDS-20]
>[  436.707189] [drm:check_encoder_state], [ENCODER:22:TMDS-22]
>[  436.707196] [drm:check_encoder_state], [ENCODER:24:TMDS-24]
>[  436.707202] [drm:check_encoder_state], [ENCODER:26:TMDS-26]
>[  436.707208] [drm:check_encoder_state], [ENCODER:28:TMDS-28]
>[  436.707216] [drm:check_crtc_state], [CRTC:3]
>[  436.707232] [drm:check_crtc_state], [CRTC:5]
>[  436.707238] [drm:check_shared_dpll_state], PCH DPLL A
>[  436.707249] [drm:check_shared_dpll_state], PCH DPLL B
>[  436.707259] [drm:drm_framebuffer_reference], FB ID: 32
>[  436.707264] [drm:drm_framebuffer_unreference], FB ID: 32
>[  443.711897] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  443.711914] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  443.711920] [drm:drm_framebuffer_unreference], FB ID: 0
>[  443.711929] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_GEM_CLOSE
>[  443.711953] [drm:drm_ioctl], pid=27312, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
>[  443.711963] [drm:__drm_framebuffer_unreference], FB ID: 0
>[  443.711970] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
>[  443.711977] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
>[  443.711985] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
>[  443.711991] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
>[  443.712062] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
>[  443.712076] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  443.712083] ironlake_crtc_disable:3457
>[  443.712091] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(0,230)@ 443.331681 -> 443.326927 [e 1 us, 0 rep]
>[  443.712099] ironlake_crtc_disable:3461
>[  443.712102] ironlake_crtc_disable:3465
>[  443.712106] ironlake_crtc_disable:3468

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Attachments on bug 67243: 82900 | 83957 | 84898 | 84929 | 85064 | 85190 | 85229 | 85244 | 85246 | 85305

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