Attachment 87496 Details for Bug 65496 – patch: Ben's patch in outside bugzilla comment 22

patch: Ben's patch in outside bugzilla comment 22

aa.txt (text/plain), 6.22 KB, created by shui yangwei on 2013-10-12 01:42:59 UTC

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Creator: shui yangwei

Created: 2013-10-12 01:42:59 UTC

Size: 6.22 KB

patch

obsolete

>From 001161e9b23537fdd5c32348802880f6ab1bd922 Mon Sep 17 00:00:00 2001
>From: Ben Widawsky <benjamin.widawsky@intel.com>
>Date: Mon, 7 Oct 2013 14:46:44 -0700
>Subject: [PATCH] drm/i915: Disable GGTT ptes on suspend
>
>Do not let the GT screw us after we've decided to suspend.
>
>Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>---
> drivers/gpu/drm/i915/i915_drv.c     |  2 ++
> drivers/gpu/drm/i915/i915_drv.h     |  4 +++-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++++++++++++---------
> 3 files changed, 34 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 0fc9658..1bfef0f 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -505,6 +505,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> 		intel_modeset_suspend_hw(dev);
> 	}
> 
>+	i915_gem_suspend_gtt_mappings(dev);
>+
> 	i915_save_state(dev);
> 
> 	intel_opregion_fini(dev);
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index ed8653f..040890e 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -507,7 +507,8 @@ struct i915_address_space {
> 				     enum i915_cache_level level);
> 	void (*clear_range)(struct i915_address_space *vm,
> 			    unsigned int first_entry,
>-			    unsigned int num_entries);
>+			    unsigned int num_entries,
>+			    bool use_scratch);
> 	void (*insert_entries)(struct i915_address_space *vm,
> 			       struct sg_table *st,
> 			       unsigned int first_entry,
>@@ -2117,6 +2118,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
> void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
> 			      struct drm_i915_gem_object *obj);
> 
>+void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
> void i915_gem_restore_gtt_mappings(struct drm_device *dev);
> int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
> void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
>diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>index e999496..57dd949 100644
>--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>@@ -236,7 +236,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
> /* PPGTT support for Sandybdrige/Gen6 and later */
> static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
> 				   unsigned first_entry,
>-				   unsigned num_entries)
>+				   unsigned num_entries,
>+				   bool use_scratch)
> {
> 	struct i915_hw_ppgtt *ppgtt =
> 		container_of(vm, struct i915_hw_ppgtt, base);
>@@ -367,7 +368,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> 	}
> 
> 	ppgtt->base.clear_range(&ppgtt->base, 0,
>-				ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES);
>+				ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
> 
> 	ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
> 
>@@ -444,7 +445,8 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
> {
> 	ppgtt->base.clear_range(&ppgtt->base,
> 				i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
>-				obj->base.size >> PAGE_SHIFT);
>+				obj->base.size >> PAGE_SHIFT,
>+				true);
> }
> 
> extern int intel_iommu_gfx_mapped;
>@@ -485,15 +487,28 @@ static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
> 		dev_priv->mm.interruptible = interruptible;
> }
> 
>+void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
>+				       dev_priv->gtt.base.start / PAGE_SIZE,
>+				       dev_priv->gtt.base.total / PAGE_SIZE,
>+				       false);
>+}
>+
> void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct drm_i915_gem_object *obj;
> 
>+	/* FIXME: restore more than just RCS */
>+	I915_WRITE(0x4194, 0x0);
>+
> 	/* First fill our portion of the GTT with scratch pages */
> 	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
> 				       dev_priv->gtt.base.start / PAGE_SIZE,
>-				       dev_priv->gtt.base.total / PAGE_SIZE);
>+				       dev_priv->gtt.base.total / PAGE_SIZE,
>+				       false);
> 
> 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
> 		i915_gem_clflush_object(obj, obj->pin_display);
>@@ -560,7 +575,8 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
> 
> static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> 				  unsigned int first_entry,
>-				  unsigned int num_entries)
>+				  unsigned int num_entries,
>+				  bool use_scratch)
> {
> 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
> 	gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
>@@ -574,6 +590,8 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> 		num_entries = max_entries;
> 
> 	scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
>+	if (!use_scratch)
>+		scratch_pte &= ~GEN6_PTE_VALID;
> 	for (i = 0; i < num_entries; i++)
> 		iowrite32(scratch_pte, &gtt_base[i]);
> 	readl(gtt_base);
>@@ -594,7 +612,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
> 
> static void i915_ggtt_clear_range(struct i915_address_space *vm,
> 				  unsigned int first_entry,
>-				  unsigned int num_entries)
>+				  unsigned int num_entries,
>+				  bool unused)
> {
> 	intel_gtt_clear_range(first_entry, num_entries);
> }
>@@ -622,7 +641,8 @@ void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
> 
> 	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
> 				       entry,
>-				       obj->base.size >> PAGE_SHIFT);
>+				       obj->base.size >> PAGE_SHIFT,
>+				       true);
> 
> 	obj->has_global_gtt_mapping = 0;
> }
>@@ -709,11 +729,11 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
> 		const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
> 		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
> 			      hole_start, hole_end);
>-		ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
>+		ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
> 	}
> 
> 	/* And finally clear the reserved guard page */
>-	ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1);
>+	ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
> }
> 
> static bool
>-- 
>1.8.4

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Attachments on bug 65496: 80458 | 80757 | 83802 | 83804 | 83806 | 87366 | 87496 | 87976 | 88135

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