Attachment 88282 Details for Bug 70507 – next patch version

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0001-drm-i915-Sanitize-the-PPT-fdi-lane-bifurcate-state-o.patch (text/plain), 5.29 KB, created by Daniel Vetter on 2013-10-29 09:09:39 UTC

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Creator: Daniel Vetter

Created: 2013-10-29 09:09:39 UTC

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obsolete

>From c99b7f0f3d6bb49cb4e10c0f12befa0082f0bb5e Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Mon, 21 Oct 2013 21:53:19 +0200
>Subject: [PATCH] drm/i915: Sanitize the PPT fdi lane bifurcate state on ivb
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>We expect this bit to be always set when possible, but some BIOSes are
>lazy and don't do this. The result is a pile of WARNs and unhappy fdi
>link training code ...
>
>v2: It's actually the inverse: The BIOS sets this bit when it's not
>strictly needed. This should be cleaned up in the
>global_modeset_resources callback, but we've failed to look at the
>active bit. Which means this won't fire (and so clean up BIOS state)
>when enabling pipe B or C for the first time.
>
>v3: Wrap lines.
>
>v4: To address issues discussed with Ville in the patch review move
>the setting of the bifurcate bit into the ->crtc_enable hook. That way
>we won't wreak havoc with this state when userspace puts all other
>outputs into dpms off state. This also moves us forward with our
>overall goal to unify the modeset and dpms on paths (which we need to
>allow runtime pm in the dpms off state).
>
>Unfortunately this requires us to move the bifurcate helpers around a
>bit.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70507
>Tested-by: Jan-Michael Brummer <jan.brummer@tabos.org>
>Cc: stable@vger.kernel.org
>Cc: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>---
> drivers/gpu/drm/i915/intel_display.c | 95 ++++++++++++++++++------------------
> 1 file changed, 48 insertions(+), 47 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 8c3bf8a89cb7..509762c85d2e 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -2421,9 +2421,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
> 			   FDI_FE_ERRC_ENABLE);
> }
> 
>-static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
>+static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
> {
>-	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
>+	return crtc->base.enabled && crtc->active &&
>+		crtc->config.has_pch_encoder;
> }
> 
> static void ivb_modeset_global_resources(struct drm_device *dev)
>@@ -3074,6 +3075,48 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
> 		   I915_READ(VSYNCSHIFT(cpu_transcoder)));
> }
> 
>+static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	uint32_t temp;
>+
>+	temp = I915_READ(SOUTH_CHICKEN1);
>+	if (temp & FDI_BC_BIFURCATION_SELECT)
>+		return;
>+
>+	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
>+	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
>+
>+	temp |= FDI_BC_BIFURCATION_SELECT;
>+	DRM_DEBUG_KMS("enabling fdi C rx\n");
>+	I915_WRITE(SOUTH_CHICKEN1, temp);
>+	POSTING_READ(SOUTH_CHICKEN1);
>+}
>+
>+static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
>+{
>+	struct drm_device *dev = intel_crtc->base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	switch (intel_crtc->pipe) {
>+	case PIPE_A:
>+		break;
>+	case PIPE_B:
>+		if (intel_crtc->config.fdi_lanes > 2)
>+			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
>+		else
>+			cpt_enable_fdi_bc_bifurcation(dev);
>+
>+		break;
>+	case PIPE_C:
>+		cpt_enable_fdi_bc_bifurcation(dev);
>+
>+		break;
>+	default:
>+		BUG();
>+	}
>+}
>+
> /*
>  * Enable PCH resources required for PCH ports:
>  *   - PCH PLLs
>@@ -3092,6 +3135,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> 
> 	assert_pch_transcoder_disabled(dev_priv, pipe);
> 
>+	if (IS_IVYBRIDGE(dev))
>+		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
>+
> 	/* Write the TU size bits before fdi link training, so that error
> 	 * detection works. */
> 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
>@@ -5849,48 +5895,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
> 	return true;
> }
> 
>-static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	uint32_t temp;
>-
>-	temp = I915_READ(SOUTH_CHICKEN1);
>-	if (temp & FDI_BC_BIFURCATION_SELECT)
>-		return;
>-
>-	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
>-	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
>-
>-	temp |= FDI_BC_BIFURCATION_SELECT;
>-	DRM_DEBUG_KMS("enabling fdi C rx\n");
>-	I915_WRITE(SOUTH_CHICKEN1, temp);
>-	POSTING_READ(SOUTH_CHICKEN1);
>-}
>-
>-static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
>-{
>-	struct drm_device *dev = intel_crtc->base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-
>-	switch (intel_crtc->pipe) {
>-	case PIPE_A:
>-		break;
>-	case PIPE_B:
>-		if (intel_crtc->config.fdi_lanes > 2)
>-			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
>-		else
>-			cpt_enable_fdi_bc_bifurcation(dev);
>-
>-		break;
>-	case PIPE_C:
>-		cpt_enable_fdi_bc_bifurcation(dev);
>-
>-		break;
>-	default:
>-		BUG();
>-	}
>-}
>-
> int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
> {
> 	/*
>@@ -6079,9 +6083,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> 					     &intel_crtc->config.fdi_m_n);
> 	}
> 
>-	if (IS_IVYBRIDGE(dev))
>-		ivybridge_update_fdi_bc_bifurcation(intel_crtc);
>-
> 	ironlake_set_pipeconf(crtc);
> 
> 	/* Set up the display plane register */
>-- 
>1.8.4.rc3
>

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Attachments on bug 70507: 87690 | 87739 | 87955 | 87969 | 87974 | 88220 | 88279 | 88282

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