Attachment 90899 Details for Bug 69882 – Kernel log on gentoo 3.12.5

Kernel log on gentoo 3.12.5

dmesg.log (text/plain), 1.16 MB, created by Matthias Nagel on 2013-12-17 20:57:08 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Matthias Nagel

Created: 2013-12-17 20:57:08 UTC

Size: 1.16 MB

patch

obsolete

>[    0.000000] Initializing cgroup subsys cpuset
>[    0.000000] Initializing cgroup subsys cpu
>[    0.000000] Initializing cgroup subsys cpuacct
>[    0.000000] Linux version 3.12.5-gentoo (root@matthias-pc) (gcc version 4.7.3 (Gentoo 4.7.3-r1 p1.3, pie-0.5.5) ) #1 SMP Sat Dec 14 17:59:31 CET 2013
>[    0.000000] Command line: \EFI\gentoo\bzImage-3.12.5.efi 
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009efff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009f000-0x000000000009ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000cb662fff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000cb663000-0x00000000cb669fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x00000000cb66a000-0x00000000cbab3fff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000cbab4000-0x00000000cbef1fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000cbef2000-0x00000000dd7a5fff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000dd7a6000-0x00000000dd9adfff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000dd9ae000-0x00000000dd9c3fff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x00000000dd9c4000-0x00000000ddf07fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x00000000ddf08000-0x00000000deffefff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000defff000-0x00000000deffffff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed03fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000041effffff] usable
>[    0.000000] e820: update [mem 0xcb0ff018-0xcb11ec57] usable ==> usable
>[    0.000000] e820: update [mem 0xcb0ee018-0xcb0fe057] usable ==> usable
>[    0.000000] e820: update [mem 0xcb0dd018-0xcb0ed057] usable ==> usable
>[    0.000000] extended physical RAM map:
>[    0.000000] reserve setup_data: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000000059000-0x000000000009efff] usable
>[    0.000000] reserve setup_data: [mem 0x000000000009f000-0x000000000009ffff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000000100000-0x00000000cb0dd017] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb0dd018-0x00000000cb0ed057] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb0ed058-0x00000000cb0ee017] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb0ee018-0x00000000cb0fe057] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb0fe058-0x00000000cb0ff017] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb0ff018-0x00000000cb11ec57] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb11ec58-0x00000000cb662fff] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cb663000-0x00000000cb669fff] ACPI NVS
>[    0.000000] reserve setup_data: [mem 0x00000000cb66a000-0x00000000cbab3fff] usable
>[    0.000000] reserve setup_data: [mem 0x00000000cbab4000-0x00000000cbef1fff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000cbef2000-0x00000000dd7a5fff] usable
>[    0.000000] reserve setup_data: [mem 0x00000000dd7a6000-0x00000000dd9adfff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000dd9ae000-0x00000000dd9c3fff] ACPI data
>[    0.000000] reserve setup_data: [mem 0x00000000dd9c4000-0x00000000ddf07fff] ACPI NVS
>[    0.000000] reserve setup_data: [mem 0x00000000ddf08000-0x00000000deffefff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000defff000-0x00000000deffffff] usable
>[    0.000000] reserve setup_data: [mem 0x00000000f8000000-0x00000000fbffffff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000fed00000-0x00000000fed03fff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] reserve setup_data: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>[    0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000041effffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.31 by American Megatrends
>[    0.000000] efi:  ACPI=0xdd9b2000  ACPI 2.0=0xdd9b2000  SMBIOS=0xf04c0  MPS=0xfd530 
>[    0.000000] efi: mem00: type=3, attr=0xf, range=[0x0000000000000000-0x0000000000008000) (0MB)
>[    0.000000] efi: mem01: type=2, attr=0xf, range=[0x0000000000008000-0x0000000000010000) (0MB)
>[    0.000000] efi: mem02: type=7, attr=0xf, range=[0x0000000000010000-0x0000000000058000) (0MB)
>[    0.000000] efi: mem03: type=0, attr=0xf, range=[0x0000000000058000-0x0000000000059000) (0MB)
>[    0.000000] efi: mem04: type=7, attr=0xf, range=[0x0000000000059000-0x000000000005f000) (0MB)
>[    0.000000] efi: mem05: type=4, attr=0xf, range=[0x000000000005f000-0x0000000000060000) (0MB)
>[    0.000000] efi: mem06: type=3, attr=0xf, range=[0x0000000000060000-0x000000000009f000) (0MB)
>[    0.000000] efi: mem07: type=6, attr=0x800000000000000f, range=[0x000000000009f000-0x00000000000a0000) (0MB)
>[    0.000000] efi: mem08: type=7, attr=0xf, range=[0x0000000000100000-0x0000000001000000) (15MB)
>[    0.000000] efi: mem09: type=2, attr=0xf, range=[0x0000000001000000-0x0000000001f63000) (15MB)
>[    0.000000] efi: mem10: type=7, attr=0xf, range=[0x0000000001f63000-0x00000000c7f10000) (3167MB)
>[    0.000000] efi: mem11: type=2, attr=0xf, range=[0x00000000c7f10000-0x00000000c8010000) (1MB)
>[    0.000000] efi: mem12: type=7, attr=0xf, range=[0x00000000c8010000-0x00000000cb0dd000) (48MB)
>[    0.000000] efi: mem13: type=2, attr=0xf, range=[0x00000000cb0dd000-0x00000000cb11f000) (0MB)
>[    0.000000] efi: mem14: type=1, attr=0xf, range=[0x00000000cb11f000-0x00000000cb663000) (5MB)
>[    0.000000] efi: mem15: type=10, attr=0xf, range=[0x00000000cb663000-0x00000000cb66a000) (0MB)
>[    0.000000] efi: mem16: type=4, attr=0xf, range=[0x00000000cb66a000-0x00000000cb7c3000) (1MB)
>[    0.000000] efi: mem17: type=3, attr=0xf, range=[0x00000000cb7c3000-0x00000000cba75000) (2MB)
>[    0.000000] efi: mem18: type=4, attr=0xf, range=[0x00000000cba75000-0x00000000cba90000) (0MB)
>[    0.000000] efi: mem19: type=3, attr=0xf, range=[0x00000000cba90000-0x00000000cbaaa000) (0MB)
>[    0.000000] efi: mem20: type=4, attr=0xf, range=[0x00000000cbaaa000-0x00000000cbab4000) (0MB)
>[    0.000000] efi: mem21: type=6, attr=0x800000000000000f, range=[0x00000000cbab4000-0x00000000cbef2000) (4MB)
>[    0.000000] efi: mem22: type=4, attr=0xf, range=[0x00000000cbef2000-0x00000000cbf00000) (0MB)
>[    0.000000] efi: mem23: type=7, attr=0xf, range=[0x00000000cbf00000-0x00000000cbf0e000) (0MB)
>[    0.000000] efi: mem24: type=2, attr=0xf, range=[0x00000000cbf0e000-0x00000000cbf0f000) (0MB)
>[    0.000000] efi: mem25: type=7, attr=0xf, range=[0x00000000cbf0f000-0x00000000cf674000) (55MB)
>[    0.000000] efi: mem26: type=4, attr=0xf, range=[0x00000000cf674000-0x00000000cfc97000) (6MB)
>[    0.000000] efi: mem27: type=7, attr=0xf, range=[0x00000000cfc97000-0x00000000cfca1000) (0MB)
>[    0.000000] efi: mem28: type=4, attr=0xf, range=[0x00000000cfca1000-0x00000000cfcb8000) (0MB)
>[    0.000000] efi: mem29: type=7, attr=0xf, range=[0x00000000cfcb8000-0x00000000cfcc1000) (0MB)
>[    0.000000] efi: mem30: type=4, attr=0xf, range=[0x00000000cfcc1000-0x00000000cfcfe000) (0MB)
>[    0.000000] efi: mem31: type=7, attr=0xf, range=[0x00000000cfcfe000-0x00000000cfd0b000) (0MB)
>[    0.000000] efi: mem32: type=4, attr=0xf, range=[0x00000000cfd0b000-0x00000000cfd6e000) (0MB)
>[    0.000000] efi: mem33: type=7, attr=0xf, range=[0x00000000cfd6e000-0x00000000cfd8e000) (0MB)
>[    0.000000] efi: mem34: type=4, attr=0xf, range=[0x00000000cfd8e000-0x00000000cfdb5000) (0MB)
>[    0.000000] efi: mem35: type=7, attr=0xf, range=[0x00000000cfdb5000-0x00000000cfdc9000) (0MB)
>[    0.000000] efi: mem36: type=4, attr=0xf, range=[0x00000000cfdc9000-0x00000000cfdf5000) (0MB)
>[    0.000000] efi: mem37: type=7, attr=0xf, range=[0x00000000cfdf5000-0x00000000cfe0c000) (0MB)
>[    0.000000] efi: mem38: type=4, attr=0xf, range=[0x00000000cfe0c000-0x00000000cfe41000) (0MB)
>[    0.000000] efi: mem39: type=7, attr=0xf, range=[0x00000000cfe41000-0x00000000cfe59000) (0MB)
>[    0.000000] efi: mem40: type=4, attr=0xf, range=[0x00000000cfe59000-0x00000000cfe86000) (0MB)
>[    0.000000] efi: mem41: type=7, attr=0xf, range=[0x00000000cfe86000-0x00000000cfe9e000) (0MB)
>[    0.000000] efi: mem42: type=4, attr=0xf, range=[0x00000000cfe9e000-0x00000000cfea7000) (0MB)
>[    0.000000] efi: mem43: type=7, attr=0xf, range=[0x00000000cfea7000-0x00000000cff3b000) (0MB)
>[    0.000000] efi: mem44: type=4, attr=0xf, range=[0x00000000cff3b000-0x00000000cff9c000) (0MB)
>[    0.000000] efi: mem45: type=7, attr=0xf, range=[0x00000000cff9c000-0x00000000cffa6000) (0MB)
>[    0.000000] efi: mem46: type=4, attr=0xf, range=[0x00000000cffa6000-0x00000000d0003000) (0MB)
>[    0.000000] efi: mem47: type=7, attr=0xf, range=[0x00000000d0003000-0x00000000d0010000) (0MB)
>[    0.000000] efi: mem48: type=4, attr=0xf, range=[0x00000000d0010000-0x00000000d0072000) (0MB)
>[    0.000000] efi: mem49: type=7, attr=0xf, range=[0x00000000d0072000-0x00000000d0092000) (0MB)
>[    0.000000] efi: mem50: type=4, attr=0xf, range=[0x00000000d0092000-0x00000000d00ba000) (0MB)
>[    0.000000] efi: mem51: type=7, attr=0xf, range=[0x00000000d00ba000-0x00000000d00ce000) (0MB)
>[    0.000000] efi: mem52: type=4, attr=0xf, range=[0x00000000d00ce000-0x00000000d00f9000) (0MB)
>[    0.000000] efi: mem53: type=7, attr=0xf, range=[0x00000000d00f9000-0x00000000d0119000) (0MB)
>[    0.000000] efi: mem54: type=4, attr=0xf, range=[0x00000000d0119000-0x00000000d0144000) (0MB)
>[    0.000000] efi: mem55: type=7, attr=0xf, range=[0x00000000d0144000-0x00000000d015c000) (0MB)
>[    0.000000] efi: mem56: type=4, attr=0xf, range=[0x00000000d015c000-0x00000000d018a000) (0MB)
>[    0.000000] efi: mem57: type=7, attr=0xf, range=[0x00000000d018a000-0x00000000d01a2000) (0MB)
>[    0.000000] efi: mem58: type=4, attr=0xf, range=[0x00000000d01a2000-0x00000000d02a0000) (0MB)
>[    0.000000] efi: mem59: type=7, attr=0xf, range=[0x00000000d02a0000-0x00000000d02aa000) (0MB)
>[    0.000000] efi: mem60: type=4, attr=0xf, range=[0x00000000d02aa000-0x00000000d02c3000) (0MB)
>[    0.000000] efi: mem61: type=7, attr=0xf, range=[0x00000000d02c3000-0x00000000d02cc000) (0MB)
>[    0.000000] efi: mem62: type=4, attr=0xf, range=[0x00000000d02cc000-0x00000000d0309000) (0MB)
>[    0.000000] efi: mem63: type=7, attr=0xf, range=[0x00000000d0309000-0x00000000d0316000) (0MB)
>[    0.000000] efi: mem64: type=4, attr=0xf, range=[0x00000000d0316000-0x00000000d0379000) (0MB)
>[    0.000000] efi: mem65: type=7, attr=0xf, range=[0x00000000d0379000-0x00000000d0399000) (0MB)
>[    0.000000] efi: mem66: type=4, attr=0xf, range=[0x00000000d0399000-0x00000000d03bf000) (0MB)
>[    0.000000] efi: mem67: type=7, attr=0xf, range=[0x00000000d03bf000-0x00000000d03d3000) (0MB)
>[    0.000000] efi: mem68: type=4, attr=0xf, range=[0x00000000d03d3000-0x00000000d03fc000) (0MB)
>[    0.000000] efi: mem69: type=7, attr=0xf, range=[0x00000000d03fc000-0x00000000d0413000) (0MB)
>[    0.000000] efi: mem70: type=4, attr=0xf, range=[0x00000000d0413000-0x00000000d0449000) (0MB)
>[    0.000000] efi: mem71: type=7, attr=0xf, range=[0x00000000d0449000-0x00000000d0461000) (0MB)
>[    0.000000] efi: mem72: type=4, attr=0xf, range=[0x00000000d0461000-0x00000000d048f000) (0MB)
>[    0.000000] efi: mem73: type=7, attr=0xf, range=[0x00000000d048f000-0x00000000d04a7000) (0MB)
>[    0.000000] efi: mem74: type=4, attr=0xf, range=[0x00000000d04a7000-0x00000000d05a4000) (0MB)
>[    0.000000] efi: mem75: type=7, attr=0xf, range=[0x00000000d05a4000-0x00000000d05ae000) (0MB)
>[    0.000000] efi: mem76: type=4, attr=0xf, range=[0x00000000d05ae000-0x00000000d05c6000) (0MB)
>[    0.000000] efi: mem77: type=7, attr=0xf, range=[0x00000000d05c6000-0x00000000d05cf000) (0MB)
>[    0.000000] efi: mem78: type=4, attr=0xf, range=[0x00000000d05cf000-0x00000000d060c000) (0MB)
>[    0.000000] efi: mem79: type=7, attr=0xf, range=[0x00000000d060c000-0x00000000d0619000) (0MB)
>[    0.000000] efi: mem80: type=4, attr=0xf, range=[0x00000000d0619000-0x00000000d067d000) (0MB)
>[    0.000000] efi: mem81: type=7, attr=0xf, range=[0x00000000d067d000-0x00000000d069d000) (0MB)
>[    0.000000] efi: mem82: type=4, attr=0xf, range=[0x00000000d069d000-0x00000000d06c3000) (0MB)
>[    0.000000] efi: mem83: type=7, attr=0xf, range=[0x00000000d06c3000-0x00000000d06d7000) (0MB)
>[    0.000000] efi: mem84: type=4, attr=0xf, range=[0x00000000d06d7000-0x00000000d0700000) (0MB)
>[    0.000000] efi: mem85: type=7, attr=0xf, range=[0x00000000d0700000-0x00000000d0717000) (0MB)
>[    0.000000] efi: mem86: type=4, attr=0xf, range=[0x00000000d0717000-0x00000000d074e000) (0MB)
>[    0.000000] efi: mem87: type=7, attr=0xf, range=[0x00000000d074e000-0x00000000d0766000) (0MB)
>[    0.000000] efi: mem88: type=4, attr=0xf, range=[0x00000000d0766000-0x00000000d0792000) (0MB)
>[    0.000000] efi: mem89: type=7, attr=0xf, range=[0x00000000d0792000-0x00000000d07aa000) (0MB)
>[    0.000000] efi: mem90: type=4, attr=0xf, range=[0x00000000d07aa000-0x00000000d08af000) (1MB)
>[    0.000000] efi: mem91: type=7, attr=0xf, range=[0x00000000d08af000-0x00000000d08b9000) (0MB)
>[    0.000000] efi: mem92: type=4, attr=0xf, range=[0x00000000d08b9000-0x00000000d08d0000) (0MB)
>[    0.000000] efi: mem93: type=7, attr=0xf, range=[0x00000000d08d0000-0x00000000d08d9000) (0MB)
>[    0.000000] efi: mem94: type=4, attr=0xf, range=[0x00000000d08d9000-0x00000000d0916000) (0MB)
>[    0.000000] efi: mem95: type=7, attr=0xf, range=[0x00000000d0916000-0x00000000d0923000) (0MB)
>[    0.000000] efi: mem96: type=4, attr=0xf, range=[0x00000000d0923000-0x00000000d0986000) (0MB)
>[    0.000000] efi: mem97: type=7, attr=0xf, range=[0x00000000d0986000-0x00000000d099b000) (0MB)
>[    0.000000] efi: mem98: type=4, attr=0xf, range=[0x00000000d099b000-0x00000000d09cc000) (0MB)
>[    0.000000] efi: mem99: type=7, attr=0xf, range=[0x00000000d09cc000-0x00000000d09e0000) (0MB)
>[    0.000000] efi: mem100: type=4, attr=0xf, range=[0x00000000d09e0000-0x00000000d0a0b000) (0MB)
>[    0.000000] efi: mem101: type=7, attr=0xf, range=[0x00000000d0a0b000-0x00000000d0a0d000) (0MB)
>[    0.000000] efi: mem102: type=4, attr=0xf, range=[0x00000000d0a0d000-0x00000000d0a59000) (0MB)
>[    0.000000] efi: mem103: type=7, attr=0xf, range=[0x00000000d0a59000-0x00000000d0a5c000) (0MB)
>[    0.000000] efi: mem104: type=4, attr=0xf, range=[0x00000000d0a5c000-0x00000000d0a9e000) (0MB)
>[    0.000000] efi: mem105: type=7, attr=0xf, range=[0x00000000d0a9e000-0x00000000d0a9f000) (0MB)
>[    0.000000] efi: mem106: type=4, attr=0xf, range=[0x00000000d0a9f000-0x00000000d0b50000) (0MB)
>[    0.000000] efi: mem107: type=7, attr=0xf, range=[0x00000000d0b50000-0x00000000d0b59000) (0MB)
>[    0.000000] efi: mem108: type=4, attr=0xf, range=[0x00000000d0b59000-0x00000000d0bc0000) (0MB)
>[    0.000000] efi: mem109: type=7, attr=0xf, range=[0x00000000d0bc0000-0x00000000d0bca000) (0MB)
>[    0.000000] efi: mem110: type=4, attr=0xf, range=[0x00000000d0bca000-0x00000000d0be1000) (0MB)
>[    0.000000] efi: mem111: type=7, attr=0xf, range=[0x00000000d0be1000-0x00000000d0bea000) (0MB)
>[    0.000000] efi: mem112: type=4, attr=0xf, range=[0x00000000d0bea000-0x00000000d0cde000) (0MB)
>[    0.000000] efi: mem113: type=7, attr=0xf, range=[0x00000000d0cde000-0x00000000d0ce5000) (0MB)
>[    0.000000] efi: mem114: type=4, attr=0xf, range=[0x00000000d0ce5000-0x00000000d0f59000) (2MB)
>[    0.000000] efi: mem115: type=7, attr=0xf, range=[0x00000000d0f59000-0x00000000d0f61000) (0MB)
>[    0.000000] efi: mem116: type=4, attr=0xf, range=[0x00000000d0f61000-0x00000000d104f000) (0MB)
>[    0.000000] efi: mem117: type=7, attr=0xf, range=[0x00000000d104f000-0x00000000d1054000) (0MB)
>[    0.000000] efi: mem118: type=4, attr=0xf, range=[0x00000000d1054000-0x00000000d10cb000) (0MB)
>[    0.000000] efi: mem119: type=7, attr=0xf, range=[0x00000000d10cb000-0x00000000d10d5000) (0MB)
>[    0.000000] efi: mem120: type=4, attr=0xf, range=[0x00000000d10d5000-0x00000000d10f4000) (0MB)
>[    0.000000] efi: mem121: type=7, attr=0xf, range=[0x00000000d10f4000-0x00000000d10fd000) (0MB)
>[    0.000000] efi: mem122: type=4, attr=0xf, range=[0x00000000d10fd000-0x00000000d1191000) (0MB)
>[    0.000000] efi: mem123: type=7, attr=0xf, range=[0x00000000d1191000-0x00000000d1194000) (0MB)
>[    0.000000] efi: mem124: type=4, attr=0xf, range=[0x00000000d1194000-0x00000000d128f000) (0MB)
>[    0.000000] efi: mem125: type=7, attr=0xf, range=[0x00000000d128f000-0x00000000d1290000) (0MB)
>[    0.000000] efi: mem126: type=4, attr=0xf, range=[0x00000000d1290000-0x00000000d13b0000) (1MB)
>[    0.000000] efi: mem127: type=7, attr=0xf, range=[0x00000000d13b0000-0x00000000d13b2000) (0MB)
>[    0.000000] efi: mem128: type=4, attr=0xf, range=[0x00000000d13b2000-0x00000000d13f6000) (0MB)
>[    0.000000] efi: mem129: type=7, attr=0xf, range=[0x00000000d13f6000-0x00000000d13f8000) (0MB)
>[    0.000000] efi: mem130: type=4, attr=0xf, range=[0x00000000d13f8000-0x00000000d164b000) (2MB)
>[    0.000000] efi: mem131: type=7, attr=0xf, range=[0x00000000d164b000-0x00000000d164c000) (0MB)
>[    0.000000] efi: mem132: type=4, attr=0xf, range=[0x00000000d164c000-0x00000000dcadf000) (180MB)
>[    0.000000] efi: mem133: type=7, attr=0xf, range=[0x00000000dcadf000-0x00000000dd093000) (5MB)
>[    0.000000] efi: mem134: type=3, attr=0xf, range=[0x00000000dd093000-0x00000000dd7a6000) (7MB)
>[    0.000000] efi: mem135: type=0, attr=0xf, range=[0x00000000dd7a6000-0x00000000dd810000) (0MB)
>[    0.000000] efi: mem136: type=0, attr=0xf, range=[0x00000000dd810000-0x00000000dd9ae000) (1MB)
>[    0.000000] efi: mem137: type=9, attr=0xf, range=[0x00000000dd9ae000-0x00000000dd9b2000) (0MB)
>[    0.000000] efi: mem138: type=9, attr=0xf, range=[0x00000000dd9b2000-0x00000000dd9c4000) (0MB)
>[    0.000000] efi: mem139: type=10, attr=0xf, range=[0x00000000dd9c4000-0x00000000ddadc000) (1MB)
>[    0.000000] efi: mem140: type=10, attr=0xf, range=[0x00000000ddadc000-0x00000000ddf08000) (4MB)
>[    0.000000] efi: mem141: type=6, attr=0x800000000000000f, range=[0x00000000ddf08000-0x00000000de688000) (7MB)
>[    0.000000] efi: mem142: type=6, attr=0x800000000000000f, range=[0x00000000de688000-0x00000000dee89000) (8MB)
>[    0.000000] efi: mem143: type=6, attr=0x800000000000000f, range=[0x00000000dee89000-0x00000000dee8b000) (0MB)
>[    0.000000] efi: mem144: type=6, attr=0x800000000000000f, range=[0x00000000dee8b000-0x00000000deebb000) (0MB)
>[    0.000000] efi: mem145: type=6, attr=0x800000000000000f, range=[0x00000000deebb000-0x00000000deebe000) (0MB)
>[    0.000000] efi: mem146: type=6, attr=0x800000000000000f, range=[0x00000000deebe000-0x00000000def5c000) (0MB)
>[    0.000000] efi: mem147: type=5, attr=0x800000000000000f, range=[0x00000000def5c000-0x00000000def7d000) (0MB)
>[    0.000000] efi: mem148: type=5, attr=0x800000000000000f, range=[0x00000000def7d000-0x00000000defff000) (0MB)
>[    0.000000] efi: mem149: type=4, attr=0xf, range=[0x00000000defff000-0x00000000df000000) (0MB)
>[    0.000000] efi: mem150: type=7, attr=0xf, range=[0x0000000100000000-0x000000041f000000) (12784MB)
>[    0.000000] efi: mem151: type=11, attr=0x8000000000000001, range=[0x00000000f8000000-0x00000000fc000000) (64MB)
>[    0.000000] efi: mem152: type=11, attr=0x8000000000000001, range=[0x00000000fec00000-0x00000000fec01000) (0MB)
>[    0.000000] efi: mem153: type=11, attr=0x8000000000000001, range=[0x00000000fed00000-0x00000000fed04000) (0MB)
>[    0.000000] efi: mem154: type=11, attr=0x8000000000000001, range=[0x00000000fed1c000-0x00000000fed20000) (0MB)
>[    0.000000] efi: mem155: type=11, attr=0x8000000000000001, range=[0x00000000fee00000-0x00000000fee01000) (0MB)
>[    0.000000] efi: mem156: type=11, attr=0x8000000000000001, range=[0x00000000ff000000-0x0000000100000000) (16MB)
>[    0.000000] SMBIOS 2.7 present.
>[    0.000000] DMI: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] No AGP bridge found
>[    0.000000] e820: last_pfn = 0x41f000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: uncachable
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-CFFFF write-protect
>[    0.000000]   D0000-DFFFF uncachable
>[    0.000000]   E0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 0000000000 mask 7C00000000 write-back
>[    0.000000]   1 base 0400000000 mask 7FF0000000 write-back
>[    0.000000]   2 base 0410000000 mask 7FF8000000 write-back
>[    0.000000]   3 base 0418000000 mask 7FFC000000 write-back
>[    0.000000]   4 base 041C000000 mask 7FFE000000 write-back
>[    0.000000]   5 base 041E000000 mask 7FFF000000 write-back
>[    0.000000]   6 base 00E0000000 mask 7FE0000000 uncachable
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
>[    0.000000] e820: update [mem 0xe0000000-0xffffffff] usable ==> reserved
>[    0.000000] e820: last_pfn = 0xdf000 max_arch_pfn = 0x400000000
>[    0.000000] found SMP MP-table at [mem 0x000fd880-0x000fd88f] mapped at [ffff8800000fd880]
>[    0.000000] Scanning 1 areas for low memory corruption
>[    0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
>[    0.000000]  [mem 0x00000000-0x000fffff] page 4k
>[    0.000000] BRK [0x02ca5000, 0x02ca5fff] PGTABLE
>[    0.000000] BRK [0x02ca6000, 0x02ca6fff] PGTABLE
>[    0.000000] BRK [0x02ca7000, 0x02ca7fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x41ee00000-0x41effffff]
>[    0.000000]  [mem 0x41ee00000-0x41effffff] page 2M
>[    0.000000] BRK [0x02ca8000, 0x02ca8fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x41c000000-0x41edfffff]
>[    0.000000]  [mem 0x41c000000-0x41edfffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x400000000-0x41bffffff]
>[    0.000000]  [mem 0x400000000-0x41bffffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x00100000-0xcb662fff]
>[    0.000000]  [mem 0x00100000-0x001fffff] page 4k
>[    0.000000]  [mem 0x00200000-0x3fffffff] page 2M
>[    0.000000]  [mem 0x40000000-0xbfffffff] page 1G
>[    0.000000]  [mem 0xc0000000-0xcb5fffff] page 2M
>[    0.000000]  [mem 0xcb600000-0xcb662fff] page 4k
>[    0.000000] init_memory_mapping: [mem 0xcb66a000-0xcbab3fff]
>[    0.000000]  [mem 0xcb66a000-0xcb7fffff] page 4k
>[    0.000000]  [mem 0xcb800000-0xcb9fffff] page 2M
>[    0.000000]  [mem 0xcba00000-0xcbab3fff] page 4k
>[    0.000000] BRK [0x02ca9000, 0x02ca9fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0xcbef2000-0xdd7a5fff]
>[    0.000000]  [mem 0xcbef2000-0xcbffffff] page 4k
>[    0.000000]  [mem 0xcc000000-0xdd5fffff] page 2M
>[    0.000000]  [mem 0xdd600000-0xdd7a5fff] page 4k
>[    0.000000] BRK [0x02caa000, 0x02caafff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0xdefff000-0xdeffffff]
>[    0.000000]  [mem 0xdefff000-0xdeffffff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x100000000-0x3ffffffff]
>[    0.000000]  [mem 0x100000000-0x3ffffffff] page 1G
>[    0.000000] ACPI: RSDP 00000000dd9b2000 00024 (v02 ALASKA)
>[    0.000000] ACPI: XSDT 00000000dd9b2080 00074 (v01 ALASKA    A M I 01072009 AMI  00010013)
>[    0.000000] ACPI: FACP 00000000dd9bef08 0010C (v05 ALASKA    A M I 01072009 AMI  00010013)
>[    0.000000] ACPI: DSDT 00000000dd9b2188 0CD7B (v02 ALASKA    A M I 00000024 INTL 20091112)
>[    0.000000] ACPI: FACS 00000000ddf06080 00040
>[    0.000000] ACPI: APIC 00000000dd9bf018 00092 (v03 ALASKA    A M I 01072009 AMI  00010013)
>[    0.000000] ACPI: FPDT 00000000dd9bf0b0 00044 (v01 ALASKA    A M I 01072009 AMI  00010013)
>[    0.000000] ACPI: SSDT 00000000dd9bf0f8 00539 (v01  PmRef  Cpu0Ist 00003000 INTL 20051117)
>[    0.000000] ACPI: SSDT 00000000dd9bf638 00AD8 (v01  PmRef    CpuPm 00003000 INTL 20051117)
>[    0.000000] ACPI: SSDT 00000000dd9c0110 001C7 (v01  PmRef LakeTiny 00003000 INTL 20051117)
>[    0.000000] ACPI: MCFG 00000000dd9c02d8 0003C (v01 ALASKA    A M I 01072009 MSFT 00000097)
>[    0.000000] ACPI: HPET 00000000dd9c0318 00038 (v01 ALASKA    A M I 01072009 AMI. 00000005)
>[    0.000000] ACPI: SSDT 00000000dd9c0350 0036D (v01 SataRe SataTabl 00001000 INTL 20091112)
>[    0.000000] ACPI: SSDT 00000000dd9c06c0 0329E (v01 SaSsdt  SaSsdt  00003000 INTL 20091112)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000041effffff]
>[    0.000000] Initmem setup node 0 [mem 0x00000000-0x41effffff]
>[    0.000000]   NODE_DATA [mem 0x41eff8000-0x41effbfff]
>[    0.000000]  [ffffea0000000000-ffffea00107fffff] PMD -> [ffff88040e600000-ffff88041e5fffff] on node 0
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x00001000-0x00ffffff]
>[    0.000000]   DMA32    [mem 0x01000000-0xffffffff]
>[    0.000000]   Normal   [mem 0x100000000-0x41effffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x00001000-0x00057fff]
>[    0.000000]   node   0: [mem 0x00059000-0x0009efff]
>[    0.000000]   node   0: [mem 0x00100000-0xcb662fff]
>[    0.000000]   node   0: [mem 0xcb66a000-0xcbab3fff]
>[    0.000000]   node   0: [mem 0xcbef2000-0xdd7a5fff]
>[    0.000000]   node   0: [mem 0xdefff000-0xdeffffff]
>[    0.000000]   node   0: [mem 0x100000000-0x41effffff]
>[    0.000000] On node 0 totalpages: 4178687
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 24 pages reserved
>[    0.000000]   DMA zone: 3997 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 14094 pages used for memmap
>[    0.000000]   DMA32 zone: 901986 pages, LIFO batch:31
>[    0.000000]   Normal zone: 51136 pages used for memmap
>[    0.000000]   Normal zone: 3272704 pages, LIFO batch:31
>[    0.000000] ACPI: PM-Timer IO Port: 0x1808
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x01] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x03] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x05] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x07] enabled)
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
>[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ2 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
>[    0.000000] smpboot: Allowing 8 CPUs, 0 hotplug CPUs
>[    0.000000] nr_irqs_gsi: 40
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb0dd000-0xcb0ddfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb0ed000-0xcb0edfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb0ee000-0xcb0eefff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb0fe000-0xcb0fefff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb0ff000-0xcb0fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb11e000-0xcb11efff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcb663000-0xcb669fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xcbab4000-0xcbef1fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xdd7a6000-0xdd9adfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xdd9ae000-0xdd9c3fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xdd9c4000-0xddf07fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xddf08000-0xdeffefff]
>[    0.000000] PM: Registered nosave memory: [mem 0xdf000000-0xf7ffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xf8000000-0xfbffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfc000000-0xfebfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfecfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed00000-0xfed03fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed04000-0xfed1bfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed20000-0xfedfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff]
>[    0.000000] e820: [mem 0xdf000000-0xf7ffffff] available for PCI devices
>[    0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1
>[    0.000000] PERCPU: Embedded 26 pages/cpu @ffff88041ec00000 s74304 r8192 d24000 u262144
>[    0.000000] pcpu-alloc: s74304 r8192 d24000 u262144 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 
>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 4113369
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: root=/dev/sda5 resume=/dev/sda4 nouveau.debug="PVP=debug,PBSP=debug,PPPP=debug"
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340
>[    0.000000] Checking aperture...
>[    0.000000] No AGP bridge found
>[    0.000000] Memory: 16146676K/16714748K available (7222K kernel code, 739K rwdata, 2588K rodata, 884K init, 1460K bss, 568072K reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] NR_IRQS:4352 nr_irqs:744 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] hpet clockevent registered
>[    0.000000] tsc: Fast TSC calibration using PIT
>[    0.001000] tsc: Detected 3292.380 MHz processor
>[    0.000001] Calibrating delay loop (skipped), value calculated using timer frequency.. 6584.76 BogoMIPS (lpj=3292380)
>[    0.000004] pid_max: default: 32768 minimum: 301
>[    0.000014] init_memory_mapping: [mem 0xcbab4000-0xcbef1fff]
>[    0.000016]  [mem 0xcbab4000-0xcbbfffff] page 4k
>[    0.000017]  [mem 0xcbc00000-0xcbdfffff] page 2M
>[    0.000018]  [mem 0xcbe00000-0xcbef1fff] page 4k
>[    0.000035] init_memory_mapping: [mem 0xddf08000-0xdef5bfff]
>[    0.000036]  [mem 0xddf08000-0xddffffff] page 4k
>[    0.000037]  [mem 0xde000000-0xdedfffff] page 2M
>[    0.000038]  [mem 0xdee00000-0xdef5bfff] page 4k
>[    0.000048] init_memory_mapping: [mem 0xdef5c000-0xdeffefff]
>[    0.000050]  [mem 0xdef5c000-0xdeffefff] page 4k
>[    0.004693] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>[    0.006724] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.007590] Mount-cache hash table entries: 256
>[    0.007713] Initializing cgroup subsys freezer
>[    0.007729] CPU: Physical Processor ID: 0
>[    0.007731] CPU: Processor Core ID: 0
>[    0.007734] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.008457] mce: CPU supports 9 MCE banks
>[    0.008468] CPU0: Thermal monitoring enabled (TM1)
>[    0.008477] Last level iTLB entries: 4KB 0, 2MB 0, 4MB 0
>Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0
>tlb_flushall_shift: 6
>[    0.008578] Freeing SMP alternatives memory: 28K (ffffffff81b2f000 - ffffffff81b36000)
>[    0.008581] ACPI: Core revision 20130725
>[    0.013312] ACPI: All ACPI Tables successfully acquired
>[    0.028258] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.038261] smpboot: CPU0: Intel(R) Xeon(R) CPU E3-1230 v3 @ 3.30GHz (fam: 06, model: 3c, stepping: 03)
>[    0.038267] TSC deadline timer enabled
>[    0.038272] Performance Events: PEBS fmt2+, 16-deep LBR, Haswell events, full-width counters, Intel PMU driver.
>[    0.038278] ... version:                3
>[    0.038279] ... bit width:              48
>[    0.038280] ... generic registers:      4
>[    0.038282] ... value mask:             0000ffffffffffff
>[    0.038283] ... max period:             0000ffffffffffff
>[    0.038284] ... fixed-purpose events:   3
>[    0.038285] ... event mask:             000000070000000f
>[    0.038407] smpboot: Booting Node   0, Processors  #   1 #   2 #   3 #   4 #   5 #   6 #   7 OK
>[    0.136111] Brought up 8 CPUs
>[    0.136115] smpboot: Total of 8 processors activated (52678.08 BogoMIPS)
>[    0.141987] devtmpfs: initialized
>[    0.142132] PM: Registering ACPI NVS region [mem 0xcb663000-0xcb669fff] (28672 bytes)
>[    0.142135] PM: Registering ACPI NVS region [mem 0xdd9c4000-0xddf07fff] (5521408 bytes)
>[    0.142283] pinctrl core: initialized pinctrl subsystem
>[    0.142349] regulator-dummy: no parameters
>[    0.142396] NET: Registered protocol family 16
>[    0.142615] cpuidle: using governor ladder
>[    0.142617] cpuidle: using governor menu
>[    0.142645] ACPI: bus type PCI registered
>[    0.142647] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>[    0.142711] dca service started, version 1.12.1
>[    0.142737] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000)
>[    0.142740] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820
>[    0.145923] PCI: Using configuration type 1 for base access
>[    0.150937] bio: create slab <bio-0> at 0
>[    0.151090] ACPI: Added _OSI(Module Device)
>[    0.151091] ACPI: Added _OSI(Processor Device)
>[    0.151093] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.151094] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.152193] ACPI: EC: Look up EC in DSDT
>[    0.153481] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.155002] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
>[    0.158930] ACPI: SSDT 00000000dd9a3c18 003D3 (v01  PmRef  Cpu0Cst 00003001 INTL 20051117)
>[    0.159204] ACPI: Dynamic OEM Table Load:
>[    0.159206] ACPI: SSDT           (null) 003D3 (v01  PmRef  Cpu0Cst 00003001 INTL 20051117)
>[    0.168027] ACPI: SSDT 00000000dd9a3618 005AA (v01  PmRef    ApIst 00003000 INTL 20051117)
>[    0.168343] ACPI: Dynamic OEM Table Load:
>[    0.168345] ACPI: SSDT           (null) 005AA (v01  PmRef    ApIst 00003000 INTL 20051117)
>[    0.172948] ACPI: SSDT 00000000dd9a2d98 00119 (v01  PmRef    ApCst 00003000 INTL 20051117)
>[    0.173219] ACPI: Dynamic OEM Table Load:
>[    0.173221] ACPI: SSDT           (null) 00119 (v01  PmRef    ApCst 00003000 INTL 20051117)
>[    0.178669] ACPI: Interpreter enabled
>[    0.178675] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20130725/hwxface-571)
>[    0.178680] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20130725/hwxface-571)
>[    0.178692] ACPI: (supports S0 S3 S4 S5)
>[    0.178693] ACPI: Using IOAPIC for interrupt routing
>[    0.178724] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.178841] ACPI: No dock devices found.
>[    0.185413] ACPI: Power Resource [FN00] (off)
>[    0.185479] ACPI: Power Resource [FN01] (off)
>[    0.185543] ACPI: Power Resource [FN02] (off)
>[    0.185608] ACPI: Power Resource [FN03] (off)
>[    0.185673] ACPI: Power Resource [FN04] (off)
>[    0.186229] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e])
>[    0.186330] acpi PNP0A08:00: Requesting ACPI _OSC control (0x1d)
>[    0.186556] acpi PNP0A08:00: ACPI _OSC control (0x1d) granted
>[    0.186822] ACPI: \_SB_.PCI0.TPMX: can't evaluate _ADR (0x5)
>[    0.186830] ACPI: \_SB_.PCI0.WMI1: can't evaluate _ADR (0x5)
>[    0.186879] ACPI: \_SB_.PCI0.PDRC: can't evaluate _ADR (0x5)
>[    0.186881] ACPI: \_SB_.PCI0.DOCK: can't evaluate _ADR (0x5)
>[    0.186895] PCI host bridge to bus 0000:00
>[    0.186897] pci_bus 0000:00: root bus resource [bus 00-3e]
>[    0.186899] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7]
>[    0.186901] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff]
>[    0.186902] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
>[    0.186904] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff]
>[    0.186906] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff]
>[    0.186908] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff]
>[    0.186910] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff]
>[    0.186911] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xfeafffff]
>[    0.186917] pci 0000:00:00.0: [8086:0c08] type 00 class 0x060000
>[    0.186993] pci 0000:00:01.0: [8086:0c01] type 01 class 0x060400
>[    0.187016] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
>[    0.187055] pci 0000:00:01.0: System wakeup disabled by ACPI
>[    0.187106] pci 0000:00:14.0: [8086:8c31] type 00 class 0x0c0330
>[    0.187122] pci 0000:00:14.0: reg 0x10: [mem 0xf7400000-0xf740ffff 64bit]
>[    0.187172] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.187204] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    0.187236] pci 0000:00:16.0: [8086:8c3a] type 00 class 0x078000
>[    0.187252] pci 0000:00:16.0: reg 0x10: [mem 0xf7419000-0xf741900f 64bit]
>[    0.187306] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
>[    0.187375] pci 0000:00:1b.0: [8086:8c20] type 00 class 0x040300
>[    0.187386] pci 0000:00:1b.0: reg 0x10: [mem 0xf7410000-0xf7413fff 64bit]
>[    0.187432] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>[    0.187466] pci 0000:00:1b.0: System wakeup disabled by ACPI
>[    0.187495] pci 0000:00:1c.0: [8086:8c10] type 01 class 0x060400
>[    0.187549] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.187583] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[    0.187612] pci 0000:00:1c.1: [8086:244e] type 01 class 0x060401
>[    0.187666] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
>[    0.187699] pci 0000:00:1c.1: System wakeup disabled by ACPI
>[    0.187729] pci 0000:00:1c.2: [8086:8c14] type 01 class 0x060400
>[    0.187782] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold
>[    0.187816] pci 0000:00:1c.2: System wakeup disabled by ACPI
>[    0.187845] pci 0000:00:1c.3: [8086:8c16] type 01 class 0x060400
>[    0.187899] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
>[    0.187937] pci 0000:00:1c.3: System wakeup disabled by ACPI
>[    0.187974] pci 0000:00:1d.0: [8086:8c26] type 00 class 0x0c0320
>[    0.187992] pci 0000:00:1d.0: reg 0x10: [mem 0xf7417000-0xf74173ff]
>[    0.188067] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
>[    0.188111] pci 0000:00:1d.0: System wakeup disabled by ACPI
>[    0.188145] pci 0000:00:1f.0: [8086:8c56] type 00 class 0x060100
>[    0.188292] pci 0000:00:1f.2: [8086:8c02] type 00 class 0x010601
>[    0.188305] pci 0000:00:1f.2: reg 0x10: [io  0xf070-0xf077]
>[    0.188310] pci 0000:00:1f.2: reg 0x14: [io  0xf060-0xf063]
>[    0.188316] pci 0000:00:1f.2: reg 0x18: [io  0xf050-0xf057]
>[    0.188322] pci 0000:00:1f.2: reg 0x1c: [io  0xf040-0xf043]
>[    0.188328] pci 0000:00:1f.2: reg 0x20: [io  0xf020-0xf03f]
>[    0.188334] pci 0000:00:1f.2: reg 0x24: [mem 0xf7416000-0xf74167ff]
>[    0.188364] pci 0000:00:1f.2: PME# supported from D3hot
>[    0.188418] pci 0000:00:1f.3: [8086:8c22] type 00 class 0x0c0500
>[    0.188430] pci 0000:00:1f.3: reg 0x10: [mem 0xf7415000-0xf74150ff 64bit]
>[    0.188447] pci 0000:00:1f.3: reg 0x20: [io  0xf000-0xf01f]
>[    0.188554] pci 0000:01:00.0: [10de:11c0] type 00 class 0x030000
>[    0.188563] pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
>[    0.188573] pci 0000:01:00.0: reg 0x14: [mem 0xe8000000-0xefffffff 64bit pref]
>[    0.188582] pci 0000:01:00.0: reg 0x1c: [mem 0xf0000000-0xf1ffffff 64bit pref]
>[    0.188589] pci 0000:01:00.0: reg 0x24: [io  0xe000-0xe07f]
>[    0.188596] pci 0000:01:00.0: reg 0x30: [mem 0xf7000000-0xf707ffff pref]
>[    0.188642] pci 0000:01:00.0: System wakeup disabled by ACPI
>[    0.188677] pci 0000:01:00.1: [10de:0e0b] type 00 class 0x040300
>[    0.188686] pci 0000:01:00.1: reg 0x10: [mem 0xf7080000-0xf7083fff]
>[    0.189935] pci 0000:00:01.0: PCI bridge to [bus 01]
>[    0.189937] pci 0000:00:01.0:   bridge window [io  0xe000-0xefff]
>[    0.189939] pci 0000:00:01.0:   bridge window [mem 0xf6000000-0xf70fffff]
>[    0.189942] pci 0000:00:01.0:   bridge window [mem 0xe8000000-0xf1ffffff 64bit pref]
>[    0.189989] pci 0000:00:1c.0: PCI bridge to [bus 02]
>[    0.190088] pci 0000:03:00.0: [1b21:1080] type 01 class 0x060401
>[    0.190214] pci 0000:03:00.0: System wakeup disabled by ACPI
>[    0.190241] pci 0000:00:1c.1: PCI bridge to [bus 03-04] (subtractive decode)
>[    0.190244] pci 0000:00:1c.1:   bridge window [io  0xd000-0xdfff]
>[    0.190247] pci 0000:00:1c.1:   bridge window [mem 0xf7300000-0xf73fffff]
>[    0.190251] pci 0000:00:1c.1:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
>[    0.190252] pci 0000:00:1c.1:   bridge window [io  0x0d00-0xffff] (subtractive decode)
>[    0.190253] pci 0000:00:1c.1:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
>[    0.190254] pci 0000:00:1c.1:   bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
>[    0.190256] pci 0000:00:1c.1:   bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
>[    0.190257] pci 0000:00:1c.1:   bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
>[    0.190258] pci 0000:00:1c.1:   bridge window [mem 0x000dc000-0x000dffff] (subtractive decode)
>[    0.190259] pci 0000:00:1c.1:   bridge window [mem 0xe0000000-0xfeafffff] (subtractive decode)
>[    0.190325] pci 0000:04:02.0: [1106:3044] type 00 class 0x0c0010
>[    0.190350] pci 0000:04:02.0: reg 0x10: [mem 0xf7300000-0xf73007ff]
>[    0.190365] pci 0000:04:02.0: reg 0x14: [io  0xd000-0xd07f]
>[    0.190472] pci 0000:04:02.0: supports D2
>[    0.190474] pci 0000:04:02.0: PME# supported from D2 D3hot D3cold
>[    0.190566] pci 0000:03:00.0: PCI bridge to [bus 04] (subtractive decode)
>[    0.190574] pci 0000:03:00.0:   bridge window [io  0xd000-0xdfff]
>[    0.190578] pci 0000:03:00.0:   bridge window [mem 0xf7300000-0xf73fffff]
>[    0.190585] pci 0000:03:00.0:   bridge window [io  0xd000-0xdfff] (subtractive decode)
>[    0.190587] pci 0000:03:00.0:   bridge window [mem 0xf7300000-0xf73fffff] (subtractive decode)
>[    0.190588] pci 0000:03:00.0:   bridge window [??? 0x00000000 flags 0x0] (subtractive decode)
>[    0.190589] pci 0000:03:00.0:   bridge window [??? 0x00000000 flags 0x0] (subtractive decode)
>[    0.190590] pci 0000:03:00.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
>[    0.190591] pci 0000:03:00.0:   bridge window [io  0x0d00-0xffff] (subtractive decode)
>[    0.190593] pci 0000:03:00.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
>[    0.190594] pci 0000:03:00.0:   bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
>[    0.190595] pci 0000:03:00.0:   bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
>[    0.190596] pci 0000:03:00.0:   bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
>[    0.190597] pci 0000:03:00.0:   bridge window [mem 0x000dc000-0x000dffff] (subtractive decode)
>[    0.190598] pci 0000:03:00.0:   bridge window [mem 0xe0000000-0xfeafffff] (subtractive decode)
>[    0.190697] pci 0000:05:00.0: [8086:1533] type 00 class 0x020000
>[    0.190716] pci 0000:05:00.0: reg 0x10: [mem 0xf7200000-0xf727ffff]
>[    0.190742] pci 0000:05:00.0: reg 0x18: [io  0xc000-0xc01f]
>[    0.190755] pci 0000:05:00.0: reg 0x1c: [mem 0xf7280000-0xf7283fff]
>[    0.190865] pci 0000:05:00.0: PME# supported from D0 D3hot D3cold
>[    0.190896] pci 0000:05:00.0: System wakeup disabled by ACPI
>[    0.192951] pci 0000:00:1c.2: PCI bridge to [bus 05]
>[    0.192954] pci 0000:00:1c.2:   bridge window [io  0xc000-0xcfff]
>[    0.192957] pci 0000:00:1c.2:   bridge window [mem 0xf7200000-0xf72fffff]
>[    0.193050] pci 0000:06:00.0: [8086:1533] type 00 class 0x020000
>[    0.193069] pci 0000:06:00.0: reg 0x10: [mem 0xf7100000-0xf717ffff]
>[    0.193094] pci 0000:06:00.0: reg 0x18: [io  0xb000-0xb01f]
>[    0.193108] pci 0000:06:00.0: reg 0x1c: [mem 0xf7180000-0xf7183fff]
>[    0.193218] pci 0000:06:00.0: PME# supported from D0 D3hot D3cold
>[    0.193249] pci 0000:06:00.0: System wakeup disabled by ACPI
>[    0.194952] pci 0000:00:1c.3: PCI bridge to [bus 06]
>[    0.194955] pci 0000:00:1c.3:   bridge window [io  0xb000-0xbfff]
>[    0.194958] pci 0000:00:1c.3:   bridge window [mem 0xf7100000-0xf71fffff]
>[    0.195524] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
>[    0.195555] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
>[    0.195584] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12 *14 15)
>[    0.195613] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 *5 6 7 10 11 12 14 15)
>[    0.195641] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
>[    0.195670] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 *15)
>[    0.195699] ACPI: PCI Interrupt Link [LNKG] (IRQs *3 4 5 6 7 10 11 12 14 15)
>[    0.195727] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 *6 7 10 11 12 14 15)
>[    0.195996] ACPI: Enabled 5 GPEs in block 00 to 3F
>[    0.196001] ACPI: \_SB_.PCI0: notify handler is installed
>[    0.196040] Found 1 acpi root devices
>[    0.196127] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none
>[    0.196129] vgaarb: loaded
>[    0.196130] vgaarb: bridge control possible 0000:01:00.0
>[    0.196199] SCSI subsystem initialized
>[    0.196234] libata version 3.00 loaded.
>[    0.196282] ACPI: bus type USB registered
>[    0.196312] usbcore: registered new interface driver usbfs
>[    0.196327] usbcore: registered new interface driver hub
>[    0.196348] usbcore: registered new device driver usb
>[    0.196400] pps_core: LinuxPPS API ver. 1 registered
>[    0.196401] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    0.196414] PTP clock support registered
>[    0.196450] EDAC MC: Ver: 3.0.0
>[    0.196716] wmi: Mapper loaded
>[    0.196734] Advanced Linux Sound Architecture Driver Initialized.
>[    0.196735] PCI: Using ACPI for IRQ routing
>[    0.197898] PCI: pci_cache_line_size set to 64 bytes
>[    0.197973] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    0.197974] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
>[    0.197975] e820: reserve RAM buffer [mem 0xcb0dd018-0xcbffffff]
>[    0.197976] e820: reserve RAM buffer [mem 0xcb0ee018-0xcbffffff]
>[    0.197977] e820: reserve RAM buffer [mem 0xcb0ff018-0xcbffffff]
>[    0.197978] e820: reserve RAM buffer [mem 0xcb663000-0xcbffffff]
>[    0.197979] e820: reserve RAM buffer [mem 0xcbab4000-0xcbffffff]
>[    0.197980] e820: reserve RAM buffer [mem 0xdd7a6000-0xdfffffff]
>[    0.197981] e820: reserve RAM buffer [mem 0xdf000000-0xdfffffff]
>[    0.197982] e820: reserve RAM buffer [mem 0x41f000000-0x41fffffff]
>[    0.198101] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    0.198106] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
>[    0.200122] Switched to clocksource hpet
>[    0.202230] pnp: PnP ACPI init
>[    0.202237] ACPI: bus type PNP registered
>[    0.202287] system 00:00: [mem 0xfed40000-0xfed44fff] has been reserved
>[    0.202290] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
>[    0.202296] pnp 00:01: [dma 4]
>[    0.202320] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active)
>[    0.202348] pnp 00:02: Plug and Play ACPI device, IDs INT0800 (active)
>[    0.202421] pnp 00:03: Plug and Play ACPI device, IDs PNP0103 (active)
>[    0.202464] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
>[    0.202549] system 00:05: [io  0x0680-0x069f] has been reserved
>[    0.202551] system 00:05: [io  0xffff] has been reserved
>[    0.202553] system 00:05: [io  0xffff] has been reserved
>[    0.202555] system 00:05: [io  0xffff] has been reserved
>[    0.202557] system 00:05: [io  0x1c00-0x1cfe] has been reserved
>[    0.202558] system 00:05: [io  0x1d00-0x1dfe] has been reserved
>[    0.202560] system 00:05: [io  0x1e00-0x1efe] has been reserved
>[    0.202562] system 00:05: [io  0x1f00-0x1ffe] has been reserved
>[    0.202564] system 00:05: [io  0x1800-0x18fe] could not be reserved
>[    0.202566] system 00:05: [io  0x164e-0x164f] has been reserved
>[    0.202568] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.202602] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    0.202646] system 00:07: [io  0x1854-0x1857] has been reserved
>[    0.202648] system 00:07: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
>[    0.202714] system 00:08: [io  0x0290-0x029f] has been reserved
>[    0.202716] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.202828] system 00:09: [io  0x04d0-0x04d1] has been reserved
>[    0.202830] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.202955] pnp 00:0a: [dma 0 disabled]
>[    0.202999] pnp 00:0a: Plug and Play ACPI device, IDs PNP0501 (active)
>[    0.203282] system 00:0b: [mem 0xfed1c000-0xfed1ffff] has been reserved
>[    0.203284] system 00:0b: [mem 0xfed10000-0xfed17fff] has been reserved
>[    0.203286] system 00:0b: [mem 0xfed18000-0xfed18fff] has been reserved
>[    0.203288] system 00:0b: [mem 0xfed19000-0xfed19fff] has been reserved
>[    0.203290] system 00:0b: [mem 0xf8000000-0xfbffffff] has been reserved
>[    0.203292] system 00:0b: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    0.203294] system 00:0b: [mem 0xfed90000-0xfed93fff] has been reserved
>[    0.203296] system 00:0b: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    0.203298] system 00:0b: [mem 0xff000000-0xffffffff] has been reserved
>[    0.203300] system 00:0b: [mem 0xfee00000-0xfeefffff] could not be reserved
>[    0.203302] system 00:0b: [mem 0xf7fef000-0xf7feffff] has been reserved
>[    0.203304] system 00:0b: [mem 0xf7ff0000-0xf7ff0fff] has been reserved
>[    0.203306] system 00:0b: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.203451] pnp: PnP ACPI: found 12 devices
>[    0.203453] ACPI: bus type PNP unregistered
>[    0.208058] pci 0000:00:1c.0: bridge window [io  0x1000-0x0fff] to [bus 02] add_size 1000
>[    0.208060] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000
>[    0.208062] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000
>[    0.208089] pci 0000:00:1c.0: res[8]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[    0.208090] pci 0000:00:1c.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[    0.208091] pci 0000:00:1c.0: res[7]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[    0.208094] pci 0000:00:1c.0: BAR 8: assigned [mem 0xe0000000-0xe01fffff]
>[    0.208097] pci 0000:00:1c.0: BAR 9: assigned [mem 0xe0200000-0xe03fffff 64bit pref]
>[    0.208100] pci 0000:00:1c.0: BAR 7: assigned [io  0x2000-0x2fff]
>[    0.208102] pci 0000:00:01.0: PCI bridge to [bus 01]
>[    0.208104] pci 0000:00:01.0:   bridge window [io  0xe000-0xefff]
>[    0.208107] pci 0000:00:01.0:   bridge window [mem 0xf6000000-0xf70fffff]
>[    0.208110] pci 0000:00:01.0:   bridge window [mem 0xe8000000-0xf1ffffff 64bit pref]
>[    0.208113] pci 0000:00:1c.0: PCI bridge to [bus 02]
>[    0.208115] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
>[    0.208119] pci 0000:00:1c.0:   bridge window [mem 0xe0000000-0xe01fffff]
>[    0.208129] pci 0000:00:1c.0:   bridge window [mem 0xe0200000-0xe03fffff 64bit pref]
>[    0.208134] pci 0000:03:00.0: PCI bridge to [bus 04]
>[    0.208137] pci 0000:03:00.0:   bridge window [io  0xd000-0xdfff]
>[    0.208144] pci 0000:03:00.0:   bridge window [mem 0xf7300000-0xf73fffff]
>[    0.208155] pci 0000:00:1c.1: PCI bridge to [bus 03-04]
>[    0.208157] pci 0000:00:1c.1:   bridge window [io  0xd000-0xdfff]
>[    0.208161] pci 0000:00:1c.1:   bridge window [mem 0xf7300000-0xf73fffff]
>[    0.208168] pci 0000:00:1c.2: PCI bridge to [bus 05]
>[    0.208170] pci 0000:00:1c.2:   bridge window [io  0xc000-0xcfff]
>[    0.208174] pci 0000:00:1c.2:   bridge window [mem 0xf7200000-0xf72fffff]
>[    0.208180] pci 0000:00:1c.3: PCI bridge to [bus 06]
>[    0.208182] pci 0000:00:1c.3:   bridge window [io  0xb000-0xbfff]
>[    0.208186] pci 0000:00:1c.3:   bridge window [mem 0xf7100000-0xf71fffff]
>[    0.208193] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
>[    0.208194] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
>[    0.208195] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
>[    0.208196] pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff]
>[    0.208197] pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff]
>[    0.208198] pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff]
>[    0.208199] pci_bus 0000:00: resource 10 [mem 0x000dc000-0x000dffff]
>[    0.208201] pci_bus 0000:00: resource 11 [mem 0xe0000000-0xfeafffff]
>[    0.208202] pci_bus 0000:01: resource 0 [io  0xe000-0xefff]
>[    0.208203] pci_bus 0000:01: resource 1 [mem 0xf6000000-0xf70fffff]
>[    0.208204] pci_bus 0000:01: resource 2 [mem 0xe8000000-0xf1ffffff 64bit pref]
>[    0.208205] pci_bus 0000:02: resource 0 [io  0x2000-0x2fff]
>[    0.208206] pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe01fffff]
>[    0.208207] pci_bus 0000:02: resource 2 [mem 0xe0200000-0xe03fffff 64bit pref]
>[    0.208208] pci_bus 0000:03: resource 0 [io  0xd000-0xdfff]
>[    0.208210] pci_bus 0000:03: resource 1 [mem 0xf7300000-0xf73fffff]
>[    0.208211] pci_bus 0000:03: resource 4 [io  0x0000-0x0cf7]
>[    0.208212] pci_bus 0000:03: resource 5 [io  0x0d00-0xffff]
>[    0.208213] pci_bus 0000:03: resource 6 [mem 0x000a0000-0x000bffff]
>[    0.208214] pci_bus 0000:03: resource 7 [mem 0x000d0000-0x000d3fff]
>[    0.208215] pci_bus 0000:03: resource 8 [mem 0x000d4000-0x000d7fff]
>[    0.208216] pci_bus 0000:03: resource 9 [mem 0x000d8000-0x000dbfff]
>[    0.208217] pci_bus 0000:03: resource 10 [mem 0x000dc000-0x000dffff]
>[    0.208218] pci_bus 0000:03: resource 11 [mem 0xe0000000-0xfeafffff]
>[    0.208219] pci_bus 0000:04: resource 0 [io  0xd000-0xdfff]
>[    0.208220] pci_bus 0000:04: resource 1 [mem 0xf7300000-0xf73fffff]
>[    0.208222] pci_bus 0000:04: resource 4 [io  0xd000-0xdfff]
>[    0.208223] pci_bus 0000:04: resource 5 [mem 0xf7300000-0xf73fffff]
>[    0.208224] pci_bus 0000:04: resource 8 [io  0x0000-0x0cf7]
>[    0.208225] pci_bus 0000:04: resource 9 [io  0x0d00-0xffff]
>[    0.208226] pci_bus 0000:04: resource 10 [mem 0x000a0000-0x000bffff]
>[    0.208227] pci_bus 0000:04: resource 11 [mem 0x000d0000-0x000d3fff]
>[    0.208228] pci_bus 0000:04: resource 12 [mem 0x000d4000-0x000d7fff]
>[    0.208229] pci_bus 0000:04: resource 13 [mem 0x000d8000-0x000dbfff]
>[    0.208230] pci_bus 0000:04: resource 14 [mem 0x000dc000-0x000dffff]
>[    0.208231] pci_bus 0000:04: resource 15 [mem 0xe0000000-0xfeafffff]
>[    0.208233] pci_bus 0000:05: resource 0 [io  0xc000-0xcfff]
>[    0.208234] pci_bus 0000:05: resource 1 [mem 0xf7200000-0xf72fffff]
>[    0.208235] pci_bus 0000:06: resource 0 [io  0xb000-0xbfff]
>[    0.208236] pci_bus 0000:06: resource 1 [mem 0xf7100000-0xf71fffff]
>[    0.208252] NET: Registered protocol family 2
>[    0.208403] TCP established hash table entries: 131072 (order: 9, 2097152 bytes)
>[    0.208594] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[    0.208691] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.208704] TCP: reno registered
>[    0.208718] UDP hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.208756] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.208818] NET: Registered protocol family 1
>[    0.208864] RPC: Registered named UNIX socket transport module.
>[    0.208866] RPC: Registered udp transport module.
>[    0.208867] RPC: Registered tcp transport module.
>[    0.208868] RPC: Registered tcp NFSv4.1 backchannel transport module.
>[    0.208933] pci 0000:00:14.0: Configurable ports to enable SuperSpeed: 0x3f
>[    0.208936] pci 0000:00:14.0: USB 3.0 ports that are now enabled under xHCI: 0x3f
>[    0.208937] pci 0000:00:14.0: Configurable USB 2.0 ports to hand over to xCHI: 0x7fff
>[    0.208940] pci 0000:00:14.0: USB 2.0 ports that are now switched over to xHCI: 0x7fff
>[    0.209021] pci 0000:00:1d.0: EHCI: BIOS handoff
>[    0.224217] pci 0000:01:00.0: Boot video device
>[    0.224253] PCI: CLS 64 bytes, default 64
>[    0.224281] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    0.224284] software IO TLB [mem 0xc70dd000-0xcb0dd000] (64MB) mapped at [ffff8800c70dd000-ffff8800cb0dcfff]
>[    0.224980] microcode: CPU0 sig=0x306c3, pf=0x2, revision=0x9
>[    0.224983] microcode: CPU1 sig=0x306c3, pf=0x2, revision=0x9
>[    0.224990] microcode: CPU2 sig=0x306c3, pf=0x2, revision=0x9
>[    0.224996] microcode: CPU3 sig=0x306c3, pf=0x2, revision=0x9
>[    0.225002] microcode: CPU4 sig=0x306c3, pf=0x2, revision=0x9
>[    0.225008] microcode: CPU5 sig=0x306c3, pf=0x2, revision=0x9
>[    0.225014] microcode: CPU6 sig=0x306c3, pf=0x2, revision=0x9
>[    0.225019] microcode: CPU7 sig=0x306c3, pf=0x2, revision=0x9
>[    0.225051] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[    0.225054] Scanning for low memory corruption every 60 seconds
>[    0.225489] sha1_ssse3: Using AVX optimized SHA-1 implementation
>[    0.225506] sha256_ssse3: Using AVX2 optimized SHA-256 implementation
>[    0.225538] sha512_ssse3: Using AVX2 optimized SHA-512 implementation
>[    0.226631] audit: initializing netlink socket (disabled)
>[    0.226643] type=2000 audit(1387308231.198:1): initialized
>[    0.229287] NFS: Registering the id_resolver key type
>[    0.229294] Key type id_resolver registered
>[    0.229296] Key type id_legacy registered
>[    0.229399] Key type cifs.idmap registered
>[    0.229431] fuse init (API version 7.22)
>[    0.229549] msgmni has been set to 31977
>[    0.229960] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>[    0.229962] io scheduler noop registered
>[    0.229964] io scheduler deadline registered
>[    0.229994] io scheduler cfq registered (default)
>[    0.230110] pcieport 0000:00:01.0: irq 40 for MSI/MSI-X
>[    0.230226] pcieport 0000:00:1c.0: irq 41 for MSI/MSI-X
>[    0.230344] pcieport 0000:00:1c.2: irq 42 for MSI/MSI-X
>[    0.230441] pcieport 0000:00:1c.3: irq 43 for MSI/MSI-X
>[    0.230537] pcieport 0000:00:01.0: Signaling PME through PCIe PME interrupt
>[    0.230539] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
>[    0.230541] pci 0000:01:00.1: Signaling PME through PCIe PME interrupt
>[    0.230543] pcie_pme 0000:00:01.0:pcie01: service driver pcie_pme loaded
>[    0.230557] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt
>[    0.230560] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded
>[    0.230570] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt
>[    0.230572] pci 0000:05:00.0: Signaling PME through PCIe PME interrupt
>[    0.230575] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded
>[    0.230585] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt
>[    0.230587] pci 0000:06:00.0: Signaling PME through PCIe PME interrupt
>[    0.230590] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded
>[    0.230627] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    0.230659] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>[    0.251219] 00:0a: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[    0.251634] Non-volatile memory driver v1.3
>[    0.251636] Linux agpgart interface v0.103
>[    0.291875] Console: switching to colour frame buffer device 128x48
>[    0.330668] simple-framebuffer simple-framebuffer.0: fb0: simplefb registered!
>[    0.331228] intel_idle: MWAIT substates: 0x42120
>[    0.331229] intel_idle: v0.4 model 0x3C
>[    0.331230] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    0.331419] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
>[    0.332029] ACPI: Power Button [PWRB]
>[    0.332346] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
>[    0.332896] ACPI: Power Button [PWRF]
>[    0.333241] ACPI: Fan [FAN0] (off)
>[    0.333527] ACPI: Fan [FAN1] (off)
>[    0.333812] ACPI: Fan [FAN2] (off)
>[    0.334097] ACPI: Fan [FAN3] (off)
>[    0.334386] ACPI: Fan [FAN4] (off)
>[    0.334732] ACPI: Requesting acpi_cpufreq
>[    0.335507] thermal LNXTHERM:00: registered as thermal_zone0
>[    0.335929] ACPI: Thermal Zone [TZ00] (28 C)
>[    0.336389] thermal LNXTHERM:01: registered as thermal_zone1
>[    0.336810] ACPI: Thermal Zone [TZ01] (30 C)
>[    0.337215] ioatdma: Intel(R) QuickData Technology Driver 4.00
>[    0.337772] [drm] Initialized drm 1.1.0 20060810
>[    0.338144] drm/i810 does not support SMP
>[    0.350404] MXM: GUID detected in BIOS
>[    0.362716] checking generic (f1000000 300000) vs hw (e8000000 8000000)
>[    0.362717] checking generic (f1000000 300000) vs hw (f0000000 2000000)
>[    0.362718] fb: conflicting fb hw usage nouveaufb vs simple - removing generic driver
>[    0.375629] Console: switching to colour dummy device 80x25
>[    0.375894] nouveau  [  DEVICE][0000:01:00.0] BOOT0  : 0x0e6000a1
>[    0.375897] nouveau  [  DEVICE][0000:01:00.0] Chipset: GK106 (NVE6)
>[    0.375898] nouveau  [  DEVICE][0000:01:00.0] Family : NVE0
>[    0.376810] nouveau  [   VBIOS][0000:01:00.0] checking PRAMIN for image...
>[    0.376817] nouveau  [   VBIOS][0000:01:00.0] ... signature not found
>[    0.376819] nouveau  [   VBIOS][0000:01:00.0] checking PROM for image...
>[    0.480469] nouveau  [   VBIOS][0000:01:00.0] ... appears to be valid
>[    0.480471] nouveau  [   VBIOS][0000:01:00.0] using image from PROM
>[    0.480555] nouveau  [   VBIOS][0000:01:00.0] BIT signature found
>[    0.480558] nouveau  [   VBIOS][0000:01:00.0] version 80.06.58.00.3a
>[    0.480924] nouveau  [     PFB][0000:01:00.0] RAM type: GDDR5
>[    0.480927] nouveau  [     PFB][0000:01:00.0] RAM size: 2048 MiB
>[    0.480928] nouveau  [     PFB][0000:01:00.0]    ZCOMP: 0 tags
>[    0.504457] nouveau  [  PTHERM][0000:01:00.0] FAN control: none / external
>[    0.504462] nouveau  [  PTHERM][0000:01:00.0] fan management: disabled
>[    0.504465] nouveau  [  PTHERM][0000:01:00.0] internal sensor: yes
>[    0.534708] nouveau D[     PVP][0000:01:00.0] created
>[    0.534712] nouveau D[     PVP][0000:01:00.0] reset
>[    0.534714] nouveau D[    PBSP][0000:01:00.0] created
>[    0.534718] nouveau D[    PBSP][0000:01:00.0] reset
>[    0.534719] nouveau D[    PPPP][0000:01:00.0] created
>[    0.534723] nouveau D[    PPPP][0000:01:00.0] reset
>[    0.534791] [TTM] Zone  kernel: Available graphics memory: 8186114 kiB
>[    0.534793] [TTM] Zone   dma32: Available graphics memory: 2097152 kiB
>[    0.534795] [TTM] Initializing pool allocator
>[    0.534797] [TTM] Initializing DMA pool allocator
>[    0.534803] nouveau  [     DRM] VRAM: 2048 MiB
>[    0.534804] nouveau  [     DRM] GART: 1048576 MiB
>[    0.534807] nouveau  [     DRM] TMDS table version 2.0
>[    0.534809] nouveau  [     DRM] DCB version 4.0
>[    0.534810] nouveau  [     DRM] DCB outp 00: 02000f00 00000000
>[    0.534812] nouveau  [     DRM] DCB outp 01: 01000f02 00020030
>[    0.534814] nouveau  [     DRM] DCB outp 03: 02011f62 00020010
>[    0.534816] nouveau  [     DRM] DCB outp 04: 04822fb6 0f420010
>[    0.534817] nouveau  [     DRM] DCB outp 05: 04022f72 00020010
>[    0.534819] nouveau  [     DRM] DCB outp 06: 08033f82 00020030
>[    0.534820] nouveau  [     DRM] DCB conn 00: 00001030
>[    0.534823] nouveau  [     DRM] DCB conn 01: 00010161
>[    0.534824] nouveau  [     DRM] DCB conn 02: 00020246
>[    0.534826] nouveau  [     DRM] DCB conn 03: 01000331
>[    0.535869] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>[    0.535871] [drm] No driver support for vblank timestamp query.
>[    0.535935] nouveau W[     DRM] voltage table 0x50 unknown
>[    0.535939] nouveau  [     DRM] 4 available performance level(s)
>[    0.535941] nouveau  [     DRM] 0: core 162MHz shader 324MHz memory 648MHz voltage 100mV
>[    0.535944] nouveau  [     DRM] 1: core 405MHz shader 810MHz memory 1080MHz voltage 80mV
>[    0.535947] nouveau  [     DRM] 2: core 1502MHz shader 3004MHz memory 1080MHz voltage 60mV
>[    0.535949] nouveau  [     DRM] 3: core 1502MHz shader 3004MHz memory 1080MHz voltage 40mV
>[    0.535951] nouveau  [     DRM] c:
>[    0.546977] nouveau  [     DRM] MM: using COPY for buffer copies
>[    0.622690] nouveau  [     DRM] allocated 1920x1200 fb: 0x80000, bo ffff88040b84c000
>[    0.622735] fbcon: nouveaufb (fb0) is primary device
>[    0.700336] Console: switching to colour frame buffer device 240x75
>[    0.701816] nouveau 0000:01:00.0: fb0: nouveaufb frame buffer device
>[    0.701821] nouveau 0000:01:00.0: registered panic notifier
>[    0.701826] [drm] Initialized nouveau 1.1.1 20120801 for 0000:01:00.0 on minor 0
>[    0.702710] loop: module loaded
>[    0.702791] mei_me 0000:00:16.0: setting latency timer to 64
>[    0.702812] mei_me 0000:00:16.0: irq 44 for MSI/MSI-X
>[    0.704633] ACPI Warning: 0x0000000000001828-0x000000000000182f SystemIO conflicts with Region \PMIO 1 (20130725/utaddress-251)
>[    0.704644] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    0.704650] ACPI Warning: 0x0000000000001c30-0x0000000000001c3f SystemIO conflicts with Region \GPIO 1 (20130725/utaddress-251)
>[    0.704657] ACPI Warning: 0x0000000000001c30-0x0000000000001c3f SystemIO conflicts with Region \GPRL 2 (20130725/utaddress-251)
>[    0.704665] ACPI Warning: 0x0000000000001c30-0x0000000000001c3f SystemIO conflicts with Region \GPR_ 3 (20130725/utaddress-251)
>[    0.704672] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    0.704677] ACPI Warning: 0x0000000000001c00-0x0000000000001c2f SystemIO conflicts with Region \GPIO 1 (20130725/utaddress-251)
>[    0.704684] ACPI Warning: 0x0000000000001c00-0x0000000000001c2f SystemIO conflicts with Region \GPRL 2 (20130725/utaddress-251)
>[    0.704691] ACPI Warning: 0x0000000000001c00-0x0000000000001c2f SystemIO conflicts with Region \GPR_ 3 (20130725/utaddress-251)
>[    0.704698] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    0.704703] lpc_ich: Resource conflict(s) found affecting gpio_ich
>[    0.705169] ahci 0000:00:1f.2: version 3.0
>[    0.705229] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X
>[    0.705266] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0xb impl SATA mode
>[    0.705273] ahci 0000:00:1f.2: flags: 64bit ncq led clo pio slum part ems apst 
>[    0.705280] ahci 0000:00:1f.2: setting latency timer to 64
>[    0.709737] scsi0 : ahci
>[    0.709815] scsi1 : ahci
>[    0.709896] scsi2 : ahci
>[    0.709984] scsi3 : ahci
>[    0.710071] scsi4 : ahci
>[    0.710160] scsi5 : ahci
>[    0.710216] ata1: SATA max UDMA/133 abar m2048@0xf7416000 port 0xf7416100 irq 45
>[    0.710221] ata2: SATA max UDMA/133 abar m2048@0xf7416000 port 0xf7416180 irq 45
>[    0.710225] ata3: DUMMY
>[    0.710228] ata4: SATA max UDMA/133 abar m2048@0xf7416000 port 0xf7416280 irq 45
>[    0.710232] ata5: DUMMY
>[    0.710234] ata6: DUMMY
>[    0.710497] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
>[    0.710502] e100: Copyright(c) 1999-2006 Intel Corporation
>[    0.710534] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
>[    0.710537] e1000: Copyright (c) 1999-2006 Intel Corporation.
>[    0.710566] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
>[    0.710570] e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
>[    0.710600] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
>[    0.710604] igb: Copyright (c) 2007-2013 Intel Corporation.
>[    0.711099] igb 0000:05:00.0: irq 46 for MSI/MSI-X
>[    0.711103] igb 0000:05:00.0: irq 47 for MSI/MSI-X
>[    0.711106] igb 0000:05:00.0: irq 48 for MSI/MSI-X
>[    0.711109] igb 0000:05:00.0: irq 49 for MSI/MSI-X
>[    0.711111] igb 0000:05:00.0: irq 50 for MSI/MSI-X
>[    0.740951] igb 0000:05:00.0: added PHC on eth0
>[    0.740957] igb 0000:05:00.0: Intel(R) Gigabit Ethernet Network Connection
>[    0.740961] igb 0000:05:00.0: eth0: (PCIe:2.5Gb/s:Width x1) ac:22:0b:8c:19:66
>[    0.741015] igb 0000:05:00.0: eth0: PBA No: 001300-000
>[    0.741018] igb 0000:05:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s)
>[    0.741528] igb 0000:06:00.0: irq 51 for MSI/MSI-X
>[    0.741532] igb 0000:06:00.0: irq 52 for MSI/MSI-X
>[    0.741534] igb 0000:06:00.0: irq 53 for MSI/MSI-X
>[    0.741537] igb 0000:06:00.0: irq 54 for MSI/MSI-X
>[    0.741540] igb 0000:06:00.0: irq 55 for MSI/MSI-X
>[    0.770936] igb 0000:06:00.0: added PHC on eth1
>[    0.770941] igb 0000:06:00.0: Intel(R) Gigabit Ethernet Network Connection
>[    0.771141] igb 0000:06:00.0: eth1: (PCIe:2.5Gb/s:Width x1) ac:22:0b:8c:19:67
>[    0.771374] igb 0000:06:00.0: eth1: PBA No: 001300-000
>[    0.771561] igb 0000:06:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s)
>[    0.771874] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
>[    0.772120] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
>[    0.772431] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
>[    0.772700] ixgbe: Copyright (c) 1999-2013 Intel Corporation.
>[    0.773026] ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.7.12-k
>[    0.773303] ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
>[    0.773634] i40e: Intel(R) Ethernet Connection XL710 Network Driver - version 0.3.9-k
>[    0.773910] i40e: Copyright (c) 2013 Intel Corporation.
>[    0.774250] ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
>[    0.774524] ixgb: Copyright (c) 1999-2008 Intel Corporation.
>[    0.774858] PPP generic driver version 2.4.2
>[    0.775201] PPP BSD Compression module registered
>[    0.775446] PPP Deflate Compression module registered
>[    0.775751] PPP MPPE Compression module registered
>[    0.776051] NET: Registered protocol family 24
>[    0.776526] pci 0000:03:00.0: setting latency timer to 64
>[    0.831113] firewire_ohci 0000:04:02.0: added OHCI v1.10 device as card 0, 4 IR + 8 IT contexts, quirks 0x11
>[    0.831643] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    0.831844] ehci_hcd: block sizes: qh 112 qtd 96 itd 192 sitd 96
>[    0.831846] ehci-pci: EHCI PCI platform driver
>[    0.832112] ehci-pci 0000:00:1d.0: setting latency timer to 64
>[    0.832117] ehci-pci 0000:00:1d.0: EHCI Host Controller
>[    0.832393] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 1
>[    0.832700] ehci-pci 0000:00:1d.0: debug port 2
>[    0.833005] ehci-pci 0000:00:1d.0: reset hcs_params 0x200002 dbg=2 cc=0 pcc=0 ordered !ppc ports=2
>[    0.833007] ehci-pci 0000:00:1d.0: reset hcc_params 36881 caching frame 1024 64 bit addr
>[    0.833019] ehci-pci 0000:00:1d.0: reset command 0080002 (park)=0 ithresh=8 period=1024 Reset HALT
>[    0.836902] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
>[    0.836904] ehci-pci 0000:00:1d.0: supports USB remote wakeup
>[    0.836914] ehci-pci 0000:00:1d.0: irq 23, io mem 0xf7417000
>[    0.837115] ehci-pci 0000:00:1d.0: init command 0010001 (park)=0 ithresh=1 period=1024 RUN
>[    0.843087] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
>[    0.843301] usb usb1: default language 0x0409
>[    0.843306] usb usb1: udev 1, busnum 1, minor = 0
>[    0.843308] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    0.843505] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    0.843785] usb usb1: Product: EHCI Host Controller
>[    0.844092] usb usb1: Manufacturer: Linux 3.12.5-gentoo ehci_hcd
>[    0.844388] usb usb1: SerialNumber: 0000:00:1d.0
>[    0.844744] usb usb1: usb_probe_device
>[    0.844745] usb usb1: configuration #1 chosen from 1 choice
>[    0.844750] usb usb1: adding 1-0:1.0 (config #1, interface 0)
>[    0.844779] hub 1-0:1.0: usb_probe_interface
>[    0.844780] hub 1-0:1.0: usb_probe_interface - got id
>[    0.844782] hub 1-0:1.0: USB hub found
>[    0.844978] hub 1-0:1.0: 2 ports detected
>[    0.845260] hub 1-0:1.0: standalone hub
>[    0.845261] hub 1-0:1.0: no power switching (usb 1.0)
>[    0.845262] hub 1-0:1.0: individual port over-current protection
>[    0.845263] hub 1-0:1.0: power on to power good time: 20ms
>[    0.845267] hub 1-0:1.0: local power source is good
>[    0.845302] usb usb1: usb port1's DeviceRemovable is changed to 1 according to platform information.
>[    0.845303] hub 1-0:1.0: trying to enable port power on non-switchable hub
>[    0.845348] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    0.845550] ohci_hcd: block sizes: ed 80 td 96
>[    0.845552] ohci-pci: OHCI PCI platform driver
>[    0.845864] uhci_hcd: USB Universal Host Controller Interface driver
>[    0.846211] xhci_hcd 0000:00:14.0: setting latency timer to 64
>[    0.846213] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    0.846451] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    0.846709] xhci_hcd 0000:00:14.0: xHCI capability registers at ffffc9000b060000:
>[    0.846711] xhci_hcd 0000:00:14.0: CAPLENGTH AND HCIVERSION 0x1000080:
>[    0.846712] xhci_hcd 0000:00:14.0: CAPLENGTH: 0x80
>[    0.846713] xhci_hcd 0000:00:14.0: HCIVERSION: 0x100
>[    0.846715] xhci_hcd 0000:00:14.0: HCSPARAMS 1: 0x15000820
>[    0.846716] xhci_hcd 0000:00:14.0:   Max device slots: 32
>[    0.846717] xhci_hcd 0000:00:14.0:   Max interrupters: 8
>[    0.846717] xhci_hcd 0000:00:14.0:   Max ports: 21
>[    0.846719] xhci_hcd 0000:00:14.0: HCSPARAMS 2: 0x84000054
>[    0.846720] xhci_hcd 0000:00:14.0:   Isoc scheduling threshold: 4
>[    0.846721] xhci_hcd 0000:00:14.0:   Maximum allowed segments in event ring: 5
>[    0.846722] xhci_hcd 0000:00:14.0: HCSPARAMS 3 0x200000a:
>[    0.846723] xhci_hcd 0000:00:14.0:   Worst case U1 device exit latency: 10
>[    0.846724] xhci_hcd 0000:00:14.0:   Worst case U2 device exit latency: 512
>[    0.846726] xhci_hcd 0000:00:14.0: HCC PARAMS 0x200077c1:
>[    0.846727] xhci_hcd 0000:00:14.0:   HC generates 64 bit addresses
>[    0.846728] xhci_hcd 0000:00:14.0:   FIXME: more HCCPARAMS debugging
>[    0.846729] xhci_hcd 0000:00:14.0: RTSOFF 0x2000:
>[    0.846730] xhci_hcd 0000:00:14.0: xHCI operational registers at ffffc9000b060080:
>[    0.846732] xhci_hcd 0000:00:14.0: USBCMD 0x0:
>[    0.846733] xhci_hcd 0000:00:14.0:   HC is being stopped
>[    0.846734] xhci_hcd 0000:00:14.0:   HC has finished hard reset
>[    0.846735] xhci_hcd 0000:00:14.0:   Event Interrupts disabled
>[    0.846736] xhci_hcd 0000:00:14.0:   Host System Error Interrupts disabled
>[    0.846737] xhci_hcd 0000:00:14.0:   HC has finished light reset
>[    0.846738] xhci_hcd 0000:00:14.0: USBSTS 0x11:
>[    0.846739] xhci_hcd 0000:00:14.0:   Event ring is empty
>[    0.846740] xhci_hcd 0000:00:14.0:   No Host System Error
>[    0.846741] xhci_hcd 0000:00:14.0:   HC is halted
>[    0.846743] xhci_hcd 0000:00:14.0: ffffc9000b060480 port status reg = 0x2a0
>[    0.846744] xhci_hcd 0000:00:14.0: ffffc9000b060484 port power reg = 0x0
>[    0.846747] xhci_hcd 0000:00:14.0: ffffc9000b060488 port link reg = 0x0
>[    0.846750] xhci_hcd 0000:00:14.0: ffffc9000b06048c port reserved reg = 0x0
>[    0.846751] xhci_hcd 0000:00:14.0: ffffc9000b060490 port status reg = 0x2a0
>[    0.846753] xhci_hcd 0000:00:14.0: ffffc9000b060494 port power reg = 0x0
>[    0.846755] xhci_hcd 0000:00:14.0: ffffc9000b060498 port link reg = 0x0
>[    0.846758] xhci_hcd 0000:00:14.0: ffffc9000b06049c port reserved reg = 0x0
>[    0.846759] xhci_hcd 0000:00:14.0: ffffc9000b0604a0 port status reg = 0x2a0
>[    0.846761] xhci_hcd 0000:00:14.0: ffffc9000b0604a4 port power reg = 0x0
>[    0.846764] xhci_hcd 0000:00:14.0: ffffc9000b0604a8 port link reg = 0x0
>[    0.846766] xhci_hcd 0000:00:14.0: ffffc9000b0604ac port reserved reg = 0x0
>[    0.846768] xhci_hcd 0000:00:14.0: ffffc9000b0604b0 port status reg = 0x2a0
>[    0.846769] xhci_hcd 0000:00:14.0: ffffc9000b0604b4 port power reg = 0x0
>[    0.846772] xhci_hcd 0000:00:14.0: ffffc9000b0604b8 port link reg = 0x0
>[    0.846774] xhci_hcd 0000:00:14.0: ffffc9000b0604bc port reserved reg = 0x0
>[    0.846776] xhci_hcd 0000:00:14.0: ffffc9000b0604c0 port status reg = 0x2a0
>[    0.846777] xhci_hcd 0000:00:14.0: ffffc9000b0604c4 port power reg = 0x0
>[    0.846780] xhci_hcd 0000:00:14.0: ffffc9000b0604c8 port link reg = 0x0
>[    0.846782] xhci_hcd 0000:00:14.0: ffffc9000b0604cc port reserved reg = 0x0
>[    0.846784] xhci_hcd 0000:00:14.0: ffffc9000b0604d0 port status reg = 0x2a0
>[    0.846786] xhci_hcd 0000:00:14.0: ffffc9000b0604d4 port power reg = 0x0
>[    0.846788] xhci_hcd 0000:00:14.0: ffffc9000b0604d8 port link reg = 0x0
>[    0.846791] xhci_hcd 0000:00:14.0: ffffc9000b0604dc port reserved reg = 0x0
>[    0.846792] xhci_hcd 0000:00:14.0: ffffc9000b0604e0 port status reg = 0x2a0
>[    0.846794] xhci_hcd 0000:00:14.0: ffffc9000b0604e4 port power reg = 0x0
>[    0.846796] xhci_hcd 0000:00:14.0: ffffc9000b0604e8 port link reg = 0x0
>[    0.846799] xhci_hcd 0000:00:14.0: ffffc9000b0604ec port reserved reg = 0x0
>[    0.846801] xhci_hcd 0000:00:14.0: ffffc9000b0604f0 port status reg = 0x2a0
>[    0.846802] xhci_hcd 0000:00:14.0: ffffc9000b0604f4 port power reg = 0x0
>[    0.846805] xhci_hcd 0000:00:14.0: ffffc9000b0604f8 port link reg = 0x0
>[    0.846807] xhci_hcd 0000:00:14.0: ffffc9000b0604fc port reserved reg = 0x0
>[    0.846809] xhci_hcd 0000:00:14.0: ffffc9000b060500 port status reg = 0x2a0
>[    0.846810] xhci_hcd 0000:00:14.0: ffffc9000b060504 port power reg = 0x0
>[    0.846813] xhci_hcd 0000:00:14.0: ffffc9000b060508 port link reg = 0x0
>[    0.846815] xhci_hcd 0000:00:14.0: ffffc9000b06050c port reserved reg = 0x0
>[    0.846817] xhci_hcd 0000:00:14.0: ffffc9000b060510 port status reg = 0x2a0
>[    0.846818] xhci_hcd 0000:00:14.0: ffffc9000b060514 port power reg = 0x0
>[    0.846821] xhci_hcd 0000:00:14.0: ffffc9000b060518 port link reg = 0x0
>[    0.846823] xhci_hcd 0000:00:14.0: ffffc9000b06051c port reserved reg = 0x0
>[    0.846825] xhci_hcd 0000:00:14.0: ffffc9000b060520 port status reg = 0x2a0
>[    0.846826] xhci_hcd 0000:00:14.0: ffffc9000b060524 port power reg = 0x0
>[    0.846829] xhci_hcd 0000:00:14.0: ffffc9000b060528 port link reg = 0x0
>[    0.846831] xhci_hcd 0000:00:14.0: ffffc9000b06052c port reserved reg = 0x0
>[    0.846833] xhci_hcd 0000:00:14.0: ffffc9000b060530 port status reg = 0x2a0
>[    0.846834] xhci_hcd 0000:00:14.0: ffffc9000b060534 port power reg = 0x0
>[    0.846837] xhci_hcd 0000:00:14.0: ffffc9000b060538 port link reg = 0x0
>[    0.846840] xhci_hcd 0000:00:14.0: ffffc9000b06053c port reserved reg = 0x0
>[    0.846841] xhci_hcd 0000:00:14.0: ffffc9000b060540 port status reg = 0x6e1
>[    0.846843] xhci_hcd 0000:00:14.0: ffffc9000b060544 port power reg = 0x0
>[    0.846845] xhci_hcd 0000:00:14.0: ffffc9000b060548 port link reg = 0x0
>[    0.846848] xhci_hcd 0000:00:14.0: ffffc9000b06054c port reserved reg = 0x0
>[    0.846849] xhci_hcd 0000:00:14.0: ffffc9000b060550 port status reg = 0x6e1
>[    0.846851] xhci_hcd 0000:00:14.0: ffffc9000b060554 port power reg = 0x0
>[    0.846854] xhci_hcd 0000:00:14.0: ffffc9000b060558 port link reg = 0x0
>[    0.846856] xhci_hcd 0000:00:14.0: ffffc9000b06055c port reserved reg = 0x0
>[    0.846858] xhci_hcd 0000:00:14.0: ffffc9000b060560 port status reg = 0x2a0
>[    0.846859] xhci_hcd 0000:00:14.0: ffffc9000b060564 port power reg = 0x0
>[    0.846862] xhci_hcd 0000:00:14.0: ffffc9000b060568 port link reg = 0x0
>[    0.846864] xhci_hcd 0000:00:14.0: ffffc9000b06056c port reserved reg = 0x0
>[    0.846866] xhci_hcd 0000:00:14.0: ffffc9000b060570 port status reg = 0x1203
>[    0.846867] xhci_hcd 0000:00:14.0: ffffc9000b060574 port power reg = 0x0
>[    0.846869] xhci_hcd 0000:00:14.0: ffffc9000b060578 port link reg = 0xe1
>[    0.846872] xhci_hcd 0000:00:14.0: ffffc9000b06057c port reserved reg = 0x0
>[    0.846873] xhci_hcd 0000:00:14.0: ffffc9000b060580 port status reg = 0x2a0
>[    0.846875] xhci_hcd 0000:00:14.0: ffffc9000b060584 port power reg = 0x0
>[    0.846877] xhci_hcd 0000:00:14.0: ffffc9000b060588 port link reg = 0x0
>[    0.846880] xhci_hcd 0000:00:14.0: ffffc9000b06058c port reserved reg = 0x0
>[    0.846882] xhci_hcd 0000:00:14.0: ffffc9000b060590 port status reg = 0x2a0
>[    0.846883] xhci_hcd 0000:00:14.0: ffffc9000b060594 port power reg = 0x0
>[    0.846886] xhci_hcd 0000:00:14.0: ffffc9000b060598 port link reg = 0x0
>[    0.846888] xhci_hcd 0000:00:14.0: ffffc9000b06059c port reserved reg = 0x0
>[    0.846890] xhci_hcd 0000:00:14.0: ffffc9000b0605a0 port status reg = 0x2a0
>[    0.846892] xhci_hcd 0000:00:14.0: ffffc9000b0605a4 port power reg = 0x0
>[    0.846894] xhci_hcd 0000:00:14.0: ffffc9000b0605a8 port link reg = 0x0
>[    0.846897] xhci_hcd 0000:00:14.0: ffffc9000b0605ac port reserved reg = 0x0
>[    0.846898] xhci_hcd 0000:00:14.0: ffffc9000b0605b0 port status reg = 0x2a0
>[    0.846900] xhci_hcd 0000:00:14.0: ffffc9000b0605b4 port power reg = 0x0
>[    0.846903] xhci_hcd 0000:00:14.0: ffffc9000b0605b8 port link reg = 0x0
>[    0.846905] xhci_hcd 0000:00:14.0: ffffc9000b0605bc port reserved reg = 0x0
>[    0.846907] xhci_hcd 0000:00:14.0: ffffc9000b0605c0 port status reg = 0x2a0
>[    0.846908] xhci_hcd 0000:00:14.0: ffffc9000b0605c4 port power reg = 0x0
>[    0.846911] xhci_hcd 0000:00:14.0: ffffc9000b0605c8 port link reg = 0x0
>[    0.846913] xhci_hcd 0000:00:14.0: ffffc9000b0605cc port reserved reg = 0x0
>[    0.846915] xhci_hcd 0000:00:14.0: // Halt the HC
>[    0.846918] xhci_hcd 0000:00:14.0: Resetting HCD
>[    0.846919] xhci_hcd 0000:00:14.0: // Reset the HC
>[    0.846925] xhci_hcd 0000:00:14.0: Wait for controller to be ready for doorbell rings
>[    0.846927] xhci_hcd 0000:00:14.0: Reset complete
>[    0.846928] xhci_hcd 0000:00:14.0: Enabling 64-bit DMA addresses.
>[    0.846929] xhci_hcd 0000:00:14.0: Calling HCD init
>[    0.846930] xhci_hcd 0000:00:14.0: xhci_init
>[    0.846931] xhci_hcd 0000:00:14.0: xHCI doesn't need link TRB QUIRK
>[    0.846932] xhci_hcd 0000:00:14.0: Supported page size register = 0x1
>[    0.846934] xhci_hcd 0000:00:14.0: Supported page size of 4K
>[    0.846935] xhci_hcd 0000:00:14.0: HCD page size set to 4K
>[    0.846936] xhci_hcd 0000:00:14.0: // xHC can handle at most 32 device slots.
>[    0.846938] xhci_hcd 0000:00:14.0: // Setting Max device slots reg = 0x20.
>[    0.846940] xhci_hcd 0000:00:14.0: // Device context base array address = 0x40bed9000 (DMA), ffff88040bed9000 (virt)
>[    0.846942] xhci_hcd 0000:00:14.0: Allocated command ring at ffff88040bed6780
>[    0.846943] xhci_hcd 0000:00:14.0: First segment DMA is 0x40beda000
>[    0.846945] xhci_hcd 0000:00:14.0: // Setting command ring address to 0x20
>[    0.846949] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr low bits + flags = @00000000
>[    0.846950] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr high bits = @00000000
>[    0.846952] xhci_hcd 0000:00:14.0: // Doorbell array is located at offset 0x3000 from cap regs base addr
>[    0.846953] xhci_hcd 0000:00:14.0: // xHCI capability registers at ffffc9000b060000:
>[    0.846955] xhci_hcd 0000:00:14.0: // @ffffc9000b060000 = 0x1000080 (CAPLENGTH AND HCIVERSION)
>[    0.846956] xhci_hcd 0000:00:14.0: //   CAPLENGTH: 0x80
>[    0.846957] xhci_hcd 0000:00:14.0: // xHCI operational registers at ffffc9000b060080:
>[    0.846959] xhci_hcd 0000:00:14.0: // @ffffc9000b060018 = 0x2000 RTSOFF
>[    0.846959] xhci_hcd 0000:00:14.0: // xHCI runtime registers at ffffc9000b062000:
>[    0.846961] xhci_hcd 0000:00:14.0: // @ffffc9000b060014 = 0x3000 DBOFF
>[    0.846962] xhci_hcd 0000:00:14.0: // Doorbell array at ffffc9000b063000:
>[    0.846963] xhci_hcd 0000:00:14.0: xHCI runtime registers at ffffc9000b062000:
>[    0.846965] xhci_hcd 0000:00:14.0:   ffffc9000b062000: Microframe index = 0x0
>[    0.846977] xhci_hcd 0000:00:14.0: // Allocating event ring
>[    0.846978] xhci_hcd 0000:00:14.0: TRB math tests passed.
>[    0.846980] xhci_hcd 0000:00:14.0: // Allocated event ring segment table at 0x40b974000
>[    0.846981] xhci_hcd 0000:00:14.0: Set ERST to 0; private num segs = 1, virt addr = ffff88040b974000, dma addr = 0x40b974000
>[    0.846983] xhci_hcd 0000:00:14.0: // Write ERST size = 1 to ir_set 0 (some bits preserved)
>[    0.846984] xhci_hcd 0000:00:14.0: // Set ERST entries to point to event ring.
>[    0.846985] xhci_hcd 0000:00:14.0: // Set ERST base address for ir_set 0 = 0x40b974000
>[    0.846989] xhci_hcd 0000:00:14.0: // Write event ring dequeue pointer, preserving EHB bit
>[    0.846990] xhci_hcd 0000:00:14.0: Wrote ERST address to ir_set 0.
>[    0.846992] xhci_hcd 0000:00:14.0: Allocating 16 scratchpad buffers
>[    0.847005] xhci_hcd 0000:00:14.0: Ext Cap ffffc9000b068000, port offset = 1, count = 15, revision = 0x2
>[    0.847006] xhci_hcd 0000:00:14.0: xHCI 1.0: support USB2 software lpm
>[    0.847008] xhci_hcd 0000:00:14.0: Ext Cap ffffc9000b068020, port offset = 16, count = 6, revision = 0x3
>[    0.847010] xhci_hcd 0000:00:14.0: Found 15 USB 2.0 ports and 6 USB 3.0 ports.
>[    0.847011] xhci_hcd 0000:00:14.0: USB 2.0 port at index 0, addr = ffffc9000b060480
>[    0.847012] xhci_hcd 0000:00:14.0: USB 2.0 port at index 1, addr = ffffc9000b060490
>[    0.847013] xhci_hcd 0000:00:14.0: USB 2.0 port at index 2, addr = ffffc9000b0604a0
>[    0.847014] xhci_hcd 0000:00:14.0: USB 2.0 port at index 3, addr = ffffc9000b0604b0
>[    0.847015] xhci_hcd 0000:00:14.0: USB 2.0 port at index 4, addr = ffffc9000b0604c0
>[    0.847016] xhci_hcd 0000:00:14.0: USB 2.0 port at index 5, addr = ffffc9000b0604d0
>[    0.847017] xhci_hcd 0000:00:14.0: USB 2.0 port at index 6, addr = ffffc9000b0604e0
>[    0.847018] xhci_hcd 0000:00:14.0: USB 2.0 port at index 7, addr = ffffc9000b0604f0
>[    0.847019] xhci_hcd 0000:00:14.0: USB 2.0 port at index 8, addr = ffffc9000b060500
>[    0.847020] xhci_hcd 0000:00:14.0: USB 2.0 port at index 9, addr = ffffc9000b060510
>[    0.847021] xhci_hcd 0000:00:14.0: USB 2.0 port at index 10, addr = ffffc9000b060520
>[    0.847022] xhci_hcd 0000:00:14.0: USB 2.0 port at index 11, addr = ffffc9000b060530
>[    0.847023] xhci_hcd 0000:00:14.0: USB 2.0 port at index 12, addr = ffffc9000b060540
>[    0.847024] xhci_hcd 0000:00:14.0: USB 2.0 port at index 13, addr = ffffc9000b060550
>[    0.847025] xhci_hcd 0000:00:14.0: USB 2.0 port at index 14, addr = ffffc9000b060560
>[    0.847027] xhci_hcd 0000:00:14.0: USB 3.0 port at index 15, addr = ffffc9000b060570
>[    0.847028] xhci_hcd 0000:00:14.0: USB 3.0 port at index 16, addr = ffffc9000b060580
>[    0.847029] xhci_hcd 0000:00:14.0: USB 3.0 port at index 17, addr = ffffc9000b060590
>[    0.847030] xhci_hcd 0000:00:14.0: USB 3.0 port at index 18, addr = ffffc9000b0605a0
>[    0.847031] xhci_hcd 0000:00:14.0: USB 3.0 port at index 19, addr = ffffc9000b0605b0
>[    0.847032] xhci_hcd 0000:00:14.0: USB 3.0 port at index 20, addr = ffffc9000b0605c0
>[    0.847033] xhci_hcd 0000:00:14.0: Finished xhci_init
>[    0.847034] xhci_hcd 0000:00:14.0: Called HCD init
>[    0.847036] xhci_hcd 0000:00:14.0: Got SBRN 48
>[    0.847039] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    0.847040] xhci_hcd 0000:00:14.0: Finished xhci_pci_reinit
>[    0.847041] xhci_hcd 0000:00:14.0: supports USB remote wakeup
>[    0.847042] xhci_hcd 0000:00:14.0: xhci_run
>[    0.847043] xhci_hcd 0000:00:14.0: Failed to enable MSI-X
>[    0.847055] xhci_hcd 0000:00:14.0: irq 56 for MSI/MSI-X
>[    0.847068] xhci_hcd 0000:00:14.0: Command ring memory map follows:
>[    0.847070] xhci_hcd 0000:00:14.0: @000000040beda000 00000000 00000000 00000000 00000000
>[    0.847071] xhci_hcd 0000:00:14.0: @000000040beda010 00000000 00000000 00000000 00000000
>[    0.847072] xhci_hcd 0000:00:14.0: @000000040beda020 00000000 00000000 00000000 00000000
>[    0.847073] xhci_hcd 0000:00:14.0: @000000040beda030 00000000 00000000 00000000 00000000
>[    0.847075] xhci_hcd 0000:00:14.0: @000000040beda040 00000000 00000000 00000000 00000000
>[    0.847080] xhci_hcd 0000:00:14.0: @000000040beda050 00000000 00000000 00000000 00000000
>[    0.847081] xhci_hcd 0000:00:14.0: @000000040beda060 00000000 00000000 00000000 00000000
>[    0.847082] xhci_hcd 0000:00:14.0: @000000040beda070 00000000 00000000 00000000 00000000
>[    0.847083] xhci_hcd 0000:00:14.0: @000000040beda080 00000000 00000000 00000000 00000000
>[    0.847084] xhci_hcd 0000:00:14.0: @000000040beda090 00000000 00000000 00000000 00000000
>[    0.847085] xhci_hcd 0000:00:14.0: @000000040beda0a0 00000000 00000000 00000000 00000000
>[    0.847086] xhci_hcd 0000:00:14.0: @000000040beda0b0 00000000 00000000 00000000 00000000
>[    0.847088] xhci_hcd 0000:00:14.0: @000000040beda0c0 00000000 00000000 00000000 00000000
>[    0.847089] xhci_hcd 0000:00:14.0: @000000040beda0d0 00000000 00000000 00000000 00000000
>[    0.847090] xhci_hcd 0000:00:14.0: @000000040beda0e0 00000000 00000000 00000000 00000000
>[    0.847091] xhci_hcd 0000:00:14.0: @000000040beda0f0 00000000 00000000 00000000 00000000
>[    0.847092] xhci_hcd 0000:00:14.0: @000000040beda100 00000000 00000000 00000000 00000000
>[    0.847093] xhci_hcd 0000:00:14.0: @000000040beda110 00000000 00000000 00000000 00000000
>[    0.847094] xhci_hcd 0000:00:14.0: @000000040beda120 00000000 00000000 00000000 00000000
>[    0.847095] xhci_hcd 0000:00:14.0: @000000040beda130 00000000 00000000 00000000 00000000
>[    0.847096] xhci_hcd 0000:00:14.0: @000000040beda140 00000000 00000000 00000000 00000000
>[    0.847097] xhci_hcd 0000:00:14.0: @000000040beda150 00000000 00000000 00000000 00000000
>[    0.847098] xhci_hcd 0000:00:14.0: @000000040beda160 00000000 00000000 00000000 00000000
>[    0.847100] xhci_hcd 0000:00:14.0: @000000040beda170 00000000 00000000 00000000 00000000
>[    0.847101] xhci_hcd 0000:00:14.0: @000000040beda180 00000000 00000000 00000000 00000000
>[    0.847102] xhci_hcd 0000:00:14.0: @000000040beda190 00000000 00000000 00000000 00000000
>[    0.847103] xhci_hcd 0000:00:14.0: @000000040beda1a0 00000000 00000000 00000000 00000000
>[    0.847104] xhci_hcd 0000:00:14.0: @000000040beda1b0 00000000 00000000 00000000 00000000
>[    0.847105] xhci_hcd 0000:00:14.0: @000000040beda1c0 00000000 00000000 00000000 00000000
>[    0.847106] xhci_hcd 0000:00:14.0: @000000040beda1d0 00000000 00000000 00000000 00000000
>[    0.847108] xhci_hcd 0000:00:14.0: @000000040beda1e0 00000000 00000000 00000000 00000000
>[    0.847109] xhci_hcd 0000:00:14.0: @000000040beda1f0 00000000 00000000 00000000 00000000
>[    0.847110] xhci_hcd 0000:00:14.0: @000000040beda200 00000000 00000000 00000000 00000000
>[    0.847111] xhci_hcd 0000:00:14.0: @000000040beda210 00000000 00000000 00000000 00000000
>[    0.847112] xhci_hcd 0000:00:14.0: @000000040beda220 00000000 00000000 00000000 00000000
>[    0.847113] xhci_hcd 0000:00:14.0: @000000040beda230 00000000 00000000 00000000 00000000
>[    0.847114] xhci_hcd 0000:00:14.0: @000000040beda240 00000000 00000000 00000000 00000000
>[    0.847115] xhci_hcd 0000:00:14.0: @000000040beda250 00000000 00000000 00000000 00000000
>[    0.847117] xhci_hcd 0000:00:14.0: @000000040beda260 00000000 00000000 00000000 00000000
>[    0.847118] xhci_hcd 0000:00:14.0: @000000040beda270 00000000 00000000 00000000 00000000
>[    0.847119] xhci_hcd 0000:00:14.0: @000000040beda280 00000000 00000000 00000000 00000000
>[    0.847120] xhci_hcd 0000:00:14.0: @000000040beda290 00000000 00000000 00000000 00000000
>[    0.847121] xhci_hcd 0000:00:14.0: @000000040beda2a0 00000000 00000000 00000000 00000000
>[    0.847122] xhci_hcd 0000:00:14.0: @000000040beda2b0 00000000 00000000 00000000 00000000
>[    0.847123] xhci_hcd 0000:00:14.0: @000000040beda2c0 00000000 00000000 00000000 00000000
>[    0.847124] xhci_hcd 0000:00:14.0: @000000040beda2d0 00000000 00000000 00000000 00000000
>[    0.847125] xhci_hcd 0000:00:14.0: @000000040beda2e0 00000000 00000000 00000000 00000000
>[    0.847126] xhci_hcd 0000:00:14.0: @000000040beda2f0 00000000 00000000 00000000 00000000
>[    0.847128] xhci_hcd 0000:00:14.0: @000000040beda300 00000000 00000000 00000000 00000000
>[    0.847129] xhci_hcd 0000:00:14.0: @000000040beda310 00000000 00000000 00000000 00000000
>[    0.847130] xhci_hcd 0000:00:14.0: @000000040beda320 00000000 00000000 00000000 00000000
>[    0.847131] xhci_hcd 0000:00:14.0: @000000040beda330 00000000 00000000 00000000 00000000
>[    0.847132] xhci_hcd 0000:00:14.0: @000000040beda340 00000000 00000000 00000000 00000000
>[    0.847133] xhci_hcd 0000:00:14.0: @000000040beda350 00000000 00000000 00000000 00000000
>[    0.847134] xhci_hcd 0000:00:14.0: @000000040beda360 00000000 00000000 00000000 00000000
>[    0.847135] xhci_hcd 0000:00:14.0: @000000040beda370 00000000 00000000 00000000 00000000
>[    0.847136] xhci_hcd 0000:00:14.0: @000000040beda380 00000000 00000000 00000000 00000000
>[    0.847137] xhci_hcd 0000:00:14.0: @000000040beda390 00000000 00000000 00000000 00000000
>[    0.847139] xhci_hcd 0000:00:14.0: @000000040beda3a0 00000000 00000000 00000000 00000000
>[    0.847140] xhci_hcd 0000:00:14.0: @000000040beda3b0 00000000 00000000 00000000 00000000
>[    0.847141] xhci_hcd 0000:00:14.0: @000000040beda3c0 00000000 00000000 00000000 00000000
>[    0.847142] xhci_hcd 0000:00:14.0: @000000040beda3d0 00000000 00000000 00000000 00000000
>[    0.847143] xhci_hcd 0000:00:14.0: @000000040beda3e0 00000000 00000000 00000000 00000000
>[    0.847145] xhci_hcd 0000:00:14.0: @000000040beda3f0 0beda000 00000004 00000000 00001802
>[    0.847146] xhci_hcd 0000:00:14.0:   Ring has not been updated
>[    0.847147] xhci_hcd 0000:00:14.0: Ring deq = ffff88040beda000 (virt), 0x40beda000 (dma)
>[    0.847148] xhci_hcd 0000:00:14.0: Ring deq updated 0 times
>[    0.847149] xhci_hcd 0000:00:14.0: Ring enq = ffff88040beda000 (virt), 0x40beda000 (dma)
>[    0.847150] xhci_hcd 0000:00:14.0: Ring enq updated 0 times
>[    0.847152] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr low bits + flags = @00000000
>[    0.847153] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr high bits = @00000000
>[    0.847154] xhci_hcd 0000:00:14.0: ERST memory map follows:
>[    0.847155] xhci_hcd 0000:00:14.0: @000000040b974000 0beda400 00000004 00000040 00000000
>[    0.847156] xhci_hcd 0000:00:14.0: Event ring:
>[    0.847157] xhci_hcd 0000:00:14.0: @000000040beda400 00000000 00000000 00000000 00000000
>[    0.847158] xhci_hcd 0000:00:14.0: @000000040beda410 00000000 00000000 00000000 00000000
>[    0.847159] xhci_hcd 0000:00:14.0: @000000040beda420 00000000 00000000 00000000 00000000
>[    0.847160] xhci_hcd 0000:00:14.0: @000000040beda430 00000000 00000000 00000000 00000000
>[    0.847161] xhci_hcd 0000:00:14.0: @000000040beda440 00000000 00000000 00000000 00000000
>[    0.847162] xhci_hcd 0000:00:14.0: @000000040beda450 00000000 00000000 00000000 00000000
>[    0.847163] xhci_hcd 0000:00:14.0: @000000040beda460 00000000 00000000 00000000 00000000
>[    0.847164] xhci_hcd 0000:00:14.0: @000000040beda470 00000000 00000000 00000000 00000000
>[    0.847166] xhci_hcd 0000:00:14.0: @000000040beda480 00000000 00000000 00000000 00000000
>[    0.847167] xhci_hcd 0000:00:14.0: @000000040beda490 00000000 00000000 00000000 00000000
>[    0.847168] xhci_hcd 0000:00:14.0: @000000040beda4a0 00000000 00000000 00000000 00000000
>[    0.847169] xhci_hcd 0000:00:14.0: @000000040beda4b0 00000000 00000000 00000000 00000000
>[    0.847170] xhci_hcd 0000:00:14.0: @000000040beda4c0 00000000 00000000 00000000 00000000
>[    0.847171] xhci_hcd 0000:00:14.0: @000000040beda4d0 00000000 00000000 00000000 00000000
>[    0.847172] xhci_hcd 0000:00:14.0: @000000040beda4e0 00000000 00000000 00000000 00000000
>[    0.847173] xhci_hcd 0000:00:14.0: @000000040beda4f0 00000000 00000000 00000000 00000000
>[    0.847174] xhci_hcd 0000:00:14.0: @000000040beda500 00000000 00000000 00000000 00000000
>[    0.847175] xhci_hcd 0000:00:14.0: @000000040beda510 00000000 00000000 00000000 00000000
>[    0.847177] xhci_hcd 0000:00:14.0: @000000040beda520 00000000 00000000 00000000 00000000
>[    0.847178] xhci_hcd 0000:00:14.0: @000000040beda530 00000000 00000000 00000000 00000000
>[    0.847179] xhci_hcd 0000:00:14.0: @000000040beda540 00000000 00000000 00000000 00000000
>[    0.847180] xhci_hcd 0000:00:14.0: @000000040beda550 00000000 00000000 00000000 00000000
>[    0.847181] xhci_hcd 0000:00:14.0: @000000040beda560 00000000 00000000 00000000 00000000
>[    0.847182] xhci_hcd 0000:00:14.0: @000000040beda570 00000000 00000000 00000000 00000000
>[    0.847183] xhci_hcd 0000:00:14.0: @000000040beda580 00000000 00000000 00000000 00000000
>[    0.847184] xhci_hcd 0000:00:14.0: @000000040beda590 00000000 00000000 00000000 00000000
>[    0.847185] xhci_hcd 0000:00:14.0: @000000040beda5a0 00000000 00000000 00000000 00000000
>[    0.847186] xhci_hcd 0000:00:14.0: @000000040beda5b0 00000000 00000000 00000000 00000000
>[    0.847187] xhci_hcd 0000:00:14.0: @000000040beda5c0 00000000 00000000 00000000 00000000
>[    0.847189] xhci_hcd 0000:00:14.0: @000000040beda5d0 00000000 00000000 00000000 00000000
>[    0.847190] xhci_hcd 0000:00:14.0: @000000040beda5e0 00000000 00000000 00000000 00000000
>[    0.847191] xhci_hcd 0000:00:14.0: @000000040beda5f0 00000000 00000000 00000000 00000000
>[    0.847192] xhci_hcd 0000:00:14.0: @000000040beda600 00000000 00000000 00000000 00000000
>[    0.847193] xhci_hcd 0000:00:14.0: @000000040beda610 00000000 00000000 00000000 00000000
>[    0.847194] xhci_hcd 0000:00:14.0: @000000040beda620 00000000 00000000 00000000 00000000
>[    0.847195] xhci_hcd 0000:00:14.0: @000000040beda630 00000000 00000000 00000000 00000000
>[    0.847196] xhci_hcd 0000:00:14.0: @000000040beda640 00000000 00000000 00000000 00000000
>[    0.847197] xhci_hcd 0000:00:14.0: @000000040beda650 00000000 00000000 00000000 00000000
>[    0.847198] xhci_hcd 0000:00:14.0: @000000040beda660 00000000 00000000 00000000 00000000
>[    0.847199] xhci_hcd 0000:00:14.0: @000000040beda670 00000000 00000000 00000000 00000000
>[    0.847201] xhci_hcd 0000:00:14.0: @000000040beda680 00000000 00000000 00000000 00000000
>[    0.847202] xhci_hcd 0000:00:14.0: @000000040beda690 00000000 00000000 00000000 00000000
>[    0.847203] xhci_hcd 0000:00:14.0: @000000040beda6a0 00000000 00000000 00000000 00000000
>[    0.847204] xhci_hcd 0000:00:14.0: @000000040beda6b0 00000000 00000000 00000000 00000000
>[    0.847205] xhci_hcd 0000:00:14.0: @000000040beda6c0 00000000 00000000 00000000 00000000
>[    0.847206] xhci_hcd 0000:00:14.0: @000000040beda6d0 00000000 00000000 00000000 00000000
>[    0.847207] xhci_hcd 0000:00:14.0: @000000040beda6e0 00000000 00000000 00000000 00000000
>[    0.847208] xhci_hcd 0000:00:14.0: @000000040beda6f0 00000000 00000000 00000000 00000000
>[    0.847209] xhci_hcd 0000:00:14.0: @000000040beda700 00000000 00000000 00000000 00000000
>[    0.847210] xhci_hcd 0000:00:14.0: @000000040beda710 00000000 00000000 00000000 00000000
>[    0.847212] xhci_hcd 0000:00:14.0: @000000040beda720 00000000 00000000 00000000 00000000
>[    0.847213] xhci_hcd 0000:00:14.0: @000000040beda730 00000000 00000000 00000000 00000000
>[    0.847214] xhci_hcd 0000:00:14.0: @000000040beda740 00000000 00000000 00000000 00000000
>[    0.847215] xhci_hcd 0000:00:14.0: @000000040beda750 00000000 00000000 00000000 00000000
>[    0.847216] xhci_hcd 0000:00:14.0: @000000040beda760 00000000 00000000 00000000 00000000
>[    0.847217] xhci_hcd 0000:00:14.0: @000000040beda770 00000000 00000000 00000000 00000000
>[    0.847218] xhci_hcd 0000:00:14.0: @000000040beda780 00000000 00000000 00000000 00000000
>[    0.847219] xhci_hcd 0000:00:14.0: @000000040beda790 00000000 00000000 00000000 00000000
>[    0.847220] xhci_hcd 0000:00:14.0: @000000040beda7a0 00000000 00000000 00000000 00000000
>[    0.847221] xhci_hcd 0000:00:14.0: @000000040beda7b0 00000000 00000000 00000000 00000000
>[    0.847223] xhci_hcd 0000:00:14.0: @000000040beda7c0 00000000 00000000 00000000 00000000
>[    0.847224] xhci_hcd 0000:00:14.0: @000000040beda7d0 00000000 00000000 00000000 00000000
>[    0.847225] xhci_hcd 0000:00:14.0: @000000040beda7e0 00000000 00000000 00000000 00000000
>[    0.847226] xhci_hcd 0000:00:14.0: @000000040beda7f0 00000000 00000000 00000000 00000000
>[    0.847227] xhci_hcd 0000:00:14.0:   Ring has not been updated
>[    0.847228] xhci_hcd 0000:00:14.0: Ring deq = ffff88040beda400 (virt), 0x40beda400 (dma)
>[    0.847229] xhci_hcd 0000:00:14.0: Ring deq updated 0 times
>[    0.847230] xhci_hcd 0000:00:14.0: Ring enq = ffff88040beda400 (virt), 0x40beda400 (dma)
>[    0.847231] xhci_hcd 0000:00:14.0: Ring enq updated 0 times
>[    0.847233] xhci_hcd 0000:00:14.0: ERST deq = 64'h40beda400
>[    0.847234] xhci_hcd 0000:00:14.0: // Set the interrupt modulation register
>[    0.847237] xhci_hcd 0000:00:14.0: // Enable interrupts, cmd = 0x4.
>[    0.847239] xhci_hcd 0000:00:14.0: // Enabling event ring interrupter ffffc9000b062020 by writing 0x2 to irq_pending
>[    0.847241] xhci_hcd 0000:00:14.0:   ffffc9000b062020: ir_set[0]
>[    0.847242] xhci_hcd 0000:00:14.0:   ffffc9000b062020: ir_set.pending = 0x2
>[    0.847244] xhci_hcd 0000:00:14.0:   ffffc9000b062024: ir_set.control = 0xa0
>[    0.847245] xhci_hcd 0000:00:14.0:   ffffc9000b062028: ir_set.erst_size = 0x1
>[    0.847249] xhci_hcd 0000:00:14.0:   ffffc9000b062030: ir_set.erst_base = @40b974000
>[    0.847251] xhci_hcd 0000:00:14.0:   ffffc9000b062038: ir_set.erst_dequeue = @40beda400
>[    0.847252] xhci_hcd 0000:00:14.0: Finished xhci_run for USB2 roothub
>[    0.847262] usb usb2: default language 0x0409
>[    0.847267] usb usb2: udev 1, busnum 2, minor = 128
>[    0.847268] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
>[    0.847463] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    0.847638] usb usb2: Product: xHCI Host Controller
>[    0.847897] usb usb2: Manufacturer: Linux 3.12.5-gentoo xhci_hcd
>[    0.848182] usb usb2: SerialNumber: 0000:00:14.0
>[    0.848522] usb usb2: usb_probe_device
>[    0.848524] usb usb2: configuration #1 chosen from 1 choice
>[    0.848525] xHCI xhci_add_endpoint called for root hub
>[    0.848526] xHCI xhci_check_bandwidth called for root hub
>[    0.848530] usb usb2: adding 2-0:1.0 (config #1, interface 0)
>[    0.848560] hub 2-0:1.0: usb_probe_interface
>[    0.848561] hub 2-0:1.0: usb_probe_interface - got id
>[    0.848562] hub 2-0:1.0: USB hub found
>[    0.848761] hub 2-0:1.0: 15 ports detected
>[    0.849027] hub 2-0:1.0: standalone hub
>[    0.849028] hub 2-0:1.0: no power switching (usb 1.0)
>[    0.849029] hub 2-0:1.0: individual port over-current protection
>[    0.849030] hub 2-0:1.0: Single TT
>[    0.849031] hub 2-0:1.0: TT requires at most 8 FS bit times (666 ns)
>[    0.849032] hub 2-0:1.0: power on to power good time: 20ms
>[    0.849035] hub 2-0:1.0: local power source is good
>[    0.850401] hub 2-0:1.0: trying to enable port power on non-switchable hub
>[    0.850405] xhci_hcd 0000:00:14.0: set port power, actual port 0 status  = 0x2a0
>[    0.850411] xhci_hcd 0000:00:14.0: set port power, actual port 1 status  = 0x2a0
>[    0.850415] xhci_hcd 0000:00:14.0: set port power, actual port 2 status  = 0x2a0
>[    0.850419] xhci_hcd 0000:00:14.0: set port power, actual port 3 status  = 0x2a0
>[    0.850424] xhci_hcd 0000:00:14.0: set port power, actual port 4 status  = 0x2a0
>[    0.850428] xhci_hcd 0000:00:14.0: set port power, actual port 5 status  = 0x2a0
>[    0.850432] xhci_hcd 0000:00:14.0: set port power, actual port 6 status  = 0x2a0
>[    0.850437] xhci_hcd 0000:00:14.0: set port power, actual port 7 status  = 0x2a0
>[    0.850441] xhci_hcd 0000:00:14.0: set port power, actual port 8 status  = 0x2a0
>[    0.850445] xhci_hcd 0000:00:14.0: set port power, actual port 9 status  = 0x2a0
>[    0.850450] xhci_hcd 0000:00:14.0: set port power, actual port 10 status  = 0x2a0
>[    0.850454] xhci_hcd 0000:00:14.0: set port power, actual port 11 status  = 0x2a0
>[    0.850458] xhci_hcd 0000:00:14.0: set port power, actual port 12 status  = 0x2a0
>[    0.850462] xhci_hcd 0000:00:14.0: set port power, actual port 13 status  = 0x2a0
>[    0.850467] xhci_hcd 0000:00:14.0: set port power, actual port 14 status  = 0x2a0
>[    0.850484] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    0.850711] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 3
>[    0.850904] xhci_hcd 0000:00:14.0: supports USB remote wakeup
>[    0.850906] xhci_hcd 0000:00:14.0: // Turn on HC, cmd = 0x5.
>[    0.850908] xhci_hcd 0000:00:14.0: Finished xhci_run for USB3 roothub
>[    0.850919] usb usb3: skipped 1 descriptor after endpoint
>[    0.850923] usb usb3: default language 0x0409
>[    0.850928] usb usb3: udev 1, busnum 3, minor = 256
>[    0.850929] usb usb3: New USB device found, idVendor=1d6b, idProduct=0003
>[    0.851136] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    0.851428] usb usb3: Product: xHCI Host Controller
>[    0.851725] usb usb3: Manufacturer: Linux 3.12.5-gentoo xhci_hcd
>[    0.852025] usb usb3: SerialNumber: 0000:00:14.0
>[    0.852382] usb usb3: usb_probe_device
>[    0.852383] usb usb3: configuration #1 chosen from 1 choice
>[    0.852385] xHCI xhci_add_endpoint called for root hub
>[    0.852385] xHCI xhci_check_bandwidth called for root hub
>[    0.852390] usb usb3: adding 3-0:1.0 (config #1, interface 0)
>[    0.852418] hub 3-0:1.0: usb_probe_interface
>[    0.852419] hub 3-0:1.0: usb_probe_interface - got id
>[    0.852420] hub 3-0:1.0: USB hub found
>[    0.852622] hub 3-0:1.0: 6 ports detected
>[    0.852912] hub 3-0:1.0: standalone hub
>[    0.852913] hub 3-0:1.0: no power switching (usb 1.0)
>[    0.852914] hub 3-0:1.0: individual port over-current protection
>[    0.852915] hub 3-0:1.0: TT requires at most 8 FS bit times (666 ns)
>[    0.852916] hub 3-0:1.0: power on to power good time: 20ms
>[    0.852920] hub 3-0:1.0: local power source is good
>[    0.853462] hub 3-0:1.0: trying to enable port power on non-switchable hub
>[    0.853465] xhci_hcd 0000:00:14.0: set port power, actual port 0 status  = 0x12b1
>[    0.853471] xhci_hcd 0000:00:14.0: set port power, actual port 1 status  = 0x802a0
>[    0.853475] xhci_hcd 0000:00:14.0: set port power, actual port 2 status  = 0x802a0
>[    0.853480] xhci_hcd 0000:00:14.0: set port power, actual port 3 status  = 0x802a0
>[    0.853484] xhci_hcd 0000:00:14.0: set port power, actual port 4 status  = 0x802a0
>[    0.853489] xhci_hcd 0000:00:14.0: set port power, actual port 5 status  = 0x802a0
>[    0.861185] usbcore: registered new interface driver usblp
>[    0.861423] usbcore: registered new interface driver usb-storage
>[    0.861767] i8042: PNP: No PS/2 controller found. Probing ports directly.
>[    0.864417] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    0.864610] serio: i8042 AUX port at 0x60,0x64 irq 12
>[    0.864876] mousedev: PS/2 mouse device common for all mice
>[    0.865277] input: PC Speaker as /devices/platform/pcspkr/input/input3
>[    0.865531] rtc_cmos 00:06: RTC can wake from S4
>[    0.865833] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0
>[    0.866042] rtc_cmos 00:06: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    0.866286] i2c /dev entries driver
>[    0.867087] sdhci: Secure Digital Host Controller Interface driver
>[    0.867278] sdhci: Copyright(c) Pierre Ossman
>[    0.867509] VUB300 Driver rom wait states = 1C irqpoll timeout = 0400
>[    0.867611] usbcore: registered new interface driver vub300
>[    0.868024] xhci_hcd 0000:00:14.0: Port Status Change Event for port 13
>[    0.868027] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    0.868041] xhci_hcd 0000:00:14.0: Port Status Change Event for port 14
>[    0.868042] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    0.868073] usbcore: registered new interface driver ushc
>[    0.868345] sdhci-pltfm: SDHCI platform and OF driver helper
>[    0.868636] EFI Variables Facility v0.08 2004-May-17
>[    0.874002] hidraw: raw HID events driver (C) Jiri Kosina
>[    0.874551] usbcore: registered new interface driver usbhid
>[    0.874736] usbhid: USB HID core driver
>[    0.875197] snd_hda_intel 0000:00:1b.0: enabling device (0000 -> 0002)
>[    0.875457] snd_hda_intel 0000:00:1b.0: irq 57 for MSI/MSI-X
>[    0.895381] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11
>[    0.895644] input: HDA Intel PCH Line Out Side as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10
>[    0.895895] input: HDA Intel PCH Line Out CLFE as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
>[    0.896151] input: HDA Intel PCH Line Out Surround as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8
>[    0.896407] input: HDA Intel PCH Line Out Front as /devices/pci0000:00/0000:00:1b.0/sound/card0/input7
>[    0.896664] input: HDA Intel PCH Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input6
>[    0.896948] input: HDA Intel PCH Rear Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input5
>[    0.897240] input: HDA Intel PCH Front Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input4
>[    0.897981] hda_intel: Disabling MSI
>[    0.945095] ehci-pci 0000:00:1d.0: GetStatus port:1 status 001803 0  ACK POWER sig=j CSC CONNECT
>[    0.945101] hub 1-0:1.0: port 1: status 0501 change 0001
>[    0.946080] xhci_hcd 0000:00:14.0: Port Status Change Event for port 16
>[    0.946083] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    0.950091] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x2a0
>[    0.950094] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950099] xhci_hcd 0000:00:14.0: get port status, actual port 1 status  = 0x2a0
>[    0.950100] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950103] xhci_hcd 0000:00:14.0: get port status, actual port 2 status  = 0x2a0
>[    0.950104] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950107] xhci_hcd 0000:00:14.0: get port status, actual port 3 status  = 0x2a0
>[    0.950108] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950111] xhci_hcd 0000:00:14.0: get port status, actual port 4 status  = 0x2a0
>[    0.950112] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950115] xhci_hcd 0000:00:14.0: get port status, actual port 5 status  = 0x2a0
>[    0.950116] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950118] xhci_hcd 0000:00:14.0: get port status, actual port 6 status  = 0x2a0
>[    0.950119] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950122] xhci_hcd 0000:00:14.0: get port status, actual port 7 status  = 0x2a0
>[    0.950123] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950126] xhci_hcd 0000:00:14.0: get port status, actual port 8 status  = 0x2a0
>[    0.950127] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950130] xhci_hcd 0000:00:14.0: get port status, actual port 9 status  = 0x2a0
>[    0.950131] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950134] xhci_hcd 0000:00:14.0: get port status, actual port 10 status  = 0x2a0
>[    0.950135] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950137] xhci_hcd 0000:00:14.0: get port status, actual port 11 status  = 0x2a0
>[    0.950138] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.950141] xhci_hcd 0000:00:14.0: get port status, actual port 12 status  = 0x206e1
>[    0.950142] xhci_hcd 0000:00:14.0: Get port status returned 0x10101
>[    0.950144] hub 2-0:1.0: port 13: status 0101 change 0001
>[    0.950147] xhci_hcd 0000:00:14.0: clear port connect change, actual port 12 status  = 0x6e1
>[    0.950150] xhci_hcd 0000:00:14.0: get port status, actual port 13 status  = 0x206e1
>[    0.950151] xhci_hcd 0000:00:14.0: Get port status returned 0x10101
>[    0.950153] hub 2-0:1.0: port 14: status 0101 change 0001
>[    0.950156] xhci_hcd 0000:00:14.0: clear port connect change, actual port 13 status  = 0x6e1
>[    0.950159] xhci_hcd 0000:00:14.0: get port status, actual port 14 status  = 0x2a0
>[    0.950160] xhci_hcd 0000:00:14.0: Get port status returned 0x100
>[    0.953092] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x2202a0
>[    0.953094] xhci_hcd 0000:00:14.0: Get port status returned 0x1102a0
>[    0.953100] xhci_hcd 0000:00:14.0: clear port connect change, actual port 0 status  = 0x2002a0
>[    0.953105] xhci_hcd 0000:00:14.0: clear port reset change, actual port 0 status  = 0x2a0
>[    0.953108] xhci_hcd 0000:00:14.0: get port status, actual port 1 status  = 0x802a0
>[    0.953109] xhci_hcd 0000:00:14.0: Get port status returned 0x2002a0
>[    0.953113] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 1 status  = 0x2a0
>[    0.953116] xhci_hcd 0000:00:14.0: get port status, actual port 2 status  = 0x802a0
>[    0.953117] xhci_hcd 0000:00:14.0: Get port status returned 0x2002a0
>[    0.953122] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 2 status  = 0x2a0
>[    0.953125] xhci_hcd 0000:00:14.0: get port status, actual port 3 status  = 0x802a0
>[    0.953126] xhci_hcd 0000:00:14.0: Get port status returned 0x2002a0
>[    0.953130] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 3 status  = 0x2a0
>[    0.953133] xhci_hcd 0000:00:14.0: get port status, actual port 4 status  = 0x802a0
>[    0.953134] xhci_hcd 0000:00:14.0: Get port status returned 0x2002a0
>[    0.953138] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 4 status  = 0x2a0
>[    0.953141] xhci_hcd 0000:00:14.0: get port status, actual port 5 status  = 0x802a0
>[    0.953142] xhci_hcd 0000:00:14.0: Get port status returned 0x2002a0
>[    0.953146] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 5 status  = 0x2a0
>[    0.962341] xhci_hcd 0000:00:14.0: Port Status Change Event for port 16
>[    0.962344] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    0.980093] xhci_hcd 0000:00:14.0: xhci_hub_status_data: stopping port polling.
>[    1.015108] ata4: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
>[    1.015317] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    1.015615] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    1.016512] ata2.00: ATA-9: ST1000DM003-1CH162, CC47, max UDMA/133
>[    1.016695] ata2.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    1.017647] ata2.00: configured for UDMA/133
>[    1.029160] ata4.00: ATAPI: PIONEER DVD-RW  DVR-221, 1.00, max UDMA/100
>[    1.029991] ata1.00: ATA-8: KINGSTON SV300S37A240G, 520ABBF0, max UDMA/133
>[    1.030185] ata1.00: 468862128 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    1.039954] ata1.00: configured for UDMA/133
>[    1.040256] scsi 0:0:0:0: Direct-Access     ATA      KINGSTON SV300S3 520A PQ: 0 ANSI: 5
>[    1.040748] sd 0:0:0:0: [sda] 468862128 512-byte logical blocks: (240 GB/223 GiB)
>[    1.040902] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[    1.041024] scsi 1:0:0:0: Direct-Access     ATA      ST1000DM003-1CH1 CC47 PQ: 0 ANSI: 5
>[    1.041213] sd 1:0:0:0: [sdb] 1953525168 512-byte logical blocks: (1.00 TB/931 GiB)
>[    1.041214] sd 1:0:0:0: [sdb] 4096-byte physical blocks
>[    1.041244] sd 1:0:0:0: Attached scsi generic sg1 type 0
>[    1.041311] sd 1:0:0:0: [sdb] Write Protect is off
>[    1.041312] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
>[    1.041340] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    1.042895] sd 0:0:0:0: [sda] Write Protect is off
>[    1.043170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    1.043177] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    1.044145]  sda: sda1 sda2 sda3 sda4 sda5
>[    1.044598] ata4.00: configured for UDMA/100
>[    1.044677] sd 0:0:0:0: [sda] Attached SCSI disk
>[    1.045088] hub 1-0:1.0: state 7 ports 2 chg 0002 evt 0000
>[    1.045112] hub 1-0:1.0: port 1, status 0501, change 0000, 480 Mb/s
>[    1.048284] scsi 3:0:0:0: CD-ROM            PIONEER  DVD-RW  DVR-221  1.00 PQ: 0 ANSI: 5
>[    1.051091] xhci_hcd 0000:00:14.0: xhci_hub_status_data: stopping port polling.
>[    1.053966] sr0: scsi3-mmc drive: 40x/40x writer dvd-ram cd/rw xa/form2 cdda tray
>[    1.054171] cdrom: Uniform CD-ROM driver Revision: 3.20
>[    1.054553] sr 3:0:0:0: Attached scsi CD-ROM sr0
>[    1.054663] sr 3:0:0:0: Attached scsi generic sg2 type 5
>[    1.075273] input: HDA NVidia HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input16
>[    1.075685] input: HDA NVidia HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input15
>[    1.075985] input: HDA NVidia HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input14
>[    1.076274] input: HDA NVidia HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:01.0/0000:01:00.1/sound/card1/input13
>[    1.077077] ip_tables: (C) 2000-2006 Netfilter Core Team
>[    1.077288] TCP: cubic registered
>[    1.077481] Initializing XFRM netlink socket
>[    1.077892] NET: Registered protocol family 10
>[    1.078262] ip6_tables: (C) 2000-2006 Netfilter Core Team
>[    1.078473] sit: IPv6 over IPv4 tunneling driver
>[    1.078805] NET: Registered protocol family 17
>[    1.079006] l2tp_core: L2TP core driver, V2.0
>[    1.079239] l2tp_ppp: PPPoL2TP kernel driver, V2.0
>[    1.079531] l2tp_ip: L2TP IP encapsulation support (L2TPv3)
>[    1.079831] l2tp_netlink: L2TP netlink interface
>[    1.080132] l2tp_eth: L2TP ethernet pseudowire support (L2TPv3)
>[    1.080425] l2tp_ip6: L2TP IP encapsulation support for IPv6 (L2TPv3)
>[    1.080727] 8021q: 802.1Q VLAN Support v1.8
>[    1.081028] Key type dns_resolver registered
>[    1.081739]  sdb: sdb1 sdb2 sdb3
>[    1.081916] registered taskstats version 1
>[    1.082242] console [netcon0] enabled
>[    1.082398] sd 1:0:0:0: [sdb] Attached SCSI disk
>[    1.082698] netconsole: network logging started
>[    1.083927] ALSA device list:
>[    1.084130]   #0: HDA Intel PCH at 0xf7410000 irq 57
>[    1.084299]   #1: HDA NVidia at 0xf7080000 irq 17
>[    1.096249] ehci-pci 0000:00:1d.0: port 1 reset complete, port enabled
>[    1.096252] ehci-pci 0000:00:1d.0: GetStatus port:1 status 001005 0  ACK POWER sig=se0 PE CONNECT
>[    1.147117] usb 1-1: new high-speed USB device number 2 using ehci-pci
>[    1.198367] ehci-pci 0000:00:1d.0: port 1 reset complete, port enabled
>[    1.198370] ehci-pci 0000:00:1d.0: GetStatus port:1 status 001005 0  ACK POWER sig=se0 PE CONNECT
>[    1.226074] tsc: Refined TSC clocksource calibration: 3292.375 MHz
>[    1.261509] usb 1-1: udev 2, busnum 1, minor = 1
>[    1.261512] usb 1-1: New USB device found, idVendor=8087, idProduct=8000
>[    1.261707] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    1.262027] usb 1-1: usb_probe_device
>[    1.262029] usb 1-1: configuration #1 chosen from 1 choice
>[    1.262137] usb 1-1: adding 1-1:1.0 (config #1, interface 0)
>[    1.262228] hub 1-1:1.0: usb_probe_interface
>[    1.262230] hub 1-1:1.0: usb_probe_interface - got id
>[    1.262232] hub 1-1:1.0: USB hub found
>[    1.262509] hub 1-1:1.0: 8 ports detected
>[    1.262704] hub 1-1:1.0: standalone hub
>[    1.262705] hub 1-1:1.0: individual port power switching
>[    1.262706] hub 1-1:1.0: individual port over-current protection
>[    1.262707] hub 1-1:1.0: Single TT
>[    1.262708] hub 1-1:1.0: TT requires at most 8 FS bit times (666 ns)
>[    1.262709] hub 1-1:1.0: power on to power good time: 0ms
>[    1.262869] hub 1-1:1.0: local power source is good
>[    1.263069] hub 1-1:1.0: enabling power on all ports
>[    1.264019] hub 2-0:1.0: state 7 ports 15 chg 6000 evt 0000
>[    1.264023] xhci_hcd 0000:00:14.0: get port status, actual port 12 status  = 0x6e1
>[    1.264024] xhci_hcd 0000:00:14.0: Get port status returned 0x101
>[    1.264038] hub 2-0:1.0: port 13, status 0101, change 0000, 12 Mb/s
>[    1.264041] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.264063] xhci_hcd 0000:00:14.0: Slot 1 output ctx = 0x40ba63000 (dma)
>[    1.264065] xhci_hcd 0000:00:14.0: Slot 1 input ctx = 0x40ba64000 (dma)
>[    1.264068] xhci_hcd 0000:00:14.0: Set slot id 1 dcbaa entry ffff88040bed9008 to 0x40ba63000
>[    1.264073] xhci_hcd 0000:00:14.0: set port reset, actual port 12 status  = 0x791
>[    1.280709] EXT3-fs (sda5): error: couldn't mount because of unsupported optional features (240)
>[    1.281090] EXT4-fs (sda5): couldn't mount as ext2 due to feature incompatibilities
>[    1.282064] EXT4-fs (sda5): INFO: recovery required on readonly filesystem
>[    1.282259] EXT4-fs (sda5): write access will be enabled during recovery
>[    1.315083] xhci_hcd 0000:00:14.0: get port status, actual port 12 status  = 0x791
>[    1.315085] xhci_hcd 0000:00:14.0: Get port status returned 0x111
>[    1.315107] hub 2-0:1.0: port 13 not reset yet, waiting 50ms
>[    1.315397] EXT4-fs (sda5): orphan cleanup on readonly fs
>[    1.315655] EXT4-fs (sda5): 9 orphan inodes deleted
>[    1.315850] EXT4-fs (sda5): recovery complete
>[    1.319214] xhci_hcd 0000:00:14.0: Port Status Change Event for port 13
>[    1.319217] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    1.324445] EXT4-fs (sda5): mounted filesystem with ordered data mode. Opts: (null)
>[    1.324642] VFS: Mounted root (ext4 filesystem) readonly on device 8:5.
>[    1.325332] devtmpfs: mounted
>[    1.325815] Freeing unused kernel memory: 884K (ffffffff81a52000 - ffffffff81b2f000)
>[    1.332197] firewire_core 0000:04:02.0: created device fw0: GUID 001e8c000066ecd8, S400
>[    1.363991] usb 1-1: link qh256-0001/ffff88040c364e00 start 1 [1/0 us]
>[    1.366077] xhci_hcd 0000:00:14.0: get port status, actual port 12 status  = 0x200603
>[    1.366078] xhci_hcd 0000:00:14.0: Get port status returned 0x100103
>[    1.417069] xhci_hcd 0000:00:14.0: clear port reset change, actual port 12 status  = 0x603
>[    1.417097] usb 2-13: new full-speed USB device number 2 using xhci_hcd
>[    1.417331] xhci_hcd 0000:00:14.0: Set root hub portnum to 13
>[    1.417333] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 13
>[    1.417334] xhci_hcd 0000:00:14.0: udev->tt = ffff88040c0bfea0
>[    1.417335] xhci_hcd 0000:00:14.0: udev->ttport = 0xd
>[    1.417336] xhci_hcd 0000:00:14.0: Slot ID 1 Input Context:
>[    1.417338] xhci_hcd 0000:00:14.0: @ffff88040ba64000 (virt) @40ba64000 (dma) 0x000000 - drop flags
>[    1.417340] xhci_hcd 0000:00:14.0: @ffff88040ba64004 (virt) @40ba64004 (dma) 0x000003 - add flags
>[    1.417341] xhci_hcd 0000:00:14.0: @ffff88040ba64008 (virt) @40ba64008 (dma) 0x000000 - rsvd2[0]
>[    1.417342] xhci_hcd 0000:00:14.0: @ffff88040ba6400c (virt) @40ba6400c (dma) 0x000000 - rsvd2[1]
>[    1.417344] xhci_hcd 0000:00:14.0: @ffff88040ba64010 (virt) @40ba64010 (dma) 0x000000 - rsvd2[2]
>[    1.417345] xhci_hcd 0000:00:14.0: @ffff88040ba64014 (virt) @40ba64014 (dma) 0x000000 - rsvd2[3]
>[    1.417346] xhci_hcd 0000:00:14.0: @ffff88040ba64018 (virt) @40ba64018 (dma) 0x000000 - rsvd2[4]
>[    1.417347] xhci_hcd 0000:00:14.0: @ffff88040ba6401c (virt) @40ba6401c (dma) 0x000000 - rsvd2[5]
>[    1.417348] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.417350] xhci_hcd 0000:00:14.0: @ffff88040ba64020 (virt) @40ba64020 (dma) 0x8100000 - dev_info
>[    1.417351] xhci_hcd 0000:00:14.0: @ffff88040ba64024 (virt) @40ba64024 (dma) 0x0d0000 - dev_info2
>[    1.417352] xhci_hcd 0000:00:14.0: @ffff88040ba64028 (virt) @40ba64028 (dma) 0x000000 - tt_info
>[    1.417353] xhci_hcd 0000:00:14.0: @ffff88040ba6402c (virt) @40ba6402c (dma) 0x000000 - dev_state
>[    1.417355] xhci_hcd 0000:00:14.0: @ffff88040ba64030 (virt) @40ba64030 (dma) 0x000000 - rsvd[0]
>[    1.417356] xhci_hcd 0000:00:14.0: @ffff88040ba64034 (virt) @40ba64034 (dma) 0x000000 - rsvd[1]
>[    1.417357] xhci_hcd 0000:00:14.0: @ffff88040ba64038 (virt) @40ba64038 (dma) 0x000000 - rsvd[2]
>[    1.417358] xhci_hcd 0000:00:14.0: @ffff88040ba6403c (virt) @40ba6403c (dma) 0x000000 - rsvd[3]
>[    1.417360] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.417361] xhci_hcd 0000:00:14.0: @ffff88040ba64040 (virt) @40ba64040 (dma) 0x000000 - ep_info
>[    1.417362] xhci_hcd 0000:00:14.0: @ffff88040ba64044 (virt) @40ba64044 (dma) 0x400026 - ep_info2
>[    1.417364] xhci_hcd 0000:00:14.0: @ffff88040ba64048 (virt) @40ba64048 (dma) 0x40beda801 - deq
>[    1.417365] xhci_hcd 0000:00:14.0: @ffff88040ba64050 (virt) @40ba64050 (dma) 0x000000 - tx_info
>[    1.417366] xhci_hcd 0000:00:14.0: @ffff88040ba64054 (virt) @40ba64054 (dma) 0x000000 - rsvd[0]
>[    1.417367] xhci_hcd 0000:00:14.0: @ffff88040ba64058 (virt) @40ba64058 (dma) 0x000000 - rsvd[1]
>[    1.417369] xhci_hcd 0000:00:14.0: @ffff88040ba6405c (virt) @40ba6405c (dma) 0x000000 - rsvd[2]
>[    1.417370] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.417371] xhci_hcd 0000:00:14.0: @ffff88040ba64060 (virt) @40ba64060 (dma) 0x000000 - ep_info
>[    1.417372] xhci_hcd 0000:00:14.0: @ffff88040ba64064 (virt) @40ba64064 (dma) 0x000000 - ep_info2
>[    1.417373] xhci_hcd 0000:00:14.0: @ffff88040ba64068 (virt) @40ba64068 (dma) 0x000000 - deq
>[    1.417375] xhci_hcd 0000:00:14.0: @ffff88040ba64070 (virt) @40ba64070 (dma) 0x000000 - tx_info
>[    1.417376] xhci_hcd 0000:00:14.0: @ffff88040ba64074 (virt) @40ba64074 (dma) 0x000000 - rsvd[0]
>[    1.417377] xhci_hcd 0000:00:14.0: @ffff88040ba64078 (virt) @40ba64078 (dma) 0x000000 - rsvd[1]
>[    1.417379] xhci_hcd 0000:00:14.0: @ffff88040ba6407c (virt) @40ba6407c (dma) 0x000000 - rsvd[2]
>[    1.417380] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.417381] xhci_hcd 0000:00:14.0: @ffff88040ba64080 (virt) @40ba64080 (dma) 0x000000 - ep_info
>[    1.417382] xhci_hcd 0000:00:14.0: @ffff88040ba64084 (virt) @40ba64084 (dma) 0x000000 - ep_info2
>[    1.417383] xhci_hcd 0000:00:14.0: @ffff88040ba64088 (virt) @40ba64088 (dma) 0x000000 - deq
>[    1.417385] xhci_hcd 0000:00:14.0: @ffff88040ba64090 (virt) @40ba64090 (dma) 0x000000 - tx_info
>[    1.417386] xhci_hcd 0000:00:14.0: @ffff88040ba64094 (virt) @40ba64094 (dma) 0x000000 - rsvd[0]
>[    1.417387] xhci_hcd 0000:00:14.0: @ffff88040ba64098 (virt) @40ba64098 (dma) 0x000000 - rsvd[1]
>[    1.417388] xhci_hcd 0000:00:14.0: @ffff88040ba6409c (virt) @40ba6409c (dma) 0x000000 - rsvd[2]
>[    1.417390] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.417463] xhci_hcd 0000:00:14.0: Successful Address Device command
>[    1.417467] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[    1.417469] xhci_hcd 0000:00:14.0: Slot ID 1 dcbaa entry @ffff88040bed9008 = 0x0000040ba63000
>[    1.417470] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40ba63000
>[    1.417471] xhci_hcd 0000:00:14.0: Slot ID 1 Input Context:
>[    1.417473] xhci_hcd 0000:00:14.0: @ffff88040ba64000 (virt) @40ba64000 (dma) 0x000000 - drop flags
>[    1.417474] xhci_hcd 0000:00:14.0: @ffff88040ba64004 (virt) @40ba64004 (dma) 0x000003 - add flags
>[    1.417476] xhci_hcd 0000:00:14.0: @ffff88040ba64008 (virt) @40ba64008 (dma) 0x000000 - rsvd2[0]
>[    1.417477] xhci_hcd 0000:00:14.0: @ffff88040ba6400c (virt) @40ba6400c (dma) 0x000000 - rsvd2[1]
>[    1.417478] xhci_hcd 0000:00:14.0: @ffff88040ba64010 (virt) @40ba64010 (dma) 0x000000 - rsvd2[2]
>[    1.417479] xhci_hcd 0000:00:14.0: @ffff88040ba64014 (virt) @40ba64014 (dma) 0x000000 - rsvd2[3]
>[    1.417481] xhci_hcd 0000:00:14.0: @ffff88040ba64018 (virt) @40ba64018 (dma) 0x000000 - rsvd2[4]
>[    1.417482] xhci_hcd 0000:00:14.0: @ffff88040ba6401c (virt) @40ba6401c (dma) 0x000000 - rsvd2[5]
>[    1.417483] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.417484] xhci_hcd 0000:00:14.0: @ffff88040ba64020 (virt) @40ba64020 (dma) 0x8100000 - dev_info
>[    1.417485] xhci_hcd 0000:00:14.0: @ffff88040ba64024 (virt) @40ba64024 (dma) 0x0d0000 - dev_info2
>[    1.417487] xhci_hcd 0000:00:14.0: @ffff88040ba64028 (virt) @40ba64028 (dma) 0x000000 - tt_info
>[    1.417488] xhci_hcd 0000:00:14.0: @ffff88040ba6402c (virt) @40ba6402c (dma) 0x000000 - dev_state
>[    1.417489] xhci_hcd 0000:00:14.0: @ffff88040ba64030 (virt) @40ba64030 (dma) 0x000000 - rsvd[0]
>[    1.417490] xhci_hcd 0000:00:14.0: @ffff88040ba64034 (virt) @40ba64034 (dma) 0x000000 - rsvd[1]
>[    1.417492] xhci_hcd 0000:00:14.0: @ffff88040ba64038 (virt) @40ba64038 (dma) 0x000000 - rsvd[2]
>[    1.417493] xhci_hcd 0000:00:14.0: @ffff88040ba6403c (virt) @40ba6403c (dma) 0x000000 - rsvd[3]
>[    1.417494] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.417496] xhci_hcd 0000:00:14.0: @ffff88040ba64040 (virt) @40ba64040 (dma) 0x000000 - ep_info
>[    1.417497] xhci_hcd 0000:00:14.0: @ffff88040ba64044 (virt) @40ba64044 (dma) 0x400026 - ep_info2
>[    1.417499] xhci_hcd 0000:00:14.0: @ffff88040ba64048 (virt) @40ba64048 (dma) 0x40beda801 - deq
>[    1.417500] xhci_hcd 0000:00:14.0: @ffff88040ba64050 (virt) @40ba64050 (dma) 0x000000 - tx_info
>[    1.417501] xhci_hcd 0000:00:14.0: @ffff88040ba64054 (virt) @40ba64054 (dma) 0x000000 - rsvd[0]
>[    1.417502] xhci_hcd 0000:00:14.0: @ffff88040ba64058 (virt) @40ba64058 (dma) 0x000000 - rsvd[1]
>[    1.417504] xhci_hcd 0000:00:14.0: @ffff88040ba6405c (virt) @40ba6405c (dma) 0x000000 - rsvd[2]
>[    1.417505] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.417506] xhci_hcd 0000:00:14.0: @ffff88040ba64060 (virt) @40ba64060 (dma) 0x000000 - ep_info
>[    1.417507] xhci_hcd 0000:00:14.0: @ffff88040ba64064 (virt) @40ba64064 (dma) 0x000000 - ep_info2
>[    1.417508] xhci_hcd 0000:00:14.0: @ffff88040ba64068 (virt) @40ba64068 (dma) 0x000000 - deq
>[    1.417510] xhci_hcd 0000:00:14.0: @ffff88040ba64070 (virt) @40ba64070 (dma) 0x000000 - tx_info
>[    1.417511] xhci_hcd 0000:00:14.0: @ffff88040ba64074 (virt) @40ba64074 (dma) 0x000000 - rsvd[0]
>[    1.417512] xhci_hcd 0000:00:14.0: @ffff88040ba64078 (virt) @40ba64078 (dma) 0x000000 - rsvd[1]
>[    1.417514] xhci_hcd 0000:00:14.0: @ffff88040ba6407c (virt) @40ba6407c (dma) 0x000000 - rsvd[2]
>[    1.417515] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.417516] xhci_hcd 0000:00:14.0: @ffff88040ba64080 (virt) @40ba64080 (dma) 0x000000 - ep_info
>[    1.417517] xhci_hcd 0000:00:14.0: @ffff88040ba64084 (virt) @40ba64084 (dma) 0x000000 - ep_info2
>[    1.417518] xhci_hcd 0000:00:14.0: @ffff88040ba64088 (virt) @40ba64088 (dma) 0x000000 - deq
>[    1.417519] xhci_hcd 0000:00:14.0: @ffff88040ba64090 (virt) @40ba64090 (dma) 0x000000 - tx_info
>[    1.417521] xhci_hcd 0000:00:14.0: @ffff88040ba64094 (virt) @40ba64094 (dma) 0x000000 - rsvd[0]
>[    1.417522] xhci_hcd 0000:00:14.0: @ffff88040ba64098 (virt) @40ba64098 (dma) 0x000000 - rsvd[1]
>[    1.417523] xhci_hcd 0000:00:14.0: @ffff88040ba6409c (virt) @40ba6409c (dma) 0x000000 - rsvd[2]
>[    1.417524] xhci_hcd 0000:00:14.0: Slot ID 1 Output Context:
>[    1.417525] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.417527] xhci_hcd 0000:00:14.0: @ffff88040ba63000 (virt) @40ba63000 (dma) 0x8100000 - dev_info
>[    1.417528] xhci_hcd 0000:00:14.0: @ffff88040ba63004 (virt) @40ba63004 (dma) 0x0d0000 - dev_info2
>[    1.417529] xhci_hcd 0000:00:14.0: @ffff88040ba63008 (virt) @40ba63008 (dma) 0x000000 - tt_info
>[    1.417530] xhci_hcd 0000:00:14.0: @ffff88040ba6300c (virt) @40ba6300c (dma) 0x10000001 - dev_state
>[    1.417532] xhci_hcd 0000:00:14.0: @ffff88040ba63010 (virt) @40ba63010 (dma) 0x000000 - rsvd[0]
>[    1.417533] xhci_hcd 0000:00:14.0: @ffff88040ba63014 (virt) @40ba63014 (dma) 0x000000 - rsvd[1]
>[    1.417534] xhci_hcd 0000:00:14.0: @ffff88040ba63018 (virt) @40ba63018 (dma) 0x000000 - rsvd[2]
>[    1.417535] xhci_hcd 0000:00:14.0: @ffff88040ba6301c (virt) @40ba6301c (dma) 0x000000 - rsvd[3]
>[    1.417537] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.417538] xhci_hcd 0000:00:14.0: @ffff88040ba63020 (virt) @40ba63020 (dma) 0x000001 - ep_info
>[    1.417539] xhci_hcd 0000:00:14.0: @ffff88040ba63024 (virt) @40ba63024 (dma) 0x400026 - ep_info2
>[    1.417540] xhci_hcd 0000:00:14.0: @ffff88040ba63028 (virt) @40ba63028 (dma) 0x40beda801 - deq
>[    1.417542] xhci_hcd 0000:00:14.0: @ffff88040ba63030 (virt) @40ba63030 (dma) 0x000000 - tx_info
>[    1.417543] xhci_hcd 0000:00:14.0: @ffff88040ba63034 (virt) @40ba63034 (dma) 0x000000 - rsvd[0]
>[    1.417544] xhci_hcd 0000:00:14.0: @ffff88040ba63038 (virt) @40ba63038 (dma) 0x000000 - rsvd[1]
>[    1.417545] xhci_hcd 0000:00:14.0: @ffff88040ba6303c (virt) @40ba6303c (dma) 0x000000 - rsvd[2]
>[    1.417547] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.417548] xhci_hcd 0000:00:14.0: @ffff88040ba63040 (virt) @40ba63040 (dma) 0x000000 - ep_info
>[    1.417549] xhci_hcd 0000:00:14.0: @ffff88040ba63044 (virt) @40ba63044 (dma) 0x000000 - ep_info2
>[    1.417550] xhci_hcd 0000:00:14.0: @ffff88040ba63048 (virt) @40ba63048 (dma) 0x000000 - deq
>[    1.417551] xhci_hcd 0000:00:14.0: @ffff88040ba63050 (virt) @40ba63050 (dma) 0x000000 - tx_info
>[    1.417553] xhci_hcd 0000:00:14.0: @ffff88040ba63054 (virt) @40ba63054 (dma) 0x000000 - rsvd[0]
>[    1.417554] xhci_hcd 0000:00:14.0: @ffff88040ba63058 (virt) @40ba63058 (dma) 0x000000 - rsvd[1]
>[    1.417555] xhci_hcd 0000:00:14.0: @ffff88040ba6305c (virt) @40ba6305c (dma) 0x000000 - rsvd[2]
>[    1.417556] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.417557] xhci_hcd 0000:00:14.0: @ffff88040ba63060 (virt) @40ba63060 (dma) 0x000000 - ep_info
>[    1.417559] xhci_hcd 0000:00:14.0: @ffff88040ba63064 (virt) @40ba63064 (dma) 0x000000 - ep_info2
>[    1.417560] xhci_hcd 0000:00:14.0: @ffff88040ba63068 (virt) @40ba63068 (dma) 0x000000 - deq
>[    1.417561] xhci_hcd 0000:00:14.0: @ffff88040ba63070 (virt) @40ba63070 (dma) 0x000000 - tx_info
>[    1.417562] xhci_hcd 0000:00:14.0: @ffff88040ba63074 (virt) @40ba63074 (dma) 0x000000 - rsvd[0]
>[    1.417564] xhci_hcd 0000:00:14.0: @ffff88040ba63078 (virt) @40ba63078 (dma) 0x000000 - rsvd[1]
>[    1.417565] xhci_hcd 0000:00:14.0: @ffff88040ba6307c (virt) @40ba6307c (dma) 0x000000 - rsvd[2]
>[    1.417566] xhci_hcd 0000:00:14.0: Internal device address = 2
>[    1.429206] usb 2-13: ep0 maxpacket = 8
>[    1.429212] xhci_hcd 0000:00:14.0: Max Packet Size for ep 0 changed.
>[    1.429214] xhci_hcd 0000:00:14.0: Max packet size in usb_device = 8
>[    1.429216] xhci_hcd 0000:00:14.0: Max packet size in xHCI HW = 64
>[    1.429218] xhci_hcd 0000:00:14.0: Issuing evaluate context command.
>[    1.429220] xhci_hcd 0000:00:14.0: Slot 1 input context
>[    1.429223] xhci_hcd 0000:00:14.0: @ffff88040ba64000 (virt) @40ba64000 (dma) 0x000000 - drop flags
>[    1.429225] xhci_hcd 0000:00:14.0: @ffff88040ba64004 (virt) @40ba64004 (dma) 0x000002 - add flags
>[    1.429227] xhci_hcd 0000:00:14.0: @ffff88040ba64008 (virt) @40ba64008 (dma) 0x000000 - rsvd2[0]
>[    1.429230] xhci_hcd 0000:00:14.0: @ffff88040ba6400c (virt) @40ba6400c (dma) 0x000000 - rsvd2[1]
>[    1.429232] xhci_hcd 0000:00:14.0: @ffff88040ba64010 (virt) @40ba64010 (dma) 0x000000 - rsvd2[2]
>[    1.429234] xhci_hcd 0000:00:14.0: @ffff88040ba64014 (virt) @40ba64014 (dma) 0x000000 - rsvd2[3]
>[    1.429236] xhci_hcd 0000:00:14.0: @ffff88040ba64018 (virt) @40ba64018 (dma) 0x000000 - rsvd2[4]
>[    1.429238] xhci_hcd 0000:00:14.0: @ffff88040ba6401c (virt) @40ba6401c (dma) 0x000000 - rsvd2[5]
>[    1.429240] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.429242] xhci_hcd 0000:00:14.0: @ffff88040ba64020 (virt) @40ba64020 (dma) 0x8100000 - dev_info
>[    1.429244] xhci_hcd 0000:00:14.0: @ffff88040ba64024 (virt) @40ba64024 (dma) 0x0d0000 - dev_info2
>[    1.429246] xhci_hcd 0000:00:14.0: @ffff88040ba64028 (virt) @40ba64028 (dma) 0x000000 - tt_info
>[    1.429248] xhci_hcd 0000:00:14.0: @ffff88040ba6402c (virt) @40ba6402c (dma) 0x000000 - dev_state
>[    1.429250] xhci_hcd 0000:00:14.0: @ffff88040ba64030 (virt) @40ba64030 (dma) 0x000000 - rsvd[0]
>[    1.429252] xhci_hcd 0000:00:14.0: @ffff88040ba64034 (virt) @40ba64034 (dma) 0x000000 - rsvd[1]
>[    1.429254] xhci_hcd 0000:00:14.0: @ffff88040ba64038 (virt) @40ba64038 (dma) 0x000000 - rsvd[2]
>[    1.429257] xhci_hcd 0000:00:14.0: @ffff88040ba6403c (virt) @40ba6403c (dma) 0x000000 - rsvd[3]
>[    1.429259] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.429261] xhci_hcd 0000:00:14.0: @ffff88040ba64040 (virt) @40ba64040 (dma) 0x000001 - ep_info
>[    1.429263] xhci_hcd 0000:00:14.0: @ffff88040ba64044 (virt) @40ba64044 (dma) 0x080026 - ep_info2
>[    1.429265] xhci_hcd 0000:00:14.0: @ffff88040ba64048 (virt) @40ba64048 (dma) 0x40beda801 - deq
>[    1.429267] xhci_hcd 0000:00:14.0: @ffff88040ba64050 (virt) @40ba64050 (dma) 0x000000 - tx_info
>[    1.429269] xhci_hcd 0000:00:14.0: @ffff88040ba64054 (virt) @40ba64054 (dma) 0x000000 - rsvd[0]
>[    1.429272] xhci_hcd 0000:00:14.0: @ffff88040ba64058 (virt) @40ba64058 (dma) 0x000000 - rsvd[1]
>[    1.429274] xhci_hcd 0000:00:14.0: @ffff88040ba6405c (virt) @40ba6405c (dma) 0x000000 - rsvd[2]
>[    1.429276] xhci_hcd 0000:00:14.0: Slot 1 output context
>[    1.429277] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.429279] xhci_hcd 0000:00:14.0: @ffff88040ba63000 (virt) @40ba63000 (dma) 0x8100000 - dev_info
>[    1.429281] xhci_hcd 0000:00:14.0: @ffff88040ba63004 (virt) @40ba63004 (dma) 0x0d0000 - dev_info2
>[    1.429283] xhci_hcd 0000:00:14.0: @ffff88040ba63008 (virt) @40ba63008 (dma) 0x000000 - tt_info
>[    1.429286] xhci_hcd 0000:00:14.0: @ffff88040ba6300c (virt) @40ba6300c (dma) 0x10000001 - dev_state
>[    1.429288] xhci_hcd 0000:00:14.0: @ffff88040ba63010 (virt) @40ba63010 (dma) 0x000000 - rsvd[0]
>[    1.429290] xhci_hcd 0000:00:14.0: @ffff88040ba63014 (virt) @40ba63014 (dma) 0x000000 - rsvd[1]
>[    1.429292] xhci_hcd 0000:00:14.0: @ffff88040ba63018 (virt) @40ba63018 (dma) 0x000000 - rsvd[2]
>[    1.429294] xhci_hcd 0000:00:14.0: @ffff88040ba6301c (virt) @40ba6301c (dma) 0x000000 - rsvd[3]
>[    1.429296] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.429298] xhci_hcd 0000:00:14.0: @ffff88040ba63020 (virt) @40ba63020 (dma) 0x000001 - ep_info
>[    1.429300] xhci_hcd 0000:00:14.0: @ffff88040ba63024 (virt) @40ba63024 (dma) 0x400026 - ep_info2
>[    1.429302] xhci_hcd 0000:00:14.0: @ffff88040ba63028 (virt) @40ba63028 (dma) 0x40beda801 - deq
>[    1.429304] xhci_hcd 0000:00:14.0: @ffff88040ba63030 (virt) @40ba63030 (dma) 0x000000 - tx_info
>[    1.429306] xhci_hcd 0000:00:14.0: @ffff88040ba63034 (virt) @40ba63034 (dma) 0x000000 - rsvd[0]
>[    1.429309] xhci_hcd 0000:00:14.0: @ffff88040ba63038 (virt) @40ba63038 (dma) 0x000000 - rsvd[1]
>[    1.429311] xhci_hcd 0000:00:14.0: @ffff88040ba6303c (virt) @40ba6303c (dma) 0x000000 - rsvd[2]
>[    1.429313] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.429332] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.437551] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.437594] usb 2-13: default language 0x0409
>[    1.439664] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.441172] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.441220] usb 2-13: udev 2, busnum 2, minor = 129
>[    1.441224] usb 2-13: New USB device found, idVendor=04a9, idProduct=2206
>[    1.441227] usb 2-13: New USB device strings: Mfr=64, Product=77, SerialNumber=0
>[    1.441230] usb 2-13: Product: CanoScan
>[    1.441232] usb 2-13: Manufacturer: Canon
>[    1.441346] usb 2-13: usb_probe_device
>[    1.441349] usb 2-13: configuration #1 chosen from 1 choice
>[    1.441355] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 1, new drop flags = 0x0, new add flags = 0x9, new slot info = 0x18100000
>[    1.441360] xhci_hcd 0000:00:14.0: add ep 0x82, slot id 1, new drop flags = 0x0, new add flags = 0x29, new slot info = 0x28100000
>[    1.441363] xhci_hcd 0000:00:14.0: add ep 0x3, slot id 1, new drop flags = 0x0, new add flags = 0x69, new slot info = 0x30100000
>[    1.441366] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040bba5000
>[    1.441367] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.441370] xhci_hcd 0000:00:14.0: @ffff88040ba64000 (virt) @40ba64000 (dma) 0x000000 - drop flags
>[    1.441372] xhci_hcd 0000:00:14.0: @ffff88040ba64004 (virt) @40ba64004 (dma) 0x000069 - add flags
>[    1.441374] xhci_hcd 0000:00:14.0: @ffff88040ba64008 (virt) @40ba64008 (dma) 0x000000 - rsvd2[0]
>[    1.441376] xhci_hcd 0000:00:14.0: @ffff88040ba6400c (virt) @40ba6400c (dma) 0x000000 - rsvd2[1]
>[    1.441379] xhci_hcd 0000:00:14.0: @ffff88040ba64010 (virt) @40ba64010 (dma) 0x000000 - rsvd2[2]
>[    1.441381] xhci_hcd 0000:00:14.0: @ffff88040ba64014 (virt) @40ba64014 (dma) 0x000000 - rsvd2[3]
>[    1.441383] xhci_hcd 0000:00:14.0: @ffff88040ba64018 (virt) @40ba64018 (dma) 0x000000 - rsvd2[4]
>[    1.441385] xhci_hcd 0000:00:14.0: @ffff88040ba6401c (virt) @40ba6401c (dma) 0x000000 - rsvd2[5]
>[    1.441387] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.441389] xhci_hcd 0000:00:14.0: @ffff88040ba64020 (virt) @40ba64020 (dma) 0x30100000 - dev_info
>[    1.441391] xhci_hcd 0000:00:14.0: @ffff88040ba64024 (virt) @40ba64024 (dma) 0x0d0000 - dev_info2
>[    1.441394] xhci_hcd 0000:00:14.0: @ffff88040ba64028 (virt) @40ba64028 (dma) 0x000000 - tt_info
>[    1.441396] xhci_hcd 0000:00:14.0: @ffff88040ba6402c (virt) @40ba6402c (dma) 0x000000 - dev_state
>[    1.441399] xhci_hcd 0000:00:14.0: @ffff88040ba64030 (virt) @40ba64030 (dma) 0x000000 - rsvd[0]
>[    1.441401] xhci_hcd 0000:00:14.0: @ffff88040ba64034 (virt) @40ba64034 (dma) 0x000000 - rsvd[1]
>[    1.441403] xhci_hcd 0000:00:14.0: @ffff88040ba64038 (virt) @40ba64038 (dma) 0x000000 - rsvd[2]
>[    1.441406] xhci_hcd 0000:00:14.0: @ffff88040ba6403c (virt) @40ba6403c (dma) 0x000000 - rsvd[3]
>[    1.441408] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.441410] xhci_hcd 0000:00:14.0: @ffff88040ba64040 (virt) @40ba64040 (dma) 0x000001 - ep_info
>[    1.441412] xhci_hcd 0000:00:14.0: @ffff88040ba64044 (virt) @40ba64044 (dma) 0x080026 - ep_info2
>[    1.441414] xhci_hcd 0000:00:14.0: @ffff88040ba64048 (virt) @40ba64048 (dma) 0x40beda801 - deq
>[    1.441416] xhci_hcd 0000:00:14.0: @ffff88040ba64050 (virt) @40ba64050 (dma) 0x000000 - tx_info
>[    1.441419] xhci_hcd 0000:00:14.0: @ffff88040ba64054 (virt) @40ba64054 (dma) 0x000000 - rsvd[0]
>[    1.441421] xhci_hcd 0000:00:14.0: @ffff88040ba64058 (virt) @40ba64058 (dma) 0x000000 - rsvd[1]
>[    1.441423] xhci_hcd 0000:00:14.0: @ffff88040ba6405c (virt) @40ba6405c (dma) 0x000000 - rsvd[2]
>[    1.441425] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.441427] xhci_hcd 0000:00:14.0: @ffff88040ba64060 (virt) @40ba64060 (dma) 0x000000 - ep_info
>[    1.441429] xhci_hcd 0000:00:14.0: @ffff88040ba64064 (virt) @40ba64064 (dma) 0x000000 - ep_info2
>[    1.441431] xhci_hcd 0000:00:14.0: @ffff88040ba64068 (virt) @40ba64068 (dma) 0x000000 - deq
>[    1.441433] xhci_hcd 0000:00:14.0: @ffff88040ba64070 (virt) @40ba64070 (dma) 0x000000 - tx_info
>[    1.441435] xhci_hcd 0000:00:14.0: @ffff88040ba64074 (virt) @40ba64074 (dma) 0x000000 - rsvd[0]
>[    1.441437] xhci_hcd 0000:00:14.0: @ffff88040ba64078 (virt) @40ba64078 (dma) 0x000000 - rsvd[1]
>[    1.441440] xhci_hcd 0000:00:14.0: @ffff88040ba6407c (virt) @40ba6407c (dma) 0x000000 - rsvd[2]
>[    1.441442] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.441444] xhci_hcd 0000:00:14.0: @ffff88040ba64080 (virt) @40ba64080 (dma) 0x070000 - ep_info
>[    1.441446] xhci_hcd 0000:00:14.0: @ffff88040ba64084 (virt) @40ba64084 (dma) 0x01003e - ep_info2
>[    1.441448] xhci_hcd 0000:00:14.0: @ffff88040ba64088 (virt) @40ba64088 (dma) 0x40ba65401 - deq
>[    1.441450] xhci_hcd 0000:00:14.0: @ffff88040ba64090 (virt) @40ba64090 (dma) 0x010001 - tx_info
>[    1.441452] xhci_hcd 0000:00:14.0: @ffff88040ba64094 (virt) @40ba64094 (dma) 0x000000 - rsvd[0]
>[    1.441454] xhci_hcd 0000:00:14.0: @ffff88040ba64098 (virt) @40ba64098 (dma) 0x000000 - rsvd[1]
>[    1.441456] xhci_hcd 0000:00:14.0: @ffff88040ba6409c (virt) @40ba6409c (dma) 0x000000 - rsvd[2]
>[    1.441458] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.441460] xhci_hcd 0000:00:14.0: @ffff88040ba640a0 (virt) @40ba640a0 (dma) 0x000000 - ep_info
>[    1.441462] xhci_hcd 0000:00:14.0: @ffff88040ba640a4 (virt) @40ba640a4 (dma) 0x000000 - ep_info2
>[    1.441465] xhci_hcd 0000:00:14.0: @ffff88040ba640a8 (virt) @40ba640a8 (dma) 0x000000 - deq
>[    1.441467] xhci_hcd 0000:00:14.0: @ffff88040ba640b0 (virt) @40ba640b0 (dma) 0x000000 - tx_info
>[    1.441469] xhci_hcd 0000:00:14.0: @ffff88040ba640b4 (virt) @40ba640b4 (dma) 0x000000 - rsvd[0]
>[    1.441471] xhci_hcd 0000:00:14.0: @ffff88040ba640b8 (virt) @40ba640b8 (dma) 0x000000 - rsvd[1]
>[    1.441473] xhci_hcd 0000:00:14.0: @ffff88040ba640bc (virt) @40ba640bc (dma) 0x000000 - rsvd[2]
>[    1.441475] xhci_hcd 0000:00:14.0: IN Endpoint 02 Context (ep_index 04):
>[    1.441477] xhci_hcd 0000:00:14.0: @ffff88040ba640c0 (virt) @40ba640c0 (dma) 0x000000 - ep_info
>[    1.441479] xhci_hcd 0000:00:14.0: @ffff88040ba640c4 (virt) @40ba640c4 (dma) 0x400036 - ep_info2
>[    1.441481] xhci_hcd 0000:00:14.0: @ffff88040ba640c8 (virt) @40ba640c8 (dma) 0x40b629001 - deq
>[    1.441483] xhci_hcd 0000:00:14.0: @ffff88040ba640d0 (virt) @40ba640d0 (dma) 0x000000 - tx_info
>[    1.441486] xhci_hcd 0000:00:14.0: @ffff88040ba640d4 (virt) @40ba640d4 (dma) 0x000000 - rsvd[0]
>[    1.441488] xhci_hcd 0000:00:14.0: @ffff88040ba640d8 (virt) @40ba640d8 (dma) 0x000000 - rsvd[1]
>[    1.441490] xhci_hcd 0000:00:14.0: @ffff88040ba640dc (virt) @40ba640dc (dma) 0x000000 - rsvd[2]
>[    1.441492] xhci_hcd 0000:00:14.0: OUT Endpoint 03 Context (ep_index 05):
>[    1.441494] xhci_hcd 0000:00:14.0: @ffff88040ba640e0 (virt) @40ba640e0 (dma) 0x000000 - ep_info
>[    1.441496] xhci_hcd 0000:00:14.0: @ffff88040ba640e4 (virt) @40ba640e4 (dma) 0x400016 - ep_info2
>[    1.441498] xhci_hcd 0000:00:14.0: @ffff88040ba640e8 (virt) @40ba640e8 (dma) 0x40b629801 - deq
>[    1.441500] xhci_hcd 0000:00:14.0: @ffff88040ba640f0 (virt) @40ba640f0 (dma) 0x000000 - tx_info
>[    1.441502] xhci_hcd 0000:00:14.0: @ffff88040ba640f4 (virt) @40ba640f4 (dma) 0x000000 - rsvd[0]
>[    1.441505] xhci_hcd 0000:00:14.0: @ffff88040ba640f8 (virt) @40ba640f8 (dma) 0x000000 - rsvd[1]
>[    1.441507] xhci_hcd 0000:00:14.0: @ffff88040ba640fc (virt) @40ba640fc (dma) 0x000000 - rsvd[2]
>[    1.441509] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.441654] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.441662] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.441663] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.441664] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.441666] xhci_hcd 0000:00:14.0: @ffff88040ba63000 (virt) @40ba63000 (dma) 0x30100000 - dev_info
>[    1.441667] xhci_hcd 0000:00:14.0: @ffff88040ba63004 (virt) @40ba63004 (dma) 0x0d0000 - dev_info2
>[    1.441669] xhci_hcd 0000:00:14.0: @ffff88040ba63008 (virt) @40ba63008 (dma) 0x000000 - tt_info
>[    1.441670] xhci_hcd 0000:00:14.0: @ffff88040ba6300c (virt) @40ba6300c (dma) 0x18000001 - dev_state
>[    1.441672] xhci_hcd 0000:00:14.0: @ffff88040ba63010 (virt) @40ba63010 (dma) 0x000000 - rsvd[0]
>[    1.441673] xhci_hcd 0000:00:14.0: @ffff88040ba63014 (virt) @40ba63014 (dma) 0x000000 - rsvd[1]
>[    1.441675] xhci_hcd 0000:00:14.0: @ffff88040ba63018 (virt) @40ba63018 (dma) 0x000000 - rsvd[2]
>[    1.441676] xhci_hcd 0000:00:14.0: @ffff88040ba6301c (virt) @40ba6301c (dma) 0x000000 - rsvd[3]
>[    1.441678] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.441679] xhci_hcd 0000:00:14.0: @ffff88040ba63020 (virt) @40ba63020 (dma) 0x000001 - ep_info
>[    1.441681] xhci_hcd 0000:00:14.0: @ffff88040ba63024 (virt) @40ba63024 (dma) 0x080026 - ep_info2
>[    1.441682] xhci_hcd 0000:00:14.0: @ffff88040ba63028 (virt) @40ba63028 (dma) 0x40beda831 - deq
>[    1.441683] xhci_hcd 0000:00:14.0: @ffff88040ba63030 (virt) @40ba63030 (dma) 0x000000 - tx_info
>[    1.441685] xhci_hcd 0000:00:14.0: @ffff88040ba63034 (virt) @40ba63034 (dma) 0x000000 - rsvd[0]
>[    1.441686] xhci_hcd 0000:00:14.0: @ffff88040ba63038 (virt) @40ba63038 (dma) 0x000000 - rsvd[1]
>[    1.441688] xhci_hcd 0000:00:14.0: @ffff88040ba6303c (virt) @40ba6303c (dma) 0x000000 - rsvd[2]
>[    1.441689] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.441691] xhci_hcd 0000:00:14.0: @ffff88040ba63040 (virt) @40ba63040 (dma) 0x000000 - ep_info
>[    1.441692] xhci_hcd 0000:00:14.0: @ffff88040ba63044 (virt) @40ba63044 (dma) 0x000000 - ep_info2
>[    1.441693] xhci_hcd 0000:00:14.0: @ffff88040ba63048 (virt) @40ba63048 (dma) 0x000000 - deq
>[    1.441695] xhci_hcd 0000:00:14.0: @ffff88040ba63050 (virt) @40ba63050 (dma) 0x000000 - tx_info
>[    1.441697] xhci_hcd 0000:00:14.0: @ffff88040ba63054 (virt) @40ba63054 (dma) 0x000000 - rsvd[0]
>[    1.441698] xhci_hcd 0000:00:14.0: @ffff88040ba63058 (virt) @40ba63058 (dma) 0x000000 - rsvd[1]
>[    1.441700] xhci_hcd 0000:00:14.0: @ffff88040ba6305c (virt) @40ba6305c (dma) 0x000000 - rsvd[2]
>[    1.441701] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.441702] xhci_hcd 0000:00:14.0: @ffff88040ba63060 (virt) @40ba63060 (dma) 0x070001 - ep_info
>[    1.441704] xhci_hcd 0000:00:14.0: @ffff88040ba63064 (virt) @40ba63064 (dma) 0x01003e - ep_info2
>[    1.441705] xhci_hcd 0000:00:14.0: @ffff88040ba63068 (virt) @40ba63068 (dma) 0x40ba65401 - deq
>[    1.441707] xhci_hcd 0000:00:14.0: @ffff88040ba63070 (virt) @40ba63070 (dma) 0x010001 - tx_info
>[    1.441708] xhci_hcd 0000:00:14.0: @ffff88040ba63074 (virt) @40ba63074 (dma) 0x000000 - rsvd[0]
>[    1.441710] xhci_hcd 0000:00:14.0: @ffff88040ba63078 (virt) @40ba63078 (dma) 0x000000 - rsvd[1]
>[    1.441711] xhci_hcd 0000:00:14.0: @ffff88040ba6307c (virt) @40ba6307c (dma) 0x000000 - rsvd[2]
>[    1.441712] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.441714] xhci_hcd 0000:00:14.0: @ffff88040ba63080 (virt) @40ba63080 (dma) 0x000000 - ep_info
>[    1.441715] xhci_hcd 0000:00:14.0: @ffff88040ba63084 (virt) @40ba63084 (dma) 0x000000 - ep_info2
>[    1.441716] xhci_hcd 0000:00:14.0: @ffff88040ba63088 (virt) @40ba63088 (dma) 0x000000 - deq
>[    1.441718] xhci_hcd 0000:00:14.0: @ffff88040ba63090 (virt) @40ba63090 (dma) 0x000000 - tx_info
>[    1.441719] xhci_hcd 0000:00:14.0: @ffff88040ba63094 (virt) @40ba63094 (dma) 0x000000 - rsvd[0]
>[    1.441721] xhci_hcd 0000:00:14.0: @ffff88040ba63098 (virt) @40ba63098 (dma) 0x000000 - rsvd[1]
>[    1.441722] xhci_hcd 0000:00:14.0: @ffff88040ba6309c (virt) @40ba6309c (dma) 0x000000 - rsvd[2]
>[    1.441723] xhci_hcd 0000:00:14.0: IN Endpoint 02 Context (ep_index 04):
>[    1.441725] xhci_hcd 0000:00:14.0: @ffff88040ba630a0 (virt) @40ba630a0 (dma) 0x000001 - ep_info
>[    1.441726] xhci_hcd 0000:00:14.0: @ffff88040ba630a4 (virt) @40ba630a4 (dma) 0x400036 - ep_info2
>[    1.441728] xhci_hcd 0000:00:14.0: @ffff88040ba630a8 (virt) @40ba630a8 (dma) 0x40b629001 - deq
>[    1.441729] xhci_hcd 0000:00:14.0: @ffff88040ba630b0 (virt) @40ba630b0 (dma) 0x000000 - tx_info
>[    1.441731] xhci_hcd 0000:00:14.0: @ffff88040ba630b4 (virt) @40ba630b4 (dma) 0x000000 - rsvd[0]
>[    1.441732] xhci_hcd 0000:00:14.0: @ffff88040ba630b8 (virt) @40ba630b8 (dma) 0x000000 - rsvd[1]
>[    1.441734] xhci_hcd 0000:00:14.0: @ffff88040ba630bc (virt) @40ba630bc (dma) 0x000000 - rsvd[2]
>[    1.441735] xhci_hcd 0000:00:14.0: OUT Endpoint 03 Context (ep_index 05):
>[    1.441736] xhci_hcd 0000:00:14.0: @ffff88040ba630c0 (virt) @40ba630c0 (dma) 0x000001 - ep_info
>[    1.441738] xhci_hcd 0000:00:14.0: @ffff88040ba630c4 (virt) @40ba630c4 (dma) 0x400016 - ep_info2
>[    1.441739] xhci_hcd 0000:00:14.0: @ffff88040ba630c8 (virt) @40ba630c8 (dma) 0x40b629801 - deq
>[    1.441741] xhci_hcd 0000:00:14.0: @ffff88040ba630d0 (virt) @40ba630d0 (dma) 0x000000 - tx_info
>[    1.441742] xhci_hcd 0000:00:14.0: @ffff88040ba630d4 (virt) @40ba630d4 (dma) 0x000000 - rsvd[0]
>[    1.441744] xhci_hcd 0000:00:14.0: @ffff88040ba630d8 (virt) @40ba630d8 (dma) 0x000000 - rsvd[1]
>[    1.441745] xhci_hcd 0000:00:14.0: @ffff88040ba630dc (virt) @40ba630dc (dma) 0x000000 - rsvd[2]
>[    1.441749] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.441750] xhci_hcd 0000:00:14.0: Endpoint 0x82 not halted, refusing to reset.
>[    1.441751] xhci_hcd 0000:00:14.0: Endpoint 0x3 not halted, refusing to reset.
>[    1.441814] usb 2-13: adding 2-13:1.0 (config #1, interface 0)
>[    1.441906] xhci_hcd 0000:00:14.0: get port status, actual port 13 status  = 0x6e1
>[    1.441908] xhci_hcd 0000:00:14.0: Get port status returned 0x101
>[    1.441919] hub 2-0:1.0: port 14, status 0101, change 0000, 12 Mb/s
>[    1.441922] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.441940] xhci_hcd 0000:00:14.0: Slot 2 output ctx = 0x40c696000 (dma)
>[    1.441943] xhci_hcd 0000:00:14.0: Slot 2 input ctx = 0x40b5b8000 (dma)
>[    1.441945] xhci_hcd 0000:00:14.0: Set slot id 2 dcbaa entry ffff88040bed9010 to 0x40c696000
>[    1.441951] xhci_hcd 0000:00:14.0: set port reset, actual port 13 status  = 0x791
>[    1.480079] xhci_hcd 0000:00:14.0: xhci_hub_status_data: stopping port polling.
>[    1.492070] xhci_hcd 0000:00:14.0: get port status, actual port 13 status  = 0xf91
>[    1.492072] xhci_hcd 0000:00:14.0: Get port status returned 0x511
>[    1.492097] hub 2-0:1.0: port 14 not reset yet, waiting 50ms
>[    1.497086] xhci_hcd 0000:00:14.0: Port Status Change Event for port 14
>[    1.497090] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    1.507354] systemd-udevd[1704]: starting version 208
>[    1.543058] xhci_hcd 0000:00:14.0: get port status, actual port 13 status  = 0x200e03
>[    1.543062] xhci_hcd 0000:00:14.0: Get port status returned 0x100503
>[    1.555396] iTCO_vendor_support: vendor-support=0
>[    1.555840] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.10
>[    1.555893] iTCO_wdt: Found a Lynx Point TCO device (Version=2, TCOBASE=0x1860)
>[    1.556536] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>[    1.559427] ACPI Warning: 0x000000000000f000-0x000000000000f01f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130725/utaddress-251)
>[    1.559434] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    1.576147] systemd-udevd[1726]: renamed network interface eth1 to enp6s0
>[    1.581127] systemd-udevd[1723]: renamed network interface eth0 to enp5s0
>[    1.595036] xhci_hcd 0000:00:14.0: clear port reset change, actual port 13 status  = 0xe03
>[    1.595060] usb 2-14: new high-speed USB device number 3 using xhci_hcd
>[    1.595063] xhci_hcd 0000:00:14.0: Set root hub portnum to 14
>[    1.595065] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 14
>[    1.595066] xhci_hcd 0000:00:14.0: udev->tt =           (null)
>[    1.595068] xhci_hcd 0000:00:14.0: udev->ttport = 0x0
>[    1.595069] xhci_hcd 0000:00:14.0: Slot ID 2 Input Context:
>[    1.595071] xhci_hcd 0000:00:14.0: @ffff88040b5b8000 (virt) @40b5b8000 (dma) 0x000000 - drop flags
>[    1.595073] xhci_hcd 0000:00:14.0: @ffff88040b5b8004 (virt) @40b5b8004 (dma) 0x000003 - add flags
>[    1.595075] xhci_hcd 0000:00:14.0: @ffff88040b5b8008 (virt) @40b5b8008 (dma) 0x000000 - rsvd2[0]
>[    1.595076] xhci_hcd 0000:00:14.0: @ffff88040b5b800c (virt) @40b5b800c (dma) 0x000000 - rsvd2[1]
>[    1.595077] xhci_hcd 0000:00:14.0: @ffff88040b5b8010 (virt) @40b5b8010 (dma) 0x000000 - rsvd2[2]
>[    1.595079] xhci_hcd 0000:00:14.0: @ffff88040b5b8014 (virt) @40b5b8014 (dma) 0x000000 - rsvd2[3]
>[    1.595080] xhci_hcd 0000:00:14.0: @ffff88040b5b8018 (virt) @40b5b8018 (dma) 0x000000 - rsvd2[4]
>[    1.595081] xhci_hcd 0000:00:14.0: @ffff88040b5b801c (virt) @40b5b801c (dma) 0x000000 - rsvd2[5]
>[    1.595083] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.595084] xhci_hcd 0000:00:14.0: @ffff88040b5b8020 (virt) @40b5b8020 (dma) 0x8300000 - dev_info
>[    1.595085] xhci_hcd 0000:00:14.0: @ffff88040b5b8024 (virt) @40b5b8024 (dma) 0x0e0000 - dev_info2
>[    1.595087] xhci_hcd 0000:00:14.0: @ffff88040b5b8028 (virt) @40b5b8028 (dma) 0x000000 - tt_info
>[    1.595088] xhci_hcd 0000:00:14.0: @ffff88040b5b802c (virt) @40b5b802c (dma) 0x000000 - dev_state
>[    1.595090] xhci_hcd 0000:00:14.0: @ffff88040b5b8030 (virt) @40b5b8030 (dma) 0x000000 - rsvd[0]
>[    1.595091] xhci_hcd 0000:00:14.0: @ffff88040b5b8034 (virt) @40b5b8034 (dma) 0x000000 - rsvd[1]
>[    1.595092] xhci_hcd 0000:00:14.0: @ffff88040b5b8038 (virt) @40b5b8038 (dma) 0x000000 - rsvd[2]
>[    1.595094] xhci_hcd 0000:00:14.0: @ffff88040b5b803c (virt) @40b5b803c (dma) 0x000000 - rsvd[3]
>[    1.595096] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.595097] xhci_hcd 0000:00:14.0: @ffff88040b5b8040 (virt) @40b5b8040 (dma) 0x000000 - ep_info
>[    1.595098] xhci_hcd 0000:00:14.0: @ffff88040b5b8044 (virt) @40b5b8044 (dma) 0x400026 - ep_info2
>[    1.595100] xhci_hcd 0000:00:14.0: @ffff88040b5b8048 (virt) @40b5b8048 (dma) 0x40b62a401 - deq
>[    1.595101] xhci_hcd 0000:00:14.0: @ffff88040b5b8050 (virt) @40b5b8050 (dma) 0x000000 - tx_info
>[    1.595103] xhci_hcd 0000:00:14.0: @ffff88040b5b8054 (virt) @40b5b8054 (dma) 0x000000 - rsvd[0]
>[    1.595104] xhci_hcd 0000:00:14.0: @ffff88040b5b8058 (virt) @40b5b8058 (dma) 0x000000 - rsvd[1]
>[    1.595105] xhci_hcd 0000:00:14.0: @ffff88040b5b805c (virt) @40b5b805c (dma) 0x000000 - rsvd[2]
>[    1.595107] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.595108] xhci_hcd 0000:00:14.0: @ffff88040b5b8060 (virt) @40b5b8060 (dma) 0x000000 - ep_info
>[    1.595110] xhci_hcd 0000:00:14.0: @ffff88040b5b8064 (virt) @40b5b8064 (dma) 0x000000 - ep_info2
>[    1.595111] xhci_hcd 0000:00:14.0: @ffff88040b5b8068 (virt) @40b5b8068 (dma) 0x000000 - deq
>[    1.595113] xhci_hcd 0000:00:14.0: @ffff88040b5b8070 (virt) @40b5b8070 (dma) 0x000000 - tx_info
>[    1.595114] xhci_hcd 0000:00:14.0: @ffff88040b5b8074 (virt) @40b5b8074 (dma) 0x000000 - rsvd[0]
>[    1.595116] xhci_hcd 0000:00:14.0: @ffff88040b5b8078 (virt) @40b5b8078 (dma) 0x000000 - rsvd[1]
>[    1.595117] xhci_hcd 0000:00:14.0: @ffff88040b5b807c (virt) @40b5b807c (dma) 0x000000 - rsvd[2]
>[    1.595118] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.595120] xhci_hcd 0000:00:14.0: @ffff88040b5b8080 (virt) @40b5b8080 (dma) 0x000000 - ep_info
>[    1.595122] xhci_hcd 0000:00:14.0: @ffff88040b5b8084 (virt) @40b5b8084 (dma) 0x000000 - ep_info2
>[    1.595124] xhci_hcd 0000:00:14.0: @ffff88040b5b8088 (virt) @40b5b8088 (dma) 0x000000 - deq
>[    1.595126] xhci_hcd 0000:00:14.0: @ffff88040b5b8090 (virt) @40b5b8090 (dma) 0x000000 - tx_info
>[    1.595128] xhci_hcd 0000:00:14.0: @ffff88040b5b8094 (virt) @40b5b8094 (dma) 0x000000 - rsvd[0]
>[    1.595130] xhci_hcd 0000:00:14.0: @ffff88040b5b8098 (virt) @40b5b8098 (dma) 0x000000 - rsvd[1]
>[    1.595133] xhci_hcd 0000:00:14.0: @ffff88040b5b809c (virt) @40b5b809c (dma) 0x000000 - rsvd[2]
>[    1.595135] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.595354] xhci_hcd 0000:00:14.0: Successful Address Device command
>[    1.595357] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[    1.595359] xhci_hcd 0000:00:14.0: Slot ID 2 dcbaa entry @ffff88040bed9010 = 0x0000040c696000
>[    1.595360] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40c696000
>[    1.595361] xhci_hcd 0000:00:14.0: Slot ID 2 Input Context:
>[    1.595363] xhci_hcd 0000:00:14.0: @ffff88040b5b8000 (virt) @40b5b8000 (dma) 0x000000 - drop flags
>[    1.595364] xhci_hcd 0000:00:14.0: @ffff88040b5b8004 (virt) @40b5b8004 (dma) 0x000003 - add flags
>[    1.595366] xhci_hcd 0000:00:14.0: @ffff88040b5b8008 (virt) @40b5b8008 (dma) 0x000000 - rsvd2[0]
>[    1.595367] xhci_hcd 0000:00:14.0: @ffff88040b5b800c (virt) @40b5b800c (dma) 0x000000 - rsvd2[1]
>[    1.595369] xhci_hcd 0000:00:14.0: @ffff88040b5b8010 (virt) @40b5b8010 (dma) 0x000000 - rsvd2[2]
>[    1.595370] xhci_hcd 0000:00:14.0: @ffff88040b5b8014 (virt) @40b5b8014 (dma) 0x000000 - rsvd2[3]
>[    1.595371] xhci_hcd 0000:00:14.0: @ffff88040b5b8018 (virt) @40b5b8018 (dma) 0x000000 - rsvd2[4]
>[    1.595373] xhci_hcd 0000:00:14.0: @ffff88040b5b801c (virt) @40b5b801c (dma) 0x000000 - rsvd2[5]
>[    1.595374] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.595375] xhci_hcd 0000:00:14.0: @ffff88040b5b8020 (virt) @40b5b8020 (dma) 0x8300000 - dev_info
>[    1.595377] xhci_hcd 0000:00:14.0: @ffff88040b5b8024 (virt) @40b5b8024 (dma) 0x0e0000 - dev_info2
>[    1.595378] xhci_hcd 0000:00:14.0: @ffff88040b5b8028 (virt) @40b5b8028 (dma) 0x000000 - tt_info
>[    1.595380] xhci_hcd 0000:00:14.0: @ffff88040b5b802c (virt) @40b5b802c (dma) 0x000000 - dev_state
>[    1.595381] xhci_hcd 0000:00:14.0: @ffff88040b5b8030 (virt) @40b5b8030 (dma) 0x000000 - rsvd[0]
>[    1.595382] xhci_hcd 0000:00:14.0: @ffff88040b5b8034 (virt) @40b5b8034 (dma) 0x000000 - rsvd[1]
>[    1.595384] xhci_hcd 0000:00:14.0: @ffff88040b5b8038 (virt) @40b5b8038 (dma) 0x000000 - rsvd[2]
>[    1.595385] xhci_hcd 0000:00:14.0: @ffff88040b5b803c (virt) @40b5b803c (dma) 0x000000 - rsvd[3]
>[    1.595387] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.595388] xhci_hcd 0000:00:14.0: @ffff88040b5b8040 (virt) @40b5b8040 (dma) 0x000000 - ep_info
>[    1.595389] xhci_hcd 0000:00:14.0: @ffff88040b5b8044 (virt) @40b5b8044 (dma) 0x400026 - ep_info2
>[    1.595391] xhci_hcd 0000:00:14.0: @ffff88040b5b8048 (virt) @40b5b8048 (dma) 0x40b62a401 - deq
>[    1.595392] xhci_hcd 0000:00:14.0: @ffff88040b5b8050 (virt) @40b5b8050 (dma) 0x000000 - tx_info
>[    1.595393] xhci_hcd 0000:00:14.0: @ffff88040b5b8054 (virt) @40b5b8054 (dma) 0x000000 - rsvd[0]
>[    1.595395] xhci_hcd 0000:00:14.0: @ffff88040b5b8058 (virt) @40b5b8058 (dma) 0x000000 - rsvd[1]
>[    1.595396] xhci_hcd 0000:00:14.0: @ffff88040b5b805c (virt) @40b5b805c (dma) 0x000000 - rsvd[2]
>[    1.595398] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.595399] xhci_hcd 0000:00:14.0: @ffff88040b5b8060 (virt) @40b5b8060 (dma) 0x000000 - ep_info
>[    1.595400] xhci_hcd 0000:00:14.0: @ffff88040b5b8064 (virt) @40b5b8064 (dma) 0x000000 - ep_info2
>[    1.595402] xhci_hcd 0000:00:14.0: @ffff88040b5b8068 (virt) @40b5b8068 (dma) 0x000000 - deq
>[    1.595403] xhci_hcd 0000:00:14.0: @ffff88040b5b8070 (virt) @40b5b8070 (dma) 0x000000 - tx_info
>[    1.595404] xhci_hcd 0000:00:14.0: @ffff88040b5b8074 (virt) @40b5b8074 (dma) 0x000000 - rsvd[0]
>[    1.595406] xhci_hcd 0000:00:14.0: @ffff88040b5b8078 (virt) @40b5b8078 (dma) 0x000000 - rsvd[1]
>[    1.595407] xhci_hcd 0000:00:14.0: @ffff88040b5b807c (virt) @40b5b807c (dma) 0x000000 - rsvd[2]
>[    1.595408] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.595410] xhci_hcd 0000:00:14.0: @ffff88040b5b8080 (virt) @40b5b8080 (dma) 0x000000 - ep_info
>[    1.595411] xhci_hcd 0000:00:14.0: @ffff88040b5b8084 (virt) @40b5b8084 (dma) 0x000000 - ep_info2
>[    1.595412] xhci_hcd 0000:00:14.0: @ffff88040b5b8088 (virt) @40b5b8088 (dma) 0x000000 - deq
>[    1.595414] xhci_hcd 0000:00:14.0: @ffff88040b5b8090 (virt) @40b5b8090 (dma) 0x000000 - tx_info
>[    1.595415] xhci_hcd 0000:00:14.0: @ffff88040b5b8094 (virt) @40b5b8094 (dma) 0x000000 - rsvd[0]
>[    1.595416] xhci_hcd 0000:00:14.0: @ffff88040b5b8098 (virt) @40b5b8098 (dma) 0x000000 - rsvd[1]
>[    1.595418] xhci_hcd 0000:00:14.0: @ffff88040b5b809c (virt) @40b5b809c (dma) 0x000000 - rsvd[2]
>[    1.595419] xhci_hcd 0000:00:14.0: Slot ID 2 Output Context:
>[    1.595420] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.595422] xhci_hcd 0000:00:14.0: @ffff88040c696000 (virt) @40c696000 (dma) 0x8300000 - dev_info
>[    1.595423] xhci_hcd 0000:00:14.0: @ffff88040c696004 (virt) @40c696004 (dma) 0x0e0000 - dev_info2
>[    1.595425] xhci_hcd 0000:00:14.0: @ffff88040c696008 (virt) @40c696008 (dma) 0x000000 - tt_info
>[    1.595426] xhci_hcd 0000:00:14.0: @ffff88040c69600c (virt) @40c69600c (dma) 0x10000002 - dev_state
>[    1.595427] xhci_hcd 0000:00:14.0: @ffff88040c696010 (virt) @40c696010 (dma) 0x000000 - rsvd[0]
>[    1.595429] xhci_hcd 0000:00:14.0: @ffff88040c696014 (virt) @40c696014 (dma) 0x000000 - rsvd[1]
>[    1.595431] xhci_hcd 0000:00:14.0: @ffff88040c696018 (virt) @40c696018 (dma) 0x000000 - rsvd[2]
>[    1.595433] xhci_hcd 0000:00:14.0: @ffff88040c69601c (virt) @40c69601c (dma) 0x000000 - rsvd[3]
>[    1.595436] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.595438] xhci_hcd 0000:00:14.0: @ffff88040c696020 (virt) @40c696020 (dma) 0x000001 - ep_info
>[    1.595440] xhci_hcd 0000:00:14.0: @ffff88040c696024 (virt) @40c696024 (dma) 0x400026 - ep_info2
>[    1.595442] xhci_hcd 0000:00:14.0: @ffff88040c696028 (virt) @40c696028 (dma) 0x40b62a401 - deq
>[    1.595444] xhci_hcd 0000:00:14.0: @ffff88040c696030 (virt) @40c696030 (dma) 0x000000 - tx_info
>[    1.595446] xhci_hcd 0000:00:14.0: @ffff88040c696034 (virt) @40c696034 (dma) 0x000000 - rsvd[0]
>[    1.595448] xhci_hcd 0000:00:14.0: @ffff88040c696038 (virt) @40c696038 (dma) 0x000000 - rsvd[1]
>[    1.595451] xhci_hcd 0000:00:14.0: @ffff88040c69603c (virt) @40c69603c (dma) 0x000000 - rsvd[2]
>[    1.595453] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.595455] xhci_hcd 0000:00:14.0: @ffff88040c696040 (virt) @40c696040 (dma) 0x000000 - ep_info
>[    1.595457] xhci_hcd 0000:00:14.0: @ffff88040c696044 (virt) @40c696044 (dma) 0x000000 - ep_info2
>[    1.595459] xhci_hcd 0000:00:14.0: @ffff88040c696048 (virt) @40c696048 (dma) 0x000000 - deq
>[    1.595460] xhci_hcd 0000:00:14.0: @ffff88040c696050 (virt) @40c696050 (dma) 0x000000 - tx_info
>[    1.595462] xhci_hcd 0000:00:14.0: @ffff88040c696054 (virt) @40c696054 (dma) 0x000000 - rsvd[0]
>[    1.595463] xhci_hcd 0000:00:14.0: @ffff88040c696058 (virt) @40c696058 (dma) 0x000000 - rsvd[1]
>[    1.595464] xhci_hcd 0000:00:14.0: @ffff88040c69605c (virt) @40c69605c (dma) 0x000000 - rsvd[2]
>[    1.595466] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.595467] xhci_hcd 0000:00:14.0: @ffff88040c696060 (virt) @40c696060 (dma) 0x000000 - ep_info
>[    1.595468] xhci_hcd 0000:00:14.0: @ffff88040c696064 (virt) @40c696064 (dma) 0x000000 - ep_info2
>[    1.595470] xhci_hcd 0000:00:14.0: @ffff88040c696068 (virt) @40c696068 (dma) 0x000000 - deq
>[    1.595471] xhci_hcd 0000:00:14.0: @ffff88040c696070 (virt) @40c696070 (dma) 0x000000 - tx_info
>[    1.595472] xhci_hcd 0000:00:14.0: @ffff88040c696074 (virt) @40c696074 (dma) 0x000000 - rsvd[0]
>[    1.595474] xhci_hcd 0000:00:14.0: @ffff88040c696078 (virt) @40c696078 (dma) 0x000000 - rsvd[1]
>[    1.595475] xhci_hcd 0000:00:14.0: @ffff88040c69607c (virt) @40c69607c (dma) 0x000000 - rsvd[2]
>[    1.595477] xhci_hcd 0000:00:14.0: Internal device address = 3
>[    1.607148] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.607164] usb 2-14: default language 0x0409
>[    1.607436] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.607451] usb 2-14: udev 3, busnum 2, minor = 130
>[    1.607453] usb 2-14: New USB device found, idVendor=05e3, idProduct=0610
>[    1.607455] usb 2-14: New USB device strings: Mfr=0, Product=1, SerialNumber=0
>[    1.607457] usb 2-14: Product: USB2.0 Hub
>[    1.607522] usb 2-14: usb_probe_device
>[    1.607524] usb 2-14: configuration #1 chosen from 1 choice
>[    1.607530] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 2, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x18300000
>[    1.607532] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040ba8a000
>[    1.607533] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.607535] xhci_hcd 0000:00:14.0: @ffff88040b5b8000 (virt) @40b5b8000 (dma) 0x000000 - drop flags
>[    1.607536] xhci_hcd 0000:00:14.0: @ffff88040b5b8004 (virt) @40b5b8004 (dma) 0x000009 - add flags
>[    1.607538] xhci_hcd 0000:00:14.0: @ffff88040b5b8008 (virt) @40b5b8008 (dma) 0x000000 - rsvd2[0]
>[    1.607540] xhci_hcd 0000:00:14.0: @ffff88040b5b800c (virt) @40b5b800c (dma) 0x000000 - rsvd2[1]
>[    1.607541] xhci_hcd 0000:00:14.0: @ffff88040b5b8010 (virt) @40b5b8010 (dma) 0x000000 - rsvd2[2]
>[    1.607542] xhci_hcd 0000:00:14.0: @ffff88040b5b8014 (virt) @40b5b8014 (dma) 0x000000 - rsvd2[3]
>[    1.607544] xhci_hcd 0000:00:14.0: @ffff88040b5b8018 (virt) @40b5b8018 (dma) 0x000000 - rsvd2[4]
>[    1.607545] xhci_hcd 0000:00:14.0: @ffff88040b5b801c (virt) @40b5b801c (dma) 0x000000 - rsvd2[5]
>[    1.607546] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.607548] xhci_hcd 0000:00:14.0: @ffff88040b5b8020 (virt) @40b5b8020 (dma) 0x18300000 - dev_info
>[    1.607549] xhci_hcd 0000:00:14.0: @ffff88040b5b8024 (virt) @40b5b8024 (dma) 0x0e0000 - dev_info2
>[    1.607550] xhci_hcd 0000:00:14.0: @ffff88040b5b8028 (virt) @40b5b8028 (dma) 0x000000 - tt_info
>[    1.607552] xhci_hcd 0000:00:14.0: @ffff88040b5b802c (virt) @40b5b802c (dma) 0x000000 - dev_state
>[    1.607553] xhci_hcd 0000:00:14.0: @ffff88040b5b8030 (virt) @40b5b8030 (dma) 0x000000 - rsvd[0]
>[    1.607555] xhci_hcd 0000:00:14.0: @ffff88040b5b8034 (virt) @40b5b8034 (dma) 0x000000 - rsvd[1]
>[    1.607556] xhci_hcd 0000:00:14.0: @ffff88040b5b8038 (virt) @40b5b8038 (dma) 0x000000 - rsvd[2]
>[    1.607557] xhci_hcd 0000:00:14.0: @ffff88040b5b803c (virt) @40b5b803c (dma) 0x000000 - rsvd[3]
>[    1.607559] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.607560] xhci_hcd 0000:00:14.0: @ffff88040b5b8040 (virt) @40b5b8040 (dma) 0x000000 - ep_info
>[    1.607562] xhci_hcd 0000:00:14.0: @ffff88040b5b8044 (virt) @40b5b8044 (dma) 0x400026 - ep_info2
>[    1.607563] xhci_hcd 0000:00:14.0: @ffff88040b5b8048 (virt) @40b5b8048 (dma) 0x40b62a401 - deq
>[    1.607565] xhci_hcd 0000:00:14.0: @ffff88040b5b8050 (virt) @40b5b8050 (dma) 0x000000 - tx_info
>[    1.607566] xhci_hcd 0000:00:14.0: @ffff88040b5b8054 (virt) @40b5b8054 (dma) 0x000000 - rsvd[0]
>[    1.607567] xhci_hcd 0000:00:14.0: @ffff88040b5b8058 (virt) @40b5b8058 (dma) 0x000000 - rsvd[1]
>[    1.607569] xhci_hcd 0000:00:14.0: @ffff88040b5b805c (virt) @40b5b805c (dma) 0x000000 - rsvd[2]
>[    1.607570] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.607572] xhci_hcd 0000:00:14.0: @ffff88040b5b8060 (virt) @40b5b8060 (dma) 0x000000 - ep_info
>[    1.607573] xhci_hcd 0000:00:14.0: @ffff88040b5b8064 (virt) @40b5b8064 (dma) 0x000000 - ep_info2
>[    1.607574] xhci_hcd 0000:00:14.0: @ffff88040b5b8068 (virt) @40b5b8068 (dma) 0x000000 - deq
>[    1.607576] xhci_hcd 0000:00:14.0: @ffff88040b5b8070 (virt) @40b5b8070 (dma) 0x000000 - tx_info
>[    1.607577] xhci_hcd 0000:00:14.0: @ffff88040b5b8074 (virt) @40b5b8074 (dma) 0x000000 - rsvd[0]
>[    1.607578] xhci_hcd 0000:00:14.0: @ffff88040b5b8078 (virt) @40b5b8078 (dma) 0x000000 - rsvd[1]
>[    1.607580] xhci_hcd 0000:00:14.0: @ffff88040b5b807c (virt) @40b5b807c (dma) 0x000000 - rsvd[2]
>[    1.607581] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.607582] xhci_hcd 0000:00:14.0: @ffff88040b5b8080 (virt) @40b5b8080 (dma) 0x0b0000 - ep_info
>[    1.607584] xhci_hcd 0000:00:14.0: @ffff88040b5b8084 (virt) @40b5b8084 (dma) 0x01003e - ep_info2
>[    1.607585] xhci_hcd 0000:00:14.0: @ffff88040b5b8088 (virt) @40b5b8088 (dma) 0x409ab4001 - deq
>[    1.607587] xhci_hcd 0000:00:14.0: @ffff88040b5b8090 (virt) @40b5b8090 (dma) 0x010001 - tx_info
>[    1.607588] xhci_hcd 0000:00:14.0: @ffff88040b5b8094 (virt) @40b5b8094 (dma) 0x000000 - rsvd[0]
>[    1.607589] xhci_hcd 0000:00:14.0: @ffff88040b5b8098 (virt) @40b5b8098 (dma) 0x000000 - rsvd[1]
>[    1.607591] xhci_hcd 0000:00:14.0: @ffff88040b5b809c (virt) @40b5b809c (dma) 0x000000 - rsvd[2]
>[    1.607592] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.607751] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.607757] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.607758] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.607759] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.607761] xhci_hcd 0000:00:14.0: @ffff88040c696000 (virt) @40c696000 (dma) 0x18300000 - dev_info
>[    1.607763] xhci_hcd 0000:00:14.0: @ffff88040c696004 (virt) @40c696004 (dma) 0x0e0000 - dev_info2
>[    1.607764] xhci_hcd 0000:00:14.0: @ffff88040c696008 (virt) @40c696008 (dma) 0x000000 - tt_info
>[    1.607766] xhci_hcd 0000:00:14.0: @ffff88040c69600c (virt) @40c69600c (dma) 0x18000002 - dev_state
>[    1.607768] xhci_hcd 0000:00:14.0: @ffff88040c696010 (virt) @40c696010 (dma) 0x000000 - rsvd[0]
>[    1.607769] xhci_hcd 0000:00:14.0: @ffff88040c696014 (virt) @40c696014 (dma) 0x000000 - rsvd[1]
>[    1.607771] xhci_hcd 0000:00:14.0: @ffff88040c696018 (virt) @40c696018 (dma) 0x000000 - rsvd[2]
>[    1.607772] xhci_hcd 0000:00:14.0: @ffff88040c69601c (virt) @40c69601c (dma) 0x000000 - rsvd[3]
>[    1.607774] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.607775] xhci_hcd 0000:00:14.0: @ffff88040c696020 (virt) @40c696020 (dma) 0x000001 - ep_info
>[    1.607777] xhci_hcd 0000:00:14.0: @ffff88040c696024 (virt) @40c696024 (dma) 0x400026 - ep_info2
>[    1.607778] xhci_hcd 0000:00:14.0: @ffff88040c696028 (virt) @40c696028 (dma) 0x40b62a401 - deq
>[    1.607780] xhci_hcd 0000:00:14.0: @ffff88040c696030 (virt) @40c696030 (dma) 0x000000 - tx_info
>[    1.607781] xhci_hcd 0000:00:14.0: @ffff88040c696034 (virt) @40c696034 (dma) 0x000000 - rsvd[0]
>[    1.607782] xhci_hcd 0000:00:14.0: @ffff88040c696038 (virt) @40c696038 (dma) 0x000000 - rsvd[1]
>[    1.607784] xhci_hcd 0000:00:14.0: @ffff88040c69603c (virt) @40c69603c (dma) 0x000000 - rsvd[2]
>[    1.607785] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.607787] xhci_hcd 0000:00:14.0: @ffff88040c696040 (virt) @40c696040 (dma) 0x000000 - ep_info
>[    1.607788] xhci_hcd 0000:00:14.0: @ffff88040c696044 (virt) @40c696044 (dma) 0x000000 - ep_info2
>[    1.607789] xhci_hcd 0000:00:14.0: @ffff88040c696048 (virt) @40c696048 (dma) 0x000000 - deq
>[    1.607791] xhci_hcd 0000:00:14.0: @ffff88040c696050 (virt) @40c696050 (dma) 0x000000 - tx_info
>[    1.607792] xhci_hcd 0000:00:14.0: @ffff88040c696054 (virt) @40c696054 (dma) 0x000000 - rsvd[0]
>[    1.607794] xhci_hcd 0000:00:14.0: @ffff88040c696058 (virt) @40c696058 (dma) 0x000000 - rsvd[1]
>[    1.607795] xhci_hcd 0000:00:14.0: @ffff88040c69605c (virt) @40c69605c (dma) 0x000000 - rsvd[2]
>[    1.607796] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.607798] xhci_hcd 0000:00:14.0: @ffff88040c696060 (virt) @40c696060 (dma) 0x0b0001 - ep_info
>[    1.607799] xhci_hcd 0000:00:14.0: @ffff88040c696064 (virt) @40c696064 (dma) 0x01003e - ep_info2
>[    1.607800] xhci_hcd 0000:00:14.0: @ffff88040c696068 (virt) @40c696068 (dma) 0x409ab4001 - deq
>[    1.607802] xhci_hcd 0000:00:14.0: @ffff88040c696070 (virt) @40c696070 (dma) 0x010001 - tx_info
>[    1.607803] xhci_hcd 0000:00:14.0: @ffff88040c696074 (virt) @40c696074 (dma) 0x000000 - rsvd[0]
>[    1.607805] xhci_hcd 0000:00:14.0: @ffff88040c696078 (virt) @40c696078 (dma) 0x000000 - rsvd[1]
>[    1.607806] xhci_hcd 0000:00:14.0: @ffff88040c69607c (virt) @40c69607c (dma) 0x000000 - rsvd[2]
>[    1.607810] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.608021] usb 2-14: adding 2-14:1.0 (config #1, interface 0)
>[    1.608047] hub 2-14:1.0: usb_probe_interface
>[    1.608049] hub 2-14:1.0: usb_probe_interface - got id
>[    1.608051] hub 2-14:1.0: USB hub found
>[    1.608324] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.608329] hub 2-14:1.0: 2 ports detected
>[    1.608331] hub 2-14:1.0: standalone hub
>[    1.608332] hub 2-14:1.0: ganged power switching
>[    1.608333] hub 2-14:1.0: global over-current protection
>[    1.608335] xhci_hcd 0000:00:14.0: xhci_drop_endpoint called for udev ffff88040ba8a000
>[    1.608337] xhci_hcd 0000:00:14.0: drop ep 0x81, slot id 2, new drop flags = 0x8, new add flags = 0x0, new slot info = 0x8300000
>[    1.608341] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 2, new drop flags = 0x8, new add flags = 0x8, new slot info = 0x18300000
>[    1.608343] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040ba8a000
>[    1.608344] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.608346] xhci_hcd 0000:00:14.0: @ffff88040b5b8000 (virt) @40b5b8000 (dma) 0x000008 - drop flags
>[    1.608347] xhci_hcd 0000:00:14.0: @ffff88040b5b8004 (virt) @40b5b8004 (dma) 0x000009 - add flags
>[    1.608349] xhci_hcd 0000:00:14.0: @ffff88040b5b8008 (virt) @40b5b8008 (dma) 0x000000 - rsvd2[0]
>[    1.608350] xhci_hcd 0000:00:14.0: @ffff88040b5b800c (virt) @40b5b800c (dma) 0x000000 - rsvd2[1]
>[    1.608352] xhci_hcd 0000:00:14.0: @ffff88040b5b8010 (virt) @40b5b8010 (dma) 0x000000 - rsvd2[2]
>[    1.608353] xhci_hcd 0000:00:14.0: @ffff88040b5b8014 (virt) @40b5b8014 (dma) 0x000000 - rsvd2[3]
>[    1.608355] xhci_hcd 0000:00:14.0: @ffff88040b5b8018 (virt) @40b5b8018 (dma) 0x000000 - rsvd2[4]
>[    1.608356] xhci_hcd 0000:00:14.0: @ffff88040b5b801c (virt) @40b5b801c (dma) 0x000000 - rsvd2[5]
>[    1.608357] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.608358] xhci_hcd 0000:00:14.0: @ffff88040b5b8020 (virt) @40b5b8020 (dma) 0x18300000 - dev_info
>[    1.608360] xhci_hcd 0000:00:14.0: @ffff88040b5b8024 (virt) @40b5b8024 (dma) 0x0e0000 - dev_info2
>[    1.608361] xhci_hcd 0000:00:14.0: @ffff88040b5b8028 (virt) @40b5b8028 (dma) 0x000000 - tt_info
>[    1.608362] xhci_hcd 0000:00:14.0: @ffff88040b5b802c (virt) @40b5b802c (dma) 0x000000 - dev_state
>[    1.608364] xhci_hcd 0000:00:14.0: @ffff88040b5b8030 (virt) @40b5b8030 (dma) 0x000000 - rsvd[0]
>[    1.608365] xhci_hcd 0000:00:14.0: @ffff88040b5b8034 (virt) @40b5b8034 (dma) 0x000000 - rsvd[1]
>[    1.608367] xhci_hcd 0000:00:14.0: @ffff88040b5b8038 (virt) @40b5b8038 (dma) 0x000000 - rsvd[2]
>[    1.608368] xhci_hcd 0000:00:14.0: @ffff88040b5b803c (virt) @40b5b803c (dma) 0x000000 - rsvd[3]
>[    1.608370] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.608371] xhci_hcd 0000:00:14.0: @ffff88040b5b8040 (virt) @40b5b8040 (dma) 0x000000 - ep_info
>[    1.608372] xhci_hcd 0000:00:14.0: @ffff88040b5b8044 (virt) @40b5b8044 (dma) 0x400026 - ep_info2
>[    1.608374] xhci_hcd 0000:00:14.0: @ffff88040b5b8048 (virt) @40b5b8048 (dma) 0x40b62a401 - deq
>[    1.608375] xhci_hcd 0000:00:14.0: @ffff88040b5b8050 (virt) @40b5b8050 (dma) 0x000000 - tx_info
>[    1.608377] xhci_hcd 0000:00:14.0: @ffff88040b5b8054 (virt) @40b5b8054 (dma) 0x000000 - rsvd[0]
>[    1.608378] xhci_hcd 0000:00:14.0: @ffff88040b5b8058 (virt) @40b5b8058 (dma) 0x000000 - rsvd[1]
>[    1.608380] xhci_hcd 0000:00:14.0: @ffff88040b5b805c (virt) @40b5b805c (dma) 0x000000 - rsvd[2]
>[    1.608381] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.608382] xhci_hcd 0000:00:14.0: @ffff88040b5b8060 (virt) @40b5b8060 (dma) 0x000000 - ep_info
>[    1.608384] xhci_hcd 0000:00:14.0: @ffff88040b5b8064 (virt) @40b5b8064 (dma) 0x000000 - ep_info2
>[    1.608385] xhci_hcd 0000:00:14.0: @ffff88040b5b8068 (virt) @40b5b8068 (dma) 0x000000 - deq
>[    1.608386] xhci_hcd 0000:00:14.0: @ffff88040b5b8070 (virt) @40b5b8070 (dma) 0x000000 - tx_info
>[    1.608388] xhci_hcd 0000:00:14.0: @ffff88040b5b8074 (virt) @40b5b8074 (dma) 0x000000 - rsvd[0]
>[    1.608389] xhci_hcd 0000:00:14.0: @ffff88040b5b8078 (virt) @40b5b8078 (dma) 0x000000 - rsvd[1]
>[    1.608391] xhci_hcd 0000:00:14.0: @ffff88040b5b807c (virt) @40b5b807c (dma) 0x000000 - rsvd[2]
>[    1.608392] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.608393] xhci_hcd 0000:00:14.0: @ffff88040b5b8080 (virt) @40b5b8080 (dma) 0x0b0000 - ep_info
>[    1.608395] xhci_hcd 0000:00:14.0: @ffff88040b5b8084 (virt) @40b5b8084 (dma) 0x01003e - ep_info2
>[    1.608396] xhci_hcd 0000:00:14.0: @ffff88040b5b8088 (virt) @40b5b8088 (dma) 0x409ab4801 - deq
>[    1.608397] xhci_hcd 0000:00:14.0: @ffff88040b5b8090 (virt) @40b5b8090 (dma) 0x010001 - tx_info
>[    1.608399] xhci_hcd 0000:00:14.0: @ffff88040b5b8094 (virt) @40b5b8094 (dma) 0x000000 - rsvd[0]
>[    1.608400] xhci_hcd 0000:00:14.0: @ffff88040b5b8098 (virt) @40b5b8098 (dma) 0x000000 - rsvd[1]
>[    1.608401] xhci_hcd 0000:00:14.0: @ffff88040b5b809c (virt) @40b5b809c (dma) 0x000000 - rsvd[2]
>[    1.608403] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.608563] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.608567] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.608568] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.608569] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.608571] xhci_hcd 0000:00:14.0: @ffff88040c696000 (virt) @40c696000 (dma) 0x18300000 - dev_info
>[    1.608572] xhci_hcd 0000:00:14.0: @ffff88040c696004 (virt) @40c696004 (dma) 0x0e0000 - dev_info2
>[    1.608573] xhci_hcd 0000:00:14.0: @ffff88040c696008 (virt) @40c696008 (dma) 0x000000 - tt_info
>[    1.608575] xhci_hcd 0000:00:14.0: @ffff88040c69600c (virt) @40c69600c (dma) 0x18000002 - dev_state
>[    1.608576] xhci_hcd 0000:00:14.0: @ffff88040c696010 (virt) @40c696010 (dma) 0x000000 - rsvd[0]
>[    1.608578] xhci_hcd 0000:00:14.0: @ffff88040c696014 (virt) @40c696014 (dma) 0x000000 - rsvd[1]
>[    1.608579] xhci_hcd 0000:00:14.0: @ffff88040c696018 (virt) @40c696018 (dma) 0x000000 - rsvd[2]
>[    1.608581] xhci_hcd 0000:00:14.0: @ffff88040c69601c (virt) @40c69601c (dma) 0x000000 - rsvd[3]
>[    1.608582] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.608583] xhci_hcd 0000:00:14.0: @ffff88040c696020 (virt) @40c696020 (dma) 0x000001 - ep_info
>[    1.608585] xhci_hcd 0000:00:14.0: @ffff88040c696024 (virt) @40c696024 (dma) 0x400026 - ep_info2
>[    1.608586] xhci_hcd 0000:00:14.0: @ffff88040c696028 (virt) @40c696028 (dma) 0x40b62a401 - deq
>[    1.608587] xhci_hcd 0000:00:14.0: @ffff88040c696030 (virt) @40c696030 (dma) 0x000000 - tx_info
>[    1.608589] xhci_hcd 0000:00:14.0: @ffff88040c696034 (virt) @40c696034 (dma) 0x000000 - rsvd[0]
>[    1.608590] xhci_hcd 0000:00:14.0: @ffff88040c696038 (virt) @40c696038 (dma) 0x000000 - rsvd[1]
>[    1.608591] xhci_hcd 0000:00:14.0: @ffff88040c69603c (virt) @40c69603c (dma) 0x000000 - rsvd[2]
>[    1.608593] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.608594] xhci_hcd 0000:00:14.0: @ffff88040c696040 (virt) @40c696040 (dma) 0x000000 - ep_info
>[    1.608596] xhci_hcd 0000:00:14.0: @ffff88040c696044 (virt) @40c696044 (dma) 0x000000 - ep_info2
>[    1.608597] xhci_hcd 0000:00:14.0: @ffff88040c696048 (virt) @40c696048 (dma) 0x000000 - deq
>[    1.608598] xhci_hcd 0000:00:14.0: @ffff88040c696050 (virt) @40c696050 (dma) 0x000000 - tx_info
>[    1.608600] xhci_hcd 0000:00:14.0: @ffff88040c696054 (virt) @40c696054 (dma) 0x000000 - rsvd[0]
>[    1.608601] xhci_hcd 0000:00:14.0: @ffff88040c696058 (virt) @40c696058 (dma) 0x000000 - rsvd[1]
>[    1.608602] xhci_hcd 0000:00:14.0: @ffff88040c69605c (virt) @40c69605c (dma) 0x000000 - rsvd[2]
>[    1.608604] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.608605] xhci_hcd 0000:00:14.0: @ffff88040c696060 (virt) @40c696060 (dma) 0x0b0001 - ep_info
>[    1.608606] xhci_hcd 0000:00:14.0: @ffff88040c696064 (virt) @40c696064 (dma) 0x01003e - ep_info2
>[    1.608608] xhci_hcd 0000:00:14.0: @ffff88040c696068 (virt) @40c696068 (dma) 0x409ab4801 - deq
>[    1.608609] xhci_hcd 0000:00:14.0: @ffff88040c696070 (virt) @40c696070 (dma) 0x010001 - tx_info
>[    1.608611] xhci_hcd 0000:00:14.0: @ffff88040c696074 (virt) @40c696074 (dma) 0x000000 - rsvd[0]
>[    1.608612] xhci_hcd 0000:00:14.0: @ffff88040c696078 (virt) @40c696078 (dma) 0x000000 - rsvd[1]
>[    1.608613] xhci_hcd 0000:00:14.0: @ffff88040c69607c (virt) @40c69607c (dma) 0x000000 - rsvd[2]
>[    1.608616] xhci_hcd 0000:00:14.0: Cached old ring, 1 ring cached
>[    1.608818] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.608827] hub 2-14:1.0: TT per port
>[    1.608828] hub 2-14:1.0: TT requires at most 32 FS bit times (2664 ns)
>[    1.608830] hub 2-14:1.0: Port indicators are supported
>[    1.608831] hub 2-14:1.0: power on to power good time: 100ms
>[    1.608912] xhci_hcd 0000:00:14.0: xHCI version 100 needs hub TT think time and number of ports
>[    1.608913] xhci_hcd 0000:00:14.0: Set up configure endpoint for hub device.
>[    1.608914] xhci_hcd 0000:00:14.0: Slot 2 Input Context:
>[    1.608916] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x000000 - drop flags
>[    1.608917] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x000001 - add flags
>[    1.608919] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - rsvd2[0]
>[    1.608920] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x000000 - rsvd2[1]
>[    1.608922] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd2[2]
>[    1.608923] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd2[3]
>[    1.608924] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd2[4]
>[    1.608926] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd2[5]
>[    1.608927] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.608928] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x1e300000 - dev_info
>[    1.608930] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x20e0000 - dev_info2
>[    1.608931] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x030000 - tt_info
>[    1.608932] xhci_hcd 0000:00:14.0: @ffff88040b73102c (virt) @40b73102c (dma) 0x000000 - dev_state
>[    1.608934] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - rsvd[0]
>[    1.608935] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[1]
>[    1.608937] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[2]
>[    1.608938] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[3]
>[    1.608939] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.608941] xhci_hcd 0000:00:14.0: @ffff88040b731040 (virt) @40b731040 (dma) 0x000000 - ep_info
>[    1.608942] xhci_hcd 0000:00:14.0: @ffff88040b731044 (virt) @40b731044 (dma) 0x000000 - ep_info2
>[    1.608943] xhci_hcd 0000:00:14.0: @ffff88040b731048 (virt) @40b731048 (dma) 0x000000 - deq
>[    1.608945] xhci_hcd 0000:00:14.0: @ffff88040b731050 (virt) @40b731050 (dma) 0x000000 - tx_info
>[    1.608946] xhci_hcd 0000:00:14.0: @ffff88040b731054 (virt) @40b731054 (dma) 0x000000 - rsvd[0]
>[    1.608948] xhci_hcd 0000:00:14.0: @ffff88040b731058 (virt) @40b731058 (dma) 0x000000 - rsvd[1]
>[    1.608949] xhci_hcd 0000:00:14.0: @ffff88040b73105c (virt) @40b73105c (dma) 0x000000 - rsvd[2]
>[    1.608951] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.609119] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.609121] xhci_hcd 0000:00:14.0: Slot 2 Output Context:
>[    1.609122] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.609123] xhci_hcd 0000:00:14.0: @ffff88040c696000 (virt) @40c696000 (dma) 0x1e300000 - dev_info
>[    1.609125] xhci_hcd 0000:00:14.0: @ffff88040c696004 (virt) @40c696004 (dma) 0x20e0000 - dev_info2
>[    1.609126] xhci_hcd 0000:00:14.0: @ffff88040c696008 (virt) @40c696008 (dma) 0x030000 - tt_info
>[    1.609128] xhci_hcd 0000:00:14.0: @ffff88040c69600c (virt) @40c69600c (dma) 0x18000002 - dev_state
>[    1.609129] xhci_hcd 0000:00:14.0: @ffff88040c696010 (virt) @40c696010 (dma) 0x000000 - rsvd[0]
>[    1.609131] xhci_hcd 0000:00:14.0: @ffff88040c696014 (virt) @40c696014 (dma) 0x000000 - rsvd[1]
>[    1.609132] xhci_hcd 0000:00:14.0: @ffff88040c696018 (virt) @40c696018 (dma) 0x000000 - rsvd[2]
>[    1.609133] xhci_hcd 0000:00:14.0: @ffff88040c69601c (virt) @40c69601c (dma) 0x000000 - rsvd[3]
>[    1.609135] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.609136] xhci_hcd 0000:00:14.0: @ffff88040c696020 (virt) @40c696020 (dma) 0x000001 - ep_info
>[    1.609137] xhci_hcd 0000:00:14.0: @ffff88040c696024 (virt) @40c696024 (dma) 0x400026 - ep_info2
>[    1.609139] xhci_hcd 0000:00:14.0: @ffff88040c696028 (virt) @40c696028 (dma) 0x40b62a401 - deq
>[    1.609140] xhci_hcd 0000:00:14.0: @ffff88040c696030 (virt) @40c696030 (dma) 0x000000 - tx_info
>[    1.609141] xhci_hcd 0000:00:14.0: @ffff88040c696034 (virt) @40c696034 (dma) 0x000000 - rsvd[0]
>[    1.609143] xhci_hcd 0000:00:14.0: @ffff88040c696038 (virt) @40c696038 (dma) 0x000000 - rsvd[1]
>[    1.609144] xhci_hcd 0000:00:14.0: @ffff88040c69603c (virt) @40c69603c (dma) 0x000000 - rsvd[2]
>[    1.609391] hub 2-14:1.0: local power source is good
>[    1.609393] hub 2-14:1.0: no over-current condition exists
>[    1.609410] hub 2-14:1.0: enabling power on all ports
>[    1.610000] hub 3-0:1.0: state 7 ports 6 chg 0000 evt 0002
>[    1.610004] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x21203
>[    1.610005] xhci_hcd 0000:00:14.0: Get port status returned 0x10203
>[    1.610041] xhci_hcd 0000:00:14.0: clear port connect change, actual port 0 status  = 0x1203
>[    1.610058] hub 3-0:1.0: port 1, status 0203, change 0001, 5.0 Gb/s
>[    1.610061] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.610062] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.636063] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.636066] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.662045] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.662048] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.688084] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.688086] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.709332] hub 2-14:1.0: port 1: status 0301 change 0001
>[    1.709838] hub 2-14:1.0: port 2: status 0301 change 0001
>[    1.714042] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.714045] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.714070] hub 3-0:1.0: debounce: port 1: total 100ms stable 100ms status 0x203
>[    1.714073] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.714098] xhci_hcd 0000:00:14.0: Slot 3 output ctx = 0x40b731000 (dma)
>[    1.714101] xhci_hcd 0000:00:14.0: Slot 3 input ctx = 0x409a5c000 (dma)
>[    1.714104] xhci_hcd 0000:00:14.0: Set slot id 3 dcbaa entry ffff88040bed9018 to 0x40b731000
>[    1.714109] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.714110] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.714138] xhci_hcd 0000:00:14.0: set port reset, actual port 0 status  = 0x1311
>[    1.714160] xhci_hcd 0000:00:14.0: Port Status Change Event for port 16
>[    1.714164] xhci_hcd 0000:00:14.0: handle_port_status: starting port polling.
>[    1.730066] xhci_hcd 0000:00:14.0: xhci_hub_status_data: stopping port polling.
>[    1.765054] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x201203
>[    1.765058] xhci_hcd 0000:00:14.0: Get port status returned 0x100203
>[    1.816048] xhci_hcd 0000:00:14.0: clear port reset change, actual port 0 status  = 0x1203
>[    1.816084] xhci_hcd 0000:00:14.0: clear port warm(BH) reset change, actual port 0 status  = 0x1203
>[    1.816121] xhci_hcd 0000:00:14.0: clear port link state change, actual port 0 status  = 0x1203
>[    1.816159] xhci_hcd 0000:00:14.0: clear port connect change, actual port 0 status  = 0x1203
>[    1.816194] xhci_hcd 0000:00:14.0: get port status, actual port 0 status  = 0x1203
>[    1.816198] xhci_hcd 0000:00:14.0: Get port status returned 0x203
>[    1.816231] xhci_hcd 0000:00:14.0: Set root hub portnum to 16
>[    1.816234] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 1
>[    1.816237] xhci_hcd 0000:00:14.0: udev->tt =           (null)
>[    1.816239] xhci_hcd 0000:00:14.0: udev->ttport = 0x0
>[    1.816241] xhci_hcd 0000:00:14.0: Slot ID 3 Input Context:
>[    1.816244] xhci_hcd 0000:00:14.0: @ffff880409a5c000 (virt) @409a5c000 (dma) 0x000000 - drop flags
>[    1.816247] xhci_hcd 0000:00:14.0: @ffff880409a5c004 (virt) @409a5c004 (dma) 0x000003 - add flags
>[    1.816249] xhci_hcd 0000:00:14.0: @ffff880409a5c008 (virt) @409a5c008 (dma) 0x000000 - rsvd2[0]
>[    1.816251] xhci_hcd 0000:00:14.0: @ffff880409a5c00c (virt) @409a5c00c (dma) 0x000000 - rsvd2[1]
>[    1.816254] xhci_hcd 0000:00:14.0: @ffff880409a5c010 (virt) @409a5c010 (dma) 0x000000 - rsvd2[2]
>[    1.816256] xhci_hcd 0000:00:14.0: @ffff880409a5c014 (virt) @409a5c014 (dma) 0x000000 - rsvd2[3]
>[    1.816258] xhci_hcd 0000:00:14.0: @ffff880409a5c018 (virt) @409a5c018 (dma) 0x000000 - rsvd2[4]
>[    1.816260] xhci_hcd 0000:00:14.0: @ffff880409a5c01c (virt) @409a5c01c (dma) 0x000000 - rsvd2[5]
>[    1.816262] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.816264] xhci_hcd 0000:00:14.0: @ffff880409a5c020 (virt) @409a5c020 (dma) 0x8400000 - dev_info
>[    1.816266] xhci_hcd 0000:00:14.0: @ffff880409a5c024 (virt) @409a5c024 (dma) 0x100000 - dev_info2
>[    1.816268] xhci_hcd 0000:00:14.0: @ffff880409a5c028 (virt) @409a5c028 (dma) 0x000000 - tt_info
>[    1.816270] xhci_hcd 0000:00:14.0: @ffff880409a5c02c (virt) @409a5c02c (dma) 0x000000 - dev_state
>[    1.816273] xhci_hcd 0000:00:14.0: @ffff880409a5c030 (virt) @409a5c030 (dma) 0x000000 - rsvd[0]
>[    1.816275] xhci_hcd 0000:00:14.0: @ffff880409a5c034 (virt) @409a5c034 (dma) 0x000000 - rsvd[1]
>[    1.816277] xhci_hcd 0000:00:14.0: @ffff880409a5c038 (virt) @409a5c038 (dma) 0x000000 - rsvd[2]
>[    1.816279] xhci_hcd 0000:00:14.0: @ffff880409a5c03c (virt) @409a5c03c (dma) 0x000000 - rsvd[3]
>[    1.816281] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.816284] xhci_hcd 0000:00:14.0: @ffff880409a5c040 (virt) @409a5c040 (dma) 0x000000 - ep_info
>[    1.816286] xhci_hcd 0000:00:14.0: @ffff880409a5c044 (virt) @409a5c044 (dma) 0x2000026 - ep_info2
>[    1.816288] xhci_hcd 0000:00:14.0: @ffff880409a5c048 (virt) @409a5c048 (dma) 0x409a76401 - deq
>[    1.816290] xhci_hcd 0000:00:14.0: @ffff880409a5c050 (virt) @409a5c050 (dma) 0x000000 - tx_info
>[    1.816292] xhci_hcd 0000:00:14.0: @ffff880409a5c054 (virt) @409a5c054 (dma) 0x000000 - rsvd[0]
>[    1.816295] xhci_hcd 0000:00:14.0: @ffff880409a5c058 (virt) @409a5c058 (dma) 0x000000 - rsvd[1]
>[    1.816297] xhci_hcd 0000:00:14.0: @ffff880409a5c05c (virt) @409a5c05c (dma) 0x000000 - rsvd[2]
>[    1.816299] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.816301] xhci_hcd 0000:00:14.0: @ffff880409a5c060 (virt) @409a5c060 (dma) 0x000000 - ep_info
>[    1.816303] xhci_hcd 0000:00:14.0: @ffff880409a5c064 (virt) @409a5c064 (dma) 0x000000 - ep_info2
>[    1.816305] xhci_hcd 0000:00:14.0: @ffff880409a5c068 (virt) @409a5c068 (dma) 0x000000 - deq
>[    1.816307] xhci_hcd 0000:00:14.0: @ffff880409a5c070 (virt) @409a5c070 (dma) 0x000000 - tx_info
>[    1.816309] xhci_hcd 0000:00:14.0: @ffff880409a5c074 (virt) @409a5c074 (dma) 0x000000 - rsvd[0]
>[    1.816311] xhci_hcd 0000:00:14.0: @ffff880409a5c078 (virt) @409a5c078 (dma) 0x000000 - rsvd[1]
>[    1.816314] xhci_hcd 0000:00:14.0: @ffff880409a5c07c (virt) @409a5c07c (dma) 0x000000 - rsvd[2]
>[    1.816316] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.816318] xhci_hcd 0000:00:14.0: @ffff880409a5c080 (virt) @409a5c080 (dma) 0x000000 - ep_info
>[    1.816320] xhci_hcd 0000:00:14.0: @ffff880409a5c084 (virt) @409a5c084 (dma) 0x000000 - ep_info2
>[    1.816322] xhci_hcd 0000:00:14.0: @ffff880409a5c088 (virt) @409a5c088 (dma) 0x000000 - deq
>[    1.816324] xhci_hcd 0000:00:14.0: @ffff880409a5c090 (virt) @409a5c090 (dma) 0x000000 - tx_info
>[    1.816326] xhci_hcd 0000:00:14.0: @ffff880409a5c094 (virt) @409a5c094 (dma) 0x000000 - rsvd[0]
>[    1.816329] xhci_hcd 0000:00:14.0: @ffff880409a5c098 (virt) @409a5c098 (dma) 0x000000 - rsvd[1]
>[    1.816331] xhci_hcd 0000:00:14.0: @ffff880409a5c09c (virt) @409a5c09c (dma) 0x000000 - rsvd[2]
>[    1.816333] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.816569] xhci_hcd 0000:00:14.0: Successful Address Device command
>[    1.816575] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[    1.816578] xhci_hcd 0000:00:14.0: Slot ID 3 dcbaa entry @ffff88040bed9018 = 0x0000040b731000
>[    1.816580] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40b731000
>[    1.816582] xhci_hcd 0000:00:14.0: Slot ID 3 Input Context:
>[    1.816585] xhci_hcd 0000:00:14.0: @ffff880409a5c000 (virt) @409a5c000 (dma) 0x000000 - drop flags
>[    1.816587] xhci_hcd 0000:00:14.0: @ffff880409a5c004 (virt) @409a5c004 (dma) 0x000003 - add flags
>[    1.816590] xhci_hcd 0000:00:14.0: @ffff880409a5c008 (virt) @409a5c008 (dma) 0x000000 - rsvd2[0]
>[    1.816592] xhci_hcd 0000:00:14.0: @ffff880409a5c00c (virt) @409a5c00c (dma) 0x000000 - rsvd2[1]
>[    1.816594] xhci_hcd 0000:00:14.0: @ffff880409a5c010 (virt) @409a5c010 (dma) 0x000000 - rsvd2[2]
>[    1.816596] xhci_hcd 0000:00:14.0: @ffff880409a5c014 (virt) @409a5c014 (dma) 0x000000 - rsvd2[3]
>[    1.816598] xhci_hcd 0000:00:14.0: @ffff880409a5c018 (virt) @409a5c018 (dma) 0x000000 - rsvd2[4]
>[    1.816600] xhci_hcd 0000:00:14.0: @ffff880409a5c01c (virt) @409a5c01c (dma) 0x000000 - rsvd2[5]
>[    1.816602] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.816604] xhci_hcd 0000:00:14.0: @ffff880409a5c020 (virt) @409a5c020 (dma) 0x8400000 - dev_info
>[    1.816606] xhci_hcd 0000:00:14.0: @ffff880409a5c024 (virt) @409a5c024 (dma) 0x100000 - dev_info2
>[    1.816608] xhci_hcd 0000:00:14.0: @ffff880409a5c028 (virt) @409a5c028 (dma) 0x000000 - tt_info
>[    1.816611] xhci_hcd 0000:00:14.0: @ffff880409a5c02c (virt) @409a5c02c (dma) 0x000000 - dev_state
>[    1.816613] xhci_hcd 0000:00:14.0: @ffff880409a5c030 (virt) @409a5c030 (dma) 0x000000 - rsvd[0]
>[    1.816615] xhci_hcd 0000:00:14.0: @ffff880409a5c034 (virt) @409a5c034 (dma) 0x000000 - rsvd[1]
>[    1.816617] xhci_hcd 0000:00:14.0: @ffff880409a5c038 (virt) @409a5c038 (dma) 0x000000 - rsvd[2]
>[    1.816619] xhci_hcd 0000:00:14.0: @ffff880409a5c03c (virt) @409a5c03c (dma) 0x000000 - rsvd[3]
>[    1.816622] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.816624] xhci_hcd 0000:00:14.0: @ffff880409a5c040 (virt) @409a5c040 (dma) 0x000000 - ep_info
>[    1.816626] xhci_hcd 0000:00:14.0: @ffff880409a5c044 (virt) @409a5c044 (dma) 0x2000026 - ep_info2
>[    1.816628] xhci_hcd 0000:00:14.0: @ffff880409a5c048 (virt) @409a5c048 (dma) 0x409a76401 - deq
>[    1.816631] xhci_hcd 0000:00:14.0: @ffff880409a5c050 (virt) @409a5c050 (dma) 0x000000 - tx_info
>[    1.816633] xhci_hcd 0000:00:14.0: @ffff880409a5c054 (virt) @409a5c054 (dma) 0x000000 - rsvd[0]
>[    1.816635] xhci_hcd 0000:00:14.0: @ffff880409a5c058 (virt) @409a5c058 (dma) 0x000000 - rsvd[1]
>[    1.816637] xhci_hcd 0000:00:14.0: @ffff880409a5c05c (virt) @409a5c05c (dma) 0x000000 - rsvd[2]
>[    1.816639] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.816641] xhci_hcd 0000:00:14.0: @ffff880409a5c060 (virt) @409a5c060 (dma) 0x000000 - ep_info
>[    1.816643] xhci_hcd 0000:00:14.0: @ffff880409a5c064 (virt) @409a5c064 (dma) 0x000000 - ep_info2
>[    1.816645] xhci_hcd 0000:00:14.0: @ffff880409a5c068 (virt) @409a5c068 (dma) 0x000000 - deq
>[    1.816647] xhci_hcd 0000:00:14.0: @ffff880409a5c070 (virt) @409a5c070 (dma) 0x000000 - tx_info
>[    1.816650] xhci_hcd 0000:00:14.0: @ffff880409a5c074 (virt) @409a5c074 (dma) 0x000000 - rsvd[0]
>[    1.816652] xhci_hcd 0000:00:14.0: @ffff880409a5c078 (virt) @409a5c078 (dma) 0x000000 - rsvd[1]
>[    1.816654] xhci_hcd 0000:00:14.0: @ffff880409a5c07c (virt) @409a5c07c (dma) 0x000000 - rsvd[2]
>[    1.816656] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.816658] xhci_hcd 0000:00:14.0: @ffff880409a5c080 (virt) @409a5c080 (dma) 0x000000 - ep_info
>[    1.816660] xhci_hcd 0000:00:14.0: @ffff880409a5c084 (virt) @409a5c084 (dma) 0x000000 - ep_info2
>[    1.816662] xhci_hcd 0000:00:14.0: @ffff880409a5c088 (virt) @409a5c088 (dma) 0x000000 - deq
>[    1.816664] xhci_hcd 0000:00:14.0: @ffff880409a5c090 (virt) @409a5c090 (dma) 0x000000 - tx_info
>[    1.816666] xhci_hcd 0000:00:14.0: @ffff880409a5c094 (virt) @409a5c094 (dma) 0x000000 - rsvd[0]
>[    1.816668] xhci_hcd 0000:00:14.0: @ffff880409a5c098 (virt) @409a5c098 (dma) 0x000000 - rsvd[1]
>[    1.816670] xhci_hcd 0000:00:14.0: @ffff880409a5c09c (virt) @409a5c09c (dma) 0x000000 - rsvd[2]
>[    1.816672] xhci_hcd 0000:00:14.0: Slot ID 3 Output Context:
>[    1.816674] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.816676] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x8400000 - dev_info
>[    1.816678] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x100000 - dev_info2
>[    1.816680] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.816683] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x10000003 - dev_state
>[    1.816685] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.816687] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.816689] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.816691] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.816693] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.816695] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.816697] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.816699] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.816701] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.816704] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.816706] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.816708] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.816710] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.816712] xhci_hcd 0000:00:14.0: @ffff88040b731040 (virt) @40b731040 (dma) 0x000000 - ep_info
>[    1.816714] xhci_hcd 0000:00:14.0: @ffff88040b731044 (virt) @40b731044 (dma) 0x000000 - ep_info2
>[    1.816716] xhci_hcd 0000:00:14.0: @ffff88040b731048 (virt) @40b731048 (dma) 0x000000 - deq
>[    1.816718] xhci_hcd 0000:00:14.0: @ffff88040b731050 (virt) @40b731050 (dma) 0x000000 - tx_info
>[    1.816720] xhci_hcd 0000:00:14.0: @ffff88040b731054 (virt) @40b731054 (dma) 0x000000 - rsvd[0]
>[    1.816722] xhci_hcd 0000:00:14.0: @ffff88040b731058 (virt) @40b731058 (dma) 0x000000 - rsvd[1]
>[    1.816724] xhci_hcd 0000:00:14.0: @ffff88040b73105c (virt) @40b73105c (dma) 0x000000 - rsvd[2]
>[    1.816726] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.816728] xhci_hcd 0000:00:14.0: @ffff88040b731060 (virt) @40b731060 (dma) 0x000000 - ep_info
>[    1.816730] xhci_hcd 0000:00:14.0: @ffff88040b731064 (virt) @40b731064 (dma) 0x000000 - ep_info2
>[    1.816733] xhci_hcd 0000:00:14.0: @ffff88040b731068 (virt) @40b731068 (dma) 0x000000 - deq
>[    1.816735] xhci_hcd 0000:00:14.0: @ffff88040b731070 (virt) @40b731070 (dma) 0x000000 - tx_info
>[    1.816737] xhci_hcd 0000:00:14.0: @ffff88040b731074 (virt) @40b731074 (dma) 0x000000 - rsvd[0]
>[    1.816739] xhci_hcd 0000:00:14.0: @ffff88040b731078 (virt) @40b731078 (dma) 0x000000 - rsvd[1]
>[    1.816741] xhci_hcd 0000:00:14.0: @ffff88040b73107c (virt) @40b73107c (dma) 0x000000 - rsvd[2]
>[    1.816743] xhci_hcd 0000:00:14.0: Internal device address = 4
>[    1.816747] usb 3-1: new SuperSpeed USB device number 2 using xhci_hcd
>[    1.828732] usb 3-1: skipped 1 descriptor after endpoint
>[    1.828736] usb 3-1: skipped 1 descriptor after endpoint
>[    1.828923] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.828930] usb 3-1: default language 0x0409
>[    1.829205] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.829512] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.829525] usb 3-1: udev 2, busnum 3, minor = 257
>[    1.829528] usb 3-1: New USB device found, idVendor=05e3, idProduct=0738
>[    1.829531] usb 3-1: New USB device strings: Mfr=0, Product=1, SerialNumber=2
>[    1.829533] usb 3-1: Product: USB Storage
>[    1.829535] usb 3-1: SerialNumber: 000000000556
>[    1.829645] usb 3-1: usb_probe_device
>[    1.829649] usb 3-1: configuration #1 chosen from 1 choice
>[    1.829660] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 3, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x18400000
>[    1.829666] xhci_hcd 0000:00:14.0: add ep 0x2, slot id 3, new drop flags = 0x0, new add flags = 0x18, new slot info = 0x20400000
>[    1.829670] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040b955800
>[    1.829673] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.829677] xhci_hcd 0000:00:14.0: @ffff880409a5c000 (virt) @409a5c000 (dma) 0x000000 - drop flags
>[    1.829681] xhci_hcd 0000:00:14.0: @ffff880409a5c004 (virt) @409a5c004 (dma) 0x000019 - add flags
>[    1.829684] xhci_hcd 0000:00:14.0: @ffff880409a5c008 (virt) @409a5c008 (dma) 0x000000 - rsvd2[0]
>[    1.829687] xhci_hcd 0000:00:14.0: @ffff880409a5c00c (virt) @409a5c00c (dma) 0x000000 - rsvd2[1]
>[    1.829691] xhci_hcd 0000:00:14.0: @ffff880409a5c010 (virt) @409a5c010 (dma) 0x000000 - rsvd2[2]
>[    1.829694] xhci_hcd 0000:00:14.0: @ffff880409a5c014 (virt) @409a5c014 (dma) 0x000000 - rsvd2[3]
>[    1.829698] xhci_hcd 0000:00:14.0: @ffff880409a5c018 (virt) @409a5c018 (dma) 0x000000 - rsvd2[4]
>[    1.829701] xhci_hcd 0000:00:14.0: @ffff880409a5c01c (virt) @409a5c01c (dma) 0x000000 - rsvd2[5]
>[    1.829704] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.829708] xhci_hcd 0000:00:14.0: @ffff880409a5c020 (virt) @409a5c020 (dma) 0x20400000 - dev_info
>[    1.829711] xhci_hcd 0000:00:14.0: @ffff880409a5c024 (virt) @409a5c024 (dma) 0x100000 - dev_info2
>[    1.829714] xhci_hcd 0000:00:14.0: @ffff880409a5c028 (virt) @409a5c028 (dma) 0x000000 - tt_info
>[    1.829717] xhci_hcd 0000:00:14.0: @ffff880409a5c02c (virt) @409a5c02c (dma) 0x000000 - dev_state
>[    1.829721] xhci_hcd 0000:00:14.0: @ffff880409a5c030 (virt) @409a5c030 (dma) 0x000000 - rsvd[0]
>[    1.829724] xhci_hcd 0000:00:14.0: @ffff880409a5c034 (virt) @409a5c034 (dma) 0x000000 - rsvd[1]
>[    1.829728] xhci_hcd 0000:00:14.0: @ffff880409a5c038 (virt) @409a5c038 (dma) 0x000000 - rsvd[2]
>[    1.829731] xhci_hcd 0000:00:14.0: @ffff880409a5c03c (virt) @409a5c03c (dma) 0x000000 - rsvd[3]
>[    1.829733] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.829736] xhci_hcd 0000:00:14.0: @ffff880409a5c040 (virt) @409a5c040 (dma) 0x000000 - ep_info
>[    1.829738] xhci_hcd 0000:00:14.0: @ffff880409a5c044 (virt) @409a5c044 (dma) 0x2000026 - ep_info2
>[    1.829740] xhci_hcd 0000:00:14.0: @ffff880409a5c048 (virt) @409a5c048 (dma) 0x409a76401 - deq
>[    1.829742] xhci_hcd 0000:00:14.0: @ffff880409a5c050 (virt) @409a5c050 (dma) 0x000000 - tx_info
>[    1.829744] xhci_hcd 0000:00:14.0: @ffff880409a5c054 (virt) @409a5c054 (dma) 0x000000 - rsvd[0]
>[    1.829746] xhci_hcd 0000:00:14.0: @ffff880409a5c058 (virt) @409a5c058 (dma) 0x000000 - rsvd[1]
>[    1.829749] xhci_hcd 0000:00:14.0: @ffff880409a5c05c (virt) @409a5c05c (dma) 0x000000 - rsvd[2]
>[    1.829751] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.829753] xhci_hcd 0000:00:14.0: @ffff880409a5c060 (virt) @409a5c060 (dma) 0x000000 - ep_info
>[    1.829755] xhci_hcd 0000:00:14.0: @ffff880409a5c064 (virt) @409a5c064 (dma) 0x000000 - ep_info2
>[    1.829757] xhci_hcd 0000:00:14.0: @ffff880409a5c068 (virt) @409a5c068 (dma) 0x000000 - deq
>[    1.829759] xhci_hcd 0000:00:14.0: @ffff880409a5c070 (virt) @409a5c070 (dma) 0x000000 - tx_info
>[    1.829761] xhci_hcd 0000:00:14.0: @ffff880409a5c074 (virt) @409a5c074 (dma) 0x000000 - rsvd[0]
>[    1.829763] xhci_hcd 0000:00:14.0: @ffff880409a5c078 (virt) @409a5c078 (dma) 0x000000 - rsvd[1]
>[    1.829765] xhci_hcd 0000:00:14.0: @ffff880409a5c07c (virt) @409a5c07c (dma) 0x000000 - rsvd[2]
>[    1.829767] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.829769] xhci_hcd 0000:00:14.0: @ffff880409a5c080 (virt) @409a5c080 (dma) 0x000000 - ep_info
>[    1.829772] xhci_hcd 0000:00:14.0: @ffff880409a5c084 (virt) @409a5c084 (dma) 0x4000436 - ep_info2
>[    1.829774] xhci_hcd 0000:00:14.0: @ffff880409a5c088 (virt) @409a5c088 (dma) 0x409a8d001 - deq
>[    1.829776] xhci_hcd 0000:00:14.0: @ffff880409a5c090 (virt) @409a5c090 (dma) 0x000000 - tx_info
>[    1.829778] xhci_hcd 0000:00:14.0: @ffff880409a5c094 (virt) @409a5c094 (dma) 0x000000 - rsvd[0]
>[    1.829780] xhci_hcd 0000:00:14.0: @ffff880409a5c098 (virt) @409a5c098 (dma) 0x000000 - rsvd[1]
>[    1.829782] xhci_hcd 0000:00:14.0: @ffff880409a5c09c (virt) @409a5c09c (dma) 0x000000 - rsvd[2]
>[    1.829784] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.829786] xhci_hcd 0000:00:14.0: @ffff880409a5c0a0 (virt) @409a5c0a0 (dma) 0x000000 - ep_info
>[    1.829788] xhci_hcd 0000:00:14.0: @ffff880409a5c0a4 (virt) @409a5c0a4 (dma) 0x4000416 - ep_info2
>[    1.829790] xhci_hcd 0000:00:14.0: @ffff880409a5c0a8 (virt) @409a5c0a8 (dma) 0x409a8d801 - deq
>[    1.829792] xhci_hcd 0000:00:14.0: @ffff880409a5c0b0 (virt) @409a5c0b0 (dma) 0x000000 - tx_info
>[    1.829794] xhci_hcd 0000:00:14.0: @ffff880409a5c0b4 (virt) @409a5c0b4 (dma) 0x000000 - rsvd[0]
>[    1.829797] xhci_hcd 0000:00:14.0: @ffff880409a5c0b8 (virt) @409a5c0b8 (dma) 0x000000 - rsvd[1]
>[    1.829799] xhci_hcd 0000:00:14.0: @ffff880409a5c0bc (virt) @409a5c0bc (dma) 0x000000 - rsvd[2]
>[    1.829801] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.829981] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.829987] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.829989] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.829991] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.829993] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.829995] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x100000 - dev_info2
>[    1.829997] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.829999] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.830001] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.830003] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.830006] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.830008] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.830022] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.830025] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.830028] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.830031] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.830034] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.830038] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.830041] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.830043] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.830045] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.830047] xhci_hcd 0000:00:14.0: @ffff88040b731040 (virt) @40b731040 (dma) 0x000000 - ep_info
>[    1.830060] xhci_hcd 0000:00:14.0: @ffff88040b731044 (virt) @40b731044 (dma) 0x000000 - ep_info2
>[    1.830063] xhci_hcd 0000:00:14.0: @ffff88040b731048 (virt) @40b731048 (dma) 0x000000 - deq
>[    1.830065] xhci_hcd 0000:00:14.0: @ffff88040b731050 (virt) @40b731050 (dma) 0x000000 - tx_info
>[    1.830068] xhci_hcd 0000:00:14.0: @ffff88040b731054 (virt) @40b731054 (dma) 0x000000 - rsvd[0]
>[    1.830070] xhci_hcd 0000:00:14.0: @ffff88040b731058 (virt) @40b731058 (dma) 0x000000 - rsvd[1]
>[    1.830072] xhci_hcd 0000:00:14.0: @ffff88040b73105c (virt) @40b73105c (dma) 0x000000 - rsvd[2]
>[    1.830075] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.830077] xhci_hcd 0000:00:14.0: @ffff88040b731060 (virt) @40b731060 (dma) 0x000001 - ep_info
>[    1.830079] xhci_hcd 0000:00:14.0: @ffff88040b731064 (virt) @40b731064 (dma) 0x4000436 - ep_info2
>[    1.830082] xhci_hcd 0000:00:14.0: @ffff88040b731068 (virt) @40b731068 (dma) 0x409a8d001 - deq
>[    1.830084] xhci_hcd 0000:00:14.0: @ffff88040b731070 (virt) @40b731070 (dma) 0x000000 - tx_info
>[    1.830087] xhci_hcd 0000:00:14.0: @ffff88040b731074 (virt) @40b731074 (dma) 0x000000 - rsvd[0]
>[    1.830089] xhci_hcd 0000:00:14.0: @ffff88040b731078 (virt) @40b731078 (dma) 0x000000 - rsvd[1]
>[    1.830091] xhci_hcd 0000:00:14.0: @ffff88040b73107c (virt) @40b73107c (dma) 0x000000 - rsvd[2]
>[    1.830094] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.830096] xhci_hcd 0000:00:14.0: @ffff88040b731080 (virt) @40b731080 (dma) 0x000001 - ep_info
>[    1.830098] xhci_hcd 0000:00:14.0: @ffff88040b731084 (virt) @40b731084 (dma) 0x4000416 - ep_info2
>[    1.830101] xhci_hcd 0000:00:14.0: @ffff88040b731088 (virt) @40b731088 (dma) 0x409a8d801 - deq
>[    1.830103] xhci_hcd 0000:00:14.0: @ffff88040b731090 (virt) @40b731090 (dma) 0x000000 - tx_info
>[    1.830106] xhci_hcd 0000:00:14.0: @ffff88040b731094 (virt) @40b731094 (dma) 0x000000 - rsvd[0]
>[    1.830108] xhci_hcd 0000:00:14.0: @ffff88040b731098 (virt) @40b731098 (dma) 0x000000 - rsvd[1]
>[    1.830110] xhci_hcd 0000:00:14.0: @ffff88040b73109c (virt) @40b73109c (dma) 0x000000 - rsvd[2]
>[    1.830115] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.830118] xhci_hcd 0000:00:14.0: Endpoint 0x2 not halted, refusing to reset.
>[    1.830610] xhci_hcd 0000:00:14.0: Set up evaluate context for LPM MEL change.
>[    1.830612] xhci_hcd 0000:00:14.0: Slot 3 Input Context:
>[    1.830615] xhci_hcd 0000:00:14.0: @ffff88040bedb000 (virt) @40bedb000 (dma) 0x000000 - drop flags
>[    1.830617] xhci_hcd 0000:00:14.0: @ffff88040bedb004 (virt) @40bedb004 (dma) 0x000001 - add flags
>[    1.830620] xhci_hcd 0000:00:14.0: @ffff88040bedb008 (virt) @40bedb008 (dma) 0x000000 - rsvd2[0]
>[    1.830622] xhci_hcd 0000:00:14.0: @ffff88040bedb00c (virt) @40bedb00c (dma) 0x000000 - rsvd2[1]
>[    1.830625] xhci_hcd 0000:00:14.0: @ffff88040bedb010 (virt) @40bedb010 (dma) 0x000000 - rsvd2[2]
>[    1.830627] xhci_hcd 0000:00:14.0: @ffff88040bedb014 (virt) @40bedb014 (dma) 0x000000 - rsvd2[3]
>[    1.830630] xhci_hcd 0000:00:14.0: @ffff88040bedb018 (virt) @40bedb018 (dma) 0x000000 - rsvd2[4]
>[    1.830632] xhci_hcd 0000:00:14.0: @ffff88040bedb01c (virt) @40bedb01c (dma) 0x000000 - rsvd2[5]
>[    1.830634] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.830636] xhci_hcd 0000:00:14.0: @ffff88040bedb020 (virt) @40bedb020 (dma) 0x20400000 - dev_info
>[    1.830639] xhci_hcd 0000:00:14.0: @ffff88040bedb024 (virt) @40bedb024 (dma) 0x10000a - dev_info2
>[    1.830641] xhci_hcd 0000:00:14.0: @ffff88040bedb028 (virt) @40bedb028 (dma) 0x000000 - tt_info
>[    1.830644] xhci_hcd 0000:00:14.0: @ffff88040bedb02c (virt) @40bedb02c (dma) 0x18000003 - dev_state
>[    1.830646] xhci_hcd 0000:00:14.0: @ffff88040bedb030 (virt) @40bedb030 (dma) 0x000000 - rsvd[0]
>[    1.830649] xhci_hcd 0000:00:14.0: @ffff88040bedb034 (virt) @40bedb034 (dma) 0x000000 - rsvd[1]
>[    1.830651] xhci_hcd 0000:00:14.0: @ffff88040bedb038 (virt) @40bedb038 (dma) 0x000000 - rsvd[2]
>[    1.830653] xhci_hcd 0000:00:14.0: @ffff88040bedb03c (virt) @40bedb03c (dma) 0x000000 - rsvd[3]
>[    1.830656] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.830658] xhci_hcd 0000:00:14.0: @ffff88040bedb040 (virt) @40bedb040 (dma) 0x000000 - ep_info
>[    1.830660] xhci_hcd 0000:00:14.0: @ffff88040bedb044 (virt) @40bedb044 (dma) 0x000000 - ep_info2
>[    1.830663] xhci_hcd 0000:00:14.0: @ffff88040bedb048 (virt) @40bedb048 (dma) 0x000000 - deq
>[    1.830665] xhci_hcd 0000:00:14.0: @ffff88040bedb050 (virt) @40bedb050 (dma) 0x000000 - tx_info
>[    1.830667] xhci_hcd 0000:00:14.0: @ffff88040bedb054 (virt) @40bedb054 (dma) 0x000000 - rsvd[0]
>[    1.830670] xhci_hcd 0000:00:14.0: @ffff88040bedb058 (virt) @40bedb058 (dma) 0x000000 - rsvd[1]
>[    1.830672] xhci_hcd 0000:00:14.0: @ffff88040bedb05c (virt) @40bedb05c (dma) 0x000000 - rsvd[2]
>[    1.830675] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.830692] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.830696] xhci_hcd 0000:00:14.0: Slot 3 Output Context:
>[    1.830697] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.830700] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.830702] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x10000a - dev_info2
>[    1.830705] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.830707] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.830710] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.830712] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.830714] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.830717] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.830719] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.830721] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.830724] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.830726] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.830729] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.830731] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.830734] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.830736] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.831316] xhci_hcd 0000:00:14.0: Set up evaluate context for LPM MEL change.
>[    1.831321] xhci_hcd 0000:00:14.0: Slot 3 Input Context:
>[    1.831324] xhci_hcd 0000:00:14.0: @ffff88040bedb000 (virt) @40bedb000 (dma) 0x000000 - drop flags
>[    1.831327] xhci_hcd 0000:00:14.0: @ffff88040bedb004 (virt) @40bedb004 (dma) 0x000001 - add flags
>[    1.831330] xhci_hcd 0000:00:14.0: @ffff88040bedb008 (virt) @40bedb008 (dma) 0x000000 - rsvd2[0]
>[    1.831333] xhci_hcd 0000:00:14.0: @ffff88040bedb00c (virt) @40bedb00c (dma) 0x000000 - rsvd2[1]
>[    1.831335] xhci_hcd 0000:00:14.0: @ffff88040bedb010 (virt) @40bedb010 (dma) 0x000000 - rsvd2[2]
>[    1.831338] xhci_hcd 0000:00:14.0: @ffff88040bedb014 (virt) @40bedb014 (dma) 0x000000 - rsvd2[3]
>[    1.831340] xhci_hcd 0000:00:14.0: @ffff88040bedb018 (virt) @40bedb018 (dma) 0x000000 - rsvd2[4]
>[    1.831343] xhci_hcd 0000:00:14.0: @ffff88040bedb01c (virt) @40bedb01c (dma) 0x000000 - rsvd2[5]
>[    1.831345] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.831347] xhci_hcd 0000:00:14.0: @ffff88040bedb020 (virt) @40bedb020 (dma) 0x20400000 - dev_info
>[    1.831349] xhci_hcd 0000:00:14.0: @ffff88040bedb024 (virt) @40bedb024 (dma) 0x1007ff - dev_info2
>[    1.831352] xhci_hcd 0000:00:14.0: @ffff88040bedb028 (virt) @40bedb028 (dma) 0x000000 - tt_info
>[    1.831354] xhci_hcd 0000:00:14.0: @ffff88040bedb02c (virt) @40bedb02c (dma) 0x18000003 - dev_state
>[    1.831357] xhci_hcd 0000:00:14.0: @ffff88040bedb030 (virt) @40bedb030 (dma) 0x000000 - rsvd[0]
>[    1.831359] xhci_hcd 0000:00:14.0: @ffff88040bedb034 (virt) @40bedb034 (dma) 0x000000 - rsvd[1]
>[    1.831362] xhci_hcd 0000:00:14.0: @ffff88040bedb038 (virt) @40bedb038 (dma) 0x000000 - rsvd[2]
>[    1.831364] xhci_hcd 0000:00:14.0: @ffff88040bedb03c (virt) @40bedb03c (dma) 0x000000 - rsvd[3]
>[    1.831367] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.831369] xhci_hcd 0000:00:14.0: @ffff88040bedb040 (virt) @40bedb040 (dma) 0x000000 - ep_info
>[    1.831371] xhci_hcd 0000:00:14.0: @ffff88040bedb044 (virt) @40bedb044 (dma) 0x000000 - ep_info2
>[    1.831374] xhci_hcd 0000:00:14.0: @ffff88040bedb048 (virt) @40bedb048 (dma) 0x000000 - deq
>[    1.831376] xhci_hcd 0000:00:14.0: @ffff88040bedb050 (virt) @40bedb050 (dma) 0x000000 - tx_info
>[    1.831379] xhci_hcd 0000:00:14.0: @ffff88040bedb054 (virt) @40bedb054 (dma) 0x000000 - rsvd[0]
>[    1.831381] xhci_hcd 0000:00:14.0: @ffff88040bedb058 (virt) @40bedb058 (dma) 0x000000 - rsvd[1]
>[    1.831384] xhci_hcd 0000:00:14.0: @ffff88040bedb05c (virt) @40bedb05c (dma) 0x000000 - rsvd[2]
>[    1.831386] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.831407] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.831411] xhci_hcd 0000:00:14.0: Slot 3 Output Context:
>[    1.831413] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.831415] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.831418] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x1007ff - dev_info2
>[    1.831420] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.831423] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.831425] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.831427] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.831430] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.831432] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.831435] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.831437] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.831439] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.831442] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.831444] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.831447] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.831449] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.831451] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.831767] usb 3-1: adding 3-1:1.0 (config #1, interface 0)
>[    1.831810] usb-storage 3-1:1.0: usb_probe_interface
>[    1.831819] usb-storage 3-1:1.0: usb_probe_interface - got id
>[    1.832520] xhci_hcd 0000:00:14.0: Set up evaluate context for LPM MEL change.
>[    1.832525] xhci_hcd 0000:00:14.0: Slot 3 Input Context:
>[    1.832529] xhci_hcd 0000:00:14.0: @ffff88040bedb000 (virt) @40bedb000 (dma) 0x000000 - drop flags
>[    1.832532] xhci_hcd 0000:00:14.0: @ffff88040bedb004 (virt) @40bedb004 (dma) 0x000001 - add flags
>[    1.832535] xhci_hcd 0000:00:14.0: @ffff88040bedb008 (virt) @40bedb008 (dma) 0x000000 - rsvd2[0]
>[    1.832537] xhci_hcd 0000:00:14.0: @ffff88040bedb00c (virt) @40bedb00c (dma) 0x000000 - rsvd2[1]
>[    1.832540] xhci_hcd 0000:00:14.0: @ffff88040bedb010 (virt) @40bedb010 (dma) 0x000000 - rsvd2[2]
>[    1.832542] xhci_hcd 0000:00:14.0: @ffff88040bedb014 (virt) @40bedb014 (dma) 0x000000 - rsvd2[3]
>[    1.832545] xhci_hcd 0000:00:14.0: @ffff88040bedb018 (virt) @40bedb018 (dma) 0x000000 - rsvd2[4]
>[    1.832547] xhci_hcd 0000:00:14.0: @ffff88040bedb01c (virt) @40bedb01c (dma) 0x000000 - rsvd2[5]
>[    1.832549] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.832552] xhci_hcd 0000:00:14.0: @ffff88040bedb020 (virt) @40bedb020 (dma) 0x20400000 - dev_info
>[    1.832554] xhci_hcd 0000:00:14.0: @ffff88040bedb024 (virt) @40bedb024 (dma) 0x100000 - dev_info2
>[    1.832557] xhci_hcd 0000:00:14.0: @ffff88040bedb028 (virt) @40bedb028 (dma) 0x000000 - tt_info
>[    1.832559] xhci_hcd 0000:00:14.0: @ffff88040bedb02c (virt) @40bedb02c (dma) 0x18000003 - dev_state
>[    1.832562] xhci_hcd 0000:00:14.0: @ffff88040bedb030 (virt) @40bedb030 (dma) 0x000000 - rsvd[0]
>[    1.832564] xhci_hcd 0000:00:14.0: @ffff88040bedb034 (virt) @40bedb034 (dma) 0x000000 - rsvd[1]
>[    1.832566] xhci_hcd 0000:00:14.0: @ffff88040bedb038 (virt) @40bedb038 (dma) 0x000000 - rsvd[2]
>[    1.832569] xhci_hcd 0000:00:14.0: @ffff88040bedb03c (virt) @40bedb03c (dma) 0x000000 - rsvd[3]
>[    1.832572] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.832574] xhci_hcd 0000:00:14.0: @ffff88040bedb040 (virt) @40bedb040 (dma) 0x000000 - ep_info
>[    1.832576] xhci_hcd 0000:00:14.0: @ffff88040bedb044 (virt) @40bedb044 (dma) 0x000000 - ep_info2
>[    1.832579] xhci_hcd 0000:00:14.0: @ffff88040bedb048 (virt) @40bedb048 (dma) 0x000000 - deq
>[    1.832581] xhci_hcd 0000:00:14.0: @ffff88040bedb050 (virt) @40bedb050 (dma) 0x000000 - tx_info
>[    1.832584] xhci_hcd 0000:00:14.0: @ffff88040bedb054 (virt) @40bedb054 (dma) 0x000000 - rsvd[0]
>[    1.832586] xhci_hcd 0000:00:14.0: @ffff88040bedb058 (virt) @40bedb058 (dma) 0x000000 - rsvd[1]
>[    1.832589] xhci_hcd 0000:00:14.0: @ffff88040bedb05c (virt) @40bedb05c (dma) 0x000000 - rsvd[2]
>[    1.832591] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.832610] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.832614] xhci_hcd 0000:00:14.0: Slot 3 Output Context:
>[    1.832616] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.832618] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.832620] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x100000 - dev_info2
>[    1.832623] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.832625] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.832628] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.832630] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.832633] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.832635] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.832637] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.832640] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.832642] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.832645] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.832647] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.832649] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.832652] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.832654] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.832657] usb-storage 3-1:1.0: USB Mass Storage device detected
>[    1.832773] scsi6 : usb-storage 3-1:1.0
>[    1.833095] xhci_hcd 0000:00:14.0: Set up evaluate context for LPM MEL change.
>[    1.833100] xhci_hcd 0000:00:14.0: Slot 3 Input Context:
>[    1.833103] xhci_hcd 0000:00:14.0: @ffff88040bedb000 (virt) @40bedb000 (dma) 0x000000 - drop flags
>[    1.833106] xhci_hcd 0000:00:14.0: @ffff88040bedb004 (virt) @40bedb004 (dma) 0x000001 - add flags
>[    1.833109] xhci_hcd 0000:00:14.0: @ffff88040bedb008 (virt) @40bedb008 (dma) 0x000000 - rsvd2[0]
>[    1.833112] xhci_hcd 0000:00:14.0: @ffff88040bedb00c (virt) @40bedb00c (dma) 0x000000 - rsvd2[1]
>[    1.833114] xhci_hcd 0000:00:14.0: @ffff88040bedb010 (virt) @40bedb010 (dma) 0x000000 - rsvd2[2]
>[    1.833116] xhci_hcd 0000:00:14.0: @ffff88040bedb014 (virt) @40bedb014 (dma) 0x000000 - rsvd2[3]
>[    1.833119] xhci_hcd 0000:00:14.0: @ffff88040bedb018 (virt) @40bedb018 (dma) 0x000000 - rsvd2[4]
>[    1.833121] xhci_hcd 0000:00:14.0: @ffff88040bedb01c (virt) @40bedb01c (dma) 0x000000 - rsvd2[5]
>[    1.833123] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.833126] xhci_hcd 0000:00:14.0: @ffff88040bedb020 (virt) @40bedb020 (dma) 0x20400000 - dev_info
>[    1.833128] xhci_hcd 0000:00:14.0: @ffff88040bedb024 (virt) @40bedb024 (dma) 0x10000a - dev_info2
>[    1.833130] xhci_hcd 0000:00:14.0: @ffff88040bedb028 (virt) @40bedb028 (dma) 0x000000 - tt_info
>[    1.833133] xhci_hcd 0000:00:14.0: @ffff88040bedb02c (virt) @40bedb02c (dma) 0x18000003 - dev_state
>[    1.833135] xhci_hcd 0000:00:14.0: @ffff88040bedb030 (virt) @40bedb030 (dma) 0x000000 - rsvd[0]
>[    1.833138] xhci_hcd 0000:00:14.0: @ffff88040bedb034 (virt) @40bedb034 (dma) 0x000000 - rsvd[1]
>[    1.833140] xhci_hcd 0000:00:14.0: @ffff88040bedb038 (virt) @40bedb038 (dma) 0x000000 - rsvd[2]
>[    1.833142] xhci_hcd 0000:00:14.0: @ffff88040bedb03c (virt) @40bedb03c (dma) 0x000000 - rsvd[3]
>[    1.833145] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.833148] xhci_hcd 0000:00:14.0: @ffff88040bedb040 (virt) @40bedb040 (dma) 0x000000 - ep_info
>[    1.833150] xhci_hcd 0000:00:14.0: @ffff88040bedb044 (virt) @40bedb044 (dma) 0x000000 - ep_info2
>[    1.833153] xhci_hcd 0000:00:14.0: @ffff88040bedb048 (virt) @40bedb048 (dma) 0x000000 - deq
>[    1.833155] xhci_hcd 0000:00:14.0: @ffff88040bedb050 (virt) @40bedb050 (dma) 0x000000 - tx_info
>[    1.833158] xhci_hcd 0000:00:14.0: @ffff88040bedb054 (virt) @40bedb054 (dma) 0x000000 - rsvd[0]
>[    1.833160] xhci_hcd 0000:00:14.0: @ffff88040bedb058 (virt) @40bedb058 (dma) 0x000000 - rsvd[1]
>[    1.833162] xhci_hcd 0000:00:14.0: @ffff88040bedb05c (virt) @40bedb05c (dma) 0x000000 - rsvd[2]
>[    1.833165] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.833184] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.833187] xhci_hcd 0000:00:14.0: Slot 3 Output Context:
>[    1.833189] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.833192] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.833194] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x10000a - dev_info2
>[    1.833197] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.833199] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.833201] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.833204] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.833206] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.833209] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.833211] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.833213] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.833216] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.833218] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.833221] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.833223] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.833225] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.833228] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.833838] xhci_hcd 0000:00:14.0: Set up evaluate context for LPM MEL change.
>[    1.833842] xhci_hcd 0000:00:14.0: Slot 3 Input Context:
>[    1.833846] xhci_hcd 0000:00:14.0: @ffff88040bedb000 (virt) @40bedb000 (dma) 0x000000 - drop flags
>[    1.833849] xhci_hcd 0000:00:14.0: @ffff88040bedb004 (virt) @40bedb004 (dma) 0x000001 - add flags
>[    1.833852] xhci_hcd 0000:00:14.0: @ffff88040bedb008 (virt) @40bedb008 (dma) 0x000000 - rsvd2[0]
>[    1.833854] xhci_hcd 0000:00:14.0: @ffff88040bedb00c (virt) @40bedb00c (dma) 0x000000 - rsvd2[1]
>[    1.833857] xhci_hcd 0000:00:14.0: @ffff88040bedb010 (virt) @40bedb010 (dma) 0x000000 - rsvd2[2]
>[    1.833859] xhci_hcd 0000:00:14.0: @ffff88040bedb014 (virt) @40bedb014 (dma) 0x000000 - rsvd2[3]
>[    1.833862] xhci_hcd 0000:00:14.0: @ffff88040bedb018 (virt) @40bedb018 (dma) 0x000000 - rsvd2[4]
>[    1.833864] xhci_hcd 0000:00:14.0: @ffff88040bedb01c (virt) @40bedb01c (dma) 0x000000 - rsvd2[5]
>[    1.833866] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.833869] xhci_hcd 0000:00:14.0: @ffff88040bedb020 (virt) @40bedb020 (dma) 0x20400000 - dev_info
>[    1.833871] xhci_hcd 0000:00:14.0: @ffff88040bedb024 (virt) @40bedb024 (dma) 0x1007ff - dev_info2
>[    1.833873] xhci_hcd 0000:00:14.0: @ffff88040bedb028 (virt) @40bedb028 (dma) 0x000000 - tt_info
>[    1.833876] xhci_hcd 0000:00:14.0: @ffff88040bedb02c (virt) @40bedb02c (dma) 0x18000003 - dev_state
>[    1.833878] xhci_hcd 0000:00:14.0: @ffff88040bedb030 (virt) @40bedb030 (dma) 0x000000 - rsvd[0]
>[    1.833881] xhci_hcd 0000:00:14.0: @ffff88040bedb034 (virt) @40bedb034 (dma) 0x000000 - rsvd[1]
>[    1.833883] xhci_hcd 0000:00:14.0: @ffff88040bedb038 (virt) @40bedb038 (dma) 0x000000 - rsvd[2]
>[    1.833886] xhci_hcd 0000:00:14.0: @ffff88040bedb03c (virt) @40bedb03c (dma) 0x000000 - rsvd[3]
>[    1.833888] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.833891] xhci_hcd 0000:00:14.0: @ffff88040bedb040 (virt) @40bedb040 (dma) 0x000000 - ep_info
>[    1.833893] xhci_hcd 0000:00:14.0: @ffff88040bedb044 (virt) @40bedb044 (dma) 0x000000 - ep_info2
>[    1.833895] xhci_hcd 0000:00:14.0: @ffff88040bedb048 (virt) @40bedb048 (dma) 0x000000 - deq
>[    1.833898] xhci_hcd 0000:00:14.0: @ffff88040bedb050 (virt) @40bedb050 (dma) 0x000000 - tx_info
>[    1.833900] xhci_hcd 0000:00:14.0: @ffff88040bedb054 (virt) @40bedb054 (dma) 0x000000 - rsvd[0]
>[    1.833903] xhci_hcd 0000:00:14.0: @ffff88040bedb058 (virt) @40bedb058 (dma) 0x000000 - rsvd[1]
>[    1.833905] xhci_hcd 0000:00:14.0: @ffff88040bedb05c (virt) @40bedb05c (dma) 0x000000 - rsvd[2]
>[    1.833908] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.833929] xhci_hcd 0000:00:14.0: Successful evaluate context command
>[    1.833932] xhci_hcd 0000:00:14.0: Slot 3 Output Context:
>[    1.833934] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.833937] xhci_hcd 0000:00:14.0: @ffff88040b731000 (virt) @40b731000 (dma) 0x20400000 - dev_info
>[    1.833939] xhci_hcd 0000:00:14.0: @ffff88040b731004 (virt) @40b731004 (dma) 0x1007ff - dev_info2
>[    1.833942] xhci_hcd 0000:00:14.0: @ffff88040b731008 (virt) @40b731008 (dma) 0x000000 - tt_info
>[    1.833944] xhci_hcd 0000:00:14.0: @ffff88040b73100c (virt) @40b73100c (dma) 0x18000003 - dev_state
>[    1.833947] xhci_hcd 0000:00:14.0: @ffff88040b731010 (virt) @40b731010 (dma) 0x000000 - rsvd[0]
>[    1.833949] xhci_hcd 0000:00:14.0: @ffff88040b731014 (virt) @40b731014 (dma) 0x000000 - rsvd[1]
>[    1.833952] xhci_hcd 0000:00:14.0: @ffff88040b731018 (virt) @40b731018 (dma) 0x000000 - rsvd[2]
>[    1.833954] xhci_hcd 0000:00:14.0: @ffff88040b73101c (virt) @40b73101c (dma) 0x000000 - rsvd[3]
>[    1.833956] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.833959] xhci_hcd 0000:00:14.0: @ffff88040b731020 (virt) @40b731020 (dma) 0x000001 - ep_info
>[    1.833961] xhci_hcd 0000:00:14.0: @ffff88040b731024 (virt) @40b731024 (dma) 0x2000026 - ep_info2
>[    1.833963] xhci_hcd 0000:00:14.0: @ffff88040b731028 (virt) @40b731028 (dma) 0x409a76401 - deq
>[    1.833966] xhci_hcd 0000:00:14.0: @ffff88040b731030 (virt) @40b731030 (dma) 0x000000 - tx_info
>[    1.833968] xhci_hcd 0000:00:14.0: @ffff88040b731034 (virt) @40b731034 (dma) 0x000000 - rsvd[0]
>[    1.833971] xhci_hcd 0000:00:14.0: @ffff88040b731038 (virt) @40b731038 (dma) 0x000000 - rsvd[1]
>[    1.833973] xhci_hcd 0000:00:14.0: @ffff88040b73103c (virt) @40b73103c (dma) 0x000000 - rsvd[2]
>[    1.834379] hub 1-1:1.0: state 7 ports 8 chg 0000 evt 0000
>[    1.834387] hub 2-14:1.0: state 7 ports 2 chg 0006 evt 0000
>[    1.834398] hub 1-1:1.0: hub_suspend
>[    1.834404] usb 1-1: unlink qh256-0001/ffff88040c364e00 start 1 [1/0 us]
>[    1.834666] hub 2-14:1.0: port 1, status 0301, change 0000, 1.5 Mb/s
>[    1.834953] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.834987] xhci_hcd 0000:00:14.0: Slot 4 output ctx = 0x40b554000 (dma)
>[    1.834992] xhci_hcd 0000:00:14.0: Slot 4 input ctx = 0x40beaa000 (dma)
>[    1.834999] xhci_hcd 0000:00:14.0: Set slot id 4 dcbaa entry ffff88040bed9020 to 0x40b554000
>[    1.836249] usb 1-1: usb auto-suspend, wakeup 1
>[    1.847056] hub 1-0:1.0: hub_suspend
>[    1.847069] usb usb1: bus auto-suspend, wakeup 1
>[    1.847072] ehci-pci 0000:00:1d.0: suspend root hub
>[    1.897337] usb 2-14.1: new low-speed USB device number 4 using xhci_hcd
>[    1.897346] xhci_hcd 0000:00:14.0: Set root hub portnum to 14
>[    1.897349] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 14
>[    1.897353] xhci_hcd 0000:00:14.0: udev->tt = ffff88040bb6fea0
>[    1.897357] xhci_hcd 0000:00:14.0: udev->ttport = 0x1
>[    1.897360] xhci_hcd 0000:00:14.0: Slot ID 4 Input Context:
>[    1.897365] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0x000000 - drop flags
>[    1.897369] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x000003 - add flags
>[    1.897373] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000000 - rsvd2[0]
>[    1.897377] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x000000 - rsvd2[1]
>[    1.897381] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd2[2]
>[    1.897384] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd2[3]
>[    1.897388] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd2[4]
>[    1.897392] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd2[5]
>[    1.897395] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.897398] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0xa200001 - dev_info
>[    1.897402] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x0e0000 - dev_info2
>[    1.897405] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x000102 - tt_info
>[    1.897409] xhci_hcd 0000:00:14.0: @ffff88040beaa02c (virt) @40beaa02c (dma) 0x000000 - dev_state
>[    1.897413] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - rsvd[0]
>[    1.897416] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[1]
>[    1.897420] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[2]
>[    1.897424] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[3]
>[    1.897427] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.897431] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[    1.897435] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x080026 - ep_info2
>[    1.897438] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x409bf7401 - deq
>[    1.897442] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[    1.897446] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[    1.897449] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[    1.897453] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[    1.897456] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.897460] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x000000 - ep_info
>[    1.897463] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x000000 - ep_info2
>[    1.897467] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x000000 - deq
>[    1.897470] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x000000 - tx_info
>[    1.897474] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[    1.897478] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[    1.897481] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[    1.897485] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.897488] xhci_hcd 0000:00:14.0: @ffff88040beaa080 (virt) @40beaa080 (dma) 0x000000 - ep_info
>[    1.897492] xhci_hcd 0000:00:14.0: @ffff88040beaa084 (virt) @40beaa084 (dma) 0x000000 - ep_info2
>[    1.897495] xhci_hcd 0000:00:14.0: @ffff88040beaa088 (virt) @40beaa088 (dma) 0x000000 - deq
>[    1.897499] xhci_hcd 0000:00:14.0: @ffff88040beaa090 (virt) @40beaa090 (dma) 0x000000 - tx_info
>[    1.897503] xhci_hcd 0000:00:14.0: @ffff88040beaa094 (virt) @40beaa094 (dma) 0x000000 - rsvd[0]
>[    1.897506] xhci_hcd 0000:00:14.0: @ffff88040beaa098 (virt) @40beaa098 (dma) 0x000000 - rsvd[1]
>[    1.897510] xhci_hcd 0000:00:14.0: @ffff88040beaa09c (virt) @40beaa09c (dma) 0x000000 - rsvd[2]
>[    1.897513] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.897801] xhci_hcd 0000:00:14.0: Successful Address Device command
>[    1.897810] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[    1.897815] xhci_hcd 0000:00:14.0: Slot ID 4 dcbaa entry @ffff88040bed9020 = 0x0000040b554000
>[    1.897819] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40b554000
>[    1.897823] xhci_hcd 0000:00:14.0: Slot ID 4 Input Context:
>[    1.897827] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0x000000 - drop flags
>[    1.897831] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x000003 - add flags
>[    1.897835] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000000 - rsvd2[0]
>[    1.897838] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x000000 - rsvd2[1]
>[    1.897842] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd2[2]
>[    1.897846] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd2[3]
>[    1.897849] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd2[4]
>[    1.897853] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd2[5]
>[    1.897856] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.897859] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0xa200001 - dev_info
>[    1.897863] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x0e0000 - dev_info2
>[    1.897867] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x000102 - tt_info
>[    1.897870] xhci_hcd 0000:00:14.0: @ffff88040beaa02c (virt) @40beaa02c (dma) 0x000000 - dev_state
>[    1.897874] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - rsvd[0]
>[    1.897878] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[1]
>[    1.897881] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[2]
>[    1.897885] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[3]
>[    1.897889] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.897893] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[    1.897896] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x080026 - ep_info2
>[    1.897900] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x409bf7401 - deq
>[    1.897903] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[    1.897907] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[    1.897911] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[    1.897914] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[    1.897918] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.897922] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x000000 - ep_info
>[    1.897925] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x000000 - ep_info2
>[    1.897929] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x000000 - deq
>[    1.897932] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x000000 - tx_info
>[    1.897936] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[    1.897939] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[    1.897943] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[    1.897946] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.897950] xhci_hcd 0000:00:14.0: @ffff88040beaa080 (virt) @40beaa080 (dma) 0x000000 - ep_info
>[    1.897953] xhci_hcd 0000:00:14.0: @ffff88040beaa084 (virt) @40beaa084 (dma) 0x000000 - ep_info2
>[    1.897957] xhci_hcd 0000:00:14.0: @ffff88040beaa088 (virt) @40beaa088 (dma) 0x000000 - deq
>[    1.897960] xhci_hcd 0000:00:14.0: @ffff88040beaa090 (virt) @40beaa090 (dma) 0x000000 - tx_info
>[    1.897964] xhci_hcd 0000:00:14.0: @ffff88040beaa094 (virt) @40beaa094 (dma) 0x000000 - rsvd[0]
>[    1.897968] xhci_hcd 0000:00:14.0: @ffff88040beaa098 (virt) @40beaa098 (dma) 0x000000 - rsvd[1]
>[    1.897971] xhci_hcd 0000:00:14.0: @ffff88040beaa09c (virt) @40beaa09c (dma) 0x000000 - rsvd[2]
>[    1.897974] xhci_hcd 0000:00:14.0: Slot ID 4 Output Context:
>[    1.897977] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.897981] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0xa200001 - dev_info
>[    1.897984] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x0e0000 - dev_info2
>[    1.897988] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000102 - tt_info
>[    1.897991] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x10000004 - dev_state
>[    1.897995] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd[0]
>[    1.897999] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd[1]
>[    1.898002] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd[2]
>[    1.898016] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd[3]
>[    1.898020] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.898023] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0x000001 - ep_info
>[    1.898027] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x080026 - ep_info2
>[    1.898030] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x409bf7401 - deq
>[    1.898034] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - tx_info
>[    1.898038] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[0]
>[    1.898041] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[1]
>[    1.898045] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[2]
>[    1.898048] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.898052] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[    1.898055] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x000000 - ep_info2
>[    1.898059] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x000000 - deq
>[    1.898062] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[    1.898066] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[    1.898070] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[    1.898073] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[    1.898077] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.898080] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[    1.898083] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[    1.898087] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[    1.898090] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[    1.898094] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[    1.898098] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[    1.898101] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[    1.898105] xhci_hcd 0000:00:14.0: Internal device address = 5
>[    1.911628] usb 2-14.1: skipped 1 descriptor after interface
>[    1.911901] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.912147] usb 2-14.1: default language 0x0409
>[    1.912922] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.913676] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.913787] usb 2-14.1: udev 4, busnum 2, minor = 131
>[    1.913795] usb 2-14.1: New USB device found, idVendor=046d, idProduct=c05a
>[    1.913800] usb 2-14.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    1.913803] usb 2-14.1: Product: USB Optical Mouse
>[    1.913807] usb 2-14.1: Manufacturer: Logitech
>[    1.913940] usb 2-14.1: usb_probe_device
>[    1.913944] usb 2-14.1: configuration #1 chosen from 1 choice
>[    1.913955] usb 2-14.1: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[    1.913961] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 4, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x1a200001
>[    1.913965] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040b5ee800
>[    1.913968] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.913973] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0x000000 - drop flags
>[    1.913977] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x000009 - add flags
>[    1.913981] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000000 - rsvd2[0]
>[    1.913985] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x000000 - rsvd2[1]
>[    1.913988] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd2[2]
>[    1.913992] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd2[3]
>[    1.913996] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd2[4]
>[    1.913999] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd2[5]
>[    1.914002] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.914022] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x1a200001 - dev_info
>[    1.914028] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x0e0000 - dev_info2
>[    1.914034] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x000102 - tt_info
>[    1.914038] xhci_hcd 0000:00:14.0: @ffff88040beaa02c (virt) @40beaa02c (dma) 0x000000 - dev_state
>[    1.914042] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - rsvd[0]
>[    1.914045] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[1]
>[    1.914050] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[2]
>[    1.914056] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[3]
>[    1.914061] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.914067] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[    1.914073] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x080026 - ep_info2
>[    1.914079] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x409bf7401 - deq
>[    1.914085] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[    1.914091] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[    1.914098] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[    1.914104] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[    1.914110] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.914116] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x000000 - ep_info
>[    1.914122] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x000000 - ep_info2
>[    1.914128] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x000000 - deq
>[    1.914133] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x000000 - tx_info
>[    1.914139] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[    1.914145] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[    1.914151] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[    1.914157] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.914164] xhci_hcd 0000:00:14.0: @ffff88040beaa080 (virt) @40beaa080 (dma) 0x060000 - ep_info
>[    1.914169] xhci_hcd 0000:00:14.0: @ffff88040beaa084 (virt) @40beaa084 (dma) 0x04003e - ep_info2
>[    1.914175] xhci_hcd 0000:00:14.0: @ffff88040beaa088 (virt) @40beaa088 (dma) 0x40b69d001 - deq
>[    1.914182] xhci_hcd 0000:00:14.0: @ffff88040beaa090 (virt) @40beaa090 (dma) 0x040004 - tx_info
>[    1.914188] xhci_hcd 0000:00:14.0: @ffff88040beaa094 (virt) @40beaa094 (dma) 0x000000 - rsvd[0]
>[    1.914194] xhci_hcd 0000:00:14.0: @ffff88040beaa098 (virt) @40beaa098 (dma) 0x000000 - rsvd[1]
>[    1.914200] xhci_hcd 0000:00:14.0: @ffff88040beaa09c (virt) @40beaa09c (dma) 0x000000 - rsvd[2]
>[    1.914206] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.914433] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.914474] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.914481] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.914485] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.914490] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x1a200001 - dev_info
>[    1.914494] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x0e0000 - dev_info2
>[    1.914498] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000102 - tt_info
>[    1.914502] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x18000004 - dev_state
>[    1.914506] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd[0]
>[    1.914510] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd[1]
>[    1.914514] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd[2]
>[    1.914517] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd[3]
>[    1.914521] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.914525] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0x000001 - ep_info
>[    1.914529] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x080026 - ep_info2
>[    1.914533] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x409bf7401 - deq
>[    1.914536] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - tx_info
>[    1.914540] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[0]
>[    1.914543] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[1]
>[    1.914547] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[2]
>[    1.914551] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.914554] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[    1.914558] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x000000 - ep_info2
>[    1.914561] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x000000 - deq
>[    1.914565] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[    1.914569] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[    1.914572] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[    1.914576] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[    1.914579] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.914583] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x060001 - ep_info
>[    1.914586] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x04003e - ep_info2
>[    1.914590] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x40b69d001 - deq
>[    1.914593] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x040004 - tx_info
>[    1.914597] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[    1.914601] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[    1.914604] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[    1.914610] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.914923] usb 2-14.1: adding 2-14.1:1.0 (config #1, interface 0)
>[    1.914987] usbhid 2-14.1:1.0: usb_probe_interface
>[    1.914992] usbhid 2-14.1:1.0: usb_probe_interface - got id
>[    1.915223] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    1.915231] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    1.915236] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    1.915239] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    1.915242] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    1.915246] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    1.915250] xhci_hcd 0000:00:14.0: New dequeue segment = ffff8800dc9711e0 (virtual)
>[    1.915253] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409bf7590 (DMA)
>[    1.915257] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    1.915262] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff8800dc9711e0 (0x409bf7400 dma), new deq ptr = ffff880409bf7590 (0x409bf7590 dma), new cycle = 1
>[    1.915265] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.915272] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e4b40, len = 0, expected = 0, status = -32
>[    1.915280] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    1.915285] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409bf7591
>[    1.916884] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb2/2-14/2-14.1/2-14.1:1.0/input/input18
>[    1.917244] hid-generic 0003:046D:C05A.0001: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-14.1/input0
>[    1.917577] hub 2-14:1.0: port 2, status 0301, change 0000, 1.5 Mb/s
>[    1.917864] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.917949] xhci_hcd 0000:00:14.0: Slot 5 output ctx = 0x40b556000 (dma)
>[    1.917957] xhci_hcd 0000:00:14.0: Slot 5 input ctx = 0x40bb71000 (dma)
>[    1.917966] xhci_hcd 0000:00:14.0: Set slot id 5 dcbaa entry ffff88040bed9028 to 0x40b556000
>[    1.980048] xhci_hcd 0000:00:14.0: xhci_hub_status_data: stopping port polling.
>[    1.980346] usb 2-14.2: new low-speed USB device number 5 using xhci_hcd
>[    1.980356] xhci_hcd 0000:00:14.0: Set root hub portnum to 14
>[    1.980361] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 14
>[    1.980366] xhci_hcd 0000:00:14.0: udev->tt = ffff88040bb6fea0
>[    1.980370] xhci_hcd 0000:00:14.0: udev->ttport = 0x2
>[    1.980374] xhci_hcd 0000:00:14.0: Slot ID 5 Input Context:
>[    1.980382] xhci_hcd 0000:00:14.0: @ffff88040bb71000 (virt) @40bb71000 (dma) 0x000000 - drop flags
>[    1.980390] xhci_hcd 0000:00:14.0: @ffff88040bb71004 (virt) @40bb71004 (dma) 0x000003 - add flags
>[    1.980398] xhci_hcd 0000:00:14.0: @ffff88040bb71008 (virt) @40bb71008 (dma) 0x000000 - rsvd2[0]
>[    1.980406] xhci_hcd 0000:00:14.0: @ffff88040bb7100c (virt) @40bb7100c (dma) 0x000000 - rsvd2[1]
>[    1.980413] xhci_hcd 0000:00:14.0: @ffff88040bb71010 (virt) @40bb71010 (dma) 0x000000 - rsvd2[2]
>[    1.980420] xhci_hcd 0000:00:14.0: @ffff88040bb71014 (virt) @40bb71014 (dma) 0x000000 - rsvd2[3]
>[    1.980428] xhci_hcd 0000:00:14.0: @ffff88040bb71018 (virt) @40bb71018 (dma) 0x000000 - rsvd2[4]
>[    1.980436] xhci_hcd 0000:00:14.0: @ffff88040bb7101c (virt) @40bb7101c (dma) 0x000000 - rsvd2[5]
>[    1.980441] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.980448] xhci_hcd 0000:00:14.0: @ffff88040bb71020 (virt) @40bb71020 (dma) 0xa200002 - dev_info
>[    1.980453] xhci_hcd 0000:00:14.0: @ffff88040bb71024 (virt) @40bb71024 (dma) 0x0e0000 - dev_info2
>[    1.980457] xhci_hcd 0000:00:14.0: @ffff88040bb71028 (virt) @40bb71028 (dma) 0x000202 - tt_info
>[    1.980462] xhci_hcd 0000:00:14.0: @ffff88040bb7102c (virt) @40bb7102c (dma) 0x000000 - dev_state
>[    1.980466] xhci_hcd 0000:00:14.0: @ffff88040bb71030 (virt) @40bb71030 (dma) 0x000000 - rsvd[0]
>[    1.980471] xhci_hcd 0000:00:14.0: @ffff88040bb71034 (virt) @40bb71034 (dma) 0x000000 - rsvd[1]
>[    1.980476] xhci_hcd 0000:00:14.0: @ffff88040bb71038 (virt) @40bb71038 (dma) 0x000000 - rsvd[2]
>[    1.980480] xhci_hcd 0000:00:14.0: @ffff88040bb7103c (virt) @40bb7103c (dma) 0x000000 - rsvd[3]
>[    1.980485] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.980490] xhci_hcd 0000:00:14.0: @ffff88040bb71040 (virt) @40bb71040 (dma) 0x000000 - ep_info
>[    1.980494] xhci_hcd 0000:00:14.0: @ffff88040bb71044 (virt) @40bb71044 (dma) 0x080026 - ep_info2
>[    1.980499] xhci_hcd 0000:00:14.0: @ffff88040bb71048 (virt) @40bb71048 (dma) 0x40b69d801 - deq
>[    1.980503] xhci_hcd 0000:00:14.0: @ffff88040bb71050 (virt) @40bb71050 (dma) 0x000000 - tx_info
>[    1.980508] xhci_hcd 0000:00:14.0: @ffff88040bb71054 (virt) @40bb71054 (dma) 0x000000 - rsvd[0]
>[    1.980512] xhci_hcd 0000:00:14.0: @ffff88040bb71058 (virt) @40bb71058 (dma) 0x000000 - rsvd[1]
>[    1.980517] xhci_hcd 0000:00:14.0: @ffff88040bb7105c (virt) @40bb7105c (dma) 0x000000 - rsvd[2]
>[    1.980522] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.980526] xhci_hcd 0000:00:14.0: @ffff88040bb71060 (virt) @40bb71060 (dma) 0x000000 - ep_info
>[    1.980531] xhci_hcd 0000:00:14.0: @ffff88040bb71064 (virt) @40bb71064 (dma) 0x000000 - ep_info2
>[    1.980535] xhci_hcd 0000:00:14.0: @ffff88040bb71068 (virt) @40bb71068 (dma) 0x000000 - deq
>[    1.980539] xhci_hcd 0000:00:14.0: @ffff88040bb71070 (virt) @40bb71070 (dma) 0x000000 - tx_info
>[    1.980544] xhci_hcd 0000:00:14.0: @ffff88040bb71074 (virt) @40bb71074 (dma) 0x000000 - rsvd[0]
>[    1.980549] xhci_hcd 0000:00:14.0: @ffff88040bb71078 (virt) @40bb71078 (dma) 0x000000 - rsvd[1]
>[    1.980553] xhci_hcd 0000:00:14.0: @ffff88040bb7107c (virt) @40bb7107c (dma) 0x000000 - rsvd[2]
>[    1.980557] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.980562] xhci_hcd 0000:00:14.0: @ffff88040bb71080 (virt) @40bb71080 (dma) 0x000000 - ep_info
>[    1.980566] xhci_hcd 0000:00:14.0: @ffff88040bb71084 (virt) @40bb71084 (dma) 0x000000 - ep_info2
>[    1.980571] xhci_hcd 0000:00:14.0: @ffff88040bb71088 (virt) @40bb71088 (dma) 0x000000 - deq
>[    1.980575] xhci_hcd 0000:00:14.0: @ffff88040bb71090 (virt) @40bb71090 (dma) 0x000000 - tx_info
>[    1.980579] xhci_hcd 0000:00:14.0: @ffff88040bb71094 (virt) @40bb71094 (dma) 0x000000 - rsvd[0]
>[    1.980584] xhci_hcd 0000:00:14.0: @ffff88040bb71098 (virt) @40bb71098 (dma) 0x000000 - rsvd[1]
>[    1.980589] xhci_hcd 0000:00:14.0: @ffff88040bb7109c (virt) @40bb7109c (dma) 0x000000 - rsvd[2]
>[    1.980593] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.980918] xhci_hcd 0000:00:14.0: Successful Address Device command
>[    1.980924] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[    1.980930] xhci_hcd 0000:00:14.0: Slot ID 5 dcbaa entry @ffff88040bed9028 = 0x0000040b556000
>[    1.980934] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40b556000
>[    1.980938] xhci_hcd 0000:00:14.0: Slot ID 5 Input Context:
>[    1.980943] xhci_hcd 0000:00:14.0: @ffff88040bb71000 (virt) @40bb71000 (dma) 0x000000 - drop flags
>[    1.980947] xhci_hcd 0000:00:14.0: @ffff88040bb71004 (virt) @40bb71004 (dma) 0x000003 - add flags
>[    1.980952] xhci_hcd 0000:00:14.0: @ffff88040bb71008 (virt) @40bb71008 (dma) 0x000000 - rsvd2[0]
>[    1.980956] xhci_hcd 0000:00:14.0: @ffff88040bb7100c (virt) @40bb7100c (dma) 0x000000 - rsvd2[1]
>[    1.980961] xhci_hcd 0000:00:14.0: @ffff88040bb71010 (virt) @40bb71010 (dma) 0x000000 - rsvd2[2]
>[    1.980965] xhci_hcd 0000:00:14.0: @ffff88040bb71014 (virt) @40bb71014 (dma) 0x000000 - rsvd2[3]
>[    1.980970] xhci_hcd 0000:00:14.0: @ffff88040bb71018 (virt) @40bb71018 (dma) 0x000000 - rsvd2[4]
>[    1.980974] xhci_hcd 0000:00:14.0: @ffff88040bb7101c (virt) @40bb7101c (dma) 0x000000 - rsvd2[5]
>[    1.980978] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.980982] xhci_hcd 0000:00:14.0: @ffff88040bb71020 (virt) @40bb71020 (dma) 0xa200002 - dev_info
>[    1.980987] xhci_hcd 0000:00:14.0: @ffff88040bb71024 (virt) @40bb71024 (dma) 0x0e0000 - dev_info2
>[    1.980991] xhci_hcd 0000:00:14.0: @ffff88040bb71028 (virt) @40bb71028 (dma) 0x000202 - tt_info
>[    1.980996] xhci_hcd 0000:00:14.0: @ffff88040bb7102c (virt) @40bb7102c (dma) 0x000000 - dev_state
>[    1.981018] xhci_hcd 0000:00:14.0: @ffff88040bb71030 (virt) @40bb71030 (dma) 0x000000 - rsvd[0]
>[    1.981026] xhci_hcd 0000:00:14.0: @ffff88040bb71034 (virt) @40bb71034 (dma) 0x000000 - rsvd[1]
>[    1.981032] xhci_hcd 0000:00:14.0: @ffff88040bb71038 (virt) @40bb71038 (dma) 0x000000 - rsvd[2]
>[    1.981037] xhci_hcd 0000:00:14.0: @ffff88040bb7103c (virt) @40bb7103c (dma) 0x000000 - rsvd[3]
>[    1.981041] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.981046] xhci_hcd 0000:00:14.0: @ffff88040bb71040 (virt) @40bb71040 (dma) 0x000000 - ep_info
>[    1.981050] xhci_hcd 0000:00:14.0: @ffff88040bb71044 (virt) @40bb71044 (dma) 0x080026 - ep_info2
>[    1.981055] xhci_hcd 0000:00:14.0: @ffff88040bb71048 (virt) @40bb71048 (dma) 0x40b69d801 - deq
>[    1.981059] xhci_hcd 0000:00:14.0: @ffff88040bb71050 (virt) @40bb71050 (dma) 0x000000 - tx_info
>[    1.981064] xhci_hcd 0000:00:14.0: @ffff88040bb71054 (virt) @40bb71054 (dma) 0x000000 - rsvd[0]
>[    1.981068] xhci_hcd 0000:00:14.0: @ffff88040bb71058 (virt) @40bb71058 (dma) 0x000000 - rsvd[1]
>[    1.981073] xhci_hcd 0000:00:14.0: @ffff88040bb7105c (virt) @40bb7105c (dma) 0x000000 - rsvd[2]
>[    1.981077] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.981081] xhci_hcd 0000:00:14.0: @ffff88040bb71060 (virt) @40bb71060 (dma) 0x000000 - ep_info
>[    1.981086] xhci_hcd 0000:00:14.0: @ffff88040bb71064 (virt) @40bb71064 (dma) 0x000000 - ep_info2
>[    1.981090] xhci_hcd 0000:00:14.0: @ffff88040bb71068 (virt) @40bb71068 (dma) 0x000000 - deq
>[    1.981094] xhci_hcd 0000:00:14.0: @ffff88040bb71070 (virt) @40bb71070 (dma) 0x000000 - tx_info
>[    1.981099] xhci_hcd 0000:00:14.0: @ffff88040bb71074 (virt) @40bb71074 (dma) 0x000000 - rsvd[0]
>[    1.981103] xhci_hcd 0000:00:14.0: @ffff88040bb71078 (virt) @40bb71078 (dma) 0x000000 - rsvd[1]
>[    1.981108] xhci_hcd 0000:00:14.0: @ffff88040bb7107c (virt) @40bb7107c (dma) 0x000000 - rsvd[2]
>[    1.981112] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.981116] xhci_hcd 0000:00:14.0: @ffff88040bb71080 (virt) @40bb71080 (dma) 0x000000 - ep_info
>[    1.981121] xhci_hcd 0000:00:14.0: @ffff88040bb71084 (virt) @40bb71084 (dma) 0x000000 - ep_info2
>[    1.981125] xhci_hcd 0000:00:14.0: @ffff88040bb71088 (virt) @40bb71088 (dma) 0x000000 - deq
>[    1.981129] xhci_hcd 0000:00:14.0: @ffff88040bb71090 (virt) @40bb71090 (dma) 0x000000 - tx_info
>[    1.981134] xhci_hcd 0000:00:14.0: @ffff88040bb71094 (virt) @40bb71094 (dma) 0x000000 - rsvd[0]
>[    1.981138] xhci_hcd 0000:00:14.0: @ffff88040bb71098 (virt) @40bb71098 (dma) 0x000000 - rsvd[1]
>[    1.981143] xhci_hcd 0000:00:14.0: @ffff88040bb7109c (virt) @40bb7109c (dma) 0x000000 - rsvd[2]
>[    1.981147] xhci_hcd 0000:00:14.0: Slot ID 5 Output Context:
>[    1.981150] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.981155] xhci_hcd 0000:00:14.0: @ffff88040b556000 (virt) @40b556000 (dma) 0xa200002 - dev_info
>[    1.981159] xhci_hcd 0000:00:14.0: @ffff88040b556004 (virt) @40b556004 (dma) 0x0e0000 - dev_info2
>[    1.981164] xhci_hcd 0000:00:14.0: @ffff88040b556008 (virt) @40b556008 (dma) 0x000202 - tt_info
>[    1.981168] xhci_hcd 0000:00:14.0: @ffff88040b55600c (virt) @40b55600c (dma) 0x10000005 - dev_state
>[    1.981173] xhci_hcd 0000:00:14.0: @ffff88040b556010 (virt) @40b556010 (dma) 0x000000 - rsvd[0]
>[    1.981177] xhci_hcd 0000:00:14.0: @ffff88040b556014 (virt) @40b556014 (dma) 0x000000 - rsvd[1]
>[    1.981182] xhci_hcd 0000:00:14.0: @ffff88040b556018 (virt) @40b556018 (dma) 0x000000 - rsvd[2]
>[    1.981186] xhci_hcd 0000:00:14.0: @ffff88040b55601c (virt) @40b55601c (dma) 0x000000 - rsvd[3]
>[    1.981190] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.981195] xhci_hcd 0000:00:14.0: @ffff88040b556020 (virt) @40b556020 (dma) 0x000001 - ep_info
>[    1.981199] xhci_hcd 0000:00:14.0: @ffff88040b556024 (virt) @40b556024 (dma) 0x080026 - ep_info2
>[    1.981204] xhci_hcd 0000:00:14.0: @ffff88040b556028 (virt) @40b556028 (dma) 0x40b69d801 - deq
>[    1.981208] xhci_hcd 0000:00:14.0: @ffff88040b556030 (virt) @40b556030 (dma) 0x000000 - tx_info
>[    1.981213] xhci_hcd 0000:00:14.0: @ffff88040b556034 (virt) @40b556034 (dma) 0x000000 - rsvd[0]
>[    1.981217] xhci_hcd 0000:00:14.0: @ffff88040b556038 (virt) @40b556038 (dma) 0x000000 - rsvd[1]
>[    1.981221] xhci_hcd 0000:00:14.0: @ffff88040b55603c (virt) @40b55603c (dma) 0x000000 - rsvd[2]
>[    1.981226] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.981230] xhci_hcd 0000:00:14.0: @ffff88040b556040 (virt) @40b556040 (dma) 0x000000 - ep_info
>[    1.981234] xhci_hcd 0000:00:14.0: @ffff88040b556044 (virt) @40b556044 (dma) 0x000000 - ep_info2
>[    1.981239] xhci_hcd 0000:00:14.0: @ffff88040b556048 (virt) @40b556048 (dma) 0x000000 - deq
>[    1.981243] xhci_hcd 0000:00:14.0: @ffff88040b556050 (virt) @40b556050 (dma) 0x000000 - tx_info
>[    1.981248] xhci_hcd 0000:00:14.0: @ffff88040b556054 (virt) @40b556054 (dma) 0x000000 - rsvd[0]
>[    1.981252] xhci_hcd 0000:00:14.0: @ffff88040b556058 (virt) @40b556058 (dma) 0x000000 - rsvd[1]
>[    1.981257] xhci_hcd 0000:00:14.0: @ffff88040b55605c (virt) @40b55605c (dma) 0x000000 - rsvd[2]
>[    1.981261] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.981265] xhci_hcd 0000:00:14.0: @ffff88040b556060 (virt) @40b556060 (dma) 0x000000 - ep_info
>[    1.981270] xhci_hcd 0000:00:14.0: @ffff88040b556064 (virt) @40b556064 (dma) 0x000000 - ep_info2
>[    1.981274] xhci_hcd 0000:00:14.0: @ffff88040b556068 (virt) @40b556068 (dma) 0x000000 - deq
>[    1.981278] xhci_hcd 0000:00:14.0: @ffff88040b556070 (virt) @40b556070 (dma) 0x000000 - tx_info
>[    1.981283] xhci_hcd 0000:00:14.0: @ffff88040b556074 (virt) @40b556074 (dma) 0x000000 - rsvd[0]
>[    1.981287] xhci_hcd 0000:00:14.0: @ffff88040b556078 (virt) @40b556078 (dma) 0x000000 - rsvd[1]
>[    1.981292] xhci_hcd 0000:00:14.0: @ffff88040b55607c (virt) @40b55607c (dma) 0x000000 - rsvd[2]
>[    1.981296] xhci_hcd 0000:00:14.0: Internal device address = 6
>[    1.995980] usb 2-14.2: skipped 1 descriptor after interface
>[    1.995990] usb 2-14.2: skipped 1 descriptor after interface
>[    1.996357] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.996488] usb 2-14.2: default language 0x0409
>[    1.997441] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.998250] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    1.998352] usb 2-14.2: udev 5, busnum 2, minor = 132
>[    1.998361] usb 2-14.2: New USB device found, idVendor=046d, idProduct=c31c
>[    1.998367] usb 2-14.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    1.998372] usb 2-14.2: Product: USB Keyboard
>[    1.998376] usb 2-14.2: Manufacturer: Logitech
>[    1.998577] usb 2-14.2: usb_probe_device
>[    1.998586] usb 2-14.2: configuration #1 chosen from 1 choice
>[    1.998597] usb 2-14.2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[    1.998605] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 5, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x1a200002
>[    1.998614] usb 2-14.2: ep 0x82 - rounding interval to 1024 microframes, ep desc says 2040 microframes
>[    1.998620] xhci_hcd 0000:00:14.0: add ep 0x82, slot id 5, new drop flags = 0x0, new add flags = 0x28, new slot info = 0x2a200002
>[    1.998625] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff88040b5ec800
>[    1.998629] xhci_hcd 0000:00:14.0: New Input Control Context:
>[    1.998635] xhci_hcd 0000:00:14.0: @ffff88040bb71000 (virt) @40bb71000 (dma) 0x000000 - drop flags
>[    1.998640] xhci_hcd 0000:00:14.0: @ffff88040bb71004 (virt) @40bb71004 (dma) 0x000029 - add flags
>[    1.998645] xhci_hcd 0000:00:14.0: @ffff88040bb71008 (virt) @40bb71008 (dma) 0x000000 - rsvd2[0]
>[    1.998650] xhci_hcd 0000:00:14.0: @ffff88040bb7100c (virt) @40bb7100c (dma) 0x000000 - rsvd2[1]
>[    1.998654] xhci_hcd 0000:00:14.0: @ffff88040bb71010 (virt) @40bb71010 (dma) 0x000000 - rsvd2[2]
>[    1.998659] xhci_hcd 0000:00:14.0: @ffff88040bb71014 (virt) @40bb71014 (dma) 0x000000 - rsvd2[3]
>[    1.998663] xhci_hcd 0000:00:14.0: @ffff88040bb71018 (virt) @40bb71018 (dma) 0x000000 - rsvd2[4]
>[    1.998668] xhci_hcd 0000:00:14.0: @ffff88040bb7101c (virt) @40bb7101c (dma) 0x000000 - rsvd2[5]
>[    1.998672] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.998676] xhci_hcd 0000:00:14.0: @ffff88040bb71020 (virt) @40bb71020 (dma) 0x2a200002 - dev_info
>[    1.998681] xhci_hcd 0000:00:14.0: @ffff88040bb71024 (virt) @40bb71024 (dma) 0x0e0000 - dev_info2
>[    1.998685] xhci_hcd 0000:00:14.0: @ffff88040bb71028 (virt) @40bb71028 (dma) 0x000202 - tt_info
>[    1.998690] xhci_hcd 0000:00:14.0: @ffff88040bb7102c (virt) @40bb7102c (dma) 0x000000 - dev_state
>[    1.998694] xhci_hcd 0000:00:14.0: @ffff88040bb71030 (virt) @40bb71030 (dma) 0x000000 - rsvd[0]
>[    1.998699] xhci_hcd 0000:00:14.0: @ffff88040bb71034 (virt) @40bb71034 (dma) 0x000000 - rsvd[1]
>[    1.998703] xhci_hcd 0000:00:14.0: @ffff88040bb71038 (virt) @40bb71038 (dma) 0x000000 - rsvd[2]
>[    1.998708] xhci_hcd 0000:00:14.0: @ffff88040bb7103c (virt) @40bb7103c (dma) 0x000000 - rsvd[3]
>[    1.998713] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.998718] xhci_hcd 0000:00:14.0: @ffff88040bb71040 (virt) @40bb71040 (dma) 0x000000 - ep_info
>[    1.998722] xhci_hcd 0000:00:14.0: @ffff88040bb71044 (virt) @40bb71044 (dma) 0x080026 - ep_info2
>[    1.998727] xhci_hcd 0000:00:14.0: @ffff88040bb71048 (virt) @40bb71048 (dma) 0x40b69d801 - deq
>[    1.998731] xhci_hcd 0000:00:14.0: @ffff88040bb71050 (virt) @40bb71050 (dma) 0x000000 - tx_info
>[    1.998736] xhci_hcd 0000:00:14.0: @ffff88040bb71054 (virt) @40bb71054 (dma) 0x000000 - rsvd[0]
>[    1.998741] xhci_hcd 0000:00:14.0: @ffff88040bb71058 (virt) @40bb71058 (dma) 0x000000 - rsvd[1]
>[    1.998745] xhci_hcd 0000:00:14.0: @ffff88040bb7105c (virt) @40bb7105c (dma) 0x000000 - rsvd[2]
>[    1.998750] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.998754] xhci_hcd 0000:00:14.0: @ffff88040bb71060 (virt) @40bb71060 (dma) 0x000000 - ep_info
>[    1.998759] xhci_hcd 0000:00:14.0: @ffff88040bb71064 (virt) @40bb71064 (dma) 0x000000 - ep_info2
>[    1.998763] xhci_hcd 0000:00:14.0: @ffff88040bb71068 (virt) @40bb71068 (dma) 0x000000 - deq
>[    1.998768] xhci_hcd 0000:00:14.0: @ffff88040bb71070 (virt) @40bb71070 (dma) 0x000000 - tx_info
>[    1.998772] xhci_hcd 0000:00:14.0: @ffff88040bb71074 (virt) @40bb71074 (dma) 0x000000 - rsvd[0]
>[    1.998777] xhci_hcd 0000:00:14.0: @ffff88040bb71078 (virt) @40bb71078 (dma) 0x000000 - rsvd[1]
>[    1.998781] xhci_hcd 0000:00:14.0: @ffff88040bb7107c (virt) @40bb7107c (dma) 0x000000 - rsvd[2]
>[    1.998786] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.998790] xhci_hcd 0000:00:14.0: @ffff88040bb71080 (virt) @40bb71080 (dma) 0x060000 - ep_info
>[    1.998795] xhci_hcd 0000:00:14.0: @ffff88040bb71084 (virt) @40bb71084 (dma) 0x08003e - ep_info2
>[    1.998799] xhci_hcd 0000:00:14.0: @ffff88040bb71088 (virt) @40bb71088 (dma) 0x409ad0401 - deq
>[    1.998804] xhci_hcd 0000:00:14.0: @ffff88040bb71090 (virt) @40bb71090 (dma) 0x080008 - tx_info
>[    1.998808] xhci_hcd 0000:00:14.0: @ffff88040bb71094 (virt) @40bb71094 (dma) 0x000000 - rsvd[0]
>[    1.998813] xhci_hcd 0000:00:14.0: @ffff88040bb71098 (virt) @40bb71098 (dma) 0x000000 - rsvd[1]
>[    1.998817] xhci_hcd 0000:00:14.0: @ffff88040bb7109c (virt) @40bb7109c (dma) 0x000000 - rsvd[2]
>[    1.998821] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.998825] xhci_hcd 0000:00:14.0: @ffff88040bb710a0 (virt) @40bb710a0 (dma) 0x000000 - ep_info
>[    1.998830] xhci_hcd 0000:00:14.0: @ffff88040bb710a4 (virt) @40bb710a4 (dma) 0x000000 - ep_info2
>[    1.998834] xhci_hcd 0000:00:14.0: @ffff88040bb710a8 (virt) @40bb710a8 (dma) 0x000000 - deq
>[    1.998839] xhci_hcd 0000:00:14.0: @ffff88040bb710b0 (virt) @40bb710b0 (dma) 0x000000 - tx_info
>[    1.998843] xhci_hcd 0000:00:14.0: @ffff88040bb710b4 (virt) @40bb710b4 (dma) 0x000000 - rsvd[0]
>[    1.998848] xhci_hcd 0000:00:14.0: @ffff88040bb710b8 (virt) @40bb710b8 (dma) 0x000000 - rsvd[1]
>[    1.998852] xhci_hcd 0000:00:14.0: @ffff88040bb710bc (virt) @40bb710bc (dma) 0x000000 - rsvd[2]
>[    1.998856] xhci_hcd 0000:00:14.0: IN Endpoint 02 Context (ep_index 04):
>[    1.998861] xhci_hcd 0000:00:14.0: @ffff88040bb710c0 (virt) @40bb710c0 (dma) 0x0a0000 - ep_info
>[    1.998865] xhci_hcd 0000:00:14.0: @ffff88040bb710c4 (virt) @40bb710c4 (dma) 0x04003e - ep_info2
>[    1.998870] xhci_hcd 0000:00:14.0: @ffff88040bb710c8 (virt) @40bb710c8 (dma) 0x409850001 - deq
>[    1.998874] xhci_hcd 0000:00:14.0: @ffff88040bb710d0 (virt) @40bb710d0 (dma) 0x040004 - tx_info
>[    1.998879] xhci_hcd 0000:00:14.0: @ffff88040bb710d4 (virt) @40bb710d4 (dma) 0x000000 - rsvd[0]
>[    1.998883] xhci_hcd 0000:00:14.0: @ffff88040bb710d8 (virt) @40bb710d8 (dma) 0x000000 - rsvd[1]
>[    1.998887] xhci_hcd 0000:00:14.0: @ffff88040bb710dc (virt) @40bb710dc (dma) 0x000000 - rsvd[2]
>[    1.998892] xhci_hcd 0000:00:14.0: // Ding dong!
>[    1.999129] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[    1.999143] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[    1.999148] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[    1.999151] xhci_hcd 0000:00:14.0: Slot Context:
>[    1.999156] xhci_hcd 0000:00:14.0: @ffff88040b556000 (virt) @40b556000 (dma) 0x2a200002 - dev_info
>[    1.999160] xhci_hcd 0000:00:14.0: @ffff88040b556004 (virt) @40b556004 (dma) 0x0e0000 - dev_info2
>[    1.999165] xhci_hcd 0000:00:14.0: @ffff88040b556008 (virt) @40b556008 (dma) 0x000202 - tt_info
>[    1.999169] xhci_hcd 0000:00:14.0: @ffff88040b55600c (virt) @40b55600c (dma) 0x18000005 - dev_state
>[    1.999174] xhci_hcd 0000:00:14.0: @ffff88040b556010 (virt) @40b556010 (dma) 0x000000 - rsvd[0]
>[    1.999178] xhci_hcd 0000:00:14.0: @ffff88040b556014 (virt) @40b556014 (dma) 0x000000 - rsvd[1]
>[    1.999183] xhci_hcd 0000:00:14.0: @ffff88040b556018 (virt) @40b556018 (dma) 0x000000 - rsvd[2]
>[    1.999187] xhci_hcd 0000:00:14.0: @ffff88040b55601c (virt) @40b55601c (dma) 0x000000 - rsvd[3]
>[    1.999192] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[    1.999196] xhci_hcd 0000:00:14.0: @ffff88040b556020 (virt) @40b556020 (dma) 0x000001 - ep_info
>[    1.999201] xhci_hcd 0000:00:14.0: @ffff88040b556024 (virt) @40b556024 (dma) 0x080026 - ep_info2
>[    1.999205] xhci_hcd 0000:00:14.0: @ffff88040b556028 (virt) @40b556028 (dma) 0x40b69d801 - deq
>[    1.999209] xhci_hcd 0000:00:14.0: @ffff88040b556030 (virt) @40b556030 (dma) 0x000000 - tx_info
>[    1.999214] xhci_hcd 0000:00:14.0: @ffff88040b556034 (virt) @40b556034 (dma) 0x000000 - rsvd[0]
>[    1.999218] xhci_hcd 0000:00:14.0: @ffff88040b556038 (virt) @40b556038 (dma) 0x000000 - rsvd[1]
>[    1.999223] xhci_hcd 0000:00:14.0: @ffff88040b55603c (virt) @40b55603c (dma) 0x000000 - rsvd[2]
>[    1.999227] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[    1.999232] xhci_hcd 0000:00:14.0: @ffff88040b556040 (virt) @40b556040 (dma) 0x000000 - ep_info
>[    1.999236] xhci_hcd 0000:00:14.0: @ffff88040b556044 (virt) @40b556044 (dma) 0x000000 - ep_info2
>[    1.999240] xhci_hcd 0000:00:14.0: @ffff88040b556048 (virt) @40b556048 (dma) 0x000000 - deq
>[    1.999245] xhci_hcd 0000:00:14.0: @ffff88040b556050 (virt) @40b556050 (dma) 0x000000 - tx_info
>[    1.999256] xhci_hcd 0000:00:14.0: @ffff88040b556054 (virt) @40b556054 (dma) 0x000000 - rsvd[0]
>[    1.999260] xhci_hcd 0000:00:14.0: @ffff88040b556058 (virt) @40b556058 (dma) 0x000000 - rsvd[1]
>[    1.999265] xhci_hcd 0000:00:14.0: @ffff88040b55605c (virt) @40b55605c (dma) 0x000000 - rsvd[2]
>[    1.999269] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[    1.999273] xhci_hcd 0000:00:14.0: @ffff88040b556060 (virt) @40b556060 (dma) 0x060001 - ep_info
>[    1.999278] xhci_hcd 0000:00:14.0: @ffff88040b556064 (virt) @40b556064 (dma) 0x08003e - ep_info2
>[    1.999282] xhci_hcd 0000:00:14.0: @ffff88040b556068 (virt) @40b556068 (dma) 0x409ad0401 - deq
>[    1.999287] xhci_hcd 0000:00:14.0: @ffff88040b556070 (virt) @40b556070 (dma) 0x080008 - tx_info
>[    1.999291] xhci_hcd 0000:00:14.0: @ffff88040b556074 (virt) @40b556074 (dma) 0x000000 - rsvd[0]
>[    1.999296] xhci_hcd 0000:00:14.0: @ffff88040b556078 (virt) @40b556078 (dma) 0x000000 - rsvd[1]
>[    1.999300] xhci_hcd 0000:00:14.0: @ffff88040b55607c (virt) @40b55607c (dma) 0x000000 - rsvd[2]
>[    1.999304] xhci_hcd 0000:00:14.0: OUT Endpoint 02 Context (ep_index 03):
>[    1.999309] xhci_hcd 0000:00:14.0: @ffff88040b556080 (virt) @40b556080 (dma) 0x000000 - ep_info
>[    1.999313] xhci_hcd 0000:00:14.0: @ffff88040b556084 (virt) @40b556084 (dma) 0x000000 - ep_info2
>[    1.999317] xhci_hcd 0000:00:14.0: @ffff88040b556088 (virt) @40b556088 (dma) 0x000000 - deq
>[    1.999322] xhci_hcd 0000:00:14.0: @ffff88040b556090 (virt) @40b556090 (dma) 0x000000 - tx_info
>[    1.999326] xhci_hcd 0000:00:14.0: @ffff88040b556094 (virt) @40b556094 (dma) 0x000000 - rsvd[0]
>[    1.999331] xhci_hcd 0000:00:14.0: @ffff88040b556098 (virt) @40b556098 (dma) 0x000000 - rsvd[1]
>[    1.999335] xhci_hcd 0000:00:14.0: @ffff88040b55609c (virt) @40b55609c (dma) 0x000000 - rsvd[2]
>[    1.999339] xhci_hcd 0000:00:14.0: IN Endpoint 02 Context (ep_index 04):
>[    1.999344] xhci_hcd 0000:00:14.0: @ffff88040b5560a0 (virt) @40b5560a0 (dma) 0x0a0001 - ep_info
>[    1.999348] xhci_hcd 0000:00:14.0: @ffff88040b5560a4 (virt) @40b5560a4 (dma) 0x04003e - ep_info2
>[    1.999353] xhci_hcd 0000:00:14.0: @ffff88040b5560a8 (virt) @40b5560a8 (dma) 0x409850001 - deq
>[    1.999357] xhci_hcd 0000:00:14.0: @ffff88040b5560b0 (virt) @40b5560b0 (dma) 0x040004 - tx_info
>[    1.999362] xhci_hcd 0000:00:14.0: @ffff88040b5560b4 (virt) @40b5560b4 (dma) 0x000000 - rsvd[0]
>[    1.999366] xhci_hcd 0000:00:14.0: @ffff88040b5560b8 (virt) @40b5560b8 (dma) 0x000000 - rsvd[1]
>[    1.999371] xhci_hcd 0000:00:14.0: @ffff88040b5560bc (virt) @40b5560bc (dma) 0x000000 - rsvd[2]
>[    1.999378] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[    1.999387] xhci_hcd 0000:00:14.0: Endpoint 0x82 not halted, refusing to reset.
>[    2.000631] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.000747] usb 2-14.2: adding 2-14.2:1.0 (config #1, interface 0)
>[    2.001684] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.001854] usbhid 2-14.2:1.0: usb_probe_interface
>[    2.001862] usbhid 2-14.2:1.0: usb_probe_interface - got id
>[    2.004911] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:14.0/usb2/2-14/2-14.2/2-14.2:1.0/input/input19
>[    2.005115] hid-generic 0003:046D:C31C.0002: input,hidraw1: USB HID v1.10 Keyboard [Logitech USB Keyboard] on usb-0000:00:14.0-14.2/input0
>[    2.005149] usb 2-14.2: adding 2-14.2:1.1 (config #1, interface 1)
>[    2.006117] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.006293] usbhid 2-14.2:1.1: usb_probe_interface
>[    2.006301] usbhid 2-14.2:1.1: usb_probe_interface - got id
>[    2.011963] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.012446] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.012833] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[    2.013091] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:14.0/usb2/2-14/2-14.2/2-14.2:1.1/input/input20
>[    2.013401] hid-generic 0003:046D:C31C.0003: input,hidraw2: USB HID v1.10 Device [Logitech USB Keyboard] on usb-0000:00:14.0-14.2/input1
>[    2.226197] Switched to clocksource tsc
>[    2.597250] Adding 33554428k swap on /dev/sda4.  Priority:-1 extents:1 across:33554428k SS
>[    2.836132] scsi 6:0:0:0: Direct-Access     Generic  STORAGE DEVICE   0556 PQ: 0 ANSI: 5
>[    2.836469] sd 6:0:0:0: Attached scsi generic sg3 type 0
>[    2.836540] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.836556] xhci_hcd 0000:00:14.0: Giveback URB ffff88040ba579c0, len = 18, expected = 96, status = -121
>[    2.836595] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.836609] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.836807] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.836816] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.836823] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.836829] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.836835] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.836841] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.836846] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.836850] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d050 (DMA)
>[    2.836855] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.836861] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d050 (0x409a8d050 dma), new cycle = 1
>[    2.836866] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.836882] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.836891] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d051
>[    2.837453] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.837467] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bb7c6c0, len = 18, expected = 96, status = -121
>[    2.837498] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.837511] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.837712] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.837724] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.837731] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.837737] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.837744] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.837752] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.837759] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.837766] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d090 (DMA)
>[    2.837773] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.837784] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d090 (0x409a8d090 dma), new cycle = 1
>[    2.837791] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.837810] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.837821] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d091
>[    2.837908] sd 6:0:0:0: [sdc] Attached SCSI removable disk
>[    2.838069] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.838081] xhci_hcd 0000:00:14.0: Giveback URB ffff88040ba57600, len = 18, expected = 96, status = -121
>[    2.838120] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.838138] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.838351] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.838360] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.838366] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.838373] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.838380] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.838386] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.838394] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.838401] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0d0 (DMA)
>[    2.838407] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.838417] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0d0 (0x409a8d0d0 dma), new cycle = 1
>[    2.838424] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.838441] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.838449] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0d1
>[    2.841740] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.841750] xhci_hcd 0000:00:14.0: Giveback URB ffff88040ba57300, len = 18, expected = 96, status = -121
>[    2.841774] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.841780] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.841975] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.841984] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.841989] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.841993] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.841997] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.842002] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.842006] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.842011] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d110 (DMA)
>[    2.842015] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.842022] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d110 (0x409a8d110 dma), new cycle = 1
>[    2.842026] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.842043] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.842054] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d111
>[    2.842333] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.842344] xhci_hcd 0000:00:14.0: Giveback URB ffff880407a220c0, len = 18, expected = 96, status = -121
>[    2.842367] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.842373] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.842464] net firewire0: IP over IEEE 1394 on card 0000:04:02.0
>[    2.842545] firewire_core 0000:04:02.0: refreshed device fw0
>[    2.842565] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.842574] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.842578] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.842582] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.842586] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.842590] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.842595] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.842602] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d150 (DMA)
>[    2.842608] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.842618] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d150 (0x409a8d150 dma), new cycle = 1
>[    2.842625] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.842646] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.842658] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d151
>[    2.844889] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.844899] xhci_hcd 0000:00:14.0: Giveback URB ffff880408801e40, len = 18, expected = 96, status = -121
>[    2.844924] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.844930] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.845130] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.845143] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.845150] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.845156] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.845163] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.845171] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.845178] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.845186] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d190 (DMA)
>[    2.845192] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.845203] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d190 (0x409a8d190 dma), new cycle = 1
>[    2.845210] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.845232] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.845245] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d191
>[    2.847655] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    2.847667] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b464a80, len = 18, expected = 96, status = -121
>[    2.847697] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    2.847713] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    2.847901] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    2.847909] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    2.847916] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    2.847922] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    2.847929] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    2.847936] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    2.847943] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    2.847950] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1d0 (DMA)
>[    2.847956] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    2.847967] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1d0 (0x409a8d1d0 dma), new cycle = 1
>[    2.847975] xhci_hcd 0000:00:14.0: // Ding dong!
>[    2.847993] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    2.848003] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1d1
>[    5.114574] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    5.114586] xhci_hcd 0000:00:14.0: Giveback URB ffff88040785f3c0, len = 18, expected = 96, status = -121
>[    5.114625] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    5.114637] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    5.114865] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    5.114875] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    5.114879] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    5.114884] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    5.114888] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    5.114892] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    5.114897] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    5.114902] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d210 (DMA)
>[    5.114906] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    5.114912] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d210 (0x409a8d210 dma), new cycle = 1
>[    5.114917] xhci_hcd 0000:00:14.0: // Ding dong!
>[    5.114935] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    5.114945] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d211
>[    7.162381] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    7.162397] xhci_hcd 0000:00:14.0: Giveback URB ffff8804059876c0, len = 18, expected = 96, status = -121
>[    7.162424] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    7.162434] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    7.162616] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    7.162623] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    7.162629] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    7.162635] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    7.162641] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    7.162648] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    7.162655] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    7.162663] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d250 (DMA)
>[    7.162669] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    7.162680] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d250 (0x409a8d250 dma), new cycle = 1
>[    7.162688] xhci_hcd 0000:00:14.0: // Ding dong!
>[    7.162708] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    7.162717] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d251
>[    9.210256] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[    9.210264] xhci_hcd 0000:00:14.0: Giveback URB ffff88040754ba80, len = 18, expected = 96, status = -121
>[    9.210292] xhci_hcd 0000:00:14.0: Stalled endpoint
>[    9.210300] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[    9.210506] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[    9.210513] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[    9.210516] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[    9.210519] xhci_hcd 0000:00:14.0: Finding endpoint context
>[    9.210522] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[    9.210525] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[    9.210529] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[    9.210532] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d290 (DMA)
>[    9.210534] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[    9.210539] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d290 (0x409a8d290 dma), new cycle = 1
>[    9.210542] xhci_hcd 0000:00:14.0: // Ding dong!
>[    9.210555] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[    9.210562] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d291
>[   11.258114] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   11.258122] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b7f2f00, len = 18, expected = 96, status = -121
>[   11.258150] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   11.258158] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   11.258365] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   11.258371] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   11.258375] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   11.258378] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   11.258381] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   11.258384] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   11.258387] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   11.258390] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2d0 (DMA)
>[   11.258393] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   11.258398] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2d0 (0x409a8d2d0 dma), new cycle = 1
>[   11.258401] xhci_hcd 0000:00:14.0: // Ding dong!
>[   11.258414] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   11.258421] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2d1
>[   13.305969] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   13.305979] xhci_hcd 0000:00:14.0: Giveback URB ffff880404faec00, len = 18, expected = 96, status = -121
>[   13.306003] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   13.306009] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   13.306185] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   13.306189] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   13.306193] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   13.306197] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   13.306201] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   13.306206] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   13.306210] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   13.306215] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d310 (DMA)
>[   13.306219] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   13.306225] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d310 (0x409a8d310 dma), new cycle = 1
>[   13.306229] xhci_hcd 0000:00:14.0: // Ding dong!
>[   13.306246] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   13.306257] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d311
>[   15.353806] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   15.353817] xhci_hcd 0000:00:14.0: Giveback URB ffff880404faec00, len = 18, expected = 96, status = -121
>[   15.353840] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   15.353846] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   15.354022] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   15.354027] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   15.354031] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   15.354035] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   15.354039] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   15.354044] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   15.354048] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   15.354053] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d350 (DMA)
>[   15.354057] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   15.354064] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d350 (0x409a8d350 dma), new cycle = 1
>[   15.354070] xhci_hcd 0000:00:14.0: // Ding dong!
>[   15.354086] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   15.354092] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d351
>[   17.401675] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   17.401685] xhci_hcd 0000:00:14.0: Giveback URB ffff880404faec00, len = 18, expected = 96, status = -121
>[   17.401709] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   17.401715] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   17.401891] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   17.401896] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   17.401900] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   17.401904] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   17.401908] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   17.401913] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   17.401917] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   17.401922] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d390 (DMA)
>[   17.401928] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   17.401938] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d390 (0x409a8d390 dma), new cycle = 1
>[   17.401945] xhci_hcd 0000:00:14.0: // Ding dong!
>[   17.401965] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   17.401980] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d391
>[   18.575372] EXT4-fs (sda5): re-mounted. Opts: acl,user_xattr
>[   18.751003] EXT4-fs (sdb3): mounted filesystem with ordered data mode. Opts: acl,user_xattr
>[   19.449551] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   19.449559] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b99480, len = 18, expected = 96, status = -121
>[   19.449591] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   19.449600] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   19.449794] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   19.449799] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   19.449803] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   19.449806] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   19.449809] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   19.449813] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   19.449817] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   19.449821] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3d0 (DMA)
>[   19.449824] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   19.449829] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3d0 (0x409a8d3d0 dma), new cycle = 1
>[   19.449832] xhci_hcd 0000:00:14.0: // Ding dong!
>[   19.449842] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   19.449847] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3d1
>[   19.608597] IPv6: ADDRCONF(NETDEV_UP): enp5s0: link is not ready
>[   19.608604] 8021q: adding VLAN 0 to HW filter on device enp5s0
>[   19.855528] IPv6: ADDRCONF(NETDEV_UP): enp6s0: link is not ready
>[   19.855534] 8021q: adding VLAN 0 to HW filter on device enp6s0
>[   21.497351] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   21.497361] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03480, len = 18, expected = 96, status = -121
>[   21.497390] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   21.497395] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   21.497580] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   21.497587] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   21.497592] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   21.497596] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   21.497599] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   21.497603] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   21.497607] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   21.497611] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d420 (DMA)
>[   21.497613] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   21.497618] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d420 (0x409a8d420 dma), new cycle = 1
>[   21.497620] xhci_hcd 0000:00:14.0: // Ding dong!
>[   21.497634] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   21.497639] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d421
>[   22.758534] igb: enp6s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
>[   22.758956] IPv6: ADDRCONF(NETDEV_CHANGE): enp6s0: link becomes ready
>[   23.545175] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   23.545178] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29f00, len = 18, expected = 96, status = -121
>[   23.545217] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   23.545221] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   23.545388] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   23.545390] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   23.545391] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   23.545393] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   23.545394] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   23.545396] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   23.545397] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   23.545399] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d460 (DMA)
>[   23.545400] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   23.545402] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d460 (0x409a8d460 dma), new cycle = 1
>[   23.545403] xhci_hcd 0000:00:14.0: // Ding dong!
>[   23.545406] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[   23.545423] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   23.545425] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d461
>[   25.593074] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   25.593078] xhci_hcd 0000:00:14.0: Giveback URB ffff88040396d3c0, len = 18, expected = 96, status = -121
>[   25.593103] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   25.593108] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   25.593286] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   25.593290] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   25.593293] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   25.593294] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   25.593296] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   25.593297] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   25.593299] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   25.593301] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4a0 (DMA)
>[   25.593302] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   25.593304] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4a0 (0x409a8d4a0 dma), new cycle = 1
>[   25.593306] xhci_hcd 0000:00:14.0: // Ding dong!
>[   25.593309] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[   25.593316] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   25.593319] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4a1
>[   27.640917] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   27.640922] xhci_hcd 0000:00:14.0: Giveback URB ffff88040396d900, len = 18, expected = 96, status = -121
>[   27.640955] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   27.640957] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   27.641136] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   27.641139] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   27.641140] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   27.641142] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   27.641143] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   27.641145] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   27.641146] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   27.641148] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4e0 (DMA)
>[   27.641149] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   27.641152] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4e0 (0x409a8d4e0 dma), new cycle = 1
>[   27.641153] xhci_hcd 0000:00:14.0: // Ding dong!
>[   27.641157] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[   27.641171] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   27.641173] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4e1
>[   28.260195] xhci_hcd 0000:00:14.0: Cancel URB ffff880409acf0c0, dev 14.1, ep 0x81, starting at offset 0x40b69d580
>[   28.260199] xhci_hcd 0000:00:14.0: // Ding dong!
>[   28.262209] xhci_hcd 0000:00:14.0: Stopped on Transfer TRB
>[   28.262214] xhci_hcd 0000:00:14.0: Removing canceled TD starting at 0x40b69d580 (dma).
>[   28.262216] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   28.262218] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   28.262219] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   28.262221] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   28.262223] xhci_hcd 0000:00:14.0: New dequeue segment = ffff8800dc971260 (virtual)
>[   28.262225] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x40b69d590 (DMA)
>[   28.262228] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff8800dc971260 (0x40b69d400 dma), new deq ptr = ffff88040b69d590 (0x40b69d590 dma), new cycle = 0
>[   28.262229] xhci_hcd 0000:00:14.0: // Ding dong!
>[   28.262235] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @40b69d590
>[   29.688783] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   29.688793] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29d80, len = 18, expected = 96, status = -121
>[   29.688817] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   29.688823] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   29.689004] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   29.689007] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   29.689009] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   29.689011] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   29.689012] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   29.689018] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   29.689021] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   29.689024] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d520 (DMA)
>[   29.689026] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   29.689029] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d520 (0x409a8d520 dma), new cycle = 1
>[   29.689032] xhci_hcd 0000:00:14.0: // Ding dong!
>[   29.689042] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   29.689054] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d521
>[   31.736727] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   31.736738] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29900, len = 18, expected = 96, status = -121
>[   31.736770] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   31.736780] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   31.736993] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   31.737005] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   31.737012] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   31.737016] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   31.737022] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   31.737030] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   31.737037] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   31.737045] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d560 (DMA)
>[   31.737051] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   31.737061] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d560 (0x409a8d560 dma), new cycle = 1
>[   31.737068] xhci_hcd 0000:00:14.0: // Ding dong!
>[   31.737092] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   31.737106] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d561
>[   33.784515] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   33.784523] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29900, len = 18, expected = 96, status = -121
>[   33.784546] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   33.784552] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   33.784747] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   33.784755] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   33.784760] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   33.784765] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   33.784770] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   33.784775] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   33.784780] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   33.784785] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5a0 (DMA)
>[   33.784790] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   33.784797] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5a0 (0x409a8d5a0 dma), new cycle = 1
>[   33.784802] xhci_hcd 0000:00:14.0: // Ding dong!
>[   33.784813] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   33.784818] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5a1
>[   35.832419] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   35.832430] xhci_hcd 0000:00:14.0: Giveback URB ffff880403694300, len = 18, expected = 96, status = -121
>[   35.832465] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   35.832475] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   35.832679] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   35.832691] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   35.832699] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   35.832705] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   35.832712] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   35.832720] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   35.832728] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   35.832735] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5e0 (DMA)
>[   35.832742] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   35.832753] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5e0 (0x409a8d5e0 dma), new cycle = 1
>[   35.832760] xhci_hcd 0000:00:14.0: // Ding dong!
>[   35.832784] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   35.832799] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5e1
>[   37.880282] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   37.880293] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29900, len = 18, expected = 96, status = -121
>[   37.880325] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   37.880335] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   37.880549] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   37.880562] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   37.880570] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   37.880576] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   37.880583] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   37.880590] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   37.880596] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   37.880601] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d620 (DMA)
>[   37.880605] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   37.880612] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d620 (0x409a8d620 dma), new cycle = 1
>[   37.880617] xhci_hcd 0000:00:14.0: // Ding dong!
>[   37.880640] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   37.880654] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d621
>[   39.928127] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   39.928139] xhci_hcd 0000:00:14.0: Giveback URB ffff880403694f00, len = 18, expected = 96, status = -121
>[   39.928172] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   39.928182] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   39.928386] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   39.928397] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   39.928404] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   39.928411] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   39.928418] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   39.928424] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   39.928432] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   39.928439] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d660 (DMA)
>[   39.928445] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   39.928456] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d660 (0x409a8d660 dma), new cycle = 1
>[   39.928464] xhci_hcd 0000:00:14.0: // Ding dong!
>[   39.928488] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   39.928502] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d661
>[   41.975975] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   41.975985] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29a80, len = 18, expected = 96, status = -121
>[   41.976011] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   41.976019] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   41.976228] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   41.976238] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   41.976244] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   41.976250] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   41.976255] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   41.976261] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   41.976266] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   41.976269] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6a0 (DMA)
>[   41.976273] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   41.976278] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6a0 (0x409a8d6a0 dma), new cycle = 1
>[   41.976283] xhci_hcd 0000:00:14.0: // Ding dong!
>[   41.976302] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   41.976309] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6a1
>[   44.023812] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   44.023822] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29300, len = 18, expected = 96, status = -121
>[   44.023848] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   44.023856] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   44.024050] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   44.024058] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   44.024064] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   44.024069] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   44.024074] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   44.024080] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   44.024093] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   44.024097] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6e0 (DMA)
>[   44.024100] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   44.024106] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6e0 (0x409a8d6e0 dma), new cycle = 1
>[   44.024110] xhci_hcd 0000:00:14.0: // Ding dong!
>[   44.024128] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   44.024134] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6e1
>[   46.071718] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   46.071729] xhci_hcd 0000:00:14.0: Giveback URB ffff880403695180, len = 18, expected = 96, status = -121
>[   46.071764] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   46.071774] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   46.071978] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   46.071990] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   46.071998] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   46.072005] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   46.072012] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   46.072019] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   46.072026] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   46.072035] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d720 (DMA)
>[   46.072041] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   46.072052] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d720 (0x409a8d720 dma), new cycle = 1
>[   46.072059] xhci_hcd 0000:00:14.0: // Ding dong!
>[   46.072083] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   46.072097] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d721
>[   48.119557] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   48.119569] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29300, len = 18, expected = 96, status = -121
>[   48.119600] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   48.119610] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   48.119819] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   48.119832] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   48.119839] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   48.119846] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   48.119853] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   48.119861] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   48.119868] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   48.119876] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d760 (DMA)
>[   48.119883] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   48.119893] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d760 (0x409a8d760 dma), new cycle = 1
>[   48.119901] xhci_hcd 0000:00:14.0: // Ding dong!
>[   48.119924] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   48.119939] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d761
>[   50.167422] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   50.167434] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29300, len = 18, expected = 96, status = -121
>[   50.167465] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   50.167476] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   50.167688] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   50.167700] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   50.167708] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   50.167714] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   50.167720] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   50.167728] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   50.167736] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   50.167744] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7a0 (DMA)
>[   50.167751] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   50.167762] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7a0 (0x409a8d7a0 dma), new cycle = 1
>[   50.167769] xhci_hcd 0000:00:14.0: // Ding dong!
>[   50.167794] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   50.167808] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7a1
>[   52.215279] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   52.215291] xhci_hcd 0000:00:14.0: Giveback URB ffff880403695a80, len = 18, expected = 96, status = -121
>[   52.215325] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   52.215334] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   52.215540] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   52.215553] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   52.215560] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   52.215567] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   52.215573] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   52.215580] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[   52.215589] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[   52.215596] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7e0 (DMA)
>[   52.215603] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   52.215613] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7e0 (0x409a8d7e0 dma), new cycle = 1
>[   52.215621] xhci_hcd 0000:00:14.0: // Ding dong!
>[   52.215645] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   52.215659] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7e1
>[   54.263143] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   54.263155] xhci_hcd 0000:00:14.0: Giveback URB ffff880403695e40, len = 18, expected = 96, status = -121
>[   54.263189] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   54.263198] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   54.263407] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   54.263420] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   54.263428] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   54.263436] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   54.263442] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   54.263447] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   54.263452] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   54.263457] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d030 (DMA)
>[   54.263461] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   54.263468] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d030 (0x409a8d030 dma), new cycle = 0
>[   54.263472] xhci_hcd 0000:00:14.0: // Ding dong!
>[   54.263496] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   54.263511] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d030
>[   56.310977] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   56.310989] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29900, len = 18, expected = 96, status = -121
>[   56.311018] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   56.311028] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   56.311224] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   56.311230] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   56.311234] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   56.311238] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   56.311242] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   56.311247] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   56.311252] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   56.311256] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d070 (DMA)
>[   56.311260] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   56.311268] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d070 (0x409a8d070 dma), new cycle = 0
>[   56.311273] xhci_hcd 0000:00:14.0: // Ding dong!
>[   56.311295] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   56.311309] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d070
>[   58.358821] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   58.358833] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29a80, len = 18, expected = 96, status = -121
>[   58.358862] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   58.358872] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   58.359061] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   58.359067] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   58.359072] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   58.359076] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   58.359080] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   58.359084] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   58.359089] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   58.359093] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0b0 (DMA)
>[   58.359098] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   58.359104] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0b0 (0x409a8d0b0 dma), new cycle = 0
>[   58.359109] xhci_hcd 0000:00:14.0: // Ding dong!
>[   58.359132] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   58.359146] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0b0
>[   60.406690] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   60.406701] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29a80, len = 18, expected = 96, status = -121
>[   60.406731] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   60.406741] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   60.406937] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   60.406943] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   60.406947] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   60.406951] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   60.406955] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   60.406960] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   60.406964] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   60.406969] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0f0 (DMA)
>[   60.406973] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   60.406980] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0f0 (0x409a8d0f0 dma), new cycle = 0
>[   60.406985] xhci_hcd 0000:00:14.0: // Ding dong!
>[   60.407008] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   60.407022] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0f0
>[   62.454551] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   62.454562] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29a80, len = 18, expected = 96, status = -121
>[   62.454593] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   62.454603] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   62.454795] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   62.454801] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   62.454805] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   62.454809] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   62.454813] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   62.454817] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   62.454822] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   62.454827] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d130 (DMA)
>[   62.454831] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   62.454837] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d130 (0x409a8d130 dma), new cycle = 0
>[   62.454842] xhci_hcd 0000:00:14.0: // Ding dong!
>[   62.454849] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[   62.454860] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   62.454869] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d130
>[   64.502402] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   64.502413] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29a80, len = 18, expected = 96, status = -121
>[   64.502443] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   64.502453] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   64.502652] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   64.502658] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   64.502662] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   64.502666] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   64.502670] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   64.502674] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   64.502679] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   64.502683] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d170 (DMA)
>[   64.502687] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   64.502695] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d170 (0x409a8d170 dma), new cycle = 0
>[   64.502700] xhci_hcd 0000:00:14.0: // Ding dong!
>[   64.502722] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   64.502737] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d170
>[   66.550271] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   66.550283] xhci_hcd 0000:00:14.0: Giveback URB ffff880404fae900, len = 18, expected = 96, status = -121
>[   66.550312] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   66.550323] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   66.550516] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   66.550522] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   66.550526] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   66.550530] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   66.550534] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   66.550538] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   66.550543] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   66.550547] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1b0 (DMA)
>[   66.550551] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   66.550558] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1b0 (0x409a8d1b0 dma), new cycle = 0
>[   66.550562] xhci_hcd 0000:00:14.0: // Ding dong!
>[   66.550577] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   66.550586] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1b0
>[   68.598123] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[   68.598135] xhci_hcd 0000:00:14.0: Giveback URB ffff880404fae900, len = 18, expected = 96, status = -121
>[   68.598166] xhci_hcd 0000:00:14.0: Stalled endpoint
>[   68.598176] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[   68.598368] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[   68.598374] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[   68.598378] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[   68.598382] xhci_hcd 0000:00:14.0: Finding endpoint context
>[   68.598386] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[   68.598391] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[   68.598395] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[   68.598400] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1f0 (DMA)
>[   68.598404] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[   68.598411] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1f0 (0x409a8d1f0 dma), new cycle = 0
>[   68.598417] xhci_hcd 0000:00:14.0: // Ding dong!
>[   68.598440] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[   68.598453] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1f0
>[ 5682.287184] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5682.287189] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5682.287191] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5682.287193] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5682.287195] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5682.287198] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5682.287200] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5682.287203] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 5682.287205] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5682.287208] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 5682.287210] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5682.287218] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5682.287222] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 5684.334842] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5684.334847] xhci_hcd 0000:00:14.0: Giveback URB ffff880403c3d300, len = 18, expected = 96, status = -121
>[ 5684.334874] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5684.334879] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5684.335054] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5684.335057] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5684.335058] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5684.335060] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5684.335061] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5684.335062] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5684.335064] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5684.335065] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 5684.335067] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5684.335069] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 5684.335070] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5684.335073] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5684.335086] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5684.335088] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 5686.382654] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5686.382659] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6dfb40, len = 18, expected = 96, status = -121
>[ 5686.382691] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5686.382693] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5686.382862] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5686.382864] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5686.382866] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5686.382867] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5686.382869] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5686.382871] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5686.382872] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5686.382874] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 5686.382876] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5686.382878] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 5686.382880] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5686.382883] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5686.382899] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5686.382901] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 5688.430538] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5688.430543] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6df480, len = 18, expected = 96, status = -121
>[ 5688.430566] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5688.430571] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5688.430745] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5688.430749] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5688.430751] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5688.430752] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5688.430753] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5688.430754] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5688.430756] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5688.430757] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 5688.430758] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5688.430760] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 5688.430761] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5688.430764] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5688.430776] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5688.430780] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 5690.478418] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5690.478423] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e4f00, len = 18, expected = 96, status = -121
>[ 5690.478445] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5690.478449] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5690.478625] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5690.478629] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5690.478631] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5690.478633] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5690.478635] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5690.478637] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5690.478639] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5690.478641] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 5690.478643] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5690.478646] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 5690.478648] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5690.478660] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5690.478663] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 5692.526258] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5692.526262] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c210840, len = 18, expected = 96, status = -121
>[ 5692.526286] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5692.526291] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5692.526464] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5692.526467] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5692.526469] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5692.526470] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5692.526471] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5692.526472] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5692.526473] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5692.526475] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 5692.526476] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5692.526477] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 5692.526479] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5692.526482] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5692.526495] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5692.526498] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 5694.574141] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5694.574147] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941000, len = 18, expected = 96, status = -121
>[ 5694.574169] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5694.574174] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5694.574346] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5694.574349] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5694.574351] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5694.574352] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5694.574354] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5694.574355] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5694.574357] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5694.574358] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 5694.574360] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5694.574362] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 5694.574364] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5694.574367] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5694.574379] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5694.574382] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 5696.621969] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5696.621974] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6dfd80, len = 18, expected = 96, status = -121
>[ 5696.621995] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5696.621998] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5696.622177] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5696.622180] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5696.622181] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5696.622182] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5696.622183] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5696.622185] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5696.622186] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5696.622187] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 5696.622188] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5696.622190] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 5696.622192] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5696.622195] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5696.622206] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5696.622209] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 5698.669842] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5698.669847] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6dfd80, len = 18, expected = 96, status = -121
>[ 5698.669867] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5698.669871] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5698.670049] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5698.670056] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5698.670058] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5698.670059] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5698.670061] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5698.670063] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5698.670064] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5698.670066] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 5698.670069] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5698.670071] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 5698.670073] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5698.670080] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5698.670082] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 5700.717664] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5700.717670] xhci_hcd 0000:00:14.0: Giveback URB ffff8804098fa240, len = 18, expected = 96, status = -121
>[ 5700.717700] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5700.717703] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5700.717870] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5700.717872] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5700.717874] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5700.717876] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5700.717882] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5700.717883] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5700.717885] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5700.717886] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 5700.717887] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5700.717889] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 5700.717893] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5700.717896] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5700.717906] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5700.717909] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 5702.765488] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5702.765493] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd1ecc0, len = 18, expected = 96, status = -121
>[ 5702.765526] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5702.765528] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5702.765695] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5702.765697] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5702.765698] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5702.765699] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5702.765701] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5702.765703] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5702.765704] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5702.765705] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 5702.765706] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5702.765709] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 5702.765710] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5702.765713] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5702.765731] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5702.765733] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 5704.813410] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5704.813416] xhci_hcd 0000:00:14.0: Giveback URB ffff88040450c0c0, len = 18, expected = 96, status = -121
>[ 5704.813439] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5704.813443] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5704.813628] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5704.813639] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5704.813641] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5704.813643] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5704.813644] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5704.813646] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5704.813649] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5704.813651] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 5704.813654] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5704.813658] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 5704.813660] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5704.813668] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5704.813671] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 5706.861236] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5706.861240] xhci_hcd 0000:00:14.0: Giveback URB ffff880405902540, len = 18, expected = 96, status = -121
>[ 5706.861275] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5706.861280] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5706.861449] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5706.861451] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5706.861452] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5706.861454] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5706.861455] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5706.861457] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5706.861458] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5706.861460] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 5706.861461] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5706.861464] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 5706.861465] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5706.861468] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5706.861483] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5706.861485] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 5708.909121] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5708.909126] xhci_hcd 0000:00:14.0: Giveback URB ffff880409bec180, len = 18, expected = 96, status = -121
>[ 5708.909154] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5708.909157] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5708.909327] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5708.909330] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5708.909332] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5708.909333] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5708.909334] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5708.909335] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5708.909337] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5708.909338] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 5708.909339] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5708.909341] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 5708.909342] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5708.909345] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5708.909358] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5708.909362] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 5710.956945] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5710.956948] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae19840, len = 18, expected = 96, status = -121
>[ 5710.956982] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5710.956984] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5710.957150] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5710.957151] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5710.957153] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5710.957154] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5710.957155] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5710.957156] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5710.957158] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5710.957159] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 5710.957160] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5710.957162] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 5710.957163] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5710.957166] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5710.957187] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5710.957189] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 5713.004830] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5713.004834] xhci_hcd 0000:00:14.0: Giveback URB ffff88038be5d900, len = 18, expected = 96, status = -121
>[ 5713.004862] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5713.004866] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5713.005049] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5713.005051] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5713.005052] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5713.005053] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5713.005054] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5713.005055] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5713.005056] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5713.005058] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 5713.005059] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5713.005060] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 5713.005062] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5713.005064] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5713.005075] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5713.005077] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 5715.052667] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5715.052672] xhci_hcd 0000:00:14.0: Giveback URB ffff88038be5d900, len = 18, expected = 96, status = -121
>[ 5715.052699] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5715.052704] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5715.052882] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5715.052884] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5715.052885] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5715.052887] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5715.052888] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5715.052889] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5715.052891] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5715.052892] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 5715.052893] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5715.052895] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 5715.052896] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5715.052903] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5715.052914] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5715.052917] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 5717.100541] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5717.100545] xhci_hcd 0000:00:14.0: Giveback URB ffff88038be5d9c0, len = 18, expected = 96, status = -121
>[ 5717.100573] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5717.100578] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5717.100753] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5717.100757] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5717.100759] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5717.100760] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5717.100761] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5717.100763] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5717.100764] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5717.100766] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 5717.100767] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5717.100769] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 5717.100770] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5717.100773] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5717.100781] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5717.100782] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 5719.148372] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5719.148377] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e600, len = 18, expected = 96, status = -121
>[ 5719.148409] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5719.148411] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5719.148578] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5719.148580] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5719.148582] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5719.148583] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5719.148584] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5719.148586] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5719.148587] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5719.148588] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 5719.148589] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5719.148591] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 5719.148592] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5719.148595] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5719.148614] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5719.148617] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 5721.196257] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5721.196261] xhci_hcd 0000:00:14.0: Giveback URB ffff8804047460c0, len = 18, expected = 96, status = -121
>[ 5721.196282] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5721.196285] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5721.196460] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5721.196464] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5721.196465] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5721.196467] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5721.196468] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5721.196469] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5721.196471] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5721.196472] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 5721.196473] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5721.196476] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 5721.196477] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5721.196480] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5721.196488] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5721.196491] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 5723.244127] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5723.244132] xhci_hcd 0000:00:14.0: Giveback URB ffff880405902600, len = 18, expected = 96, status = -121
>[ 5723.244155] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5723.244160] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5723.244340] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5723.244343] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5723.244344] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5723.244345] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5723.244346] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5723.244348] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5723.244349] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5723.244350] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 5723.244351] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5723.244353] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 5723.244354] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5723.244357] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5723.244374] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5723.244377] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 5725.291977] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5725.291982] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a6840, len = 18, expected = 96, status = -121
>[ 5725.292003] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5725.292006] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5725.292183] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5725.292190] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5725.292192] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5725.292193] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5725.292195] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5725.292196] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5725.292198] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5725.292199] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 5725.292200] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5725.292202] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 5725.292203] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5725.292206] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5725.292214] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5725.292216] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 5727.339815] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5727.339819] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a6840, len = 18, expected = 96, status = -121
>[ 5727.339843] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5727.339847] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5727.340019] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5727.340022] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5727.340023] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5727.340024] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5727.340025] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5727.340026] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5727.340028] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5727.340029] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 5727.340030] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5727.340031] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 5727.340033] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5727.340036] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5727.340051] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5727.340052] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 5729.387640] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5729.387645] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a6840, len = 18, expected = 96, status = -121
>[ 5729.387677] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5729.387680] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5729.387847] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5729.387849] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5729.387851] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5729.387852] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5729.387854] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5729.387855] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5729.387857] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5729.387858] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 5729.387860] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5729.387862] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 5729.387864] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5729.387867] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5729.387882] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5729.387884] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 5731.435513] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5731.435517] xhci_hcd 0000:00:14.0: Giveback URB ffff880406826a80, len = 18, expected = 96, status = -121
>[ 5731.435550] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5731.435553] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5731.435721] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5731.435723] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5731.435725] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5731.435726] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5731.435727] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5731.435729] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5731.435730] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5731.435732] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 5731.435733] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5731.435735] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 5731.435736] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5731.435740] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5731.435758] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5731.435762] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 5733.483369] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5733.483375] xhci_hcd 0000:00:14.0: Giveback URB ffff880406826d80, len = 18, expected = 96, status = -121
>[ 5733.483408] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5733.483413] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5733.483592] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5733.483596] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5733.483598] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5733.483600] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5733.483602] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5733.483604] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5733.483605] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5733.483607] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 5733.483608] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5733.483610] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 5733.483612] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5733.483616] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5733.483622] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5733.483625] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 5735.531249] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5735.531255] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da540, len = 18, expected = 96, status = -121
>[ 5735.531287] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5735.531293] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5735.531461] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5735.531467] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5735.531469] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5735.531470] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5735.531472] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5735.531474] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5735.531476] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5735.531477] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 5735.531478] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5735.531481] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 5735.531483] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5735.531485] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5735.531496] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5735.531498] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 5737.579099] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5737.579102] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fe6c0, len = 18, expected = 96, status = -121
>[ 5737.579131] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5737.579135] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5737.579306] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5737.579309] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5737.579310] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5737.579311] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5737.579313] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5737.579314] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5737.579315] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5737.579316] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 5737.579317] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5737.579319] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 5737.579320] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5737.579323] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5737.579339] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5737.579340] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 5739.626937] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5739.626940] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fe6c0, len = 18, expected = 96, status = -121
>[ 5739.626974] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5739.626976] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5739.627144] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5739.627145] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5739.627147] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5739.627148] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5739.627149] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5739.627150] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5739.627151] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5739.627152] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 5739.627153] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5739.627155] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 5739.627157] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5739.627159] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5739.627179] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5739.627180] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 5741.674806] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5741.674810] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fed80, len = 18, expected = 96, status = -121
>[ 5741.674843] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5741.674846] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5741.675013] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5741.675015] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5741.675017] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5741.675018] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5741.675019] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5741.675021] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5741.675022] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5741.675023] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 5741.675024] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5741.675026] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 5741.675028] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5741.675031] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5741.675048] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5741.675050] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 5743.722661] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5743.722666] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fed80, len = 18, expected = 96, status = -121
>[ 5743.722699] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5743.722701] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5743.722863] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5743.722865] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5743.722867] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5743.722868] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5743.722869] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5743.722870] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5743.722872] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5743.722873] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 5743.722874] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5743.722876] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 5743.722878] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5743.722880] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5743.722898] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5743.722900] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 5745.770514] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5745.770517] xhci_hcd 0000:00:14.0: Giveback URB ffff880407a23000, len = 18, expected = 96, status = -121
>[ 5745.770552] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5745.770554] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5745.770721] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5745.770723] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5745.770724] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5745.770725] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5745.770726] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5745.770727] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5745.770729] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5745.770730] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 5745.770731] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5745.770732] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 5745.770734] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5745.770736] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5745.770757] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5745.770758] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 5747.818405] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5747.818415] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fbd80, len = 18, expected = 96, status = -121
>[ 5747.818528] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5747.818533] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5747.818709] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5747.818713] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5747.818715] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5747.818718] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5747.818720] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5747.818722] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5747.818725] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5747.818728] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 5747.818730] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5747.818733] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 5747.818736] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5747.818741] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5747.818748] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5747.818753] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 5749.866237] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5749.866242] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fbd80, len = 18, expected = 96, status = -121
>[ 5749.866275] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5749.866279] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5749.866451] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5749.866455] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5749.866456] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5749.866458] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5749.866460] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5749.866462] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5749.866464] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5749.866466] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 5749.866467] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5749.866470] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 5749.866472] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5749.866475] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5749.866484] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5749.866487] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 5751.914137] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5751.914148] xhci_hcd 0000:00:14.0: Giveback URB ffff8804069dca80, len = 18, expected = 96, status = -121
>[ 5751.914173] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5751.914179] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5751.914355] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5751.914360] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5751.914364] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5751.914369] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5751.914373] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5751.914377] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5751.914382] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5751.914387] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 5751.914391] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5751.914398] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 5751.914403] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5751.914420] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5751.914430] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 5753.961955] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5753.961961] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b61ecc0, len = 18, expected = 96, status = -121
>[ 5753.961992] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5753.961995] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5753.962161] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5753.962164] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5753.962166] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5753.962168] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5753.962169] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5753.962171] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5753.962173] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5753.962174] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 5753.962176] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5753.962178] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 5753.962180] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5753.962182] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5753.962197] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5753.962200] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 5756.009871] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5756.009879] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5f4f00, len = 18, expected = 96, status = -121
>[ 5756.009909] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5756.009915] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5756.010103] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5756.010111] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5756.010116] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5756.010121] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5756.010125] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5756.010130] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5756.010135] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5756.010140] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 5756.010144] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5756.010150] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 5756.010155] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5756.010164] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5756.010169] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 5758.057692] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5758.057698] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692ed80, len = 18, expected = 96, status = -121
>[ 5758.057727] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5758.057731] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5758.057909] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5758.057912] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5758.057914] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5758.057915] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5758.057917] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5758.057919] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5758.057921] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5758.057923] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 5758.057924] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5758.057927] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 5758.057929] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5758.057940] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5758.057945] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 5760.105557] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5760.105563] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692ed80, len = 18, expected = 96, status = -121
>[ 5760.105589] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5760.105596] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5760.105781] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5760.105784] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5760.105788] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5760.105790] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5760.105792] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5760.105795] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5760.105797] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5760.105800] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 5760.105802] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5760.105806] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 5760.105807] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5760.105815] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5760.105819] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 5762.153417] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5762.153424] xhci_hcd 0000:00:14.0: Giveback URB ffff8804064a0900, len = 18, expected = 96, status = -121
>[ 5762.153449] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5762.153454] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5762.153644] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5762.153650] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5762.153654] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5762.153657] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5762.153666] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5762.153668] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5762.153671] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5762.153673] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 5762.153675] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5762.153679] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 5762.153681] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5762.153693] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5762.153698] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 5764.201264] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5764.201270] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692ee40, len = 18, expected = 96, status = -121
>[ 5764.201299] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5764.201303] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5764.201484] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5764.201490] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5764.201494] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5764.201497] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5764.201500] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5764.201504] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5764.201508] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5764.201511] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 5764.201514] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5764.201519] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 5764.201521] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5764.201535] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5764.201539] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 5766.249143] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5766.249153] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fecc0, len = 18, expected = 96, status = -121
>[ 5766.249177] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5766.249184] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5766.249370] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5766.249377] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5766.249381] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5766.249385] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5766.249389] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5766.249394] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5766.249399] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5766.249403] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 5766.249407] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5766.249414] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 5766.249419] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5766.249432] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5766.249438] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 5768.296971] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5768.296977] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369b3c0, len = 18, expected = 96, status = -121
>[ 5768.297000] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5768.297005] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5768.297184] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5768.297188] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5768.297191] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5768.297193] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5768.297195] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5768.297197] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5768.297200] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5768.297202] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 5768.297204] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5768.297208] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 5768.297210] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5768.297218] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5768.297221] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 5770.344861] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5770.344869] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369bcc0, len = 18, expected = 96, status = -121
>[ 5770.344899] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5770.344906] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5770.345099] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5770.345103] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5770.345109] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5770.345112] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5770.345115] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5770.345118] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5770.345122] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5770.345125] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 5770.345127] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5770.345132] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 5770.345135] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5770.345145] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5770.345149] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 5772.392714] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5772.392721] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b7f2780, len = 18, expected = 96, status = -121
>[ 5772.392746] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5772.392751] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5772.392925] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5772.392928] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5772.392931] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5772.392932] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5772.392934] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5772.392937] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5772.392939] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5772.392941] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 5772.392943] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5772.392946] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 5772.392949] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5772.392952] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5772.392961] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5772.392963] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 5774.440535] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5774.440542] xhci_hcd 0000:00:14.0: Giveback URB ffff8804064a0cc0, len = 18, expected = 96, status = -121
>[ 5774.440571] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5774.440575] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5774.440747] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5774.440750] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5774.440752] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5774.440753] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5774.440755] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5774.440762] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5774.440764] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5774.440766] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 5774.440767] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5774.440773] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 5774.440775] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5774.440779] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5774.440786] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5774.440791] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 5776.488421] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5776.488431] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b2000, len = 18, expected = 96, status = -121
>[ 5776.488456] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5776.488461] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5776.488644] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5776.488652] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5776.488656] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5776.488659] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5776.488662] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5776.488666] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5776.488671] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5776.488675] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 5776.488679] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5776.488685] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 5776.488689] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5776.488700] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5776.488704] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 5778.536258] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5778.536268] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941600, len = 18, expected = 96, status = -121
>[ 5778.536292] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5778.536298] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5778.536475] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5778.536479] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5778.536483] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5778.536486] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5778.536489] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5778.536493] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5778.536497] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5778.536501] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 5778.536504] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5778.536509] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 5778.536512] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5778.536516] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5778.536527] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5778.536533] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 5780.584118] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5780.584122] xhci_hcd 0000:00:14.0: Giveback URB ffff8804034e5e40, len = 18, expected = 96, status = -121
>[ 5780.584144] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5780.584147] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5780.584323] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5780.584325] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5780.584326] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5780.584328] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5780.584329] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5780.584331] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5780.584332] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5780.584333] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 5780.584335] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5780.584336] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 5780.584337] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5780.584340] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5780.584353] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5780.584358] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 5782.631958] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5782.631964] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d3a0c0, len = 18, expected = 96, status = -121
>[ 5782.631993] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5782.631997] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5782.632169] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5782.632173] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5782.632175] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5782.632178] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5782.632181] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5782.632182] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5782.632184] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5782.632186] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 5782.632189] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5782.632193] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 5782.632195] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5782.632198] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5782.632208] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5782.632218] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 5784.679818] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5784.679826] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dcb3fa80, len = 18, expected = 96, status = -121
>[ 5784.679854] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5784.679858] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5784.680030] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5784.680034] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5784.680037] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5784.680040] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5784.680043] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5784.680046] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5784.680050] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5784.680053] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 5784.680056] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5784.680060] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 5784.680064] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5784.680069] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5784.680077] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5784.680082] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 5786.727729] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5786.727737] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d3a9c0, len = 18, expected = 96, status = -121
>[ 5786.727764] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5786.727770] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5786.727948] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5786.727953] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5786.727955] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5786.727957] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5786.727958] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5786.727960] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5786.727963] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5786.727965] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 5786.727967] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5786.727971] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 5786.727972] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5786.727985] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5786.727990] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 5788.775571] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5788.775577] xhci_hcd 0000:00:14.0: Giveback URB ffff88040459acc0, len = 18, expected = 96, status = -121
>[ 5788.775600] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5788.775604] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5788.775782] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5788.775788] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5788.775791] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5788.775794] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5788.775796] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5788.775799] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5788.775802] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5788.775804] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 5788.775805] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5788.775808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 5788.775810] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5788.775820] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5788.775824] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 5790.823354] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5790.823360] xhci_hcd 0000:00:14.0: Giveback URB ffff8803cb5fe480, len = 18, expected = 96, status = -121
>[ 5790.823391] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5790.823394] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5790.823560] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5790.823562] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5790.823564] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5790.823566] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5790.823567] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5790.823569] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5790.823572] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5790.823573] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 5790.823575] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5790.823578] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 5790.823580] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5790.823583] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5790.823596] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5790.823598] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 5792.871296] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5792.871302] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5f49c0, len = 18, expected = 96, status = -121
>[ 5792.871324] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5792.871327] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5792.871502] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5792.871505] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5792.871507] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5792.871508] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5792.871510] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5792.871511] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5792.871513] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5792.871515] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 5792.871516] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5792.871519] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 5792.871520] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5792.871523] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5792.871539] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5792.871543] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 5794.825458] tun: Universal TUN/TAP device driver, 1.6
>[ 5794.825461] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
>[ 5794.919128] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5794.919133] xhci_hcd 0000:00:14.0: Giveback URB ffff8804039410c0, len = 18, expected = 96, status = -121
>[ 5794.919155] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5794.919158] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5794.919324] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5794.919327] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5794.919329] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5794.919331] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5794.919332] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5794.919334] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5794.919336] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5794.919338] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 5794.919340] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5794.919343] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 5794.919345] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5794.919349] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5794.919361] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5794.919363] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 5796.966961] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5796.966965] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941000, len = 18, expected = 96, status = -121
>[ 5796.966992] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5796.966996] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5796.967169] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5796.967172] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5796.967173] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5796.967174] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5796.967175] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5796.967177] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5796.967178] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5796.967179] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 5796.967180] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5796.967182] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 5796.967183] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5796.967186] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5796.967200] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5796.967202] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 5799.014816] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5799.014819] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941000, len = 18, expected = 96, status = -121
>[ 5799.014852] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5799.014854] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5799.015015] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5799.015017] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5799.015018] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5799.015019] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5799.015020] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5799.015021] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5799.015023] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5799.015024] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 5799.015025] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5799.015027] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 5799.015028] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5799.015031] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5799.015052] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5799.015053] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 5801.062754] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5801.062769] xhci_hcd 0000:00:14.0: Giveback URB ffff88040649da80, len = 18, expected = 96, status = -121
>[ 5801.062805] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5801.062814] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5801.063003] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5801.063013] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5801.063021] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5801.063028] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5801.063035] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5801.063042] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5801.063050] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5801.063058] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 5801.063064] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5801.063075] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 5801.063083] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5801.063108] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5801.063123] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 5803.110567] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5803.110573] xhci_hcd 0000:00:14.0: Giveback URB ffff88040649d780, len = 18, expected = 96, status = -121
>[ 5803.110600] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5803.110603] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5803.110782] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5803.110788] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5803.110791] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5803.110792] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5803.110794] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5803.110796] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5803.110798] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5803.110801] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 5803.110802] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5803.110807] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 5803.110809] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5803.110820] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5803.110823] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 5805.158461] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5805.158477] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dacb6d80, len = 18, expected = 96, status = -121
>[ 5805.158575] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5805.158585] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5805.158773] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5805.158782] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5805.158790] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5805.158796] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5805.158803] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5805.158810] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5805.158817] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5805.158824] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 5805.158830] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5805.158840] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 5805.158848] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5805.158872] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5805.158887] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 5807.206246] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5807.206251] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884fe40, len = 18, expected = 96, status = -121
>[ 5807.206284] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5807.206286] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5807.206452] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5807.206454] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5807.206456] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5807.206457] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5807.206458] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5807.206460] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5807.206461] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5807.206462] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 5807.206464] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5807.206466] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 5807.206467] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5807.206470] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5807.206489] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5807.206491] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 5809.254082] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5809.254088] xhci_hcd 0000:00:14.0: Giveback URB ffff880403bbff00, len = 18, expected = 96, status = -121
>[ 5809.254120] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5809.254124] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5809.254297] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5809.254300] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5809.254302] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5809.254303] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5809.254305] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5809.254307] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5809.254309] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5809.254311] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 5809.254313] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5809.254316] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 5809.254318] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5809.254321] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5809.254330] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5809.254334] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 5811.301965] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5811.301968] xhci_hcd 0000:00:14.0: Giveback URB ffff88040685e000, len = 18, expected = 96, status = -121
>[ 5811.301996] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5811.302000] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5811.302178] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5811.302180] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5811.302181] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5811.302182] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5811.302183] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5811.302185] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5811.302186] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5811.302187] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 5811.302188] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5811.302190] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 5811.302191] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5811.302194] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5811.302204] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5811.302206] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 5813.349820] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5813.349825] xhci_hcd 0000:00:14.0: Giveback URB ffff880403bbf6c0, len = 18, expected = 96, status = -121
>[ 5813.349844] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5813.349847] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5813.350020] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5813.350023] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5813.350026] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5813.350027] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5813.350028] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5813.350030] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5813.350031] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5813.350033] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 5813.350034] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5813.350036] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 5813.350037] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5813.350041] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5813.350050] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5813.350052] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 5815.397714] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5815.397724] xhci_hcd 0000:00:14.0: Giveback URB ffff880406023540, len = 18, expected = 96, status = -121
>[ 5815.397772] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5815.397782] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5815.397984] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5815.397992] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5815.397998] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5815.398002] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5815.398006] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5815.398010] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5815.398022] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5815.398024] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 5815.398026] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5815.398031] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 5815.398035] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5815.398051] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5815.398058] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 5817.445580] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5817.445587] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae3f600, len = 18, expected = 96, status = -121
>[ 5817.445616] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5817.445620] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5817.445786] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5817.445790] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5817.445792] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5817.445794] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5817.445796] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5817.445798] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5817.445800] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5817.445802] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 5817.445804] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5817.445808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 5817.445810] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5817.445813] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5817.445828] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5817.445833] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 5819.493400] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5819.493407] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c61d0c0, len = 18, expected = 96, status = -121
>[ 5819.493435] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5819.493439] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5819.493615] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5819.493618] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5819.493621] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5819.493624] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5819.493627] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5819.493629] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5819.493631] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5819.493633] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 5819.493636] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5819.493640] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 5819.493642] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5819.493646] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5819.493654] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5819.493658] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 5821.541291] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5821.541307] xhci_hcd 0000:00:14.0: Giveback URB ffff880407778cc0, len = 18, expected = 96, status = -121
>[ 5821.541350] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5821.541359] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5821.541564] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5821.541578] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5821.541586] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5821.541594] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5821.541600] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5821.541608] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5821.541616] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5821.541623] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 5821.541627] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5821.541634] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 5821.541639] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5821.541651] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5821.541657] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 5823.589073] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5823.589078] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369b3c0, len = 18, expected = 96, status = -121
>[ 5823.589110] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5823.589112] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5823.589284] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5823.589288] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5823.589291] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5823.589293] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5823.589294] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5823.589296] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5823.589298] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5823.589300] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 5823.589302] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5823.589305] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 5823.589307] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5823.589311] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5823.589317] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5823.589322] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 5825.636997] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5825.637002] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc1a4b40, len = 18, expected = 96, status = -121
>[ 5825.637025] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5825.637029] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5825.637209] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5825.637212] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5825.637214] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5825.637217] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5825.637219] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5825.637222] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5825.637224] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5825.637226] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 5825.637228] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5825.637232] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 5825.637235] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5825.637242] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5825.637246] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 5827.684855] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5827.684862] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5f4000, len = 18, expected = 96, status = -121
>[ 5827.684887] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5827.684892] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5827.685076] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5827.685083] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5827.685087] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5827.685090] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5827.685093] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5827.685096] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5827.685099] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5827.685101] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 5827.685103] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5827.685107] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 5827.685109] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5827.685122] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5827.685126] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 5829.732758] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5829.732765] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c56ba80, len = 18, expected = 96, status = -121
>[ 5829.732790] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5829.732795] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5829.732985] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5829.732992] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5829.732996] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5829.732999] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5829.733002] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5829.733006] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5829.733010] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5829.733013] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 5829.733016] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5829.733020] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 5829.733022] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5829.733035] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5829.733039] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 5831.780559] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5831.780563] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae80840, len = 18, expected = 96, status = -121
>[ 5831.780587] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5831.780592] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5831.780763] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5831.780766] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5831.780768] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5831.780769] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5831.780769] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5831.780771] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5831.780772] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5831.780773] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 5831.780774] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5831.780775] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 5831.780776] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5831.780779] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5831.780797] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5831.780799] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 5833.828395] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5833.828402] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f170c0, len = 18, expected = 96, status = -121
>[ 5833.828430] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5833.828434] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5833.828616] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5833.828625] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5833.828627] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5833.828628] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5833.828630] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5833.828632] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5833.828634] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5833.828636] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 5833.828640] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5833.828643] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 5833.828645] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5833.828653] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5833.828656] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 5835.876260] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5835.876265] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ffa240, len = 18, expected = 96, status = -121
>[ 5835.876297] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5835.876299] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5835.876466] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5835.876468] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5835.876470] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5835.876472] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5835.876474] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5835.876476] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5835.876478] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5835.876480] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 5835.876482] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5835.876484] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 5835.876486] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5835.876490] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5835.876502] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5835.876504] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 5837.924096] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5837.924101] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c56be40, len = 18, expected = 96, status = -121
>[ 5837.924134] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5837.924136] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5837.924302] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5837.924304] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5837.924306] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5837.924308] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5837.924310] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5837.924311] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5837.924313] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5837.924315] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 5837.924317] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5837.924320] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 5837.924322] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5837.924325] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5837.924339] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5837.924341] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 5839.971963] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5839.971968] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da9340c0, len = 18, expected = 96, status = -121
>[ 5839.971999] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5839.972002] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5839.972180] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5839.972183] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5839.972186] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5839.972187] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5839.972189] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5839.972191] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5839.972193] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5839.972195] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 5839.972196] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5839.972199] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 5839.972202] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5839.972205] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5839.972214] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5839.972218] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 5842.019846] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5842.019851] xhci_hcd 0000:00:14.0: Giveback URB ffff880405888f00, len = 18, expected = 96, status = -121
>[ 5842.019875] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5842.019877] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5842.020042] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5842.020044] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5842.020046] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5842.020047] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5842.020049] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5842.020050] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5842.020051] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5842.020053] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 5842.020054] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5842.020056] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 5842.020058] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5842.020060] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5842.020080] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5842.020082] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 5844.067679] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5844.067686] xhci_hcd 0000:00:14.0: Giveback URB ffff880403746900, len = 18, expected = 96, status = -121
>[ 5844.067720] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5844.067724] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5844.067900] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5844.067904] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5844.067907] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5844.067909] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5844.067912] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5844.067915] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5844.067918] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5844.067920] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 5844.067923] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5844.067927] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 5844.067930] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5844.067935] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5844.067940] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5844.067944] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 5846.115537] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5846.115543] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbb11f00, len = 18, expected = 96, status = -121
>[ 5846.115573] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5846.115576] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5846.115742] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5846.115745] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5846.115748] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5846.115750] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5846.115752] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5846.115753] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5846.115755] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5846.115756] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 5846.115757] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5846.115761] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 5846.115763] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5846.115767] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5846.115778] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5846.115784] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 5848.163408] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5848.163414] xhci_hcd 0000:00:14.0: Giveback URB ffff8804059020c0, len = 18, expected = 96, status = -121
>[ 5848.163435] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5848.163439] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5848.163616] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5848.163619] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5848.163622] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5848.163625] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5848.163627] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5848.163629] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5848.163631] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5848.163633] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 5848.163635] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5848.163638] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 5848.163639] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5848.163646] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5848.163649] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 5850.211280] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5850.211286] xhci_hcd 0000:00:14.0: Giveback URB ffff8804034e5300, len = 18, expected = 96, status = -121
>[ 5850.211306] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5850.211309] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5850.211486] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5850.211489] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5850.211491] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5850.211493] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5850.211495] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5850.211496] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5850.211498] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5850.211500] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 5850.211502] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5850.211505] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 5850.211507] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5850.211510] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5850.211515] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5850.211519] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 5852.259090] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5852.259096] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc383600, len = 18, expected = 96, status = -121
>[ 5852.259126] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5852.259130] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5852.259302] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5852.259305] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5852.259307] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5852.259308] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5852.259310] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5852.259311] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5852.259314] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5852.259316] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 5852.259317] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5852.259320] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 5852.259322] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5852.259325] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5852.259339] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5852.259342] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 5854.306989] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5854.306995] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da180, len = 18, expected = 96, status = -121
>[ 5854.307018] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5854.307023] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5854.307200] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5854.307203] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5854.307205] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5854.307207] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5854.307211] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5854.307214] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5854.307216] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5854.307219] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 5854.307221] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5854.307225] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 5854.307227] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5854.307234] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5854.307238] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 5856.354832] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5856.354841] xhci_hcd 0000:00:14.0: Giveback URB ffff880405b373c0, len = 18, expected = 96, status = -121
>[ 5856.354866] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5856.354871] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5856.355047] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5856.355055] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5856.355057] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5856.355059] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5856.355060] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5856.355063] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5856.355066] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5856.355069] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 5856.355072] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5856.355076] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 5856.355079] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5856.355083] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5856.355090] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5856.355094] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 5858.403683] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5858.403692] xhci_hcd 0000:00:14.0: Giveback URB ffff880409bec840, len = 18, expected = 96, status = -121
>[ 5858.403717] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5858.403722] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5858.403895] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5858.403899] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5858.403902] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5858.403904] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5858.403906] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5858.403909] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5858.403911] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5858.403914] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 5858.403916] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5858.403919] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 5858.403922] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5858.403927] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5858.403936] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5858.403944] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 5860.450577] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5860.450582] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea7180, len = 18, expected = 96, status = -121
>[ 5860.450603] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5860.450606] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5860.450784] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5860.450792] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5860.450794] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5860.450795] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5860.450797] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5860.450799] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5860.450800] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5860.450802] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 5860.450805] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5860.450808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 5860.450809] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5860.450816] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5860.450819] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 5862.498408] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5862.498414] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db446180, len = 18, expected = 96, status = -121
>[ 5862.498443] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5862.498447] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5862.498628] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5862.498631] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5862.498633] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5862.498634] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5862.498636] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5862.498640] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5862.498642] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5862.498645] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 5862.498647] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5862.498650] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 5862.498652] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5862.498660] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5862.498663] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 5864.546265] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5864.546269] xhci_hcd 0000:00:14.0: Giveback URB ffff880405888a80, len = 18, expected = 96, status = -121
>[ 5864.546293] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5864.546297] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5864.546482] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5864.546485] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5864.546486] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5864.546488] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5864.546489] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5864.546490] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5864.546491] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5864.546492] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 5864.546493] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5864.546495] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 5864.546497] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5864.546500] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5864.546504] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5864.546507] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 5866.594121] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5866.594125] xhci_hcd 0000:00:14.0: Giveback URB ffff880405888a80, len = 18, expected = 96, status = -121
>[ 5866.594146] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5866.594149] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5866.594323] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5866.594327] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5866.594328] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5866.594330] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5866.594331] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5866.594332] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5866.594334] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5866.594335] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 5866.594336] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5866.594338] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 5866.594340] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5866.594343] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5866.594352] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5866.594354] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 5868.641966] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5868.641972] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7eb000, len = 18, expected = 96, status = -121
>[ 5868.642003] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5868.642005] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5868.642171] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5868.642173] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5868.642174] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5868.642175] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5868.642176] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5868.642179] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5868.642180] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5868.642182] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 5868.642184] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5868.642186] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 5868.642188] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5868.642191] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5868.642208] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5868.642210] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 5870.689823] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5870.689831] xhci_hcd 0000:00:14.0: Giveback URB ffff880407778180, len = 18, expected = 96, status = -121
>[ 5870.689862] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5870.689869] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5870.690056] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5870.690059] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5870.690061] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5870.690063] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5870.690066] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5870.690069] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5870.690072] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5870.690074] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 5870.690076] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5870.690080] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 5870.690082] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5870.690090] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5870.690093] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 5872.737670] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5872.737676] xhci_hcd 0000:00:14.0: Giveback URB ffff880406a7f480, len = 18, expected = 96, status = -121
>[ 5872.737708] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5872.737714] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5872.737893] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5872.737896] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5872.737897] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5872.737899] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5872.737900] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5872.737901] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5872.737903] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5872.737905] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 5872.737906] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5872.737908] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 5872.737909] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5872.737912] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5872.737924] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5872.737927] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 5874.785525] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5874.785530] xhci_hcd 0000:00:14.0: Giveback URB ffff880407778840, len = 18, expected = 96, status = -121
>[ 5874.785561] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5874.785564] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5874.785736] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5874.785739] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5874.785740] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5874.785741] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5874.785743] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5874.785746] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5874.785748] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5874.785750] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 5874.785751] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5874.785754] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 5874.785756] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5874.785766] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5874.785769] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 5876.833426] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5876.833435] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae1a0c0, len = 18, expected = 96, status = -121
>[ 5876.833467] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5876.833475] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5876.833668] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5876.833675] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5876.833679] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5876.833682] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5876.833685] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5876.833688] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5876.833691] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5876.833693] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 5876.833696] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5876.833701] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 5876.833704] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5876.833719] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5876.833725] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 5878.881267] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5878.881272] xhci_hcd 0000:00:14.0: Giveback URB ffff880405023b40, len = 18, expected = 96, status = -121
>[ 5878.881302] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5878.881305] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5878.881472] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5878.881475] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5878.881476] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5878.881477] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5878.881478] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5878.881480] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5878.881481] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5878.881483] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 5878.881484] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5878.881486] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 5878.881487] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5878.881490] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5878.881506] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5878.881509] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 5880.929102] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5880.929110] xhci_hcd 0000:00:14.0: Giveback URB ffff880403cc2e40, len = 18, expected = 96, status = -121
>[ 5880.929138] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5880.929143] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5880.929316] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5880.929319] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5880.929321] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5880.929323] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5880.929325] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5880.929327] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5880.929329] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5880.929331] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 5880.929333] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5880.929335] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 5880.929338] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5880.929342] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5880.929349] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5880.929352] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 5882.976949] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5882.976957] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd94b40, len = 18, expected = 96, status = -121
>[ 5882.976987] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5882.976994] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5882.977179] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5882.977183] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5882.977185] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5882.977188] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5882.977190] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5882.977192] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5882.977195] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5882.977197] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 5882.977199] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5882.977203] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 5882.977205] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5882.977216] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5882.977220] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 5885.024813] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5885.024818] xhci_hcd 0000:00:14.0: Giveback URB ffff880409bec840, len = 18, expected = 96, status = -121
>[ 5885.024850] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5885.024852] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5885.025020] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5885.025022] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5885.025024] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5885.025025] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5885.025027] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5885.025028] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5885.025030] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5885.025032] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 5885.025033] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5885.025035] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 5885.025037] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5885.025040] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5885.025054] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5885.025057] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 5887.072763] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5887.072780] xhci_hcd 0000:00:14.0: Giveback URB ffff880406826c00, len = 18, expected = 96, status = -121
>[ 5887.072821] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5887.072834] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5887.073028] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5887.073038] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5887.073046] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5887.073052] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5887.073059] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5887.073066] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5887.073074] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5887.073082] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 5887.073089] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5887.073099] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 5887.073106] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5887.073130] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5887.073144] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 5889.120583] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5889.120594] xhci_hcd 0000:00:14.0: Giveback URB ffff880406826900, len = 18, expected = 96, status = -121
>[ 5889.120623] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5889.120631] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5889.120822] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5889.120830] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5889.120833] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5889.120836] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5889.120839] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5889.120842] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5889.120846] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5889.120851] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 5889.120856] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5889.120863] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 5889.120868] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5889.120883] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5889.120891] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 5891.168383] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5891.168389] xhci_hcd 0000:00:14.0: Giveback URB ffff88040364a780, len = 18, expected = 96, status = -121
>[ 5891.168419] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5891.168422] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5891.168607] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5891.168610] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5891.168612] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5891.168614] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5891.168616] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5891.168618] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5891.168620] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5891.168622] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 5891.168624] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5891.168626] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 5891.168628] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5891.168632] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5891.168641] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5891.168644] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 5893.216324] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5893.216336] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae19180, len = 18, expected = 96, status = -121
>[ 5893.216367] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5893.216378] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5893.216590] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5893.216603] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5893.216610] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5893.216617] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5893.216623] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5893.216630] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5893.216638] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5893.216646] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 5893.216653] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5893.216664] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 5893.216668] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5893.216695] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5893.216704] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 5895.264177] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5895.264194] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fa240, len = 18, expected = 96, status = -121
>[ 5895.264238] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5895.264255] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5895.264468] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5895.264477] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5895.264482] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5895.264486] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5895.264490] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5895.264495] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5895.264500] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5895.264505] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 5895.264509] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5895.264516] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 5895.264520] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5895.264537] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5895.264548] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 5897.311999] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5897.312008] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6b0240, len = 18, expected = 96, status = -121
>[ 5897.312032] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5897.312037] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5897.312208] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5897.312211] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5897.312214] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5897.312217] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5897.312220] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5897.312223] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5897.312226] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5897.312229] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 5897.312231] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5897.312236] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 5897.312239] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5897.312243] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5897.312255] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5897.312264] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 5899.359932] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5899.359945] xhci_hcd 0000:00:14.0: Giveback URB ffff880403cc23c0, len = 18, expected = 96, status = -121
>[ 5899.359990] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5899.360003] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5899.360216] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5899.360224] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5899.360230] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5899.360236] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5899.360244] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5899.360251] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5899.360259] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5899.360266] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 5899.360272] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5899.360283] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 5899.360290] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5899.360314] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5899.360344] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 5901.407796] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5901.407808] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fa780, len = 18, expected = 96, status = -121
>[ 5901.407840] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5901.407850] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5901.408063] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5901.408076] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5901.408085] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5901.408092] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5901.408098] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5901.408104] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5901.408109] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5901.408114] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 5901.408118] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5901.408124] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 5901.408129] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5901.408160] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5901.408171] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 5903.455575] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5903.455585] xhci_hcd 0000:00:14.0: Giveback URB ffff880407a23600, len = 18, expected = 96, status = -121
>[ 5903.455609] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5903.455615] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5903.455792] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5903.455796] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5903.455800] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5903.455803] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5903.455806] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5903.455810] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5903.455814] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5903.455817] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 5903.455821] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5903.455826] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 5903.455830] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5903.455837] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5903.455846] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5903.455856] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 5905.503449] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5905.503458] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900240, len = 18, expected = 96, status = -121
>[ 5905.503490] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5905.503498] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5905.503690] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5905.503699] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5905.503704] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5905.503708] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5905.503712] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5905.503718] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5905.503723] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5905.503728] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 5905.503732] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5905.503739] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 5905.503744] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5905.503756] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5905.503764] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 5907.551294] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5907.551304] xhci_hcd 0000:00:14.0: Giveback URB ffff880408801c00, len = 18, expected = 96, status = -121
>[ 5907.551328] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5907.551334] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5907.551516] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5907.551520] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5907.551524] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5907.551526] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5907.551529] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5907.551532] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5907.551536] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5907.551539] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 5907.551542] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5907.551546] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 5907.551549] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5907.551565] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5907.551573] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 5909.599087] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5909.599092] xhci_hcd 0000:00:14.0: Giveback URB ffff88040580ae40, len = 18, expected = 96, status = -121
>[ 5909.599124] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5909.599127] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5909.599293] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5909.599295] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5909.599297] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5909.599299] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5909.599300] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5909.599302] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5909.599304] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5909.599306] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 5909.599307] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5909.599309] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 5909.599310] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5909.599313] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5909.599329] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5909.599331] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 5911.647036] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5911.647048] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8cc0, len = 18, expected = 96, status = -121
>[ 5911.647080] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5911.647090] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5911.647300] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5911.647313] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5911.647321] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5911.647328] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5911.647334] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5911.647342] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5911.647349] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5911.647357] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 5911.647364] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5911.647375] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 5911.647382] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5911.647406] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5911.647425] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 5913.694862] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5913.694872] xhci_hcd 0000:00:14.0: Giveback URB ffff88040580acc0, len = 18, expected = 96, status = -121
>[ 5913.694895] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5913.694901] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5913.695082] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5913.695087] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5913.695090] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5913.695093] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5913.695095] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5913.695097] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5913.695100] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5913.695103] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 5913.695105] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5913.695108] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 5913.695111] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5913.695122] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5913.695128] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 5915.742728] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5915.742739] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8540, len = 18, expected = 96, status = -121
>[ 5915.742771] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5915.742780] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5915.742977] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5915.742988] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5915.742994] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5915.742999] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5915.743005] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5915.743010] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5915.743016] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5915.743022] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 5915.743027] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5915.743036] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 5915.743041] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5915.743062] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5915.743073] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 5917.790614] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5917.790627] xhci_hcd 0000:00:14.0: Giveback URB ffff8804063db600, len = 18, expected = 96, status = -121
>[ 5917.790657] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5917.790667] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5917.790859] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5917.790865] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5917.790869] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5917.790873] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5917.790877] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5917.790882] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5917.790887] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5917.790891] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 5917.790896] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5917.790903] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 5917.790908] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5917.790922] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5917.790930] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 5919.838514] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5919.838527] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc383e40, len = 18, expected = 96, status = -121
>[ 5919.838574] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5919.838584] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5919.838785] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5919.838794] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5919.838801] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5919.838808] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5919.838815] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5919.838822] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5919.838829] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5919.838837] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 5919.838843] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5919.838854] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 5919.838862] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5919.838886] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5919.838894] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 5921.886288] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5921.886298] xhci_hcd 0000:00:14.0: Giveback URB ffff880404dc0600, len = 18, expected = 96, status = -121
>[ 5921.886321] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5921.886326] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5921.886498] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5921.886502] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5921.886506] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5921.886510] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5921.886514] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5921.886518] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5921.886522] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5921.886526] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 5921.886530] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5921.886536] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 5921.886540] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5921.886545] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5921.886552] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5921.886559] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 5923.934121] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5923.934127] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e90a80, len = 18, expected = 96, status = -121
>[ 5923.934156] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5923.934160] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5923.934335] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5923.934339] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5923.934342] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5923.934345] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5923.934348] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5923.934351] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5923.934354] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5923.934357] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 5923.934360] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5923.934363] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 5923.934370] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5923.934374] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5923.934379] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5923.934383] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 5925.982053] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5925.982070] xhci_hcd 0000:00:14.0: Giveback URB ffff8804063db480, len = 18, expected = 96, status = -121
>[ 5925.982113] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5925.982130] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5925.982337] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5925.982347] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5925.982353] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5925.982360] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5925.982367] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5925.982375] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5925.982382] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5925.982390] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 5925.982397] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5925.982408] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 5925.982416] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5925.982438] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5925.982447] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 5928.029817] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5928.029823] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789fa80, len = 18, expected = 96, status = -121
>[ 5928.029854] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5928.029857] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5928.030029] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5928.030033] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5928.030035] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5928.030037] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5928.030038] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5928.030040] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5928.030043] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5928.030045] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 5928.030047] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5928.030050] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 5928.030052] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5928.030060] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5928.030064] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 5930.077696] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5930.077705] xhci_hcd 0000:00:14.0: Giveback URB ffff8804063db900, len = 18, expected = 96, status = -121
>[ 5930.077730] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5930.077736] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5930.077907] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5930.077911] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5930.077914] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5930.077917] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5930.077921] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5930.077924] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5930.077928] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5930.077932] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 5930.077935] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5930.077941] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 5930.077944] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5930.077950] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5930.077959] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5930.077966] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 5932.125617] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5932.125628] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd97540, len = 18, expected = 96, status = -121
>[ 5932.125665] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5932.125673] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5932.125865] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5932.125876] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5932.125882] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5932.125886] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5932.125890] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5932.125894] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5932.125898] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5932.125902] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 5932.125905] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5932.125911] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 5932.125915] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5932.125929] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5932.125939] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 5934.173486] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5934.173503] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd97540, len = 18, expected = 96, status = -121
>[ 5934.173531] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5934.173540] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5934.173744] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5934.173755] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5934.173760] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5934.173764] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5934.173768] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5934.173773] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5934.173778] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5934.173782] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 5934.173786] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5934.173793] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 5934.173799] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5934.173818] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5934.173838] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 5936.221339] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5936.221350] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd97780, len = 18, expected = 96, status = -121
>[ 5936.221388] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5936.221398] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5936.221598] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5936.221609] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5936.221616] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5936.221621] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5936.221627] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5936.221633] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5936.221639] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5936.221644] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 5936.221647] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5936.221653] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 5936.221657] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5936.221671] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5936.221680] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 5938.269185] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5938.269200] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd97540, len = 18, expected = 96, status = -121
>[ 5938.269238] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5938.269251] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5938.269438] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5938.269443] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5938.269447] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5938.269451] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5938.269455] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5938.269460] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5938.269465] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5938.269469] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 5938.269473] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5938.269481] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 5938.269486] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5938.269494] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5938.269504] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5938.269513] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 5940.316963] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5940.316968] xhci_hcd 0000:00:14.0: Giveback URB ffff8804077b30c0, len = 18, expected = 96, status = -121
>[ 5940.316999] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5940.317002] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5940.317170] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5940.317173] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5940.317175] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5940.317176] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5940.317178] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5940.317181] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5940.317183] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5940.317185] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 5940.317187] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5940.317190] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 5940.317192] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5940.317196] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5940.317204] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5940.317206] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 5942.364810] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5942.364814] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bbea180, len = 18, expected = 96, status = -121
>[ 5942.364847] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5942.364849] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5942.365014] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5942.365016] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5942.365018] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5942.365019] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5942.365020] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5942.365022] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5942.365023] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5942.365025] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 5942.365026] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5942.365028] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 5942.365029] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5942.365032] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5942.365046] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5942.365048] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 5944.412681] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5944.412685] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbe95240, len = 18, expected = 96, status = -121
>[ 5944.412717] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5944.412720] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5944.412944] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5944.412947] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5944.412948] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5944.412950] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5944.412951] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5944.412953] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5944.412955] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5944.412957] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 5944.412958] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5944.412961] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 5944.412962] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5944.412966] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5944.412979] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5944.412981] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 5946.460572] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5946.460579] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a6240, len = 18, expected = 96, status = -121
>[ 5946.460607] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5946.460611] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5946.460782] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5946.460785] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5946.460787] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5946.460790] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5946.460792] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5946.460795] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5946.460798] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5946.460801] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 5946.460804] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5946.460808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 5946.460811] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5946.460815] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5946.460823] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5946.460828] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 5948.508368] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5948.508375] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b2b40, len = 18, expected = 96, status = -121
>[ 5948.508404] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5948.508408] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5948.508585] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5948.508587] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5948.508589] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5948.508594] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5948.508597] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5948.508600] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5948.508603] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5948.508606] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 5948.508608] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5948.508612] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 5948.508614] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5948.508620] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5948.508625] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5948.508631] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 5950.556329] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5950.556342] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbb72f00, len = 18, expected = 96, status = -121
>[ 5950.556378] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5950.556387] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5950.556598] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5950.556610] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5950.556616] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5950.556623] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5950.556630] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5950.556637] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5950.556644] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5950.556652] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 5950.556658] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5950.556668] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 5950.556675] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5950.556692] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5950.556702] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 5952.604197] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5952.604209] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b2b40, len = 18, expected = 96, status = -121
>[ 5952.604242] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5952.604252] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5952.604441] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5952.604447] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5952.604451] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5952.604455] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5952.604459] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5952.604464] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5952.604468] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5952.604473] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 5952.604477] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5952.604484] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 5952.604489] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5952.604511] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5952.604520] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 5954.652026] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5954.652033] xhci_hcd 0000:00:14.0: Giveback URB ffff88040380c9c0, len = 18, expected = 96, status = -121
>[ 5954.652061] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5954.652067] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5954.652248] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5954.652253] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5954.652255] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5954.652257] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5954.652260] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5954.652262] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5954.652265] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5954.652268] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 5954.652272] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5954.652276] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 5954.652279] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5954.652292] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5954.652297] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 5956.699845] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5956.699853] xhci_hcd 0000:00:14.0: Giveback URB ffff880409adf780, len = 18, expected = 96, status = -121
>[ 5956.699883] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5956.699890] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5956.700074] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5956.700078] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5956.700081] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5956.700083] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5956.700085] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5956.700087] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5956.700090] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5956.700092] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 5956.700094] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5956.700098] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 5956.700100] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5956.700108] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5956.700111] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 5958.747738] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5958.747746] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbb72b40, len = 18, expected = 96, status = -121
>[ 5958.747773] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5958.747778] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5958.747949] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5958.747953] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5958.747956] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5958.747959] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5958.747961] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5958.747965] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5958.747968] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5958.747971] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 5958.747974] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5958.747978] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 5958.747981] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5958.747986] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5958.747996] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5958.748006] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 5960.795630] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5960.795642] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbb72c00, len = 18, expected = 96, status = -121
>[ 5960.795677] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5960.795686] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5960.795891] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5960.795903] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5960.795911] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5960.795917] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5960.795924] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5960.795931] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 5960.795939] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5960.795947] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 5960.795954] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5960.795981] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 5960.795987] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5960.796010] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5960.796022] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 5962.843467] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5962.843478] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7240, len = 18, expected = 96, status = -121
>[ 5962.843515] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5962.843526] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5962.843717] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5962.843725] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5962.843730] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5962.843734] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5962.843738] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5962.843743] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5962.843747] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5962.843752] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 5962.843757] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5962.843764] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 5962.843768] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5962.843780] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5962.843787] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 5964.891346] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5964.891359] xhci_hcd 0000:00:14.0: Giveback URB ffff880403746240, len = 18, expected = 96, status = -121
>[ 5964.891404] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5964.891417] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5964.891630] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5964.891639] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5964.891644] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5964.891650] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5964.891657] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5964.891664] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5964.891672] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5964.891679] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 5964.891685] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5964.891695] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 5964.891702] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5964.891727] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5964.891758] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 5966.939146] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5966.939157] xhci_hcd 0000:00:14.0: Giveback URB ffff880403a31780, len = 18, expected = 96, status = -121
>[ 5966.939183] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5966.939190] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5966.939381] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5966.939389] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5966.939392] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5966.939395] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5966.939398] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5966.939402] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5966.939405] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5966.939408] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 5966.939411] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5966.939415] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 5966.939419] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5966.939435] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5966.939445] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 5968.987023] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5968.987040] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7240, len = 18, expected = 96, status = -121
>[ 5968.987077] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5968.987088] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5968.987294] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5968.987306] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5968.987313] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5968.987319] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5968.987325] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5968.987332] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5968.987339] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5968.987347] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 5968.987369] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5968.987377] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 5968.987382] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5968.987403] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5968.987411] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 5971.034879] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5971.034887] xhci_hcd 0000:00:14.0: Giveback URB ffff880403a31180, len = 18, expected = 96, status = -121
>[ 5971.034914] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5971.034919] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5971.035090] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5971.035093] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5971.035097] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5971.035099] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5971.035102] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5971.035105] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5971.035108] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5971.035111] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 5971.035114] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5971.035118] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 5971.035121] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5971.035125] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5971.035134] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5971.035141] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 5973.082713] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5973.082722] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dcb3fd80, len = 18, expected = 96, status = -121
>[ 5973.082748] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5973.082752] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5973.082924] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5973.082928] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5973.082930] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5973.082932] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5973.082934] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5973.082936] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5973.082938] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5973.082943] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 5973.082946] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5973.082950] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 5973.082952] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5973.082956] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5973.082967] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5973.082972] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 5975.130655] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5975.130667] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7a80, len = 18, expected = 96, status = -121
>[ 5975.130698] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5975.130708] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5975.130900] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5975.130906] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5975.130910] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5975.130914] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5975.130918] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5975.130923] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5975.130927] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5975.130932] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 5975.130936] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5975.130943] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 5975.130947] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5975.130955] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5975.130966] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5975.130975] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 5977.178502] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5977.178515] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d3ae40, len = 18, expected = 96, status = -121
>[ 5977.178551] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5977.178560] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5977.178768] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5977.178780] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5977.178787] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5977.178792] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5977.178797] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5977.178801] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5977.178808] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5977.178816] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 5977.178823] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5977.178833] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 5977.178840] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5977.178857] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5977.178868] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 5979.226272] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5979.226278] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fa540, len = 18, expected = 96, status = -121
>[ 5979.226307] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5979.226311] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5979.226484] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5979.226487] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5979.226488] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5979.226490] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5979.226491] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5979.226495] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5979.226497] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5979.226499] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 5979.226500] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5979.226504] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 5979.226506] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5979.226509] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5979.226518] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5979.226520] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 5981.274204] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5981.274216] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b78aa80, len = 18, expected = 96, status = -121
>[ 5981.274249] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5981.274259] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5981.274472] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5981.274484] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5981.274491] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5981.274498] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5981.274503] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5981.274508] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5981.274512] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5981.274520] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 5981.274527] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5981.274537] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 5981.274545] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5981.274568] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5981.274578] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 5983.321984] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5983.321990] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fa0c0, len = 18, expected = 96, status = -121
>[ 5983.322021] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5983.322024] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5983.322190] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5983.322192] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5983.322194] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5983.322196] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5983.322198] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5983.322200] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5983.322202] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5983.322204] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 5983.322205] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5983.322207] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 5983.322209] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5983.322213] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5983.322226] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5983.322228] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 5985.369914] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5985.369924] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7dc600, len = 18, expected = 96, status = -121
>[ 5985.369962] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5985.369972] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5985.370175] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5985.370185] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5985.370192] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5985.370197] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5985.370202] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5985.370208] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5985.370214] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5985.370221] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 5985.370227] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5985.370235] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 5985.370241] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5985.370256] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5985.370261] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 5987.417714] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5987.417728] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b78a780, len = 18, expected = 96, status = -121
>[ 5987.417764] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5987.417779] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5987.417989] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5987.418009] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5987.418015] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5987.418020] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5987.418025] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5987.418031] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5987.418037] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5987.418054] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 5987.418057] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5987.418064] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 5987.418068] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5987.418087] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5987.418098] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 5989.465541] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5989.465547] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbe469c0, len = 18, expected = 96, status = -121
>[ 5989.465577] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5989.465580] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5989.465766] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5989.465771] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5989.465774] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5989.465776] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5989.465778] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5989.465780] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5989.465783] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5989.465785] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 5989.465787] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5989.465790] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 5989.465792] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5989.465796] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5989.465801] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5989.465805] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 5991.513509] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5991.513521] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dac419c0, len = 18, expected = 96, status = -121
>[ 5991.513565] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5991.513579] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5991.513792] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5991.513801] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5991.513806] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5991.513813] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5991.513820] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5991.513827] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5991.513834] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 5991.513842] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 5991.513849] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5991.513859] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 5991.513866] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5991.513891] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5991.513919] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 5993.561297] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5993.561309] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db4489c0, len = 18, expected = 96, status = -121
>[ 5993.561342] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5993.561356] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5993.561545] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5993.561551] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5993.561555] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5993.561559] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5993.561564] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5993.561569] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5993.561573] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5993.561578] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 5993.561582] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5993.561589] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 5993.561593] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5993.561606] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5993.561613] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 5995.609125] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5995.609133] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db448240, len = 18, expected = 96, status = -121
>[ 5995.609161] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5995.609165] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5995.609337] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5995.609340] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5995.609343] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5995.609346] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5995.609348] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5995.609351] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5995.609354] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5995.609357] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 5995.609360] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5995.609364] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 5995.609367] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5995.609372] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 5995.609379] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5995.609385] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 5997.657039] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5997.657049] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db480300, len = 18, expected = 96, status = -121
>[ 5997.657073] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5997.657079] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5997.657249] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5997.657253] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5997.657257] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5997.657260] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5997.657264] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5997.657267] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5997.657271] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5997.657275] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 5997.657278] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5997.657284] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 5997.657287] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5997.657301] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5997.657310] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 5999.704894] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 5999.704904] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b78b480, len = 18, expected = 96, status = -121
>[ 5999.704951] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 5999.704957] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 5999.705169] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 5999.705174] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 5999.705178] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 5999.705186] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 5999.705190] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 5999.705195] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 5999.705200] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 5999.705205] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 5999.705209] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 5999.705216] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 5999.705220] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 5999.705230] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 5999.705235] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6001.752714] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6001.752726] xhci_hcd 0000:00:14.0: Giveback URB ffff880403746c00, len = 18, expected = 96, status = -121
>[ 6001.752759] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6001.752774] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6001.752961] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6001.752968] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6001.752972] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6001.752976] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6001.752983] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6001.752990] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6001.752995] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6001.753000] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6001.753004] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6001.753011] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6001.753016] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6001.753039] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6001.753048] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6003.800576] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6003.800593] xhci_hcd 0000:00:14.0: Giveback URB ffff88040990ce40, len = 18, expected = 96, status = -121
>[ 6003.800629] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6003.800641] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6003.800836] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6003.800847] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6003.800853] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6003.800860] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6003.800866] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6003.800874] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6003.800881] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6003.800888] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6003.800895] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6003.800906] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6003.800914] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6003.800938] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6003.800948] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6005.848424] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6005.848430] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc39dcc0, len = 18, expected = 96, status = -121
>[ 6005.848460] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6005.848464] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6005.848630] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6005.848632] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6005.848636] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6005.848638] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6005.848639] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6005.848641] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6005.848643] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6005.848645] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6005.848647] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6005.848650] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6005.848651] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6005.848654] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6005.848665] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6005.848668] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6007.896274] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6007.896282] xhci_hcd 0000:00:14.0: Giveback URB ffff880405b37a80, len = 18, expected = 96, status = -121
>[ 6007.896305] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6007.896311] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6007.896503] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6007.896509] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6007.896512] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6007.896515] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6007.896518] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6007.896521] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6007.896524] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6007.896527] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6007.896529] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6007.896533] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6007.896537] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6007.896549] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6007.896556] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6009.944189] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6009.944208] xhci_hcd 0000:00:14.0: Giveback URB ffff8804065b7d80, len = 18, expected = 96, status = -121
>[ 6009.944273] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6009.944289] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6009.944507] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6009.944518] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6009.944526] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6009.944532] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6009.944538] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6009.944546] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6009.944553] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6009.944561] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6009.944568] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6009.944576] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6009.944581] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6009.944603] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6009.944618] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6011.992020] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6011.992029] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7f00, len = 18, expected = 96, status = -121
>[ 6011.992053] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6011.992059] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6011.992247] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6011.992254] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6011.992259] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6011.992262] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6011.992266] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6011.992269] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6011.992273] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6011.992278] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6011.992281] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6011.992286] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6011.992290] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6011.992302] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6011.992308] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6014.039934] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6014.039945] xhci_hcd 0000:00:14.0: Giveback URB ffff88040990c9c0, len = 18, expected = 96, status = -121
>[ 6014.039983] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6014.039992] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6014.040195] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6014.040205] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6014.040211] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6014.040216] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6014.040219] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6014.040223] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6014.040227] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6014.040231] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6014.040234] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6014.040240] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6014.040244] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6014.040258] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6014.040264] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6016.087757] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6016.087770] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bc900, len = 18, expected = 96, status = -121
>[ 6016.087802] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6016.087811] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6016.088009] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6016.088017] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6016.088023] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6016.088029] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6016.088035] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6016.088041] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6016.088047] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6016.088053] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6016.088058] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6016.088066] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6016.088071] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6016.088089] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6016.088096] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6018.135622] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6018.135635] xhci_hcd 0000:00:14.0: Giveback URB ffff88040450c600, len = 18, expected = 96, status = -121
>[ 6018.135670] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6018.135680] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6018.135888] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6018.135900] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6018.135908] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6018.135915] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6018.135922] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6018.135929] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6018.135936] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6018.135944] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6018.135951] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6018.135961] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6018.135969] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6018.135993] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6018.136002] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6020.183460] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6020.183470] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29240, len = 18, expected = 96, status = -121
>[ 6020.183504] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6020.183512] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6020.183709] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6020.183728] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6020.183734] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6020.183740] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6020.183745] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6020.183751] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6020.183757] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6020.183763] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6020.183768] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6020.183774] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6020.183778] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6020.183798] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6020.183810] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6022.231251] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6022.231256] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bcf00, len = 18, expected = 96, status = -121
>[ 6022.231287] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6022.231290] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6022.231457] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6022.231459] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6022.231461] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6022.231462] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6022.231464] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6022.231466] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6022.231468] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6022.231469] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6022.231471] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6022.231473] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6022.231475] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6022.231478] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6022.231493] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6022.231495] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6024.279223] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6024.279235] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e89240, len = 18, expected = 96, status = -121
>[ 6024.279266] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6024.279276] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6024.279490] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6024.279502] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6024.279508] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6024.279512] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6024.279517] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6024.279524] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6024.279532] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6024.279539] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6024.279545] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6024.279555] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6024.279562] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6024.279580] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6024.279591] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6026.327066] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6026.327083] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bc6c0, len = 18, expected = 96, status = -121
>[ 6026.327118] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6026.327129] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6026.327322] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6026.327331] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6026.327338] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6026.327345] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6026.327353] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6026.327361] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6026.327368] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6026.327376] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6026.327383] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6026.327394] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6026.327401] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6026.327423] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6026.327432] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6028.374828] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6028.374835] xhci_hcd 0000:00:14.0: Giveback URB ffff880403cc2e40, len = 18, expected = 96, status = -121
>[ 6028.374864] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6028.374870] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6028.375051] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6028.375055] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6028.375058] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6028.375060] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6028.375062] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6028.375064] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6028.375067] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6028.375069] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6028.375072] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6028.375075] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6028.375077] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6028.375089] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6028.375094] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6030.422732] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6030.422742] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bc6c0, len = 18, expected = 96, status = -121
>[ 6030.422769] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6030.422777] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6030.422956] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6030.422965] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6030.422971] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6030.422986] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6030.422989] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6030.422993] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6030.422997] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6030.423001] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6030.423004] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6030.423010] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6030.423013] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6030.423026] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6030.423033] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6032.470571] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6032.470576] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bcb40, len = 18, expected = 96, status = -121
>[ 6032.470599] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6032.470602] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6032.470769] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6032.470772] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6032.470774] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6032.470775] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6032.470776] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6032.470778] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6032.470779] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6032.470781] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6032.470782] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6032.470784] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6032.470786] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6032.470788] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6032.470804] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6032.470807] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6034.518493] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6034.518504] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7dbc00, len = 18, expected = 96, status = -121
>[ 6034.518541] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6034.518551] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6034.518754] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6034.518765] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6034.518771] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6034.518776] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6034.518779] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6034.518783] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6034.518787] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6034.518791] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6034.518794] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6034.518799] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6034.518803] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6034.518818] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6034.518828] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6036.566383] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6036.566397] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc383840, len = 18, expected = 96, status = -121
>[ 6036.566442] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6036.566455] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6036.566666] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6036.566674] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6036.566679] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6036.566686] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6036.566693] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6036.566700] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6036.566707] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6036.566714] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6036.566721] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6036.566731] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6036.566738] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6036.566762] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6036.566792] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6038.614163] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6038.614169] xhci_hcd 0000:00:14.0: Giveback URB ffff880403697b40, len = 18, expected = 96, status = -121
>[ 6038.614191] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6038.614195] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6038.614373] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6038.614377] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6038.614379] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6038.614381] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6038.614383] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6038.614385] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6038.614387] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6038.614389] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6038.614390] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6038.614393] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6038.614395] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6038.614400] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6038.614405] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6038.614410] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6040.662066] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6040.662078] xhci_hcd 0000:00:14.0: Giveback URB ffff880405886a80, len = 18, expected = 96, status = -121
>[ 6040.662113] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6040.662123] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6040.662330] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6040.662343] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6040.662351] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6040.662358] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6040.662365] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6040.662372] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6040.662380] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6040.662388] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6040.662394] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6040.662402] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6040.662407] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6040.662426] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6040.662433] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6042.709872] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6042.709882] xhci_hcd 0000:00:14.0: Giveback URB ffff880405886480, len = 18, expected = 96, status = -121
>[ 6042.709906] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6042.709911] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6042.710097] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6042.710105] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6042.710109] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6042.710112] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6042.710116] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6042.710120] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6042.710124] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6042.710127] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6042.710131] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6042.710136] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6042.710140] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6042.710156] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6042.710166] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6044.757713] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6044.757723] xhci_hcd 0000:00:14.0: Giveback URB ffff8804036940c0, len = 18, expected = 96, status = -121
>[ 6044.757747] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6044.757753] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6044.757932] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6044.757938] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6044.757940] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6044.757943] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6044.757945] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6044.757950] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6044.757954] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6044.757958] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6044.757961] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6044.757967] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6044.757969] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6044.757974] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6044.757985] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6044.757990] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6046.805622] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6046.805632] xhci_hcd 0000:00:14.0: Giveback URB ffff8804036940c0, len = 18, expected = 96, status = -121
>[ 6046.805657] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6046.805662] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6046.805839] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6046.805844] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6046.805847] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6046.805851] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6046.805854] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6046.805858] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6046.805861] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6046.805865] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6046.805868] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6046.805873] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6046.805878] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6046.805892] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6046.805900] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6048.853455] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6048.853464] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bc540, len = 18, expected = 96, status = -121
>[ 6048.853488] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6048.853495] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6048.853685] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6048.853691] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6048.853694] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6048.853698] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6048.853701] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6048.853705] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6048.853709] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6048.853713] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6048.853714] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6048.853718] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6048.853720] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6048.853730] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6048.853735] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6050.901336] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6050.901348] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8bc540, len = 18, expected = 96, status = -121
>[ 6050.901379] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6050.901389] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6050.901582] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6050.901588] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6050.901592] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6050.901596] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6050.901600] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6050.901605] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6050.901609] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6050.901614] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6050.901618] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6050.901625] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6050.901630] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6050.901645] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6050.901654] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6052.949162] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6052.949170] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dac41900, len = 18, expected = 96, status = -121
>[ 6052.949198] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6052.949202] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6052.949382] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6052.949388] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6052.949399] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6052.949402] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6052.949404] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6052.949406] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6052.949408] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6052.949410] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6052.949414] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6052.949418] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6052.949421] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6052.949425] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6052.949431] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6052.949436] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6054.996997] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6054.997008] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dac419c0, len = 18, expected = 96, status = -121
>[ 6054.997034] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6054.997040] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6054.997216] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6054.997221] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6054.997226] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6054.997230] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6054.997235] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6054.997240] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6054.997245] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6054.997250] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6054.997254] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6054.997261] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6054.997266] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6054.997273] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6054.997284] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6054.997295] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6057.044896] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6057.044908] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dac419c0, len = 18, expected = 96, status = -121
>[ 6057.044938] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6057.044948] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6057.045139] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6057.045152] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6057.045156] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6057.045161] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6057.045165] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6057.045169] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6057.045174] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6057.045179] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6057.045183] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6057.045190] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6057.045195] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6057.045210] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6057.045220] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6059.092732] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6059.092742] xhci_hcd 0000:00:14.0: Giveback URB ffff8804061f9240, len = 18, expected = 96, status = -121
>[ 6059.092767] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6059.092772] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6059.092943] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6059.092948] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6059.092951] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6059.092955] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6059.092958] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6059.092962] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6059.092965] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6059.092969] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6059.092973] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6059.092978] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6059.092980] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6059.092985] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6059.092995] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6059.093001] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6061.140570] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6061.140581] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c2fe000, len = 18, expected = 96, status = -121
>[ 6061.140605] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6061.140612] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6061.140790] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6061.140795] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6061.140800] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6061.140804] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6061.140808] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6061.140818] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6061.140822] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6061.140824] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6061.140827] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6061.140833] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6061.140836] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6061.140841] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6061.140851] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6061.140856] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6063.188507] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6063.188518] xhci_hcd 0000:00:14.0: Giveback URB ffff8804059020c0, len = 18, expected = 96, status = -121
>[ 6063.188555] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6063.188565] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6063.188767] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6063.188777] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6063.188782] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6063.188786] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6063.188789] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6063.188793] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6063.188797] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6063.188800] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6063.188804] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6063.188809] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6063.188813] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6063.188831] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6063.188838] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6065.236326] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6065.236332] xhci_hcd 0000:00:14.0: Giveback URB ffff8804064a09c0, len = 18, expected = 96, status = -121
>[ 6065.236355] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6065.236359] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6065.236539] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6065.236542] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6065.236544] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6065.236548] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6065.236550] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6065.236552] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6065.236555] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6065.236557] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6065.236559] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6065.236562] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6065.236564] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6065.236576] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6065.236584] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6067.284246] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6067.284259] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d3a600, len = 18, expected = 96, status = -121
>[ 6067.284304] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6067.284317] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6067.284532] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6067.284546] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6067.284554] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6067.284561] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6067.284567] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6067.284573] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6067.284577] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6067.284582] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6067.284586] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6067.284593] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6067.284598] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6067.284621] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6067.284637] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6069.332088] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6069.332098] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b9f1300, len = 18, expected = 96, status = -121
>[ 6069.332135] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6069.332145] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6069.332348] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6069.332358] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6069.332364] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6069.332370] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6069.332373] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6069.332377] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6069.332381] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6069.332387] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6069.332392] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6069.332410] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6069.332412] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6069.332431] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6069.332439] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6071.379915] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6071.379923] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b780, len = 18, expected = 96, status = -121
>[ 6071.379954] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6071.379962] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6071.380153] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6071.380160] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6071.380163] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6071.380166] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6071.380168] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6071.380171] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6071.380174] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6071.380177] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6071.380180] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6071.380184] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6071.380187] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6071.380199] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6071.380209] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6073.427777] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6073.427790] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db6243c0, len = 18, expected = 96, status = -121
>[ 6073.427819] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6073.427836] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6073.428046] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6073.428059] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6073.428067] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6073.428074] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6073.428081] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6073.428086] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6073.428091] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6073.428096] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6073.428099] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6073.428107] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6073.428113] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6073.428132] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6073.428151] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6075.475549] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6075.475555] xhci_hcd 0000:00:14.0: Giveback URB ffff880403cc20c0, len = 18, expected = 96, status = -121
>[ 6075.475585] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6075.475588] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6075.475779] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6075.475783] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6075.475785] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6075.475787] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6075.475789] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6075.475791] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6075.475794] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6075.475796] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6075.475798] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6075.475801] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6075.475804] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6075.475808] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6075.475818] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6075.475825] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6077.523426] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6077.523434] xhci_hcd 0000:00:14.0: Giveback URB ffff880407efe000, len = 18, expected = 96, status = -121
>[ 6077.523464] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6077.523472] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6077.523653] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6077.523655] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6077.523656] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6077.523659] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6077.523661] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6077.523663] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6077.523665] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6077.523667] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6077.523669] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6077.523672] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6077.523674] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6077.523677] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6077.523685] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6077.523688] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6079.571299] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6079.571305] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbabd180, len = 18, expected = 96, status = -121
>[ 6079.571330] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6079.571335] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6079.571521] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6079.571528] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6079.571531] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6079.571534] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6079.571536] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6079.571539] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6079.571541] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6079.571543] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6079.571545] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6079.571551] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6079.571553] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6079.571565] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6079.571569] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6081.619145] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6081.619150] xhci_hcd 0000:00:14.0: Giveback URB ffff880407710a80, len = 18, expected = 96, status = -121
>[ 6081.619177] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6081.619182] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6081.619355] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6081.619358] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6081.619360] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6081.619361] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6081.619368] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6081.619370] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6081.619372] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6081.619373] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6081.619375] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6081.619380] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6081.619381] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6081.619384] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6081.619390] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6081.619392] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6083.666989] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6083.666997] xhci_hcd 0000:00:14.0: Giveback URB ffff880407efed80, len = 18, expected = 96, status = -121
>[ 6083.667024] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6083.667032] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6083.667206] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6083.667215] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6083.667217] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6083.667218] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6083.667219] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6083.667220] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6083.667222] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6083.667223] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6083.667224] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6083.667227] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6083.667230] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6083.667242] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6083.667245] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6085.714875] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6085.714882] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e89780, len = 18, expected = 96, status = -121
>[ 6085.714905] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6085.714909] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6085.715094] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6085.715100] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6085.715103] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6085.715106] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6085.715108] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6085.715110] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6085.715112] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6085.715115] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6085.715116] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6085.715120] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6085.715123] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6085.715134] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6085.715138] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6087.762671] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6087.762677] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9aa80, len = 18, expected = 96, status = -121
>[ 6087.762710] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6087.762715] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6087.762900] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6087.762904] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6087.762906] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6087.762907] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6087.762909] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6087.762911] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6087.762912] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6087.762914] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6087.762915] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6087.762918] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6087.762920] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6087.762929] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6087.762933] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6089.810566] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6089.810573] xhci_hcd 0000:00:14.0: Giveback URB ffff8804036990c0, len = 18, expected = 96, status = -121
>[ 6089.810605] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6089.810611] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6089.810793] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6089.810797] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6089.810799] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6089.810801] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6089.810803] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6089.810805] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6089.810807] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6089.810809] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6089.810811] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6089.810814] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6089.810816] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6089.810823] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6089.810826] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6091.858436] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6091.858441] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068cab40, len = 18, expected = 96, status = -121
>[ 6091.858465] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6091.858469] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6091.858642] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6091.858646] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6091.858649] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6091.858651] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6091.858652] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6091.858653] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6091.858654] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6091.858656] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6091.858657] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6091.858659] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6091.858660] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6091.858663] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6091.858673] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6091.858674] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6093.906289] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6093.906293] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692ef00, len = 18, expected = 96, status = -121
>[ 6093.906317] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6093.906321] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6093.906494] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6093.906497] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6093.906498] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6093.906499] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6093.906500] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6093.906501] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6093.906503] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6093.906504] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6093.906505] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6093.906506] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6093.906508] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6093.906511] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6093.906525] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6093.906527] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6095.954161] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6095.954165] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692ef00, len = 18, expected = 96, status = -121
>[ 6095.954189] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6095.954193] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6095.954367] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6095.954370] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6095.954372] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6095.954374] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6095.954376] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6095.954377] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6095.954378] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6095.954379] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6095.954381] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6095.954382] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6095.954384] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6095.954387] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6095.954396] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6095.954398] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6098.002032] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6098.002038] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692e3c0, len = 18, expected = 96, status = -121
>[ 6098.002056] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6098.002060] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6098.002300] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6098.002304] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6098.002305] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6098.002307] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6098.002308] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6098.002310] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6098.002312] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6098.002314] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6098.002315] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6098.002317] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6098.002319] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6098.002323] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6098.002327] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6098.002331] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6100.049864] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6100.049868] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a66c0, len = 18, expected = 96, status = -121
>[ 6100.049892] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6100.049897] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6100.050069] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6100.050073] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6100.050074] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6100.050075] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6100.050076] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6100.050078] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6100.050079] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6100.050080] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6100.050081] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6100.050083] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6100.050084] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6100.050088] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6100.050100] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6100.050102] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6102.097719] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6102.097723] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7a69c0, len = 18, expected = 96, status = -121
>[ 6102.097746] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6102.097751] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6102.097923] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6102.097926] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6102.097927] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6102.097928] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6102.097929] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6102.097930] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6102.097932] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6102.097933] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6102.097934] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6102.097936] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6102.097937] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6102.097940] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6102.097956] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6102.097959] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6104.145572] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6104.145577] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369ba80, len = 18, expected = 96, status = -121
>[ 6104.145600] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6104.145605] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6104.145785] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6104.145789] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6104.145791] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6104.145793] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6104.145794] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6104.145796] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6104.145797] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6104.145799] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6104.145800] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6104.145802] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6104.145803] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6104.145807] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6104.145816] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6104.145820] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6106.193440] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6106.193450] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbcf9000, len = 18, expected = 96, status = -121
>[ 6106.193475] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6106.193481] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6106.193663] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6106.193668] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6106.193672] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6106.193676] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6106.193679] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6106.193682] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6106.193686] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6106.193690] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6106.193693] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6106.193698] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6106.193701] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6106.193714] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6106.193719] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6108.241279] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6108.241286] xhci_hcd 0000:00:14.0: Giveback URB ffff880403a31180, len = 18, expected = 96, status = -121
>[ 6108.241313] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6108.241317] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6108.241490] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6108.241493] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6108.241496] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6108.241498] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6108.241500] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6108.241502] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6108.241505] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6108.241508] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6108.241510] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6108.241514] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6108.241516] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6108.241519] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6108.241526] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6108.241536] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6110.289127] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6110.289133] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f1ce40, len = 18, expected = 96, status = -121
>[ 6110.289166] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6110.289170] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6110.289344] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6110.289347] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6110.289348] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6110.289349] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6110.289350] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6110.289352] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6110.289353] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6110.289354] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6110.289355] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6110.289357] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6110.289359] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6110.289362] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6110.289374] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6110.289375] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6112.336960] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6112.336967] xhci_hcd 0000:00:14.0: Giveback URB ffff88040beb90c0, len = 18, expected = 96, status = -121
>[ 6112.336996] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6112.337000] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6112.337167] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6112.337170] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6112.337173] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6112.337176] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6112.337178] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6112.337181] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6112.337184] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6112.337187] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6112.337189] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6112.337193] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6112.337196] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6112.337200] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6112.337205] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6112.337208] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6114.384846] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6114.384852] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b2cc0, len = 18, expected = 96, status = -121
>[ 6114.384883] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6114.384887] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6114.385053] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6114.385060] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6114.385062] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6114.385064] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6114.385065] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6114.385068] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6114.385070] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6114.385073] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6114.385075] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6114.385078] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6114.385080] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6114.385083] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6114.385091] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6114.385094] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6116.432708] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6116.432712] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941780, len = 18, expected = 96, status = -121
>[ 6116.432736] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6116.432740] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6116.432913] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6116.432916] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6116.432918] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6116.432919] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6116.432920] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6116.432921] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6116.432922] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6116.432923] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6116.432925] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6116.432926] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6116.432928] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6116.432931] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6116.432944] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6116.432945] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6118.480609] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6118.480615] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd1e3c0, len = 18, expected = 96, status = -121
>[ 6118.480637] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6118.480642] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6118.480821] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6118.480825] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6118.480828] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6118.480830] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6118.480832] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6118.480834] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6118.480837] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6118.480839] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6118.480841] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6118.480845] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6118.480847] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6118.480854] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6118.480857] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6120.528455] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6120.528461] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941b40, len = 18, expected = 96, status = -121
>[ 6120.528482] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6120.528486] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6120.528667] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6120.528670] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6120.528672] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6120.528673] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6120.528677] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6120.528679] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6120.528681] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6120.528683] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6120.528685] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6120.528688] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6120.528690] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6120.528698] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6120.528700] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 6122.576312] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6122.576319] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc8e9b40, len = 18, expected = 96, status = -121
>[ 6122.576351] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6122.576355] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6122.576533] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6122.576536] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6122.576538] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6122.576541] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6122.576544] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6122.576547] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6122.576550] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6122.576553] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 6122.576556] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6122.576560] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 6122.576563] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6122.576568] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6122.576573] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6122.576577] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 6124.624169] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6124.624175] xhci_hcd 0000:00:14.0: Giveback URB ffff880409adf3c0, len = 18, expected = 96, status = -121
>[ 6124.624200] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6124.624206] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6124.624389] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6124.624395] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6124.624399] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6124.624402] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6124.624406] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6124.624409] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6124.624412] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6124.624415] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 6124.624417] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6124.624421] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 6124.624423] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6124.624435] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6124.624439] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 6126.672005] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6126.672015] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b983c0, len = 18, expected = 96, status = -121
>[ 6126.672040] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6126.672045] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6126.672224] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6126.672229] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6126.672232] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6126.672236] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6126.672239] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6126.672243] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6126.672247] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6126.672251] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 6126.672254] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6126.672259] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 6126.672263] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6126.672269] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6126.672278] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6126.672284] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 6128.719868] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6128.719874] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b983c0, len = 18, expected = 96, status = -121
>[ 6128.719900] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6128.719904] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6128.720070] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6128.720072] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6128.720074] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6128.720076] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6128.720078] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6128.720080] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6128.720082] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6128.720083] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 6128.720084] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6128.720087] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 6128.720090] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6128.720093] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6128.720106] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6128.720108] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6130.767701] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6130.767706] xhci_hcd 0000:00:14.0: Giveback URB ffff880403699240, len = 18, expected = 96, status = -121
>[ 6130.767740] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6130.767747] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6130.767920] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6130.767923] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6130.767925] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6130.767927] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6130.767928] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6130.767931] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6130.767933] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6130.767934] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6130.767936] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6130.767939] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6130.767941] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6130.767944] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6130.767954] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6130.767957] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6132.815548] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6132.815554] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbed4cc0, len = 18, expected = 96, status = -121
>[ 6132.815584] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6132.815587] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6132.815756] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6132.815758] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6132.815760] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6132.815761] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6132.815767] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6132.815769] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6132.815771] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6132.815773] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6132.815775] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6132.815778] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6132.815779] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6132.815783] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6132.815794] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6132.815801] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6134.863464] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6134.863470] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bb7ca80, len = 18, expected = 96, status = -121
>[ 6134.863500] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6134.863503] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6134.863670] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6134.863672] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6134.863674] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6134.863676] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6134.863678] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6134.863680] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6134.863682] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6134.863683] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6134.863684] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6134.863686] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6134.863689] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6134.863692] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6134.863705] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6134.863707] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6136.911290] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6136.911297] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea7840, len = 18, expected = 96, status = -121
>[ 6136.911325] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6136.911329] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6136.911502] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6136.911505] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6136.911508] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6136.911511] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6136.911513] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6136.911516] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6136.911519] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6136.911522] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6136.911531] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6136.911534] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6136.911536] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6136.911541] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6136.911548] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6136.911552] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6138.959123] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6138.959131] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789f3c0, len = 18, expected = 96, status = -121
>[ 6138.959162] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6138.959170] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6138.959346] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6138.959349] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6138.959351] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6138.959353] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6138.959355] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6138.959357] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6138.959359] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6138.959361] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6138.959362] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6138.959365] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6138.959367] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6138.959371] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6138.959380] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6138.959384] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6141.007017] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6141.007022] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db624600, len = 18, expected = 96, status = -121
>[ 6141.007042] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6141.007046] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6141.007224] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6141.007227] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6141.007229] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6141.007231] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6141.007233] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6141.007235] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6141.007237] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6141.007239] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6141.007240] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6141.007243] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6141.007245] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6141.007253] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6141.007256] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6143.054868] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6143.054872] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c56bc00, len = 18, expected = 96, status = -121
>[ 6143.054895] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6143.054900] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6143.055074] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6143.055077] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6143.055079] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6143.055080] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6143.055081] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6143.055082] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6143.055084] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6143.055085] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6143.055086] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6143.055088] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6143.055089] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6143.055092] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6143.055105] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6143.055106] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6145.102690] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6145.102694] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd1eb40, len = 18, expected = 96, status = -121
>[ 6145.102726] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6145.102729] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6145.102895] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6145.102898] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6145.102899] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6145.102901] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6145.102902] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6145.102903] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6145.102904] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6145.102906] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6145.102907] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6145.102909] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6145.102910] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6145.102913] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6145.102932] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6145.102933] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6147.150575] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6147.150580] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae1a180, len = 18, expected = 96, status = -121
>[ 6147.150607] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6147.150610] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6147.150786] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6147.150788] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6147.150790] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6147.150792] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6147.150793] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6147.150795] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6147.150797] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6147.150799] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6147.150800] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6147.150803] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6147.150805] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6147.150808] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6147.150813] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6147.150815] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6149.198502] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6149.198518] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7ca300, len = 18, expected = 96, status = -121
>[ 6149.198554] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6149.198565] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6149.198760] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6149.198769] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6149.198775] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6149.198782] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6149.198789] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6149.198797] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6149.198804] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6149.198811] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6149.198818] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6149.198828] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6149.198835] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6149.198860] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6149.198874] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6151.246336] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6151.246343] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea7c00, len = 18, expected = 96, status = -121
>[ 6151.246368] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6151.246374] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6151.246555] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6151.246565] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6151.246567] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6151.246570] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6151.246572] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6151.246574] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6151.246576] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6151.246579] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6151.246580] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6151.246584] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6151.246586] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6151.246599] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6151.246604] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6153.294222] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6153.294233] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea7480, len = 18, expected = 96, status = -121
>[ 6153.294272] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6153.294281] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6153.294486] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6153.294497] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6153.294503] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6153.294509] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6153.294514] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6153.294520] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6153.294526] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6153.294532] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6153.294537] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6153.294542] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6153.294546] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6153.294561] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6153.294570] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6155.341998] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6155.342004] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ef00, len = 18, expected = 96, status = -121
>[ 6155.342036] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6155.342042] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6155.342220] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6155.342224] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6155.342226] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6155.342229] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6155.342231] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6155.342233] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6155.342235] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6155.342236] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6155.342238] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6155.342240] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6155.342241] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6155.342245] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6155.342251] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6155.342254] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6157.389871] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6157.389875] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dcb3f540, len = 18, expected = 96, status = -121
>[ 6157.389898] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6157.389903] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6157.390077] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6157.390081] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6157.390083] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6157.390085] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6157.390087] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6157.390088] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6157.390089] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6157.390091] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6157.390092] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6157.390094] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6157.390095] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6157.390098] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6157.390107] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6157.390109] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6159.437700] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6159.437707] xhci_hcd 0000:00:14.0: Giveback URB ffff880407664cc0, len = 18, expected = 96, status = -121
>[ 6159.437739] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6159.437745] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6159.437931] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6159.437934] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6159.437937] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6159.437940] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6159.437942] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6159.437944] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6159.437946] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6159.437949] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6159.437951] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6159.437954] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6159.437957] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6159.437965] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6159.437973] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6161.485573] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6161.485579] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ea80, len = 18, expected = 96, status = -121
>[ 6161.485612] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6161.485618] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6161.485797] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6161.485800] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6161.485801] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6161.485803] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6161.485805] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6161.485807] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6161.485809] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6161.485811] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6161.485813] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6161.485816] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6161.485818] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6161.485829] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6161.485834] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6163.533452] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6163.533457] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b9f1600, len = 18, expected = 96, status = -121
>[ 6163.533478] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6163.533482] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6163.533656] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6163.533659] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6163.533661] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6163.533662] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6163.533663] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6163.533665] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6163.533666] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6163.533668] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6163.533669] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6163.533671] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6163.533673] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6163.533676] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6163.533690] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6163.533693] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6165.581285] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6165.581290] xhci_hcd 0000:00:14.0: Giveback URB ffff880406b62840, len = 18, expected = 96, status = -121
>[ 6165.581311] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6165.581314] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6165.581488] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6165.581490] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6165.581492] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6165.581494] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6165.581496] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6165.581498] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6165.581500] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6165.581502] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6165.581503] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6165.581511] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6165.581512] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6165.581516] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6165.581521] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6165.581523] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6167.629228] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6167.629240] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbdf1840, len = 18, expected = 96, status = -121
>[ 6167.629267] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6167.629276] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6167.629470] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6167.629476] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6167.629480] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6167.629484] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6167.629488] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6167.629493] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6167.629497] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6167.629502] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6167.629506] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6167.629512] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6167.629517] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6167.629525] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6167.629535] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6167.629544] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6169.676993] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6169.677003] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc9f53c0, len = 18, expected = 96, status = -121
>[ 6169.677027] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6169.677033] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6169.677220] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6169.677227] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6169.677231] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6169.677235] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6169.677238] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6169.677243] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6169.677247] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6169.677251] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6169.677254] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6169.677260] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6169.677264] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6169.677285] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6169.677290] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6171.724906] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6171.724912] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb840, len = 18, expected = 96, status = -121
>[ 6171.724936] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6171.724940] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6171.725127] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6171.725132] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6171.725134] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6171.725136] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6171.725138] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6171.725140] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6171.725142] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6171.725145] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6171.725148] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6171.725152] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6171.725154] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6171.725165] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6171.725169] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6173.772732] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6173.772736] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb840, len = 18, expected = 96, status = -121
>[ 6173.772757] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6173.772760] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6173.772931] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6173.772934] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6173.772935] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6173.772936] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6173.772938] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6173.772939] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6173.772941] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6173.772942] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6173.772943] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6173.772945] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6173.772947] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6173.772950] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6173.772966] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6173.772968] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6175.820586] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6175.820590] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fa9c0, len = 18, expected = 96, status = -121
>[ 6175.820611] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6175.820615] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6175.820792] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6175.820798] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6175.820799] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6175.820800] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6175.820800] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6175.820801] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6175.820804] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6175.820806] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6175.820807] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6175.820809] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6175.820810] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6175.820813] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6175.820822] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6175.820825] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6177.868414] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6177.868420] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7b40, len = 18, expected = 96, status = -121
>[ 6177.868450] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6177.868453] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6177.868620] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6177.868623] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6177.868625] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6177.868627] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6177.868629] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6177.868631] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6177.868634] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6177.868636] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6177.868638] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6177.868642] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6177.868644] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6177.868648] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6177.868660] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6177.868666] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6179.916311] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6179.916316] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b989c0, len = 18, expected = 96, status = -121
>[ 6179.916338] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6179.916341] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6179.916524] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6179.916527] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6179.916529] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6179.916531] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6179.916533] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6179.916535] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6179.916537] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6179.916539] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6179.916541] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6179.916544] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6179.916546] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6179.916553] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6179.916556] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6181.964162] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6181.964167] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae1a6c0, len = 18, expected = 96, status = -121
>[ 6181.964190] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6181.964195] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6181.964369] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6181.964373] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6181.964375] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6181.964376] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6181.964377] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6181.964378] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6181.964380] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6181.964381] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6181.964382] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6181.964384] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6181.964386] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6181.964389] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6181.964398] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6181.964400] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6184.012058] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6184.012075] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03180, len = 18, expected = 96, status = -121
>[ 6184.012122] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6184.012138] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6184.012343] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6184.012349] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6184.012353] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6184.012358] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6184.012372] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6184.012378] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6184.012384] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6184.012389] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6184.012394] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6184.012413] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6184.012420] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6184.012437] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6184.012449] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6186.059859] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6186.059864] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd980c0, len = 18, expected = 96, status = -121
>[ 6186.059891] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6186.059896] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6186.060072] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6186.060075] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6186.060076] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6186.060078] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6186.060079] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6186.060081] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6186.060082] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6186.060084] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6186.060085] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6186.060087] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6186.060089] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6186.060092] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6186.060104] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6186.060106] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6188.107673] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6188.107677] xhci_hcd 0000:00:14.0: Giveback URB ffff88040ba68b40, len = 18, expected = 96, status = -121
>[ 6188.107710] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6188.107712] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6188.107876] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6188.107879] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6188.107880] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6188.107881] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6188.107883] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6188.107884] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6188.107885] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6188.107887] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6188.107888] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6188.107890] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6188.107891] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6188.107894] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6188.107910] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6188.107911] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6190.155561] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6190.155568] xhci_hcd 0000:00:14.0: Giveback URB ffff8804063f49c0, len = 18, expected = 96, status = -121
>[ 6190.155597] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6190.155600] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6190.155768] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6190.155771] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6190.155773] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6190.155779] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6190.155781] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6190.155783] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6190.155784] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6190.155786] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6190.155787] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6190.155792] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6190.155793] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6190.155797] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6190.155808] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6190.155813] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6192.203419] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6192.203426] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbd986c0, len = 18, expected = 96, status = -121
>[ 6192.203455] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6192.203459] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6192.203625] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6192.203628] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6192.203631] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6192.203633] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6192.203636] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6192.203639] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6192.203642] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6192.203645] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6192.203648] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6192.203653] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6192.203656] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6192.203660] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6192.203665] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6192.203669] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6194.251278] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6194.251289] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ece0c0, len = 18, expected = 96, status = -121
>[ 6194.251315] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6194.251321] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6194.251515] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6194.251523] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6194.251527] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6194.251529] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6194.251532] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6194.251535] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6194.251539] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6194.251542] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6194.251545] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6194.251549] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6194.251553] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6194.251565] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6194.251573] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6196.299160] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6196.299166] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db480a80, len = 18, expected = 96, status = -121
>[ 6196.299189] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6196.299193] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6196.299373] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6196.299379] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6196.299383] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6196.299385] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6196.299387] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6196.299389] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6196.299392] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6196.299394] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6196.299395] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6196.299399] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6196.299402] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6196.299413] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6196.299417] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6198.347031] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6198.347037] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db480000, len = 18, expected = 96, status = -121
>[ 6198.347059] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6198.347064] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6198.347244] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6198.347250] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6198.347252] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6198.347253] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6198.347255] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6198.347257] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6198.347259] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6198.347261] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6198.347264] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6198.347268] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6198.347270] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6198.347280] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6198.347283] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6200.394851] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6200.394857] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789fb40, len = 18, expected = 96, status = -121
>[ 6200.394890] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6200.394894] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6200.395074] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6200.395076] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6200.395078] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6200.395079] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6200.395081] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6200.395083] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6200.395085] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6200.395087] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6200.395088] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6200.395091] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6200.395093] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6200.395096] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6200.395104] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6200.395106] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6202.442726] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6202.442731] xhci_hcd 0000:00:14.0: Giveback URB ffff88040990ccc0, len = 18, expected = 96, status = -121
>[ 6202.442754] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6202.442759] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6202.442939] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6202.442942] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6202.442943] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6202.442945] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6202.442946] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6202.442948] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6202.442949] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6202.442951] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6202.442953] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6202.442955] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6202.442957] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6202.442960] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6202.442968] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6202.442970] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6204.490600] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6204.490605] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea7c00, len = 18, expected = 96, status = -121
>[ 6204.490626] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6204.490629] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6204.490809] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6204.490818] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6204.490819] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6204.490821] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6204.490822] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6204.490824] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6204.490826] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6204.490828] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6204.490830] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6204.490833] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6204.490835] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6204.490842] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6204.490844] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6206.538432] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6206.538440] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b9de840, len = 18, expected = 96, status = -121
>[ 6206.538466] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6206.538471] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6206.538643] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6206.538647] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6206.538650] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6206.538654] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6206.538657] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6206.538660] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6206.538663] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6206.538667] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6206.538670] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6206.538673] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6206.538676] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6206.538680] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6206.538688] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6206.538692] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6208.586310] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6208.586316] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dacb6780, len = 18, expected = 96, status = -121
>[ 6208.586339] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6208.586344] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6208.586528] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6208.586538] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6208.586540] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6208.586542] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6208.586544] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6208.586548] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6208.586550] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6208.586553] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6208.586555] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6208.586558] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6208.586561] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6208.586573] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6208.586579] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6210.634161] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6210.634166] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789f540, len = 18, expected = 96, status = -121
>[ 6210.634193] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6210.634198] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6210.634376] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6210.634378] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6210.634381] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6210.634382] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6210.634383] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6210.634384] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6210.634386] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6210.634387] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6210.634388] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6210.634390] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6210.634391] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6210.634394] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6210.634408] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6210.634412] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6212.682018] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6212.682024] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03180, len = 18, expected = 96, status = -121
>[ 6212.682051] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6212.682058] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6212.682240] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6212.682243] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6212.682245] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6212.682247] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6212.682248] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6212.682251] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6212.682254] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6212.682257] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6212.682259] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6212.682262] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6212.682264] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6212.682269] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6212.682273] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6212.682276] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6214.729882] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6214.729886] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b969c0, len = 18, expected = 96, status = -121
>[ 6214.729913] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6214.729915] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6214.730087] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6214.730088] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6214.730089] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6214.730090] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6214.730092] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6214.730094] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6214.730095] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6214.730096] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6214.730097] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6214.730099] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6214.730100] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6214.730103] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6214.730119] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6214.730121] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6216.777688] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6216.777693] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03d80, len = 18, expected = 96, status = -121
>[ 6216.777726] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6216.777730] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6216.777900] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6216.777903] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6216.777905] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6216.777906] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6216.777908] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6216.777910] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6216.777912] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6216.777914] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6216.777915] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6216.777918] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6216.777920] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6216.777923] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6216.777934] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6216.777936] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6218.825541] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6218.825545] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789f0c0, len = 18, expected = 96, status = -121
>[ 6218.825579] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6218.825580] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6218.825741] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6218.825742] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6218.825743] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6218.825744] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6218.825746] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6218.825747] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6218.825748] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6218.825749] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6218.825750] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6218.825752] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6218.825753] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6218.825755] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6218.825778] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6218.825780] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6220.873425] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6220.873428] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7dc300, len = 18, expected = 96, status = -121
>[ 6220.873462] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6220.873464] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6220.873625] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6220.873626] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6220.873628] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6220.873629] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6220.873630] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6220.873631] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6220.873632] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6220.873633] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6220.873634] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6220.873636] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6220.873637] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6220.873639] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6220.873661] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6220.873663] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6222.921277] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6222.921283] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db7dc240, len = 18, expected = 96, status = -121
>[ 6222.921313] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6222.921319] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6222.921493] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6222.921496] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6222.921498] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6222.921500] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6222.921502] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6222.921504] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6222.921506] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6222.921508] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6222.921509] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6222.921512] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6222.921514] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6222.921518] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6222.921528] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6222.921532] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6224.969170] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6224.969176] xhci_hcd 0000:00:14.0: Giveback URB ffff880407ea73c0, len = 18, expected = 96, status = -121
>[ 6224.969199] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6224.969204] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6224.969388] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6224.969394] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6224.969397] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6224.969400] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6224.969403] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6224.969406] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6224.969410] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6224.969413] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6224.969416] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6224.969420] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6224.969424] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6224.969433] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6224.969438] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6227.017003] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6227.017009] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db99fd80, len = 18, expected = 96, status = -121
>[ 6227.017039] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6227.017042] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6227.017216] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6227.017219] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6227.017221] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6227.017223] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6227.017225] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6227.017226] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6227.017228] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6227.017230] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6227.017232] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6227.017236] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6227.017238] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6227.017241] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6227.017253] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6227.017257] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6229.064843] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6229.064850] xhci_hcd 0000:00:14.0: Giveback URB ffff880407664f00, len = 18, expected = 96, status = -121
>[ 6229.064881] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6229.064887] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6229.065065] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6229.065068] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6229.065070] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6229.065072] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6229.065073] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6229.065074] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6229.065076] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6229.065078] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6229.065079] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6229.065081] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6229.065082] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6229.065092] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6229.065097] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6229.065101] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6231.112717] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6231.112721] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c1fa240, len = 18, expected = 96, status = -121
>[ 6231.112756] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6231.112761] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6231.112934] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6231.112937] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6231.112938] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6231.112940] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6231.112942] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6231.112944] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6231.112946] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6231.112948] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6231.112949] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6231.112952] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6231.112954] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6231.112957] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6231.112969] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6231.112972] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6233.160561] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6233.160565] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03600, len = 18, expected = 96, status = -121
>[ 6233.160598] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6233.160601] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6233.160771] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6233.160774] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6233.160776] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6233.160778] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6233.160780] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6233.160782] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6233.160785] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6233.160787] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6233.160789] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6233.160792] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6233.160794] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6233.160798] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6233.160804] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6233.160807] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6235.208446] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6235.208450] xhci_hcd 0000:00:14.0: Giveback URB ffff8804077b3600, len = 18, expected = 96, status = -121
>[ 6235.208474] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6235.208479] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6235.208658] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6235.208660] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6235.208661] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6235.208664] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6235.208666] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6235.208667] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6235.208669] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6235.208671] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6235.208672] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6235.208675] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6235.208676] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6235.208680] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6235.208688] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6235.208690] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6237.256305] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6237.256311] xhci_hcd 0000:00:14.0: Giveback URB ffff880404f71f00, len = 18, expected = 96, status = -121
>[ 6237.256340] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6237.256345] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6237.256520] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6237.256523] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6237.256525] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6237.256526] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6237.256528] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6237.256529] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6237.256531] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6237.256532] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6237.256534] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6237.256536] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6237.256538] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6237.256541] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6237.256556] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6237.256560] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6239.304168] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6239.304172] xhci_hcd 0000:00:14.0: Giveback URB ffff880404af9180, len = 18, expected = 96, status = -121
>[ 6239.304194] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6239.304196] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6239.304367] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6239.304370] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6239.304372] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6239.304373] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6239.304374] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6239.304375] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6239.304377] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6239.304378] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6239.304379] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6239.304381] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6239.304382] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6239.304385] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6239.304398] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6239.304400] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6241.352021] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6241.352026] xhci_hcd 0000:00:14.0: Giveback URB ffff880404aeb600, len = 18, expected = 96, status = -121
>[ 6241.352045] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6241.352048] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6241.352223] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6241.352228] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6241.352229] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6241.352231] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6241.352232] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6241.352234] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6241.352236] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6241.352239] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6241.352241] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6241.352244] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6241.352245] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6241.352249] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6241.352253] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6241.352255] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6243.399900] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6243.399906] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c2fea80, len = 18, expected = 96, status = -121
>[ 6243.399926] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6243.399929] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6243.400108] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6243.400111] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6243.400113] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6243.400114] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6243.400117] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6243.400120] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6243.400122] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6243.400124] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6243.400126] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6243.400129] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6243.400131] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6243.400138] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6243.400141] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6245.447711] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6245.447715] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbeb7180, len = 18, expected = 96, status = -121
>[ 6245.447743] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6245.447747] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6245.447919] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6245.447922] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6245.447924] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6245.447925] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6245.447926] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6245.447927] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6245.447928] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6245.447929] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6245.447930] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6245.447932] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6245.447933] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6245.447936] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6245.447951] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6245.447953] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6247.495617] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6247.495624] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf293c0, len = 18, expected = 96, status = -121
>[ 6247.495654] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6247.495658] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6247.495835] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6247.495840] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6247.495843] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6247.495847] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6247.495849] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6247.495852] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6247.495854] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6247.495856] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6247.495858] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6247.495861] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6247.495864] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6247.495869] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6247.495874] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6247.495880] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6249.543475] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6249.543481] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbdbbc00, len = 18, expected = 96, status = -121
>[ 6249.543504] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6249.543508] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6249.543688] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6249.543694] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6249.543697] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6249.543700] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6249.543702] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6249.543704] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6249.543706] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6249.543708] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6249.543710] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6249.543712] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6249.543715] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6249.543724] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6249.543729] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 6251.591279] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6251.591286] xhci_hcd 0000:00:14.0: Giveback URB ffff8804070d8480, len = 18, expected = 96, status = -121
>[ 6251.591318] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6251.591325] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6251.591497] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6251.591500] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6251.591502] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6251.591504] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6251.591505] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6251.591507] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6251.591509] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6251.591511] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 6251.591512] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6251.591514] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 6251.591516] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6251.591520] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6251.591531] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6251.591533] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 6253.639146] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6253.639153] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e3a540, len = 18, expected = 96, status = -121
>[ 6253.639182] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6253.639186] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6253.639351] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6253.639353] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6253.639355] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6253.639358] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6253.639361] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6253.639363] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6253.639365] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6253.639366] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 6253.639368] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6253.639371] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 6253.639373] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6253.639376] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6253.639393] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6253.639398] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 6255.686991] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6255.686998] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03240, len = 18, expected = 96, status = -121
>[ 6255.687029] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6255.687037] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6255.687277] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6255.687281] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6255.687284] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6255.687286] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6255.687289] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6255.687292] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6255.687295] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6255.687298] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 6255.687301] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6255.687305] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 6255.687308] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6255.687317] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6255.687322] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 6257.734834] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6257.734840] xhci_hcd 0000:00:14.0: Giveback URB ffff880405054840, len = 18, expected = 96, status = -121
>[ 6257.734871] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6257.734874] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6257.735040] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6257.735043] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6257.735045] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6257.735047] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6257.735049] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6257.735052] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6257.735054] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6257.735057] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 6257.735059] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6257.735062] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 6257.735065] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6257.735068] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6257.735076] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6257.735079] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6259.782764] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6259.782771] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369b780, len = 18, expected = 96, status = -121
>[ 6259.782796] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6259.782801] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6259.782985] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6259.782991] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6259.782994] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6259.783001] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6259.783003] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6259.783005] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6259.783007] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6259.783009] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6259.783011] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6259.783015] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6259.783017] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6259.783028] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6259.783032] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6261.830585] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6261.830589] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369b3c0, len = 18, expected = 96, status = -121
>[ 6261.830617] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6261.830621] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6261.830799] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6261.830800] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6261.830802] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6261.830803] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6261.830804] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6261.830805] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6261.830806] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6261.830808] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6261.830809] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6261.830810] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6261.830811] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6261.830814] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6261.830824] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6261.830826] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6263.878457] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6263.878461] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b7f2d80, len = 18, expected = 96, status = -121
>[ 6263.878483] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6263.878486] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6263.878658] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6263.878662] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6263.878663] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6263.878665] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6263.878666] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6263.878667] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6263.878669] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6263.878670] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6263.878671] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6263.878673] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6263.878674] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6263.878677] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6263.878688] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6263.878689] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6265.926277] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6265.926282] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae1ab40, len = 18, expected = 96, status = -121
>[ 6265.926303] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6265.926306] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6265.926476] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6265.926479] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6265.926480] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6265.926481] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6265.926482] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6265.926484] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6265.926485] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6265.926486] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6265.926487] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6265.926489] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6265.926490] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6265.926493] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6265.926510] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6265.926513] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6267.974138] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6267.974143] xhci_hcd 0000:00:14.0: Giveback URB ffff8804077786c0, len = 18, expected = 96, status = -121
>[ 6267.974174] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6267.974177] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6267.974343] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6267.974346] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6267.974347] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6267.974349] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6267.974350] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6267.974351] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6267.974353] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6267.974354] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6267.974355] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6267.974357] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6267.974358] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6267.974361] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6267.974384] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6267.974389] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6270.022045] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6270.022055] xhci_hcd 0000:00:14.0: Giveback URB ffff880403d03900, len = 18, expected = 96, status = -121
>[ 6270.022082] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6270.022090] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6270.022286] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6270.022296] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6270.022302] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6270.022308] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6270.022314] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6270.022320] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6270.022336] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6270.022341] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6270.022345] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6270.022357] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6270.022363] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6270.022384] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6270.022392] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6272.069861] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6272.069868] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db448900, len = 18, expected = 96, status = -121
>[ 6272.069897] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6272.069901] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6272.070073] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6272.070076] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6272.070078] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6272.070080] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6272.070082] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6272.070085] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6272.070094] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6272.070096] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6272.070098] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6272.070100] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6272.070102] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6272.070108] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6272.070114] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6272.070117] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6274.117754] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6274.117762] xhci_hcd 0000:00:14.0: Giveback URB ffff8804044fd780, len = 18, expected = 96, status = -121
>[ 6274.117793] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6274.117800] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6274.117985] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6274.117989] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6274.117992] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6274.117994] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6274.117996] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6274.117998] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6274.118001] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6274.118003] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6274.118005] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6274.118009] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6274.118011] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6274.118019] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6274.118022] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6276.165581] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6276.165586] xhci_hcd 0000:00:14.0: Giveback URB ffff880403696480, len = 18, expected = 96, status = -121
>[ 6276.165617] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6276.165620] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6276.165788] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6276.165790] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6276.165792] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6276.165794] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6276.165796] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6276.165798] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6276.165800] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6276.165802] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6276.165803] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6276.165806] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6276.165808] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6276.165811] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6276.165822] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6276.165824] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6278.213415] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6278.213419] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5f0000, len = 18, expected = 96, status = -121
>[ 6278.213452] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6278.213454] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6278.213620] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6278.213622] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6278.213623] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6278.213625] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6278.213626] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6278.213628] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6278.213629] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6278.213631] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6278.213633] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6278.213635] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6278.213636] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6278.213639] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6278.213657] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6278.213659] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6280.261303] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6280.261309] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068239c0, len = 18, expected = 96, status = -121
>[ 6280.261339] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6280.261342] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6280.261508] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6280.261511] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6280.261513] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6280.261515] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6280.261517] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6280.261519] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6280.261521] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6280.261524] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6280.261526] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6280.261529] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6280.261530] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6280.261533] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6280.261544] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6280.261546] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6282.309145] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6282.309152] xhci_hcd 0000:00:14.0: Giveback URB ffff880409bec480, len = 18, expected = 96, status = -121
>[ 6282.309181] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6282.309185] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6282.309358] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6282.309366] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6282.309367] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6282.309369] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6282.309370] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6282.309373] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6282.309375] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6282.309377] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6282.309378] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6282.309382] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6282.309383] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6282.309387] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6282.309395] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6282.309398] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6284.357009] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6284.357013] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dba70c00, len = 18, expected = 96, status = -121
>[ 6284.357046] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6284.357048] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6284.357215] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6284.357218] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6284.357219] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6284.357220] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6284.357222] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6284.357224] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6284.357225] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6284.357227] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6284.357228] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6284.357230] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6284.357232] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6284.357235] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6284.357251] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6284.357253] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6286.404845] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6286.404850] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae1a840, len = 18, expected = 96, status = -121
>[ 6286.404885] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6286.404890] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6286.405058] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6286.405061] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6286.405062] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6286.405064] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6286.405065] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6286.405067] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6286.405069] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6286.405070] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6286.405072] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6286.405074] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6286.405075] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6286.405079] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6286.405093] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6286.405095] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6288.452754] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6288.452760] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc9f5840, len = 18, expected = 96, status = -121
>[ 6288.452785] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6288.452791] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6288.452965] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6288.452971] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6288.452973] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6288.452976] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6288.452978] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6288.452980] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6288.452982] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6288.452985] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6288.452992] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6288.452995] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6288.452996] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6288.453006] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6288.453009] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6290.500575] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6290.500580] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e90780, len = 18, expected = 96, status = -121
>[ 6290.500611] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6290.500614] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6290.500780] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6290.500782] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6290.500784] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6290.500786] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6290.500788] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6290.500790] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6290.500792] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6290.500794] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6290.500795] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6290.500798] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6290.500800] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6290.500804] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6290.500816] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6290.500818] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6292.548431] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6292.548436] xhci_hcd 0000:00:14.0: Giveback URB ffff880404f713c0, len = 18, expected = 96, status = -121
>[ 6292.548467] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6292.548470] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6292.548636] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6292.548638] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6292.548640] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6292.548646] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6292.548648] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6292.548649] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6292.548650] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6292.548652] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6292.548653] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6292.548655] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6292.548658] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6292.548661] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6292.548672] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6292.548675] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6294.596261] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6294.596266] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c56be40, len = 18, expected = 96, status = -121
>[ 6294.596297] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6294.596300] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6294.596466] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6294.596469] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6294.596471] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6294.596473] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6294.596476] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6294.596478] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6294.596480] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6294.596482] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6294.596485] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6294.596488] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6294.596491] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6294.596494] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6294.596502] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6294.596505] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6296.644178] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6296.644190] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fbe40, len = 18, expected = 96, status = -121
>[ 6296.644217] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6296.644224] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6296.644405] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6296.644411] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6296.644416] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6296.644422] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6296.644427] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6296.644432] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6296.644438] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6296.644443] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6296.644448] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6296.644455] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6296.644460] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6296.644478] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6296.644488] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6298.692007] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6298.692015] xhci_hcd 0000:00:14.0: Giveback URB ffff880405902780, len = 18, expected = 96, status = -121
>[ 6298.692046] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6298.692053] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6298.692232] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6298.692234] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6298.692236] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6298.692238] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6298.692240] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6298.692241] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6298.692243] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6298.692245] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6298.692247] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6298.692250] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6298.692251] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6298.692255] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6298.692265] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6298.692267] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6300.739877] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6300.739883] xhci_hcd 0000:00:14.0: Giveback URB ffff880405ac0000, len = 18, expected = 96, status = -121
>[ 6300.739904] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6300.739908] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6300.740085] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6300.740087] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6300.740090] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6300.740092] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6300.740094] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6300.740097] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6300.740099] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6300.740101] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6300.740103] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6300.740106] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6300.740107] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6300.740114] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6300.740118] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6302.787757] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6302.787762] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b7f2a80, len = 18, expected = 96, status = -121
>[ 6302.787789] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6302.787795] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6302.787983] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6302.787990] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6302.787992] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6302.787994] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6302.787996] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6302.787998] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6302.788000] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6302.788002] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6302.788004] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6302.788008] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6302.788010] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6302.788014] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6302.788019] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6302.788021] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6304.835638] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6304.835650] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b7f2840, len = 18, expected = 96, status = -121
>[ 6304.835680] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6304.835693] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6304.835906] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6304.835916] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6304.835921] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6304.835926] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6304.835929] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6304.835933] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6304.835937] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6304.835940] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6304.835944] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6304.835950] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6304.835956] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6304.835969] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6304.835976] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6306.883434] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6306.883440] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ed80, len = 18, expected = 96, status = -121
>[ 6306.883471] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6306.883476] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6306.883647] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6306.883652] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6306.883655] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6306.883657] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6306.883659] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6306.883661] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6306.883664] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6306.883666] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6306.883668] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6306.883671] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6306.883673] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6306.883676] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6306.883689] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6306.883693] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6308.931314] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6308.931319] xhci_hcd 0000:00:14.0: Giveback URB ffff8804071c6780, len = 18, expected = 96, status = -121
>[ 6308.931338] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6308.931341] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6308.931514] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6308.931517] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6308.931519] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6308.931521] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6308.931522] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6308.931524] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6308.931525] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6308.931526] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6308.931527] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6308.931530] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6308.931531] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6308.931534] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6308.931545] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6308.931547] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6310.979163] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6310.979167] xhci_hcd 0000:00:14.0: Giveback URB ffff8804070bbcc0, len = 18, expected = 96, status = -121
>[ 6310.979189] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6310.979191] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6310.979364] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6310.979367] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6310.979368] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6310.979369] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6310.979370] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6310.979371] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6310.979373] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6310.979374] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6310.979375] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6310.979377] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6310.979378] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6310.979381] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6310.979393] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6310.979395] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6313.027048] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6313.027055] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e780, len = 18, expected = 96, status = -121
>[ 6313.027078] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6313.027082] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6313.027262] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6313.027267] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6313.027269] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6313.027272] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6313.027274] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6313.027276] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6313.027279] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6313.027281] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6313.027283] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6313.027287] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6313.027289] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6313.027296] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6313.027300] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6315.074867] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6315.074875] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e600, len = 18, expected = 96, status = -121
>[ 6315.074901] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6315.074906] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6315.075076] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6315.075079] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6315.075082] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6315.075086] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6315.075088] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6315.075091] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6315.075094] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6315.075097] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6315.075099] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6315.075103] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6315.075106] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6315.075110] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6315.075118] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6315.075126] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6317.122730] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6317.122736] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b96cc0, len = 18, expected = 96, status = -121
>[ 6317.122770] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6317.122777] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6317.122949] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6317.122953] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6317.122957] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6317.122959] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6317.122963] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6317.122966] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6317.122969] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6317.122972] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6317.122974] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6317.122977] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6317.122980] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6317.122983] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6317.122988] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6317.122992] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6319.170582] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6319.170589] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db624540, len = 18, expected = 96, status = -121
>[ 6319.170618] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6319.170622] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6319.170794] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6319.170796] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6319.170798] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6319.170801] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6319.170803] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6319.170805] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6319.170807] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6319.170810] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6319.170811] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6319.170820] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6319.170825] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6319.170828] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6319.170836] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6319.170841] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6321.218468] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6321.218474] xhci_hcd 0000:00:14.0: Giveback URB ffff880403699240, len = 18, expected = 96, status = -121
>[ 6321.218496] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6321.218499] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6321.218676] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6321.218681] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6321.218688] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6321.218690] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6321.218691] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6321.218693] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6321.218695] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6321.218697] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6321.218699] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6321.218701] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6321.218704] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6321.218715] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6321.218717] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6323.266272] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6323.266277] xhci_hcd 0000:00:14.0: Giveback URB ffff8804039c46c0, len = 18, expected = 96, status = -121
>[ 6323.266308] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6323.266311] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6323.266479] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6323.266482] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6323.266483] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6323.266484] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6323.266486] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6323.266487] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6323.266488] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6323.266489] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6323.266490] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6323.266492] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6323.266493] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6323.266496] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6323.266513] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6323.266515] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6325.314160] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6325.314166] xhci_hcd 0000:00:14.0: Giveback URB ffff8804073f1a80, len = 18, expected = 96, status = -121
>[ 6325.314188] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6325.314192] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6325.314376] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6325.314381] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6325.314383] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6325.314385] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6325.314387] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6325.314390] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6325.314392] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6325.314395] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6325.314397] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6325.314400] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6325.314402] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6325.314410] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6325.314412] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6327.362037] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6327.362041] xhci_hcd 0000:00:14.0: Giveback URB ffff8804036993c0, len = 18, expected = 96, status = -121
>[ 6327.362062] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6327.362065] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6327.362244] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6327.362247] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6327.362249] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6327.362251] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6327.362252] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6327.362254] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6327.362256] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6327.362258] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6327.362259] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6327.362262] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6327.362263] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6327.362267] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6327.362273] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6327.362276] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6329.409887] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6329.409896] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db99f840, len = 18, expected = 96, status = -121
>[ 6329.409925] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6329.409934] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6329.410117] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6329.410121] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6329.410124] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6329.410128] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6329.410131] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6329.410134] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6329.410136] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6329.410138] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6329.410141] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6329.410146] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6329.410149] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6329.410153] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6329.410163] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6329.410170] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6331.457788] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6331.457797] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bf00, len = 18, expected = 96, status = -121
>[ 6331.457826] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6331.457832] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6331.458014] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6331.458021] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6331.458024] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6331.458027] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6331.458030] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6331.458033] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6331.458036] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6331.458039] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6331.458041] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6331.458045] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6331.458048] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6331.458060] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6331.458067] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6333.505592] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6333.505597] xhci_hcd 0000:00:14.0: Giveback URB ffff880407d71d80, len = 18, expected = 96, status = -121
>[ 6333.505624] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6333.505630] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6333.505810] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6333.505813] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6333.505815] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6333.505817] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6333.505819] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6333.505821] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6333.505823] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6333.505825] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6333.505827] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6333.505830] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6333.505832] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6333.505839] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6333.505841] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6335.553431] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6335.553437] xhci_hcd 0000:00:14.0: Giveback URB ffff8804070bb6c0, len = 18, expected = 96, status = -121
>[ 6335.553470] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6335.553477] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6335.553650] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6335.553653] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6335.553656] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6335.553658] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6335.553660] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6335.553662] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6335.553665] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6335.553667] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6335.553669] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6335.553673] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6335.553675] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6335.553680] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6335.553684] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6335.553688] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6337.601316] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6337.601321] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e3a540, len = 18, expected = 96, status = -121
>[ 6337.601348] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6337.601354] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6337.601532] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6337.601536] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6337.601537] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6337.601538] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6337.601539] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6337.601542] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6337.601543] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6337.601544] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6337.601545] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6337.601547] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6337.601549] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6337.601552] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6337.601562] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6337.601565] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6339.649134] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6339.649138] xhci_hcd 0000:00:14.0: Giveback URB ffff880406b62180, len = 18, expected = 96, status = -121
>[ 6339.649171] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6339.649173] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6339.649340] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6339.649342] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6339.649344] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6339.649345] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6339.649347] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6339.649348] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6339.649350] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6339.649352] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6339.649353] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6339.649356] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6339.649357] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6339.649360] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6339.649375] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6339.649378] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6341.697027] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6341.697032] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc39e900, len = 18, expected = 96, status = -121
>[ 6341.697054] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6341.697057] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6341.697232] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6341.697235] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6341.697236] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6341.697237] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6341.697238] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6341.697240] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6341.697241] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6341.697242] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6341.697243] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6341.697245] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6341.697246] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6341.697249] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6341.697263] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6341.697266] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6343.744896] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6343.744902] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbdb8d80, len = 18, expected = 96, status = -121
>[ 6343.744924] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6343.744927] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6343.745104] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6343.745109] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6343.745118] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6343.745120] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6343.745121] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6343.745124] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6343.745126] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6343.745128] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6343.745130] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6343.745133] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6343.745136] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6343.745144] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6343.745148] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6345.792753] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6345.792757] xhci_hcd 0000:00:14.0: Giveback URB ffff880409acc0c0, len = 18, expected = 96, status = -121
>[ 6345.792781] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6345.792786] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6345.792963] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6345.792965] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6345.792966] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6345.792967] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6345.792967] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6345.792970] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6345.792971] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6345.792973] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6345.792973] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6345.792975] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6345.792976] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6345.792979] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6345.792996] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6345.792999] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6347.840541] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6347.840546] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc1a4840, len = 18, expected = 96, status = -121
>[ 6347.840577] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6347.840580] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6347.840747] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6347.840750] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6347.840751] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6347.840753] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6347.840755] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6347.840757] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6347.840759] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6347.840761] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6347.840762] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6347.840765] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6347.840767] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6347.840770] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6347.840782] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6347.840785] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6349.888480] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6349.888487] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e31cc0, len = 18, expected = 96, status = -121
>[ 6349.888514] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6349.888521] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6349.888707] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6349.888715] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6349.888719] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6349.888723] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6349.888727] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6349.888730] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6349.888734] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6349.888744] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6349.888746] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6349.888750] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6349.888753] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6349.888766] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6349.888771] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6351.936300] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6351.936305] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbdf1840, len = 18, expected = 96, status = -121
>[ 6351.936332] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6351.936337] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6351.936518] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6351.936521] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6351.936522] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6351.936524] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6351.936525] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6351.936528] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6351.936531] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6351.936532] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6351.936534] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6351.936537] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6351.936539] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6351.936543] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6351.936548] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6351.936550] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6353.984214] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6353.984231] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb540, len = 18, expected = 96, status = -121
>[ 6353.984266] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6353.984276] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6353.984472] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6353.984481] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6353.984485] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6353.984490] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6353.984495] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6353.984503] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6353.984510] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6353.984518] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6353.984524] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6353.984535] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6353.984542] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6353.984560] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6353.984571] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6356.031990] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6356.031995] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc9f53c0, len = 18, expected = 96, status = -121
>[ 6356.032026] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6356.032029] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6356.032214] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6356.032216] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6356.032218] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6356.032219] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6356.032221] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6356.032223] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6356.032225] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6356.032226] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6356.032228] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6356.032230] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6356.032232] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6356.032236] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6356.032248] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6356.032251] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6358.079862] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6358.079871] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb300, len = 18, expected = 96, status = -121
>[ 6358.079902] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6358.079911] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6358.080093] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6358.080096] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6358.080097] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6358.080103] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6358.080105] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6358.080108] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6358.080111] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6358.080114] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6358.080116] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6358.080119] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6358.080122] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6358.080125] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6358.080131] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6358.080135] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6360.127754] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6360.127760] xhci_hcd 0000:00:14.0: Giveback URB ffff88040369b3c0, len = 18, expected = 96, status = -121
>[ 6360.127785] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6360.127791] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6360.127975] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6360.127979] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6360.127982] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6360.127984] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6360.127987] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6360.127989] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6360.127992] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6360.127995] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6360.127997] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6360.128001] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6360.128004] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6360.128012] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6360.128015] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6362.175619] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6362.175625] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dc39e240, len = 18, expected = 96, status = -121
>[ 6362.175652] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6362.175656] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6362.175838] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6362.175843] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6362.175845] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6362.175847] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6362.175849] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6362.175851] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6362.175853] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6362.175857] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6362.175859] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6362.175862] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6362.175865] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6362.175875] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6362.175878] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6364.223455] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6364.223460] xhci_hcd 0000:00:14.0: Giveback URB ffff880404af9480, len = 18, expected = 96, status = -121
>[ 6364.223487] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6364.223493] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6364.223672] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6364.223676] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6364.223683] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6364.223684] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6364.223686] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6364.223687] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6364.223689] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6364.223693] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6364.223695] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6364.223698] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6364.223701] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6364.223704] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6364.223711] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6364.223714] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6366.271332] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6366.271341] xhci_hcd 0000:00:14.0: Giveback URB ffff880404af9300, len = 18, expected = 96, status = -121
>[ 6366.271366] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6366.271372] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6366.271543] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6366.271548] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6366.271551] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6366.271553] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6366.271555] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6366.271566] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6366.271570] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6366.271573] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6366.271579] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6366.271583] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6366.271586] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6366.271591] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6366.271598] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6366.271604] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6368.319271] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6368.319289] xhci_hcd 0000:00:14.0: Giveback URB ffff880407778d80, len = 18, expected = 96, status = -121
>[ 6368.319353] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6368.319368] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6368.319582] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6368.319593] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6368.319600] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6368.319607] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6368.319613] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6368.319621] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6368.319626] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6368.319631] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6368.319635] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6368.319648] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6368.319654] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6368.319675] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6368.319683] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6370.367051] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6370.367057] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dae80f00, len = 18, expected = 96, status = -121
>[ 6370.367079] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6370.367082] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6370.367263] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6370.367266] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6370.367270] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6370.367273] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6370.367275] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6370.367277] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6370.367280] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6370.367282] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6370.367284] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6370.367288] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6370.367290] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6370.367297] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6370.367301] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6372.414874] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6372.414882] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db618180, len = 18, expected = 96, status = -121
>[ 6372.414908] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6372.414913] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6372.415102] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6372.415109] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6372.415113] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6372.415117] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6372.415120] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6372.415124] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6372.415129] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6372.415133] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6372.415137] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6372.415142] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6372.415146] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6372.415163] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6372.415167] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6374.462794] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6374.462806] xhci_hcd 0000:00:14.0: Giveback URB ffff880407a23900, len = 18, expected = 96, status = -121
>[ 6374.462832] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6374.462842] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6374.463046] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6374.463053] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6374.463057] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6374.463061] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6374.463066] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6374.463070] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6374.463075] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6374.463080] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6374.463084] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6374.463091] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6374.463096] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6374.463111] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6374.463119] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6376.510626] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6376.510632] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5ed840, len = 18, expected = 96, status = -121
>[ 6376.510654] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6376.510659] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6376.510838] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6376.510844] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6376.510846] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6376.510847] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6376.510849] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6376.510851] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6376.510853] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6376.510855] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6376.510858] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6376.510862] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6376.510864] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6376.510875] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6376.510878] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6378.558433] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6378.558438] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da8fbf00, len = 18, expected = 96, status = -121
>[ 6378.558469] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6378.558472] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6378.558638] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6378.558640] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6378.558646] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6378.558648] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6378.558649] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6378.558650] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6378.558651] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6378.558652] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6378.558653] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6378.558657] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6378.558659] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6378.558662] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6378.558675] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6378.558680] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 6380.606321] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6380.606329] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db618900, len = 18, expected = 96, status = -121
>[ 6380.606359] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6380.606367] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6380.606549] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6380.606552] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6380.606554] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6380.606557] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6380.606559] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6380.606562] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6380.606564] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6380.606572] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 6380.606574] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6380.606577] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 6380.606582] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6380.606587] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6380.606594] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6380.606597] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 6382.654188] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6382.654194] xhci_hcd 0000:00:14.0: Giveback URB ffff88040396dd80, len = 18, expected = 96, status = -121
>[ 6382.654215] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6382.654218] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6382.654384] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6382.654386] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6382.654388] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6382.654390] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6382.654392] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6382.654394] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6382.654396] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6382.654398] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 6382.654400] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6382.654403] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 6382.654405] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6382.654408] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6382.654420] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6382.654422] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 6384.702005] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6384.702009] xhci_hcd 0000:00:14.0: Giveback URB ffff88040396dd80, len = 18, expected = 96, status = -121
>[ 6384.702043] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6384.702045] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6384.702205] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6384.702207] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6384.702208] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6384.702209] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6384.702210] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6384.702212] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6384.702213] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6384.702214] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 6384.702215] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6384.702217] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 6384.702218] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6384.702220] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6384.702243] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6384.702244] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 6386.749910] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6386.749916] xhci_hcd 0000:00:14.0: Giveback URB ffff880403694d80, len = 18, expected = 96, status = -121
>[ 6386.749939] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6386.749944] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6386.750130] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6386.750140] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6386.750141] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6386.750143] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6386.750145] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6386.750147] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6386.750149] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6386.750152] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 6386.750155] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6386.750159] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 6386.750161] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6386.750168] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6386.750171] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6388.797708] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6388.797714] xhci_hcd 0000:00:14.0: Giveback URB ffff880407efe540, len = 18, expected = 96, status = -121
>[ 6388.797747] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6388.797752] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6388.797932] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6388.797934] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6388.797936] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6388.797939] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6388.797941] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6388.797943] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6388.797945] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6388.797947] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6388.797948] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6388.797951] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6388.797952] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6388.797961] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6388.797964] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6390.845604] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6390.845611] xhci_hcd 0000:00:14.0: Giveback URB ffff880407664180, len = 18, expected = 96, status = -121
>[ 6390.845639] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6390.845644] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6390.845816] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6390.845821] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6390.845827] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6390.845829] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6390.845831] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6390.845834] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6390.845837] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6390.845841] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6390.845843] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6390.845848] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6390.845850] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6390.845854] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6390.845863] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6390.845870] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6392.893471] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6392.893478] xhci_hcd 0000:00:14.0: Giveback URB ffff880405b37e40, len = 18, expected = 96, status = -121
>[ 6392.893509] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6392.893513] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6392.893683] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6392.893686] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6392.893688] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6392.893691] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6392.893693] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6392.893695] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6392.893698] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6392.893700] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6392.893703] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6392.893706] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6392.893709] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6392.893713] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6392.893722] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6392.893726] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6394.941309] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6394.941315] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e90300, len = 18, expected = 96, status = -121
>[ 6394.941348] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6394.941354] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6394.941536] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6394.941539] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6394.941543] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6394.941545] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6394.941547] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6394.941549] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6394.941552] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6394.941554] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6394.941556] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6394.941560] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6394.941562] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6394.941570] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6394.941574] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6396.989155] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6396.989161] xhci_hcd 0000:00:14.0: Giveback URB ffff880407efe3c0, len = 18, expected = 96, status = -121
>[ 6396.989194] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6396.989200] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6396.989378] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6396.989381] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6396.989383] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6396.989385] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6396.989386] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6396.989387] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6396.989389] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6396.989390] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6396.989391] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6396.989393] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6396.989395] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6396.989398] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6396.989409] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6396.989411] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6399.037023] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6399.037029] xhci_hcd 0000:00:14.0: Giveback URB ffff8804064a0300, len = 18, expected = 96, status = -121
>[ 6399.037063] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6399.037070] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6399.037243] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6399.037245] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6399.037247] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6399.037249] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6399.037251] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6399.037253] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6399.037255] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6399.037257] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6399.037259] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6399.037261] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6399.037264] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6399.037267] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6399.037276] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6399.037279] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6401.084860] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6401.084865] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f180, len = 18, expected = 96, status = -121
>[ 6401.084897] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6401.084899] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6401.085123] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6401.085126] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6401.085128] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6401.085129] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6401.085131] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6401.085133] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6401.085135] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6401.085137] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6401.085138] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6401.085141] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6401.085143] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6401.085146] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6401.085158] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6401.085160] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6403.132727] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6403.132732] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b78a900, len = 18, expected = 96, status = -121
>[ 6403.132764] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6403.132766] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6403.132933] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6403.132936] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6403.132938] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6403.132939] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6403.132941] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6403.132942] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6403.132944] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6403.132946] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6403.132947] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6403.132950] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6403.132951] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6403.132954] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6403.132969] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6403.132972] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6405.180596] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6405.180600] xhci_hcd 0000:00:14.0: Giveback URB ffff880403697c00, len = 18, expected = 96, status = -121
>[ 6405.180627] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6405.180633] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6405.180813] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6405.180816] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6405.180819] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6405.180821] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6405.180823] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6405.180825] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6405.180827] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6405.180829] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6405.180831] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6405.180834] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6405.180836] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6405.180842] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6405.180846] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6407.228404] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6407.228410] xhci_hcd 0000:00:14.0: Giveback URB ffff8804036970c0, len = 18, expected = 96, status = -121
>[ 6407.228441] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6407.228444] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6407.228610] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6407.228612] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6407.228616] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6407.228617] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6407.228619] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6407.228621] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6407.228622] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6407.228624] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6407.228626] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6407.228628] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6407.228630] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6407.228633] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6407.228646] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6407.228649] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6409.276327] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6409.276333] xhci_hcd 0000:00:14.0: Giveback URB ffff880403bbfb40, len = 18, expected = 96, status = -121
>[ 6409.276357] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6409.276361] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6409.276546] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6409.276552] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6409.276555] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6409.276557] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6409.276559] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6409.276561] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6409.276563] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6409.276565] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6409.276567] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6409.276572] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6409.276574] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6409.276585] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6409.276588] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6411.324123] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6411.324126] xhci_hcd 0000:00:14.0: Giveback URB ffff88040be38540, len = 18, expected = 96, status = -121
>[ 6411.324163] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6411.324166] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6411.324330] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6411.324332] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6411.324333] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6411.324334] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6411.324336] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6411.324337] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6411.324338] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6411.324339] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6411.324340] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6411.324342] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6411.324344] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6411.324346] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6411.324366] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6411.324368] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6413.372000] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6413.372006] xhci_hcd 0000:00:14.0: Giveback URB ffff880404746540, len = 18, expected = 96, status = -121
>[ 6413.372039] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6413.372045] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6413.372223] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6413.372226] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6413.372228] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6413.372229] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6413.372230] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6413.372231] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6413.372233] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6413.372234] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6413.372235] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6413.372237] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6413.372239] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6413.372247] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6413.372254] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6413.372257] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6415.419865] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6415.419870] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb540, len = 18, expected = 96, status = -121
>[ 6415.419903] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6415.419905] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6415.420071] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6415.420073] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6415.420075] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6415.420076] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6415.420077] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6415.420078] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6415.420079] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6415.420081] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6415.420082] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6415.420084] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6415.420085] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6415.420087] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6415.420108] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6415.420110] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6417.467718] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6417.467722] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dbbeb600, len = 18, expected = 96, status = -121
>[ 6417.467755] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6417.467757] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6417.467919] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6417.467921] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6417.467922] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6417.467923] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6417.467925] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6417.467926] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6417.467927] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6417.467928] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6417.467929] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6417.467931] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6417.467932] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6417.467934] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6417.467955] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6417.467957] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6419.515570] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6419.515574] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c61a000, len = 18, expected = 96, status = -121
>[ 6419.515610] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6419.515614] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6419.515783] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6419.515785] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6419.515787] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6419.515788] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6419.515789] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6419.515790] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6419.515792] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6419.515793] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6419.515794] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6419.515796] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6419.515798] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6419.515801] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6419.515818] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6419.515820] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6421.563426] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6421.563431] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068daf00, len = 18, expected = 96, status = -121
>[ 6421.563463] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6421.563465] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6421.563632] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6421.563635] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6421.563636] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6421.563637] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6421.563638] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6421.563639] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6421.563642] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6421.563644] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6421.563645] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6421.563647] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6421.563649] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6421.563652] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6421.563668] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6421.563670] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6423.611348] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6423.611355] xhci_hcd 0000:00:14.0: Giveback URB ffff880403697f00, len = 18, expected = 96, status = -121
>[ 6423.611382] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6423.611389] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6423.611579] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6423.611586] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6423.611591] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6423.611595] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6423.611599] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6423.611603] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6423.611607] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6423.611611] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6423.611614] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6423.611620] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6423.611624] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6423.611634] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6423.611638] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6425.659158] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6425.659167] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ece6c0, len = 18, expected = 96, status = -121
>[ 6425.659199] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6425.659210] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6425.659399] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6425.659403] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6425.659406] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6425.659408] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6425.659410] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6425.659415] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6425.659418] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6425.659421] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6425.659423] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6425.659427] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6425.659430] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6425.659434] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6425.659443] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6425.659450] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6427.706984] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6427.706989] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bb7cb40, len = 18, expected = 96, status = -121
>[ 6427.707021] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6427.707024] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6427.707190] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6427.707192] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6427.707194] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6427.707196] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6427.707197] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6427.707199] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6427.707200] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6427.707202] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6427.707204] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6427.707206] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6427.707208] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6427.707211] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6427.707226] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6427.707228] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6429.754869] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6429.754874] xhci_hcd 0000:00:14.0: Giveback URB ffff8804039c4540, len = 18, expected = 96, status = -121
>[ 6429.754905] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6429.754908] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6429.755074] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6429.755076] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6429.755078] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6429.755080] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6429.755081] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6429.755083] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6429.755085] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6429.755087] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6429.755089] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6429.755092] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6429.755094] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6429.755097] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6429.755110] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6429.755113] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6431.802739] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6431.802744] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e900, len = 18, expected = 96, status = -121
>[ 6431.802777] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6431.802782] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6431.802950] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6431.802952] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6431.802953] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6431.802954] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6431.802956] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6431.802957] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6431.802958] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6431.802960] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6431.802961] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6431.802963] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6431.802964] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6431.802967] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6431.802985] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6431.802986] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6433.850604] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6433.850609] xhci_hcd 0000:00:14.0: Giveback URB ffff880403696240, len = 18, expected = 96, status = -121
>[ 6433.850630] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6433.850633] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6433.850805] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6433.850808] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6433.850809] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6433.850810] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6433.850811] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6433.850813] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6433.850814] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6433.850815] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6433.850816] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6433.850818] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6433.850819] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6433.850822] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6433.850835] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6433.850837] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6435.898461] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6435.898465] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b240, len = 18, expected = 96, status = -121
>[ 6435.898489] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6435.898493] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6435.898665] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6435.898667] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6435.898669] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6435.898670] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6435.898671] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6435.898672] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6435.898673] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6435.898675] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6435.898676] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6435.898677] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6435.898678] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6435.898685] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6435.898698] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6435.898701] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6436.785021] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6436.785031] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6436.785038] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6436.785044] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6437.946324] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6437.946332] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900a80, len = 18, expected = 96, status = -121
>[ 6437.946363] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6437.946371] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6437.946556] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6437.946559] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6437.946563] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6437.946565] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6437.946568] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6437.946570] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6437.946573] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6437.946575] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6437.946577] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6437.946581] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6437.946583] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6437.946592] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6437.946595] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6439.994154] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6439.994159] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900a80, len = 18, expected = 96, status = -121
>[ 6439.994193] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6439.994207] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6439.994386] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6439.994388] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6439.994389] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6439.994390] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6439.994391] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6439.994393] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6439.994397] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6439.994398] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6439.994400] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6439.994411] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6439.994412] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6439.994414] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6439.994420] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6439.994422] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6442.042016] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6442.042021] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b9aa80, len = 18, expected = 96, status = -121
>[ 6442.042045] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6442.042049] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6442.042229] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6442.042233] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6442.042234] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6442.042236] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6442.042237] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6442.042238] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6442.042239] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6442.042241] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6442.042242] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6442.042244] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6442.042245] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6442.042248] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6442.042258] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6442.042260] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6444.089891] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6444.089895] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941c00, len = 18, expected = 96, status = -121
>[ 6444.089916] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6444.089919] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6444.090113] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6444.090116] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6444.090117] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6444.090119] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6444.090120] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6444.090122] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6444.090123] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6444.090125] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6444.090126] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6444.090128] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6444.090130] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6444.090133] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6444.090137] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6444.090140] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6446.137744] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6446.137748] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941c00, len = 18, expected = 96, status = -121
>[ 6446.137770] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6446.137772] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6446.137944] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6446.137947] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6446.137949] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6446.137950] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6446.137951] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6446.137953] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6446.137954] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6446.137955] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6446.137956] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6446.137958] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6446.137959] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6446.137962] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6446.137974] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6446.137976] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6448.185597] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6448.185601] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941600, len = 18, expected = 96, status = -121
>[ 6448.185634] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6448.185636] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6448.185799] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6448.185800] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6448.185802] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6448.185803] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6448.185804] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6448.185805] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6448.185806] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6448.185808] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6448.185809] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6448.185810] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6448.185812] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6448.185814] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6448.185836] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6448.185838] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6450.040687] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6450.040694] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6450.040699] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6450.040705] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6450.233462] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6450.233466] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941240, len = 18, expected = 96, status = -121
>[ 6450.233491] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6450.233496] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6450.233684] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6450.233688] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6450.233690] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6450.233691] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6450.233692] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6450.233694] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6450.233696] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6450.233697] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6450.233699] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6450.233701] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6450.233702] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6450.233706] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6450.233711] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6450.233714] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6452.281350] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6452.281355] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b9ad80, len = 18, expected = 96, status = -121
>[ 6452.281376] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6452.281379] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6452.281551] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6452.281554] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6452.281555] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6452.281556] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6452.281557] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6452.281559] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6452.281560] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6452.281561] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6452.281562] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6452.281564] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6452.281565] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6452.281569] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6452.281581] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6452.281583] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6454.329189] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6454.329193] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bd80, len = 18, expected = 96, status = -121
>[ 6454.329216] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6454.329221] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6454.329401] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6454.329404] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6454.329405] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6454.329407] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6454.329408] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6454.329410] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6454.329411] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6454.329413] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6454.329414] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6454.329417] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6454.329418] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6454.329421] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6454.329432] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6454.329434] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6456.377027] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6456.377031] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900600, len = 18, expected = 96, status = -121
>[ 6456.377076] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6456.377080] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6456.377254] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6456.377256] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6456.377257] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6456.377258] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6456.377259] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6456.377260] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6456.377261] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6456.377262] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6456.377262] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6456.377264] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6456.377265] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6456.377270] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6456.377286] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6456.377289] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6458.424871] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6458.424875] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c61a240, len = 18, expected = 96, status = -121
>[ 6458.424897] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6458.424899] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6458.425076] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6458.425079] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6458.425081] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6458.425082] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6458.425084] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6458.425085] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6458.425086] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6458.425087] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6458.425088] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6458.425090] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6458.425091] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6458.425094] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6458.425101] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6458.425103] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6460.472746] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6460.472750] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c61a0c0, len = 18, expected = 96, status = -121
>[ 6460.472774] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6460.472779] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6460.472951] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6460.472953] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6460.472955] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6460.472956] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6460.472957] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6460.472958] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6460.472959] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6460.472960] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6460.472961] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6460.472963] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6460.472964] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6460.472967] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6460.472982] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6460.472984] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6462.520620] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6462.520624] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c61a240, len = 18, expected = 96, status = -121
>[ 6462.520645] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6462.520648] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6462.520826] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6462.520829] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6462.520831] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6462.520832] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6462.520833] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6462.520835] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6462.520836] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6462.520838] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6462.520839] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6462.520841] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6462.520843] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6462.520846] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6462.520854] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6462.520856] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6463.296342] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6463.296349] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6463.296354] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6463.296358] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6464.568454] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6464.568458] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ea80, len = 18, expected = 96, status = -121
>[ 6464.568486] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6464.568490] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6464.568668] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6464.568670] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6464.568671] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6464.568672] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6464.568674] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6464.568675] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6464.568676] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6464.568677] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6464.568678] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6464.568680] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6464.568681] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6464.568684] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6464.568694] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6464.568695] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6466.616279] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6466.616284] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ea80, len = 18, expected = 96, status = -121
>[ 6466.616318] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6466.616323] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6466.616495] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6466.616498] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6466.616499] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6466.616500] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6466.616501] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6466.616503] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6466.616504] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6466.616505] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6466.616506] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6466.616508] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6466.616509] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6466.616512] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6466.616526] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6466.616528] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6468.664164] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6468.664168] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ea80, len = 18, expected = 96, status = -121
>[ 6468.664202] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6468.664203] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6468.664364] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6468.664366] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6468.664367] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6468.664368] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6468.664369] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6468.664370] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6468.664371] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6468.664373] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6468.664374] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6468.664375] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6468.664377] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6468.664379] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6468.664401] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6468.664403] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6470.712032] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6470.712036] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941840, len = 18, expected = 96, status = -121
>[ 6470.712060] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6470.712064] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6470.712238] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6470.712241] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6470.712242] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6470.712243] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6470.712245] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6470.712246] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6470.712247] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6470.712248] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6470.712249] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6470.712251] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6470.712252] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6470.712255] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6470.712269] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6470.712270] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6472.759884] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6472.759888] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789ea80, len = 18, expected = 96, status = -121
>[ 6472.759921] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6472.759923] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6472.760084] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6472.760086] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6472.760087] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6472.760088] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6472.760089] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6472.760090] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6472.760091] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6472.760093] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6472.760094] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6472.760095] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6472.760096] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6472.760099] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6472.760120] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6472.760122] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6474.807755] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6474.807759] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bbea900, len = 18, expected = 96, status = -121
>[ 6474.807783] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6474.807787] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6474.807967] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6474.807970] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6474.807971] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6474.807972] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6474.807973] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6474.807975] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6474.807976] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6474.807977] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6474.807978] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6474.807980] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6474.807981] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6474.807984] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6474.807998] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6474.808000] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6476.551998] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6476.552005] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6476.552010] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6476.552015] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6476.855578] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6476.855582] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e780, len = 18, expected = 96, status = -121
>[ 6476.855617] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6476.855620] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6476.855797] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6476.855799] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6476.855800] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6476.855801] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6476.855802] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6476.855803] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6476.855805] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6476.855806] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6476.855807] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6476.855808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6476.855809] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6476.855812] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6476.855832] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6476.855833] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6478.903460] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6478.903464] xhci_hcd 0000:00:14.0: Giveback URB ffff880403941780, len = 18, expected = 96, status = -121
>[ 6478.903489] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6478.903493] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6478.903667] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6478.903670] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6478.903671] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6478.903672] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6478.903673] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6478.903674] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6478.903676] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6478.903677] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6478.903678] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6478.903679] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6478.903681] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6478.903684] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6478.903698] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6478.903700] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6480.951336] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6480.951340] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b9ad80, len = 18, expected = 96, status = -121
>[ 6480.951365] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6480.951369] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6480.951597] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6480.951600] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6480.951602] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6480.951603] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6480.951604] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6480.951605] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6480.951606] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6480.951607] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6480.951609] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6480.951610] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6480.951612] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6480.951619] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6480.951622] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6482.999187] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6482.999192] xhci_hcd 0000:00:14.0: Giveback URB ffff880403b9a9c0, len = 18, expected = 96, status = -121
>[ 6482.999224] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6482.999227] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6482.999394] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6482.999397] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6482.999399] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6482.999400] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6482.999402] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6482.999404] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6482.999405] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6482.999407] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6482.999409] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6482.999411] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6482.999413] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6482.999416] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6482.999431] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6482.999434] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6485.047032] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6485.047036] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5edd80, len = 18, expected = 96, status = -121
>[ 6485.047061] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6485.047065] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6485.047249] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6485.047252] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6485.047253] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6485.047255] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6485.047256] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6485.047257] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6485.047258] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6485.047260] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6485.047261] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6485.047262] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6485.047264] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6485.047267] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6485.047271] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6485.047274] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6487.094859] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6487.094862] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6487.094896] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6487.094898] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6487.095059] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6487.095060] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6487.095061] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6487.095062] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6487.095063] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6487.095064] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6487.095066] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6487.095067] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6487.095068] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6487.095070] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6487.095071] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6487.095073] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6487.095095] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6487.095097] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6489.142760] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6489.142764] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b000, len = 18, expected = 96, status = -121
>[ 6489.142786] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6489.142788] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6489.142963] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6489.142966] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6489.142968] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6489.142970] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6489.142971] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6489.142972] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6489.142973] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6489.142975] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6489.142976] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6489.142977] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6489.142979] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6489.142982] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6489.142990] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6489.142992] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6489.807659] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6489.807667] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6489.807672] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6489.807677] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6491.190584] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6491.190590] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ece540, len = 18, expected = 96, status = -121
>[ 6491.190623] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6491.190628] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6491.190805] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6491.190808] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6491.190809] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6491.190811] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6491.190812] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6491.190813] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6491.190814] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6491.190816] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6491.190817] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6491.190818] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6491.190820] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6491.190827] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6491.190836] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6491.190839] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6493.238452] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6493.238457] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6493.238490] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6493.238492] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6493.238661] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6493.238663] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6493.238665] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6493.238666] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6493.238668] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6493.238669] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6493.238671] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6493.238672] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6493.238674] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6493.238676] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6493.238677] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6493.238681] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6493.238695] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6493.238697] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6495.286301] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6495.286306] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bd80, len = 18, expected = 96, status = -121
>[ 6495.286330] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6495.286333] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6495.286512] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6495.286514] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6495.286515] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6495.286516] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6495.286518] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6495.286519] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6495.286520] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6495.286522] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6495.286523] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6495.286525] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6495.286526] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6495.286529] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6495.286547] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6495.286548] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6497.334160] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6497.334165] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6497.334197] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6497.334199] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6497.334366] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6497.334368] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6497.334370] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6497.334372] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6497.334373] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6497.334375] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6497.334377] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6497.334378] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6497.334380] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6497.334383] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6497.334384] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6497.334388] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6497.334401] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6497.334404] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6499.382015] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6499.382020] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ece540, len = 18, expected = 96, status = -121
>[ 6499.382054] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6499.382059] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6499.382227] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6499.382230] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6499.382231] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6499.382233] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6499.382234] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6499.382235] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6499.382241] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6499.382242] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6499.382244] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6499.382246] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6499.382247] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6499.382251] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6499.382264] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6499.382266] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6501.429871] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6501.429877] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e180, len = 18, expected = 96, status = -121
>[ 6501.429910] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6501.429915] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6501.430094] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6501.430101] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6501.430102] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6501.430104] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6501.430105] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6501.430107] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6501.430108] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6501.430110] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6501.430112] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6501.430115] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6501.430117] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6501.430121] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6501.430125] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6501.430128] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6503.063316] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6503.063324] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6503.063329] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6503.063334] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6503.477738] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6503.477744] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6503.477775] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6503.477777] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6503.477945] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6503.477948] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6503.477950] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6503.477951] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6503.477957] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6503.477959] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6503.477961] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6503.477962] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6503.477964] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6503.477969] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6503.477971] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6503.477975] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6503.477983] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6503.477989] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6505.525613] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6505.525621] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6505.525648] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6505.525653] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6505.525826] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6505.525830] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6505.525838] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6505.525840] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6505.525841] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6505.525843] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6505.525845] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6505.525849] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6505.525851] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6505.525855] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6505.525857] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6505.525861] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6505.525870] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6505.525873] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6507.573524] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6507.573533] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29000, len = 18, expected = 96, status = -121
>[ 6507.573565] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6507.573574] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6507.573767] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6507.573774] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6507.573778] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6507.573781] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6507.573784] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6507.573787] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6507.573790] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6507.573793] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6507.573796] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6507.573800] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6507.573803] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6507.573816] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6507.573824] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 6509.621319] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6509.621327] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068dad80, len = 18, expected = 96, status = -121
>[ 6509.621353] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6509.621358] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6509.621530] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6509.621534] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6509.621537] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6509.621540] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6509.621543] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6509.621546] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6509.621549] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6509.621553] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 6509.621555] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6509.621560] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 6509.621562] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6509.621566] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6509.621574] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6509.621586] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 6511.669204] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6511.669209] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29000, len = 18, expected = 96, status = -121
>[ 6511.669232] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6511.669237] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6511.669419] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6511.669428] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6511.669430] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6511.669431] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6511.669433] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6511.669435] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6511.669437] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6511.669439] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 6511.669443] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6511.669446] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 6511.669448] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6511.669455] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6511.669458] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 6513.717045] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6513.717049] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29000, len = 18, expected = 96, status = -121
>[ 6513.717074] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6513.717077] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6513.717251] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6513.717254] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6513.717255] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6513.717256] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6513.717257] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6513.717258] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6513.717260] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6513.717261] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 6513.717262] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6513.717264] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 6513.717265] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6513.717268] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6513.717281] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6513.717283] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 6515.764899] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6515.764903] xhci_hcd 0000:00:14.0: Giveback URB ffff8800daf29000, len = 18, expected = 96, status = -121
>[ 6515.764927] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6515.764931] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6515.765117] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6515.765120] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6515.765121] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6515.765122] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6515.765123] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6515.765125] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6515.765126] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6515.765127] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 6515.765128] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6515.765130] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 6515.765131] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6515.765134] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6515.765138] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6515.765141] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6516.318963] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6516.318972] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6516.318977] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6516.318982] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6517.812733] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6517.812738] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900540, len = 18, expected = 96, status = -121
>[ 6517.812771] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6517.812776] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6517.812949] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6517.812952] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6517.812954] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6517.812955] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6517.812956] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6517.812958] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6517.812959] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6517.812960] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6517.812961] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6517.812963] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6517.812965] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6517.812968] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6517.812980] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6517.812982] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6519.860577] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6519.860582] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e180, len = 18, expected = 96, status = -121
>[ 6519.860616] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6519.860621] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6519.860794] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6519.860797] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6519.860798] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6519.860800] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6519.860801] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6519.860802] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6519.860803] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6519.860805] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6519.860806] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6519.860808] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6519.860809] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6519.860812] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6519.860824] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6519.860826] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6521.908461] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6521.908465] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b240, len = 18, expected = 96, status = -121
>[ 6521.908487] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6521.908489] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6521.908682] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6521.908685] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6521.908686] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6521.908687] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6521.908688] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6521.908689] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6521.908691] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6521.908692] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6521.908693] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6521.908695] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6521.908696] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6521.908699] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6521.908705] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6521.908707] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6523.956300] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6523.956304] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b240, len = 18, expected = 96, status = -121
>[ 6523.956338] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6523.956339] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6523.956502] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6523.956504] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6523.956505] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6523.956506] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6523.956507] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6523.956508] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6523.956509] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6523.956511] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6523.956512] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6523.956513] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6523.956514] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6523.956517] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6523.956540] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6523.956542] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6526.004183] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6526.004187] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b240, len = 18, expected = 96, status = -121
>[ 6526.004211] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6526.004216] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6526.004393] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6526.004395] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6526.004396] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6526.004398] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6526.004399] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6526.004400] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6526.004402] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6526.004403] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6526.004404] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6526.004406] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6526.004407] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6526.004410] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6526.004426] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6526.004429] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6528.052052] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6528.052057] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b240, len = 18, expected = 96, status = -121
>[ 6528.052077] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6528.052081] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6528.052260] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6528.052263] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6528.052264] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6528.052266] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6528.052267] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6528.052271] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6528.052273] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6528.052275] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6528.052277] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6528.052279] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6528.052281] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6528.052288] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6528.052291] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6529.574631] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6529.574638] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6529.574644] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6529.574649] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6530.099892] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6530.099896] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b780, len = 18, expected = 96, status = -121
>[ 6530.099921] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6530.099924] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6530.100110] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6530.100113] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6530.100114] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6530.100115] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6530.100116] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6530.100118] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6530.100119] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6530.100120] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6530.100121] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6530.100123] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6530.100124] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6530.100127] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6530.100131] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6530.100134] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6532.147729] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6532.147734] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bf00, len = 18, expected = 96, status = -121
>[ 6532.147767] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6532.147769] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6532.147931] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6532.147933] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6532.147934] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6532.147936] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6532.147937] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6532.147939] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6532.147940] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6532.147942] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6532.147943] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6532.147945] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6532.147947] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6532.147949] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6532.147968] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6532.147970] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6534.195628] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6534.195635] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b000, len = 18, expected = 96, status = -121
>[ 6534.195660] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6534.195666] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6534.195849] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6534.195856] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6534.195860] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6534.195863] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6534.195866] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6534.195870] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6534.195873] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6534.195876] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6534.195878] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6534.195882] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6534.195884] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6534.195897] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6534.195902] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6536.243492] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6536.243498] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516b000, len = 18, expected = 96, status = -121
>[ 6536.243522] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6536.243526] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6536.243707] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6536.243712] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6536.243716] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6536.243718] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6536.243721] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6536.243724] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6536.243726] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6536.243728] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6536.243730] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6536.243733] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6536.243735] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6536.243747] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6536.243752] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6538.291344] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6538.291350] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bb40, len = 18, expected = 96, status = -121
>[ 6538.291372] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6538.291376] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6538.291556] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6538.291560] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6538.291562] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6538.291563] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6538.291565] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6538.291567] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6538.291568] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6538.291570] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6538.291572] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6538.291574] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6538.291576] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6538.291580] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6538.291585] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6538.291589] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6540.339206] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6540.339210] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bb40, len = 18, expected = 96, status = -121
>[ 6540.339234] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6540.339238] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6540.339415] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6540.339417] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6540.339419] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6540.339420] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6540.339421] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6540.339422] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6540.339424] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6540.339425] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6540.339426] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6540.339428] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6540.339429] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6540.339432] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6540.339448] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6540.339451] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6542.387156] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6542.387168] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bb40, len = 18, expected = 96, status = -121
>[ 6542.387214] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6542.387228] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6542.387442] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6542.387456] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6542.387464] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6542.387470] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6542.387477] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6542.387482] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6542.387487] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6542.387491] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6542.387496] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6542.387503] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6542.387508] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6542.387531] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6542.387547] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6542.830293] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6542.830302] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6542.830308] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6542.830314] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6544.434893] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6544.434897] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bc00, len = 18, expected = 96, status = -121
>[ 6544.434921] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6544.434926] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6544.435099] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6544.435103] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6544.435105] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6544.435106] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6544.435107] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6544.435109] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6544.435110] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6544.435111] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6544.435112] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6544.435114] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6544.435115] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6544.435118] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6544.435129] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6544.435131] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6546.482747] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6546.482751] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bc00, len = 18, expected = 96, status = -121
>[ 6546.482775] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6546.482779] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6546.482952] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6546.482954] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6546.482956] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6546.482957] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6546.482958] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6546.482959] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6546.482960] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6546.482962] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6546.482963] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6546.482964] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6546.482966] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6546.482968] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6546.482983] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6546.482985] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6548.530619] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6548.530623] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bc00, len = 18, expected = 96, status = -121
>[ 6548.530647] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6548.530651] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6548.530830] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6548.530833] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6548.530834] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6548.530835] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6548.530836] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6548.530837] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6548.530839] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6548.530840] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6548.530841] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6548.530843] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6548.530844] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6548.530847] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6548.530855] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6548.530856] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6550.578451] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6550.578458] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900a80, len = 18, expected = 96, status = -121
>[ 6550.578487] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6550.578491] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6550.578671] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6550.578679] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6550.578681] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6550.578683] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6550.578684] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6550.578686] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6550.578688] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6550.578690] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6550.578693] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6550.578696] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6550.578698] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6550.578702] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6550.578707] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6550.578710] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6552.626322] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6552.626327] xhci_hcd 0000:00:14.0: Giveback URB ffff8800da900a80, len = 18, expected = 96, status = -121
>[ 6552.626358] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6552.626361] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6552.626527] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6552.626530] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6552.626531] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6552.626533] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6552.626534] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6552.626536] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6552.626538] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6552.626539] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6552.626541] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6552.626543] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6552.626545] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6552.626548] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6552.626563] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6552.626565] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6554.674191] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6554.674196] xhci_hcd 0000:00:14.0: Giveback URB ffff88040516bd80, len = 18, expected = 96, status = -121
>[ 6554.674219] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6554.674224] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6554.674399] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6554.674403] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6554.674405] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6554.674407] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6554.674408] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6554.674409] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6554.674410] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6554.674412] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6554.674413] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6554.674415] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6554.674416] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6554.674419] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6554.674427] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6554.674429] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6556.085948] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6556.085954] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6556.085959] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6556.085964] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6556.722032] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6556.722036] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e780, len = 18, expected = 96, status = -121
>[ 6556.722064] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6556.722069] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6556.722244] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6556.722251] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6556.722253] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6556.722254] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6556.722255] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6556.722257] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6556.722258] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6556.722261] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6556.722263] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6556.722265] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6556.722267] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6556.722270] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6556.722274] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6556.722276] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6558.769883] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6558.769887] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bbea900, len = 18, expected = 96, status = -121
>[ 6558.769920] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6558.769922] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6558.770094] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6558.770096] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6558.770097] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6558.770098] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6558.770099] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6558.770101] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6558.770102] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6558.770103] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6558.770104] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6558.770106] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6558.770108] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6558.770110] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6558.770122] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6558.770124] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6560.817757] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6560.817761] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bbea900, len = 18, expected = 96, status = -121
>[ 6560.817784] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6560.817789] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6560.817963] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6560.817966] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6560.817968] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6560.817970] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6560.817971] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6560.817973] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6560.817974] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6560.817975] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6560.817976] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6560.817978] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6560.817979] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6560.817982] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6560.817992] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6560.817994] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6562.865602] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6562.865607] xhci_hcd 0000:00:14.0: Giveback URB ffff88040789e780, len = 18, expected = 96, status = -121
>[ 6562.865641] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6562.865646] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6562.865814] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6562.865816] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6562.865818] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6562.865820] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6562.865821] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6562.865823] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6562.865825] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6562.865827] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6562.865828] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6562.865831] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6562.865833] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6562.865836] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6562.865849] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6562.865851] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6564.913492] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6564.913496] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bbea480, len = 18, expected = 96, status = -121
>[ 6564.913520] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6564.913524] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6564.913698] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6564.913701] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6564.913702] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6564.913703] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6564.913704] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6564.913705] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6564.913707] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6564.913708] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6564.913709] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6564.913711] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6564.913712] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6564.913715] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6564.913728] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6564.913730] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6565.341869] nouveau E[     DRM] GPU lockup - switching to software fbcon
>[ 6569.341603] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6569.341613] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6569.341620] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6569.341626] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6569.495287] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6573.790131] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6578.084978] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6580.346685] nouveau E[ X[2948]] failed to idle channel 0xcccc0001 [X[2948]]
>[ 6580.347400] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6580.347403] xhci_hcd 0000:00:14.0: Giveback URB ffff880404e89d80, len = 18, expected = 96, status = -121
>[ 6580.347440] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6580.347444] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6580.347620] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6580.347622] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6580.347623] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6580.347624] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6580.347625] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6580.347627] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6580.347628] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6580.347629] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6580.347630] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6580.347632] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6580.347633] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6580.347636] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6580.347653] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6580.347655] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6582.379826] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6582.597259] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6582.597270] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6582.597276] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6582.597282] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6586.674676] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6590.969525] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6595.264374] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6595.345649] nouveau E[ X[2948]] failed to idle channel 0xcccc0001 [X[2948]]
>[ 6595.852916] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6595.852927] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6595.852934] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6595.852941] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6597.348642] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6597.679209] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6597.679220] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ece0c0, len = 18, expected = 96, status = -121
>[ 6597.679246] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6597.679254] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6597.679451] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6597.679456] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6597.679461] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6597.679465] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6597.679469] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6597.679474] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6597.679480] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6597.679485] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6597.679489] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6597.679495] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6597.679500] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6597.679519] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6597.679531] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6599.559228] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6599.727080] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6599.727096] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da3c0, len = 18, expected = 96, status = -121
>[ 6599.727137] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6599.727150] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6599.727343] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6599.727352] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6599.727359] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6599.727365] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6599.727372] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6599.727379] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6599.727384] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6599.727389] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6599.727392] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6599.727404] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6599.727410] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6599.727429] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6599.727437] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6601.774868] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6601.774875] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ecec00, len = 18, expected = 96, status = -121
>[ 6601.774903] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6601.774907] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6601.775100] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6601.775104] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6601.775107] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6601.775109] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6601.775112] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6601.775115] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6601.775118] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6601.775121] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6601.775124] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6601.775128] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6601.775131] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6601.775136] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6601.775143] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6601.775148] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6603.822776] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6603.822783] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ecec00, len = 18, expected = 96, status = -121
>[ 6603.822818] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6603.822823] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6603.822994] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6603.822998] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6603.823001] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6603.823004] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6603.823007] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6603.823010] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6603.823013] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6603.823016] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6603.823019] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6603.823023] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6603.823026] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6603.823030] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6603.823035] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6603.823039] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6603.854081] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6605.870588] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6605.870594] xhci_hcd 0000:00:14.0: Giveback URB ffff880404ecec00, len = 18, expected = 96, status = -121
>[ 6605.870623] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6605.870626] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6605.870810] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6605.870815] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6605.870817] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6605.870819] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6605.870821] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6605.870823] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6605.870825] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6605.870827] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6605.870829] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6605.870832] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6605.870834] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6605.870841] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6605.870845] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6607.918494] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6607.918502] xhci_hcd 0000:00:14.0: Giveback URB ffff880404eceb40, len = 18, expected = 96, status = -121
>[ 6607.918528] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6607.918532] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6607.918726] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6607.918730] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6607.918733] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6607.918735] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6607.918738] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6607.918741] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6607.918744] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6607.918747] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6607.918750] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6607.918754] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6607.918757] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6607.918767] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6607.918774] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6608.148930] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6609.108577] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6609.108587] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6609.108594] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6609.108600] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6609.966332] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6609.966339] xhci_hcd 0000:00:14.0: Giveback URB ffff880404eceb40, len = 18, expected = 96, status = -121
>[ 6609.966367] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6609.966371] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6609.966559] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6609.966562] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6609.966564] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6609.966567] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6609.966569] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6609.966572] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6609.966574] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6609.966577] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6609.966580] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6609.966583] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6609.966586] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6609.966590] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6609.966596] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6609.966601] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6612.014180] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6612.014186] xhci_hcd 0000:00:14.0: Giveback URB ffff880404eceb40, len = 18, expected = 96, status = -121
>[ 6612.014214] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6612.014218] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6612.014402] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6612.014405] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6612.014407] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6612.014410] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6612.014412] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6612.014414] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6612.014417] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6612.014419] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6612.014421] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6612.014425] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6612.014427] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6612.014431] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6612.014440] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6612.014447] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6612.347474] nouveau E[ X[2948]] failed to idle channel 0xcccc0000 [X[2948]]
>[ 6612.443778] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6614.062047] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6614.062051] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db49c540, len = 18, expected = 96, status = -121
>[ 6614.062084] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6614.062087] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6614.062263] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6614.062265] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6614.062266] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6614.062268] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6614.062269] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6614.062271] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6614.062272] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6614.062274] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6614.062275] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6614.062277] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6614.062278] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6614.062282] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6614.062293] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6614.062297] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6616.109941] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6616.109953] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da240, len = 18, expected = 96, status = -121
>[ 6616.109982] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6616.109996] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6616.110211] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6616.110220] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6616.110227] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6616.110233] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6616.110240] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6616.110247] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6616.110255] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6616.110279] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6616.110283] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6616.110291] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6616.110300] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6616.110312] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6616.110318] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6616.738628] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6618.157755] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6618.157761] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da240, len = 18, expected = 96, status = -121
>[ 6618.157790] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6618.157794] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6618.157969] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6618.157973] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6618.157975] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6618.157978] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6618.157981] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6618.157983] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6618.157986] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6618.157989] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6618.157992] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6618.157996] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6618.157998] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6618.158003] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6618.158011] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6618.158017] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6620.205603] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6620.205609] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da240, len = 18, expected = 96, status = -121
>[ 6620.205639] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6620.205643] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6620.205811] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6620.205813] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6620.205816] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6620.205818] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6620.205819] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6620.205822] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6620.205824] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6620.205826] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6620.205828] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6620.205831] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6620.205834] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6620.205837] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6620.205848] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6620.205851] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6621.033481] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6622.253481] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6622.253492] xhci_hcd 0000:00:14.0: Giveback URB ffff88040693f900, len = 18, expected = 96, status = -121
>[ 6622.253518] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6622.253527] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6622.253725] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6622.253731] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6622.253735] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6622.253745] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6622.253748] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6622.253751] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6622.253754] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6622.253757] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6622.253760] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6622.253764] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6622.253767] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6622.253780] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6622.253784] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6622.364234] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6622.364243] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6622.364250] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6622.364256] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6624.301372] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6624.301382] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db49c3c0, len = 18, expected = 96, status = -121
>[ 6624.301419] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6624.301427] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6624.301653] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6624.301659] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6624.301665] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6624.301681] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6624.301684] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6624.301688] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6624.301692] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6624.301695] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6624.301698] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6624.301709] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6624.301713] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6624.301720] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6624.301734] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6624.301742] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6625.328331] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6626.349187] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6626.349192] xhci_hcd 0000:00:14.0: Giveback URB ffff8800db49c3c0, len = 18, expected = 96, status = -121
>[ 6626.349224] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6626.349228] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6626.349406] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6626.349409] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6626.349411] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6626.349413] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6626.349414] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6626.349417] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6626.349419] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6626.349421] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6626.349423] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6626.349426] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6626.349428] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6626.349431] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6626.349441] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6626.349450] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6627.346419] nouveau E[ X[2948]] failed to idle channel 0xcccc0000 [X[2948]]
>[ 6627.346908] nouveau E[   PFIFO][0000:01:00.0] PFIFO: read fault at 0x0000023000 [PAGE_NOT_PRESENT] from (unknown enum 0x00000007)/(unknown enum 0x00000007) on channel 0x027f95f000 [unknown]
>[ 6628.397083] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6628.397094] xhci_hcd 0000:00:14.0: Giveback URB ffff880404eceb40, len = 18, expected = 96, status = -121
>[ 6628.397120] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6628.397129] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6628.397307] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6628.397313] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6628.397318] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6628.397323] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6628.397329] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6628.397334] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6628.397342] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6628.397348] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6628.397353] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6628.397361] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6628.397366] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6628.397389] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6628.397403] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6629.349828] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6629.403300] xhci_hcd 0000:00:14.0: Cancel URB ffff8804034c50c0, dev 14.1, ep 0x81, starting at offset 0x40b69d3a0
>[ 6629.403305] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6629.405216] xhci_hcd 0000:00:14.0: Stopped on Transfer TRB
>[ 6629.405222] xhci_hcd 0000:00:14.0: Removing canceled TD starting at 0x40b69d3a0 (dma).
>[ 6629.405225] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6629.405227] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6629.405229] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6629.405232] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6629.405234] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040bf9ca20 (virtual)
>[ 6629.405236] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x40b69d3b0 (DMA)
>[ 6629.405240] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040bf9ca20 (0x40b69d000 dma), new deq ptr = ffff88040b69d3b0 (0x40b69d3b0 dma), new cycle = 1
>[ 6629.405242] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6629.405249] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @40b69d3b1
>[ 6629.623181] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6630.444954] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6630.444965] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f17300, len = 18, expected = 96, status = -121
>[ 6630.444990] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6630.444998] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6630.445177] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6630.445183] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6630.445188] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6630.445194] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6630.445200] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6630.445206] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6630.445212] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6630.445218] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6630.445223] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6630.445231] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6630.445237] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6630.445255] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6630.445262] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6632.492791] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6632.492803] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f17300, len = 18, expected = 96, status = -121
>[ 6632.492827] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6632.492835] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6632.493015] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6632.493021] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6632.493026] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6632.493031] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6632.493037] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6632.493042] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6632.493048] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6632.493055] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6632.493060] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6632.493068] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6632.493074] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6632.493093] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6632.493100] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6633.918033] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6634.540658] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6634.540668] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f173c0, len = 18, expected = 96, status = -121
>[ 6634.540691] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6634.540699] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6634.540876] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6634.540881] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6634.540887] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6634.540892] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6634.540897] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6634.540902] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6634.540909] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6634.540915] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6634.540920] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6634.540928] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6634.540934] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6634.540951] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6634.540959] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6635.619897] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6635.619911] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6635.619921] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6635.619931] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6636.588512] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6636.588522] xhci_hcd 0000:00:14.0: Giveback URB ffff880403bbf540, len = 18, expected = 96, status = -121
>[ 6636.588545] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6636.588552] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6636.588731] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6636.588737] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6636.588742] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6636.588747] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6636.588752] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6636.588757] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6636.588763] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6636.588770] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6636.588775] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6636.588783] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6636.588789] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6636.588805] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6636.588812] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6638.212885] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6638.636346] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6638.636355] xhci_hcd 0000:00:14.0: Giveback URB ffff880403f17300, len = 18, expected = 96, status = -121
>[ 6638.636384] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6638.636391] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6638.636571] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6638.636577] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6638.636582] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6638.636587] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6638.636592] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6638.636597] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6638.636603] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6638.636609] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6638.636614] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6638.636622] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6638.636628] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6638.636644] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6638.636651] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6640.684230] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6640.684242] xhci_hcd 0000:00:14.0: Giveback URB ffff88040450cf00, len = 18, expected = 96, status = -121
>[ 6640.684266] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6640.684274] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6640.684454] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6640.684460] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6640.684465] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6640.684470] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6640.684476] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6640.684482] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6640.684488] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6640.684494] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6640.684499] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6640.684506] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6640.684512] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6640.684530] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6640.684537] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6642.507737] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6642.732069] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6642.732078] xhci_hcd 0000:00:14.0: Giveback URB ffff88040450cf00, len = 18, expected = 96, status = -121
>[ 6642.732108] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6642.732115] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6642.732297] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6642.732303] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6642.732308] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6642.732313] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6642.732318] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6642.732323] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6642.732329] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6642.732335] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6642.732341] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6642.732349] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6642.732354] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6642.732372] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6642.732378] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6644.443228] nouveau E[kwin[3145]] failed to idle channel 0xcccc0000 [kwin[3145]]
>[ 6644.779940] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6644.779951] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da780, len = 18, expected = 96, status = -121
>[ 6644.779976] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6644.779986] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6644.780166] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6644.780173] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6644.780178] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6644.780184] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6644.780189] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6644.780195] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6644.780202] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6644.780208] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6644.780213] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6644.780221] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6644.780227] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6644.780239] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6644.780248] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6646.802588] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6646.827788] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6646.827798] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da780, len = 18, expected = 96, status = -121
>[ 6646.827824] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6646.827832] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6646.828010] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6646.828017] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6646.828022] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6646.828027] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6646.828033] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6646.828038] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6646.828044] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6646.828049] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6646.828056] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6646.828065] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6646.828070] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6646.828090] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6646.828102] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6648.875553] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6648.875567] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6648.875578] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6648.875588] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6648.875695] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6648.875702] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da780, len = 18, expected = 96, status = -121
>[ 6648.875731] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6648.875738] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6648.875924] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6648.875930] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6648.875936] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6648.875941] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6648.875946] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6648.875952] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6648.875957] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6648.875963] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6648.875968] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6648.875975] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6648.875990] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6648.876006] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6648.876035] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6648.876059] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6650.923492] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6650.923501] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da780, len = 18, expected = 96, status = -121
>[ 6650.923528] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6650.923537] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6650.923714] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6650.923721] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6650.923726] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6650.923731] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6650.923736] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6650.923742] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6650.923747] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6650.923753] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6650.923758] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6650.923766] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6650.923773] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6650.923785] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6650.923794] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6651.097442] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6652.971346] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6652.971356] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da900, len = 18, expected = 96, status = -121
>[ 6652.971382] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6652.971391] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6652.971573] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6652.971579] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6652.971585] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6652.971590] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6652.971595] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6652.971601] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6652.971606] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6652.971612] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6652.971617] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6652.971626] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6652.971632] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6652.971645] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6652.971654] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6655.019202] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6655.019211] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da900, len = 18, expected = 96, status = -121
>[ 6655.019237] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6655.019245] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6655.019423] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6655.019430] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6655.019435] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6655.019440] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6655.019445] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6655.019450] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6655.019456] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6655.019461] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6655.019466] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6655.019474] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6655.019479] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6655.019494] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6655.019502] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6655.392293] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6657.067075] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6657.067084] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da900, len = 18, expected = 96, status = -121
>[ 6657.067112] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6657.067119] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6657.067302] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6657.067307] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6657.067312] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6657.067317] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6657.067323] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6657.067328] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6657.067333] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6657.067340] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6657.067346] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6657.067353] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6657.067359] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6657.067378] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6657.067389] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6659.114939] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6659.114950] xhci_hcd 0000:00:14.0: Giveback URB ffff8804068da900, len = 18, expected = 96, status = -121
>[ 6659.114975] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6659.114985] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6659.115167] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6659.115174] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6659.115179] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6659.115184] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6659.115190] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6659.115195] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6659.115203] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6659.115209] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6659.115214] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6659.115222] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6659.115228] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6659.115250] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6659.115263] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6659.442181] nouveau E[kwin[3145]] failed to idle channel 0xcccc0000 [kwin[3145]]
>[ 6659.687144] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6661.162793] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6661.162802] xhci_hcd 0000:00:14.0: Giveback URB ffff88040990d3c0, len = 18, expected = 96, status = -121
>[ 6661.162831] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6661.162839] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6661.163018] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6661.163024] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6661.163029] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6661.163034] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6661.163039] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6661.163044] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6661.163050] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6661.163057] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6661.163062] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6661.163070] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6661.163075] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6661.163093] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6661.163100] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6661.442352] nouveau E[   PFIFO][0000:01:00.0] channel 4 [kwin[3145]] kick timeout
>[ 6661.445420] nouveau W[   PFIFO][0000:01:00.0] unknown status 0x00000100
>[ 6662.131214] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch 4 [0x027f7e0000 kwin[3145]]
>[ 6662.131228] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6662.131239] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6662.131248] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6663.210656] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6663.210670] xhci_hcd 0000:00:14.0: Giveback URB ffff880408801300, len = 18, expected = 96, status = -121
>[ 6663.210696] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6663.210706] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6663.210886] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6663.210893] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6663.210898] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6663.210903] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6663.210909] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6663.210916] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6663.210922] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6663.210928] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6663.210933] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6663.210940] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6663.210946] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6663.210967] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6663.210984] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6663.445348] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6663.445367] nouveau ![   PFIFO][0000:01:00.0] unhandled status 0x00000001
>[ 6665.258482] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6665.258491] xhci_hcd 0000:00:14.0: Giveback URB ffff880407dbc840, len = 18, expected = 96, status = -121
>[ 6665.258517] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6665.258522] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6665.258700] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6665.258703] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6665.258707] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6665.258710] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6665.258713] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6665.258716] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6665.258720] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6665.258723] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6665.258726] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6665.258731] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6665.258734] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6665.258739] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6665.258747] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6665.258752] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0
>[ 6665.539764] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6667.306353] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6667.306363] xhci_hcd 0000:00:14.0: Giveback URB ffff88040b61ecc0, len = 18, expected = 96, status = -121
>[ 6667.306388] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6667.306394] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6667.306570] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6667.306575] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6667.306579] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6667.306583] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6667.306587] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6667.306592] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6667.306596] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6667.306601] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d410 (DMA)
>[ 6667.306605] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6667.306611] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d410 (0x409a8d410 dma), new cycle = 0
>[ 6667.306616] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6667.306622] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6667.306636] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6667.306641] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d410
>[ 6667.562162] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6669.354163] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6669.354175] xhci_hcd 0000:00:14.0: Giveback URB ffff8800dab91180, len = 18, expected = 96, status = -121
>[ 6669.354198] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6669.354205] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6669.354393] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6669.354400] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6669.354405] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6669.354408] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6669.354410] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6669.354415] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6669.354418] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6669.354421] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d450 (DMA)
>[ 6669.354425] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6669.354431] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d450 (0x409a8d450 dma), new cycle = 0
>[ 6669.354446] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6669.354461] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6669.354468] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d450
>[ 6671.402123] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6671.402133] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f540, len = 18, expected = 96, status = -121
>[ 6671.402169] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6671.402179] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6671.402382] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6671.402392] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6671.402398] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6671.402403] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6671.402408] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6671.402414] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6671.402420] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6671.402427] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d490 (DMA)
>[ 6671.402432] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6671.402441] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d490 (0x409a8d490 dma), new cycle = 0
>[ 6671.402447] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6671.402462] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6671.402471] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d490
>[ 6673.450010] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6673.450022] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f540, len = 18, expected = 96, status = -121
>[ 6673.450069] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6673.450079] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6673.450282] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6673.450294] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6673.450299] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6673.450304] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6673.450308] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6673.450313] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6673.450317] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6673.450322] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4d0 (DMA)
>[ 6673.450326] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6673.450333] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4d0 (0x409a8d4d0 dma), new cycle = 0
>[ 6673.450337] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6673.450354] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6673.450366] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4d0
>[ 6675.386894] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6675.386909] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6675.386918] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6675.386926] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6675.497862] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6675.497874] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f540, len = 18, expected = 96, status = -121
>[ 6675.497919] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6675.497933] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6675.498148] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6675.498161] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6675.498167] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6675.498171] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6675.498175] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6675.498180] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6675.498185] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6675.498190] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d510 (DMA)
>[ 6675.498194] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6675.498200] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d510 (0x409a8d510 dma), new cycle = 0
>[ 6675.498205] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6675.498222] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6675.498228] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d510
>[ 6677.545716] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6677.545728] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f540, len = 18, expected = 96, status = -121
>[ 6677.545772] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6677.545785] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6677.545999] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6677.546009] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6677.546014] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6677.546019] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6677.546023] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6677.546028] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6677.546033] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6677.546037] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d550 (DMA)
>[ 6677.546041] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6677.546049] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d550 (0x409a8d550 dma), new cycle = 0
>[ 6677.546056] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6677.546089] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6677.546097] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d550
>[ 6679.593583] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6679.593596] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f6c0, len = 18, expected = 96, status = -121
>[ 6679.593643] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6679.593656] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6679.593867] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6679.593876] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6679.593883] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6679.593890] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6679.593897] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6679.593905] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6679.593912] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6679.593920] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d590 (DMA)
>[ 6679.593927] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6679.593937] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d590 (0x409a8d590 dma), new cycle = 0
>[ 6679.593945] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6679.593969] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6679.593977] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d590
>[ 6681.641439] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6681.641451] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884f6c0, len = 18, expected = 96, status = -121
>[ 6681.641495] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6681.641508] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6681.641717] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6681.641728] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6681.641734] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6681.641740] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6681.641746] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6681.641754] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6681.641762] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6681.641770] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5d0 (DMA)
>[ 6681.641776] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6681.641787] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5d0 (0x409a8d5d0 dma), new cycle = 0
>[ 6681.641794] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6681.641826] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6681.641837] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5d0
>[ 6682.771581] xhci_hcd 0000:00:14.0: Cancel URB ffff8804034c50c0, dev 14.1, ep 0x81, starting at offset 0x40b69d3b0
>[ 6682.771587] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6682.773558] xhci_hcd 0000:00:14.0: Stopped on Transfer TRB
>[ 6682.773565] xhci_hcd 0000:00:14.0: Removing canceled TD starting at 0x40b69d3b0 (dma).
>[ 6682.773568] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6682.773570] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6682.773572] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6682.773575] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6682.773578] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040bf9ca20 (virtual)
>[ 6682.773580] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x40b69d3c0 (DMA)
>[ 6682.773584] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040bf9ca20 (0x40b69d000 dma), new deq ptr = ffff88040b69d3c0 (0x40b69d3c0 dma), new cycle = 1
>[ 6682.773587] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6682.773595] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @40b69d3c1
>[ 6683.689168] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6683.689171] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6683.689208] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6683.689211] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6683.689379] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6683.689381] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6683.689382] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6683.689396] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6683.689398] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6683.689400] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6683.689401] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6683.689403] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d610 (DMA)
>[ 6683.689414] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6683.689416] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d610 (0x409a8d610 dma), new cycle = 0
>[ 6683.689418] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6683.689420] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6683.689423] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6683.689425] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d610
>[ 6685.737005] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6685.737008] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6685.737044] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6685.737047] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6685.737214] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6685.737216] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6685.737217] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6685.737231] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6685.737233] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6685.737234] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6685.737236] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6685.737238] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d650 (DMA)
>[ 6685.737239] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6685.737251] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d650 (0x409a8d650 dma), new cycle = 0
>[ 6685.737252] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6685.737255] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6685.737260] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6685.737262] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d650
>[ 6687.784854] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6687.784857] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bac69c0, len = 18, expected = 96, status = -121
>[ 6687.784898] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6687.784900] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6687.785068] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6687.785070] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6687.785071] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6687.785072] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6687.785073] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6687.785086] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6687.785087] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6687.785088] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d690 (DMA)
>[ 6687.785089] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6687.785090] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d690 (0x409a8d690 dma), new cycle = 0
>[ 6687.785091] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6687.785094] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6687.785106] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6687.785109] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d690
>[ 6688.642519] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6688.642526] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6688.642532] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6688.642537] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6689.832751] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6689.832754] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5900, len = 18, expected = 96, status = -121
>[ 6689.832788] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6689.832790] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6689.832965] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6689.832967] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6689.832968] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6689.832969] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6689.832970] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6689.832971] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6689.832973] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6689.832974] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6d0 (DMA)
>[ 6689.832975] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6689.832977] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6d0 (0x409a8d6d0 dma), new cycle = 0
>[ 6689.832978] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6689.832981] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6689.833000] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6689.833001] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6d0
>[ 6691.880581] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6691.880584] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5900, len = 18, expected = 96, status = -121
>[ 6691.880620] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6691.880622] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6691.880790] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6691.880792] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6691.880793] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6691.880794] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6691.880795] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6691.880796] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6691.880797] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6691.880799] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d710 (DMA)
>[ 6691.880800] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6691.880801] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d710 (0x409a8d710 dma), new cycle = 0
>[ 6691.880802] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6691.880805] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6691.880824] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6691.880825] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d710
>[ 6693.928434] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6693.928437] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5900, len = 18, expected = 96, status = -121
>[ 6693.928474] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6693.928475] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6693.928644] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6693.928645] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6693.928646] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6693.928648] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6693.928649] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6693.928650] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6693.928651] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6693.928652] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d750 (DMA)
>[ 6693.928653] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6693.928655] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d750 (0x409a8d750 dma), new cycle = 0
>[ 6693.928656] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6693.928659] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6693.928679] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6693.928680] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d750
>[ 6695.976287] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6695.976290] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5540, len = 18, expected = 96, status = -121
>[ 6695.976326] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6695.976328] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6695.976497] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6695.976498] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6695.976499] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6695.976500] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6695.976501] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6695.976503] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6695.976504] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6695.976505] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d790 (DMA)
>[ 6695.976506] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6695.976508] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d790 (0x409a8d790 dma), new cycle = 0
>[ 6695.976509] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6695.976511] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6695.976531] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6695.976533] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d790
>[ 6698.024165] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6698.024168] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5540, len = 18, expected = 96, status = -121
>[ 6698.024204] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6698.024206] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6698.024375] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6698.024376] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6698.024377] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6698.024378] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6698.024379] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6698.024380] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6698.024381] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6698.024383] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7d0 (DMA)
>[ 6698.024384] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6698.024385] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7d0 (0x409a8d7d0 dma), new cycle = 0
>[ 6698.024387] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6698.024389] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6698.024409] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6698.024410] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7d0
>[ 6700.072018] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6700.072021] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5540, len = 18, expected = 96, status = -121
>[ 6700.072056] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6700.072058] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6700.072227] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6700.072228] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6700.072230] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6700.072231] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6700.072232] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6700.072233] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6700.072234] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6700.072235] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d020 (DMA)
>[ 6700.072236] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6700.072238] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d020 (0x409a8d020 dma), new cycle = 1
>[ 6700.072239] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6700.072242] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6700.072261] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6700.072263] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d021
>[ 6701.898185] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6701.898192] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6701.898198] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6701.898203] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6702.119871] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6702.119873] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5540, len = 18, expected = 96, status = -121
>[ 6702.119910] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6702.119913] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6702.120080] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6702.120082] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6702.120083] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6702.120084] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6702.120085] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6702.120086] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6702.120087] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6702.120089] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d060 (DMA)
>[ 6702.120090] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6702.120091] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d060 (0x409a8d060 dma), new cycle = 1
>[ 6702.120093] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6702.120095] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6702.120115] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6702.120117] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d061
>[ 6703.744086] nouveau E[X[22274]] failed to idle channel 0xcccc0001 [X[22274]]
>[ 6704.167804] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6704.167817] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e80c0, len = 18, expected = 96, status = -121
>[ 6704.167843] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6704.167853] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6704.168033] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6704.168040] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6704.168046] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6704.168051] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6704.168057] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6704.168064] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6704.168070] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6704.168076] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0a0 (DMA)
>[ 6704.168081] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6704.168089] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0a0 (0x409a8d0a0 dma), new cycle = 1
>[ 6704.168095] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6704.168115] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6704.168126] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0a1
>[ 6706.215674] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6706.215687] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8600, len = 18, expected = 96, status = -121
>[ 6706.215714] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6706.215724] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6706.215909] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6706.215925] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6706.215931] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6706.215936] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6706.215942] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6706.215947] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6706.215953] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6706.215959] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0e0 (DMA)
>[ 6706.215965] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6706.215973] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0e0 (0x409a8d0e0 dma), new cycle = 1
>[ 6706.215978] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6706.215986] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6706.216000] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6706.216012] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0e1
>[ 6708.263518] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6708.263527] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8600, len = 18, expected = 96, status = -121
>[ 6708.263554] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6708.263562] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6708.263742] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6708.263748] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6708.263753] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6708.263759] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6708.263764] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6708.263769] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6708.263777] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6708.263783] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d120 (DMA)
>[ 6708.263788] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6708.263796] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d120 (0x409a8d120 dma), new cycle = 1
>[ 6708.263802] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6708.263824] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6708.263838] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d121
>[ 6710.311368] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6710.311378] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8600, len = 18, expected = 96, status = -121
>[ 6710.311403] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6710.311411] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6710.311595] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6710.311601] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6710.311607] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6710.311612] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6710.311617] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6710.311623] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6710.311629] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6710.311636] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d160 (DMA)
>[ 6710.311641] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6710.311649] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d160 (0x409a8d160 dma), new cycle = 1
>[ 6710.311655] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6710.311676] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6710.311690] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d161
>[ 6712.359228] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6712.359238] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8600, len = 18, expected = 96, status = -121
>[ 6712.359263] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6712.359272] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6712.359455] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6712.359461] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6712.359467] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6712.359472] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6712.359477] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6712.359482] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6712.359490] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6712.359496] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1a0 (DMA)
>[ 6712.359501] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6712.359509] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1a0 (0x409a8d1a0 dma), new cycle = 1
>[ 6712.359515] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6712.359537] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6712.359551] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1a1
>[ 6714.407104] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6714.407115] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058e8600, len = 18, expected = 96, status = -121
>[ 6714.407140] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6714.407148] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6714.407330] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6714.407337] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6714.407342] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6714.407349] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6714.407354] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6714.407360] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6714.407366] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6714.407371] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1e0 (DMA)
>[ 6714.407377] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6714.407384] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1e0 (0x409a8d1e0 dma), new cycle = 1
>[ 6714.407390] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6714.407411] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6714.407425] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1e1
>[ 6715.153853] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6715.153869] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6715.153880] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6715.153890] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6716.454947] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6716.454958] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1c00, len = 18, expected = 96, status = -121
>[ 6716.454981] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6716.454988] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6716.455166] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6716.455171] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6716.455176] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6716.455180] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6716.455184] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6716.455188] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6716.455193] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6716.455198] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d220 (DMA)
>[ 6716.455204] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6716.455214] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d220 (0x409a8d220 dma), new cycle = 1
>[ 6716.455219] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6716.455237] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6716.455248] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d221
>[ 6718.502804] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6718.502815] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1c00, len = 18, expected = 96, status = -121
>[ 6718.502844] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6718.502857] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6718.503047] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6718.503053] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6718.503058] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6718.503065] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6718.503072] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6718.503077] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6718.503082] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6718.503086] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d260 (DMA)
>[ 6718.503090] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6718.503097] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d260 (0x409a8d260 dma), new cycle = 1
>[ 6718.503101] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6718.503126] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6718.503146] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d261
>[ 6718.743075] nouveau E[X[22274]] failed to idle channel 0xcccc0001 [X[22274]]
>[ 6720.550651] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6720.550661] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1c00, len = 18, expected = 96, status = -121
>[ 6720.550686] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6720.550692] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6720.550869] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6720.550874] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6720.550878] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6720.550882] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6720.550886] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6720.550891] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6720.550895] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6720.550900] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2a0 (DMA)
>[ 6720.550904] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6720.550910] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2a0 (0x409a8d2a0 dma), new cycle = 1
>[ 6720.550916] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6720.550932] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6720.550941] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2a1
>[ 6720.746311] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6722.598507] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6722.598518] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6722.598549] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6722.598565] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6722.598751] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6722.598756] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6722.598760] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6722.598765] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6722.598769] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6722.598776] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6722.598784] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6722.598791] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2e0 (DMA)
>[ 6722.598797] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6722.598804] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2e0 (0x409a8d2e0 dma), new cycle = 1
>[ 6722.598808] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6722.598825] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6722.598839] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2e1
>[ 6724.646362] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6724.646373] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6724.646401] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6724.646412] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6724.646599] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6724.646604] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6724.646609] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6724.646613] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6724.646617] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6724.646622] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6724.646627] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6724.646634] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d320 (DMA)
>[ 6724.646641] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6724.646651] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d320 (0x409a8d320 dma), new cycle = 1
>[ 6724.646657] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6724.646673] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6724.646691] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d321
>[ 6726.694228] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6726.694238] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6726.694268] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6726.694283] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6726.694470] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6726.694476] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6726.694480] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6726.694485] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6726.694491] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6726.694499] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6726.694506] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6726.694512] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d360 (DMA)
>[ 6726.694516] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6726.694523] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d360 (0x409a8d360 dma), new cycle = 1
>[ 6726.694527] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6726.694542] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6726.694561] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d361
>[ 6728.409512] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6728.409528] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6728.409540] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6728.409550] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6728.742084] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6728.742095] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6728.742123] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6728.742135] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6728.742321] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6728.742327] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6728.742331] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6728.742335] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6728.742339] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6728.742345] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6728.742352] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6728.742361] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3a0 (DMA)
>[ 6728.742367] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6728.742374] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3a0 (0x409a8d3a0 dma), new cycle = 1
>[ 6728.742378] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6728.742391] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6728.742405] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3a1
>[ 6730.789935] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6730.789946] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6730.789975] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6730.789987] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6730.790172] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6730.790177] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6730.790182] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6730.790186] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6730.790190] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6730.790194] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6730.790200] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6730.790207] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3e0 (DMA)
>[ 6730.790214] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6730.790224] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3e0 (0x409a8d3e0 dma), new cycle = 1
>[ 6730.790229] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6730.790246] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6730.790256] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3e1
>[ 6732.837773] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6732.837785] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6732.837814] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6732.837826] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6732.838011] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6732.838016] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6732.838020] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6732.838024] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6732.838028] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6732.838033] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6732.838038] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6732.838042] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d430 (DMA)
>[ 6732.838046] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6732.838053] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d430 (0x409a8d430 dma), new cycle = 1
>[ 6732.838058] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6732.838104] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6732.838116] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d431
>[ 6734.885660] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6734.885671] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6734.885702] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6734.885717] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6734.885904] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6734.885910] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6734.885914] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6734.885921] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6734.885928] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6734.885935] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6734.885941] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6734.885946] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d470 (DMA)
>[ 6734.885950] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6734.885957] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d470 (0x409a8d470 dma), new cycle = 1
>[ 6734.885961] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6734.885976] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6734.885995] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d471
>[ 6735.744866] nouveau E[X[22274]] failed to idle channel 0xcccc0000 [X[22274]]
>[ 6736.933508] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6736.933519] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6736.933548] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6736.933559] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6736.933746] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6736.933752] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6736.933756] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6736.933760] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6736.933764] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6736.933769] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6736.933775] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6736.933783] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4b0 (DMA)
>[ 6736.933790] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6736.933799] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4b0 (0x409a8d4b0 dma), new cycle = 1
>[ 6736.933804] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6736.933826] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6736.933843] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4b1
>[ 6738.981349] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6738.981359] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6738.981388] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6738.981398] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6738.981581] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6738.981587] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6738.981591] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6738.981595] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6738.981599] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6738.981604] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6738.981608] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6738.981613] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d4f0 (DMA)
>[ 6738.981617] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6738.981624] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d4f0 (0x409a8d4f0 dma), new cycle = 1
>[ 6738.981628] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6738.981643] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6738.981651] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d4f1
>[ 6741.029233] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6741.029243] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6741.029273] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6741.029286] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6741.029470] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6741.029476] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6741.029480] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6741.029484] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6741.029490] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6741.029497] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6741.029505] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6741.029512] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d530 (DMA)
>[ 6741.029516] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6741.029523] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d530 (0x409a8d530 dma), new cycle = 1
>[ 6741.029528] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6741.029556] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6741.029575] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d531
>[ 6741.665170] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6741.665185] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6741.665196] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6741.665206] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6743.022813] hub 2-14:1.0: state 7 ports 2 chg 0000 evt 0002
>[ 6743.023312] hub 2-14:1.0: port 1, status 0100, change 0001, 12 Mb/s
>[ 6743.023615] usb 2-14.1: USB disconnect, device number 9
>[ 6743.023624] usb 2-14.1: unregistering device
>[ 6743.023629] usb 2-14.1: unregistering interface 2-14.1:1.0
>[ 6743.077090] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6743.077101] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6743.077130] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6743.077141] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6743.077328] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6743.077334] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6743.077338] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6743.077342] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6743.077349] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6743.077356] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6743.077364] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6743.077371] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d570 (DMA)
>[ 6743.077375] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6743.077382] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d570 (0x409a8d570 dma), new cycle = 1
>[ 6743.077387] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6743.077406] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6743.077428] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d571
>[ 6745.124940] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6745.124951] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6745.124977] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6745.124989] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6745.125171] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6745.125176] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6745.125181] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6745.125185] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6745.125189] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6745.125194] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6745.125198] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6745.125204] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5b0 (DMA)
>[ 6745.125211] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6745.125221] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5b0 (0x409a8d5b0 dma), new cycle = 1
>[ 6745.125228] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6745.125245] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6745.125255] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5b1
>[ 6747.172778] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6747.172789] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6747.172818] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6747.172830] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6747.173016] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6747.173021] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6747.173026] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6747.173030] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6747.173034] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6747.173039] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6747.173043] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6747.173048] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d5f0 (DMA)
>[ 6747.173052] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6747.173059] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d5f0 (0x409a8d5f0 dma), new cycle = 1
>[ 6747.173067] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6747.173105] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6747.173119] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d5f1
>[ 6749.220647] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6749.220658] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6749.220686] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6749.220698] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6749.220886] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6749.220892] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6749.220896] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6749.220900] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6749.220904] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6749.220909] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6749.220914] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6749.220921] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d630 (DMA)
>[ 6749.220928] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6749.220938] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d630 (0x409a8d630 dma), new cycle = 1
>[ 6749.220944] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6749.220960] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6749.220971] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d631
>[ 6750.743822] nouveau E[X[22274]] failed to idle channel 0xcccc0000 [X[22274]]
>[ 6751.269485] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6751.269498] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1e40, len = 18, expected = 96, status = -121
>[ 6751.269524] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6751.269534] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6751.269715] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6751.269722] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6751.269727] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6751.269733] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6751.269738] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6751.269744] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6751.269749] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6751.269755] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d670 (DMA)
>[ 6751.269760] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6751.269768] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d670 (0x409a8d670 dma), new cycle = 1
>[ 6751.269773] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6751.269787] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6751.269796] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d671
>[ 6752.746781] nouveau E[   PFIFO][0000:01:00.0] playlist 0 update timeout
>[ 6752.759037] usb 2-14.1: usb_disable_device nuking all URBs
>[ 6752.759052] xhci_hcd 0000:00:14.0: xhci_drop_endpoint called for udev ffff8800dafbe000
>[ 6752.759064] xhci_hcd 0000:00:14.0: drop ep 0x81, slot id 9, new drop flags = 0x8, new add flags = 0x0, new slot info = 0xa200001
>[ 6752.759073] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff8800dafbe000
>[ 6752.759079] xhci_hcd 0000:00:14.0: New Input Control Context:
>[ 6752.759088] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000008 - drop flags
>[ 6752.759096] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000001 - add flags
>[ 6752.759105] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6752.759113] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6752.759121] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6752.759128] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6752.759136] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6752.759144] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6752.759151] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.759159] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6752.759166] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6752.759174] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6752.759182] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6752.759190] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6752.759198] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6752.759206] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6752.759214] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6752.759223] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.759231] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6752.759239] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6752.759248] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6752.759256] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6752.759264] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6752.759272] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6752.759280] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6752.759288] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.759523] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[ 6752.759561] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[ 6752.759569] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[ 6752.759576] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.759586] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0xa200001 - dev_info
>[ 6752.759595] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6752.759603] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6752.759611] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x10000009 - dev_state
>[ 6752.759617] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6752.759622] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6752.759641] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6752.759660] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6752.759690] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.759709] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6752.759729] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6752.759748] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850991 - deq
>[ 6752.759768] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6752.759786] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6752.759802] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6752.759821] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6752.759840] xhci_hcd 0000:00:14.0: Cached old ring, 1 ring cached
>[ 6752.760147] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.865022] hub 2-14:1.0: debounce: port 1: total 100ms stable 100ms status 0x301
>[ 6752.865033] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.865070] xhci_hcd 0000:00:14.0: Slot 10 output ctx = 0x40beaa000 (dma)
>[ 6752.865077] xhci_hcd 0000:00:14.0: Slot 10 input ctx = 0x40b554000 (dma)
>[ 6752.865085] xhci_hcd 0000:00:14.0: Set slot id 10 dcbaa entry ffff88040bed9050 to 0x40beaa000
>[ 6752.926994] usb 2-14.1: new low-speed USB device number 10 using xhci_hcd
>[ 6752.927004] xhci_hcd 0000:00:14.0: Set root hub portnum to 14
>[ 6752.927009] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 14
>[ 6752.927014] xhci_hcd 0000:00:14.0: udev->tt = ffff88040bb6fea0
>[ 6752.927019] xhci_hcd 0000:00:14.0: udev->ttport = 0x1
>[ 6752.927023] xhci_hcd 0000:00:14.0: Slot ID 10 Input Context:
>[ 6752.927029] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6752.927035] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000003 - add flags
>[ 6752.927040] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6752.927045] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6752.927049] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6752.927054] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6752.927059] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6752.927063] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6752.927067] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.927072] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6752.927077] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6752.927081] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6752.927086] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6752.927091] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6752.927096] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6752.927100] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6752.927105] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6752.927110] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.927115] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6752.927120] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6752.927125] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6752.927129] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6752.927134] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6752.927139] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6752.927144] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6752.927149] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6752.927153] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6752.927158] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6752.927162] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6752.927167] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6752.927172] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6752.927176] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6752.927181] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6752.927185] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6752.927190] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x000000 - ep_info
>[ 6752.927194] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x000000 - ep_info2
>[ 6752.927199] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x000000 - deq
>[ 6752.927203] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x000000 - tx_info
>[ 6752.927208] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6752.927212] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6752.927217] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6752.927222] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.927470] xhci_hcd 0000:00:14.0: Successful Address Device command
>[ 6752.927476] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[ 6752.927482] xhci_hcd 0000:00:14.0: Slot ID 10 dcbaa entry @ffff88040bed9050 = 0x0000040beaa000
>[ 6752.927487] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40beaa000
>[ 6752.927491] xhci_hcd 0000:00:14.0: Slot ID 10 Input Context:
>[ 6752.927496] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6752.927500] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000003 - add flags
>[ 6752.927505] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6752.927510] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6752.927514] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6752.927519] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6752.927524] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6752.927528] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6752.927532] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.927537] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6752.927542] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6752.927546] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6752.927551] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6752.927556] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6752.927560] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6752.927565] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6752.927569] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6752.927574] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.927578] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6752.927583] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6752.927588] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6752.927592] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6752.927597] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6752.927602] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6752.927606] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6752.927610] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6752.927615] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6752.927620] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6752.927624] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6752.927629] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6752.927633] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6752.927638] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6752.927642] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6752.927647] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6752.927651] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x000000 - ep_info
>[ 6752.927656] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x000000 - ep_info2
>[ 6752.927670] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x000000 - deq
>[ 6752.927675] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x000000 - tx_info
>[ 6752.927680] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6752.927685] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6752.927689] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6752.927694] xhci_hcd 0000:00:14.0: Slot ID 10 Output Context:
>[ 6752.927697] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.927702] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0xa200001 - dev_info
>[ 6752.927707] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6752.927712] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6752.927716] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x1000000a - dev_state
>[ 6752.927721] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6752.927726] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6752.927731] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6752.927735] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6752.927739] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.927744] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6752.927748] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6752.927753] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850801 - deq
>[ 6752.927757] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6752.927762] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6752.927779] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6752.927792] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6752.927805] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6752.927818] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[ 6752.927831] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x000000 - ep_info2
>[ 6752.927845] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x000000 - deq
>[ 6752.927859] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[ 6752.927872] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[ 6752.927885] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[ 6752.927899] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[ 6752.927912] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6752.927925] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x000000 - ep_info
>[ 6752.927939] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x000000 - ep_info2
>[ 6752.927950] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x000000 - deq
>[ 6752.927962] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x000000 - tx_info
>[ 6752.927973] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[ 6752.927987] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[ 6752.928000] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[ 6752.928005] xhci_hcd 0000:00:14.0: Internal device address = 11
>[ 6752.941212] usb 2-14.1: skipped 1 descriptor after interface
>[ 6752.941485] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6752.941586] usb 2-14.1: default language 0x0409
>[ 6752.942503] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6752.943212] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6752.943313] usb 2-14.1: udev 10, busnum 2, minor = 137
>[ 6752.943325] usb 2-14.1: New USB device found, idVendor=046d, idProduct=c05a
>[ 6752.943333] usb 2-14.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[ 6752.943340] usb 2-14.1: Product: USB Optical Mouse
>[ 6752.943347] usb 2-14.1: Manufacturer: Logitech
>[ 6752.943523] usb 2-14.1: usb_probe_device
>[ 6752.943530] usb 2-14.1: configuration #1 chosen from 1 choice
>[ 6752.943541] usb 2-14.1: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[ 6752.943549] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 10, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x1a200001
>[ 6752.943555] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff8800daa2c000
>[ 6752.943559] xhci_hcd 0000:00:14.0: New Input Control Context:
>[ 6752.943565] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6752.943570] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000009 - add flags
>[ 6752.943575] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6752.943579] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6752.943584] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6752.943589] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6752.943593] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6752.943598] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6752.943602] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.943606] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0x1a200001 - dev_info
>[ 6752.943611] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6752.943616] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6752.943620] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6752.943625] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6752.943630] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6752.943641] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6752.943644] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6752.943648] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.943651] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6752.943654] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6752.943660] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6752.943682] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6752.943687] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6752.943698] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6752.943703] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6752.943707] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6752.943711] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6752.943714] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6752.943718] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6752.943722] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6752.943726] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6752.943730] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6752.943734] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6752.943738] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6752.943742] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x060000 - ep_info
>[ 6752.943746] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x04003e - ep_info2
>[ 6752.943750] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x40b69d401 - deq
>[ 6752.943754] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x040004 - tx_info
>[ 6752.943757] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6752.943761] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6752.943765] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6752.943769] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.944001] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[ 6752.944028] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[ 6752.944035] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[ 6752.944042] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6752.944051] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0x1a200001 - dev_info
>[ 6752.944059] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6752.944067] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6752.944075] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x1800000a - dev_state
>[ 6752.944083] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6752.944091] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6752.944099] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6752.944107] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6752.944115] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6752.944124] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6752.944132] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6752.944140] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850801 - deq
>[ 6752.944149] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6752.944157] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6752.944166] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6752.944174] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6752.944182] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6752.944190] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[ 6752.944198] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x000000 - ep_info2
>[ 6752.944206] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x000000 - deq
>[ 6752.944213] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[ 6752.944221] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[ 6752.944229] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[ 6752.944237] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[ 6752.944244] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6752.944252] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x060001 - ep_info
>[ 6752.944260] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x04003e - ep_info2
>[ 6752.944267] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x40b69d401 - deq
>[ 6752.944275] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x040004 - tx_info
>[ 6752.944283] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[ 6752.944291] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[ 6752.944299] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[ 6752.944310] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[ 6752.944601] usb 2-14.1: adding 2-14.1:1.0 (config #1, interface 0)
>[ 6752.944717] usbhid 2-14.1:1.0: usb_probe_interface
>[ 6752.944723] usbhid 2-14.1:1.0: usb_probe_interface - got id
>[ 6752.944933] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6752.944942] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6752.944949] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6752.944955] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6752.944962] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6752.944969] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6752.944976] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040bf9c700 (virtual)
>[ 6752.944984] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409850990 (DMA)
>[ 6752.944990] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6752.945000] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040bf9c700 (0x409850800 dma), new deq ptr = ffff880409850990 (0x409850990 dma), new cycle = 1
>[ 6752.945008] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6752.945019] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692e540, len = 0, expected = 0, status = -32
>[ 6752.945043] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6752.945049] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409850991
>[ 6752.946751] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb2/2-14/2-14.1/2-14.1:1.0/input/input25
>[ 6752.946939] hid-generic 0003:046D:C05A.0008: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-14.1/input0
>[ 6752.946998] hub 2-14:1.0: state 7 ports 2 chg 0000 evt 0002
>[ 6753.316449] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6753.316461] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884fb40, len = 18, expected = 96, status = -121
>[ 6753.316506] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6753.316519] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6753.316732] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6753.316741] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6753.316746] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6753.316751] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6753.316755] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6753.316760] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6753.316765] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6753.316771] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6b0 (DMA)
>[ 6753.316777] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6753.316785] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6b0 (0x409a8d6b0 dma), new cycle = 1
>[ 6753.316790] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6753.316806] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6753.316813] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6b1
>[ 6754.920850] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6754.920864] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6754.920874] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6754.920882] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6755.364303] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6755.364315] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884fb40, len = 18, expected = 96, status = -121
>[ 6755.364360] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6755.364373] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6755.364584] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6755.364597] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6755.364606] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6755.364613] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6755.364619] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6755.364627] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6755.364634] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6755.364640] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d6f0 (DMA)
>[ 6755.364644] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6755.364651] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d6f0 (0x409a8d6f0 dma), new cycle = 1
>[ 6755.364656] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6755.364673] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6755.364683] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d6f1
>[ 6757.412162] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6757.412174] xhci_hcd 0000:00:14.0: Giveback URB ffff88040884fb40, len = 18, expected = 96, status = -121
>[ 6757.412218] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6757.412232] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6757.412442] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6757.412454] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6757.412462] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6757.412469] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6757.412476] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6757.412483] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6757.412491] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6757.412497] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d730 (DMA)
>[ 6757.412502] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6757.412508] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d730 (0x409a8d730 dma), new cycle = 1
>[ 6757.412513] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6757.412530] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6757.412541] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d731
>[ 6768.176491] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6768.176508] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6768.176519] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6768.176529] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6779.242829] INFO: rcu_sched self-detected stall on CPU { 7}  (t=21000 jiffies g=334584 c=334583 q=2595)
>[ 6779.242843] sending NMI to all CPUs:
>[ 6779.242852] NMI backtrace for cpu 7
>[ 6779.242861] CPU: 7 PID: 22305 Comm: kworker/7:0 Not tainted 3.12.5-gentoo #1
>[ 6779.242866] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.242876] Workqueue: pm pm_runtime_work
>[ 6779.242883] task: ffff880407bfe540 ti: ffff8800da9e8000 task.ti: ffff8800da9e8000
>[ 6779.242889] RIP: 0010:[<ffffffff8127bfba>]  [<ffffffff8127bfba>] delay_tsc+0x24/0x46
>[ 6779.242903] RSP: 0018:ffff88041edc3e50  EFLAGS: 00000097
>[ 6779.242909] RAX: 00000000ffc503c6 RBX: 0000000000002710 RCX: 00000000ffc50353
>[ 6779.242915] RDX: 0000000000000073 RSI: 0000000000000007 RDI: 0000000000323cf6
>[ 6779.242920] RBP: ffff88041edcd7f0 R08: 0000000000000002 R09: 0000000000000000
>[ 6779.242925] R10: 0000000000000000 R11: 000000000000d400 R12: ffffffff819d4100
>[ 6779.242931] R13: ffff88041edccfb8 R14: ffff8800da9e8000 R15: 0000000000000007
>[ 6779.242938] FS:  0000000000000000(0000) GS:ffff88041edc0000(0000) knlGS:0000000000000000
>[ 6779.242943] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.242949] CR2: 00007f9ffc1e2fc0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.242954] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.242960] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.242963] Stack:
>[ 6779.242967]  ffffffff81025095 ffffffff819d4100 ffffffff810d83f6 00000000810b92f3
>[ 6779.242977]  0000000000000a23 0000000000000020 0000000000000007 ffff88041edc3e80
>[ 6779.242985]  ffff880407bfe540 0000000000000000 0000000000000007 ffff88041edccfb8
>[ 6779.242994] Call Trace:
>[ 6779.242998]  <IRQ> 
>
>[ 6779.243012]  [<ffffffff81025095>] ? arch_trigger_all_cpu_backtrace+0x63/0x6e
>[ 6779.243026]  [<ffffffff810d83f6>] ? rcu_check_callbacks+0x1a0/0x4c2
>[ 6779.243038]  [<ffffffff81088336>] ? update_process_times+0x31/0x5c
>[ 6779.243049]  [<ffffffff810bd786>] ? tick_sched_timer+0x30/0x4c
>[ 6779.243062]  [<ffffffff810988b6>] ? __run_hrtimer.isra.25+0x4b/0xa4
>[ 6779.243070]  [<ffffffff81098e60>] ? hrtimer_interrupt+0xd9/0x1d4
>[ 6779.243079]  [<ffffffff81023fd9>] ? smp_apic_timer_interrupt+0x36/0x46
>[ 6779.243089]  [<ffffffff8170a94a>] ? apic_timer_interrupt+0x6a/0x70
>[ 6779.243093]  <EOI> 
>
>[ 6779.243106]  [<ffffffff81281b26>] ? ioread32+0xb/0x2c
>[ 6779.243117]  [<ffffffff813f62d2>] ? nouveau_fence_done+0x36/0x7a
>[ 6779.243126]  [<ffffffff813f629e>] ? nouveau_fence_done+0x2/0x7a
>[ 6779.243136]  [<ffffffff813f6789>] ? nouveau_fence_wait+0xf7/0x12a
>[ 6779.243146]  [<ffffffff813f62d2>] ? nouveau_fence_done+0x36/0x7a
>[ 6779.243158]  [<ffffffff81345317>] ? ttm_bo_wait+0x9d/0x151
>[ 6779.243170]  [<ffffffff813479ce>] ? ttm_bo_move_accel_cleanup+0x8b/0x2e8
>[ 6779.243181]  [<ffffffff813f7f69>] ? nouveau_bo_move_m2mf.isra.21+0xe2/0x116
>[ 6779.243192]  [<ffffffff813f862d>] ? nouveau_bo_move+0x267/0x2f5
>[ 6779.243202]  [<ffffffff813f826d>] ? nouveau_ttm_tt_populate+0x71/0x1ca
>[ 6779.243214]  [<ffffffff813463ce>] ? ttm_bo_handle_move_mem+0x199/0x2db
>[ 6779.243224]  [<ffffffff813f6ec4>] ? nouveau_gart_manager_new+0x1f/0xcb
>[ 6779.243234]  [<ffffffff81346c50>] ? ttm_bo_mem_space+0xf5/0x2a5
>[ 6779.243245]  [<ffffffff813f8700>] ? nouveau_bo_placement_set+0x45/0xfa
>[ 6779.243255]  [<ffffffff813466af>] ? ttm_bo_evict+0x19f/0x2a8
>[ 6779.243266]  [<ffffffff813468b5>] ? ttm_mem_evict_first+0xfd/0x166
>[ 6779.243277]  [<ffffffff81346978>] ? ttm_bo_force_list_clean+0x5a/0x9d
>[ 6779.243287]  [<ffffffff813f3e95>] ? nouveau_do_suspend+0x91/0x23b
>[ 6779.243297]  [<ffffffff813f4070>] ? nouveau_pmops_runtime_suspend+0x31/0x6b
>[ 6779.243306]  [<ffffffff8129a4a4>] ? pci_pm_runtime_suspend+0x60/0x119
>[ 6779.243318]  [<ffffffff8142f632>] ? __rpm_callback+0x28/0x4c
>[ 6779.243328]  [<ffffffff8142f6a1>] ? rpm_callback+0x4b/0x69
>[ 6779.243339]  [<ffffffff8142fc4d>] ? rpm_suspend+0x2a9/0x3f9
>[ 6779.243349]  [<ffffffff8158eb39>] ? cs_dbs_timer+0xb3/0xcb
>[ 6779.243357]  [<ffffffff814308f5>] ? pm_runtime_work+0x65/0x7b
>[ 6779.243368]  [<ffffffff810914cd>] ? process_one_work+0x1c5/0x2e4
>[ 6779.243379]  [<ffffffff81091a2b>] ? worker_thread+0x1c7/0x2bc
>[ 6779.243389]  [<ffffffff81091864>] ? rescuer_thread+0x253/0x253
>[ 6779.243399]  [<ffffffff8109653a>] ? kthread+0xad/0xb5
>[ 6779.243409]  [<ffffffff8109648d>] ? kthread_freezable_should_stop+0x40/0x40
>[ 6779.243417]  [<ffffffff81709d7c>] ? ret_from_fork+0x7c/0xb0
>[ 6779.243427]  [<ffffffff8109648d>] ? kthread_freezable_should_stop+0x40/0x40
>[ 6779.243432] Code: 7a 01 e9 93 ff ff ff 65 8b 34 25 1c b0 00 00 0f 1f 00 0f ae e8 0f 31 89 c1 0f 1f 00 0f ae e8 0f 31 89 c2 29 ca 39 fa 73 23 f3 90 <65> 44 8b 04 25 1c b0 00 00 44 39 c6 74 e0 29 c1 01 cf 0f 1f 00 
>[ 6779.243526] NMI backtrace for cpu 5
>[ 6779.243539] CPU: 5 PID: 0 Comm: swapper/5 Not tainted 3.12.5-gentoo #1
>[ 6779.243545] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.243551] task: ffff88040c4dd7c0 ti: ffff88040c514000 task.ti: ffff88040c514000
>[ 6779.243557] RIP: 0010:[<ffffffff8170a8e0>]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.243571] RSP: 0018:ffff88040c515e68  EFLAGS: 00000012
>[ 6779.243577] RAX: 0000062a84e57906 RBX: ffff88041ed57150 RCX: 0000000000000018
>[ 6779.243583] RDX: 0000000225c17d03 RSI: ffff88040c515fd8 RDI: 00000000000efadc
>[ 6779.243588] RBP: 0000000000000005 R08: 00000000000003cf R09: 0000000000000008
>[ 6779.243594] R10: ffff88041ed4d6a0 R11: 0000000000011640 R12: 0000062a84d67e2a
>[ 6779.243599] R13: ffff88040c515fd8 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.243606] FS:  0000000000000000(0000) GS:ffff88041ed40000(0000) knlGS:0000000000000000
>[ 6779.243612] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.243618] CR2: 00007f9ffc1e2fc0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.243623] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.243628] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.243632] Stack:
>[ 6779.243636]  ffffffff81590829 0000000000000010 0000000000000212 ffff88040c515e98
>[ 6779.243646]  0000000000000018 ffffffff81590822 0000000000000005 ffffffff819ee5b0
>[ 6779.243654]  0000000000000000 ffff88041ed57150 ffffffff819ee5b0 ffff88040c515fd8
>[ 6779.243663] Call Trace:
>[ 6779.243675]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.243685]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.243695]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.243708]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.243720]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.243725] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.243819] NMI backtrace for cpu 6
>[ 6779.243831] CPU: 6 PID: 0 Comm: swapper/6 Not tainted 3.12.5-gentoo #1
>[ 6779.243837] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.243844] task: ffff88040c4dde80 ti: ffff88040c516000 task.ti: ffff88040c516000
>[ 6779.243850] RIP: 0010:[<ffffffff8170a8e0>]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.243863] RSP: 0018:ffff88040c517e68  EFLAGS: 00000002
>[ 6779.243869] RAX: 0000062a84e578fc RBX: ffff88041ed97150 RCX: 0000000000000018
>[ 6779.243875] RDX: 0000000225c17d03 RSI: ffff88040c517fd8 RDI: 000000000009b429
>[ 6779.243881] RBP: 0000000000000005 R08: 00000000000003c9 R09: 0000000000000008
>[ 6779.243886] R10: 000000000000b800 R11: 0000000000011640 R12: 0000062a84dbc4d3
>[ 6779.243892] R13: ffff88040c517fd8 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.243898] FS:  0000000000000000(0000) GS:ffff88041ed80000(0000) knlGS:0000000000000000
>[ 6779.243904] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.243910] CR2: 00007f9ffc1e2fc0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.243915] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.243920] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.243924] Stack:
>[ 6779.243928]  ffffffff81590829 0000000000000010 0000000000000202 ffff88040c517e98
>[ 6779.243937]  0000000000000018 ffffffff81590822 0000000000000005 ffffffff819ee5b0
>[ 6779.243946]  0000000000000000 ffff88041ed97150 ffffffff819ee5b0 ffff88040c517fd8
>[ 6779.243954] Call Trace:
>[ 6779.243966]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.243976]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.243985]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.243997]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.244008]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.244013] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.244107] NMI backtrace for cpu 4
>[ 6779.244115] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 1.253 msecs
>[ 6779.244130] CPU: 4 PID: 0 Comm: swapper/4 Not tainted 3.12.5-gentoo #1
>[ 6779.244135] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.244142] task: ffff88040c4dd100 ti: ffff88040c512000 task.ti: ffff88040c512000
>[ 6779.244147] RIP: 0010:[<ffffffff8170a8e0>]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.244161] RSP: 0018:ffff88040c513e68  EFLAGS: 00000012
>[ 6779.244167] RAX: 0000062a84e57901 RBX: ffff88041ed17150 RCX: 0000000000000018
>[ 6779.244173] RDX: 0000000225c17d03 RSI: ffff88040c513fd8 RDI: 00000000000eebab
>[ 6779.244178] RBP: 0000000000000005 R08: 00000000000003d0 R09: 0000000000000008
>[ 6779.244195] R10: ffff88041ed0d6a0 R11: 0000000000011640 R12: 0000062a84d68d56
>[ 6779.244215] R13: ffff88040c513fd8 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.244237] FS:  0000000000000000(0000) GS:ffff88041ed00000(0000) knlGS:0000000000000000
>[ 6779.244259] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.244280] CR2: 00007f9ffc1e2fc0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.244298] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.244319] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.244335] Stack:
>[ 6779.244354]  ffffffff81590829 0000000000000010 0000000000000212 ffff88040c513e98
>[ 6779.244424]  0000000000000018 ffffffff81590822 0000000000000005 ffffffff819ee5b0
>[ 6779.244493]  0000000000000000 ffff88041ed17150 ffffffff819ee5b0 ffff88040c513fd8
>[ 6779.244563] Call Trace:
>[ 6779.244595]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.244605]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.244615]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.244626]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.244636]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.244641] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.244736] NMI backtrace for cpu 1
>[ 6779.244743] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 1.882 msecs
>[ 6779.244757] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.5-gentoo #1
>[ 6779.244762] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.244768] task: ffff88040c4dbcc0 ti: ffff88040c50c000 task.ti: ffff88040c50c000
>[ 6779.244773] RIP: 0010:[<ffffffff8170a8e0>]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.244786] RSP: 0018:ffff88040c50de68  EFLAGS: 00000012
>[ 6779.244790] RAX: 0000062a84e578fc RBX: ffff88041ec57150 RCX: 0000000000000018
>[ 6779.244793] RDX: 0000000225c17d03 RSI: ffff88040c50dfd8 RDI: 00000000000efacd
>[ 6779.244796] RBP: 0000000000000005 R08: 00000000000003ce R09: 0000000000000008
>[ 6779.244800] R10: ffff88041ec4d6a0 R11: 0000000000011640 R12: 0000062a84d67e2f
>[ 6779.244803] R13: ffff88040c50dfd8 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.244807] FS:  0000000000000000(0000) GS:ffff88041ec40000(0000) knlGS:0000000000000000
>[ 6779.244810] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.244814] CR2: 00007f9f70872018 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.244817] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.244820] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.244822] Stack:
>[ 6779.244826]  ffffffff81590829 0000000000000010 0000000000000212 ffff88040c50de98
>[ 6779.244834]  0000000000000018 ffffffff81590822 0000000000000005 ffffffff819ee5b0
>[ 6779.244842]  0000000000000000 ffff88041ec57150 ffffffff819ee5b0 ffff88040c50dfd8
>[ 6779.244848] Call Trace:
>[ 6779.244855]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.244862]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.244869]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.244877]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.244885]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.244890] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.244959] NMI backtrace for cpu 3
>[ 6779.244965] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 2.105 msecs
>[ 6779.244977] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.5-gentoo #1
>[ 6779.244982] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.244988] task: ffff88040c4dca40 ti: ffff88040c510000 task.ti: ffff88040c510000
>[ 6779.244993] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6779.245018] RSP: 0018:ffff88040c511e58  EFLAGS: 00000046
>[ 6779.245021] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6779.245023] RDX: 0000000000000000 RSI: ffff88040c511fd8 RDI: 0000000000000003
>[ 6779.245026] RBP: 0000000000000005 R08: 0000000000000316 R09: 0000000000000005
>[ 6779.245029] R10: ffff88041eccd6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6779.245031] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.245035] FS:  0000000000000000(0000) GS:ffff88041ecc0000(0000) knlGS:0000000000000000
>[ 6779.245038] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.245041] CR2: 00007f532036b3b0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.245043] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.245046] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.245047] Stack:
>[ 6779.245048]  0000000000000000
>[ 6779.245050]  00000003000f2af5
>[ 6779.245051]  ffffffff81590829
>[ 6779.245052]  ffff88041ecd7150
>
>[ 6779.245055]  ffffffff819ee780
>[ 6779.245056]  0000062a84e53dd3
>[ 6779.245058]  ffff88040c511fd8
>[ 6779.245059]  ffffffff8159081b
>
>[ 6779.245061]  0000000000000005
>[ 6779.245062]  ffffffff819ee5b0
>[ 6779.245063]  0000000000000000
>[ 6779.245065]  ffff88041ecd7150
>
>[ 6779.245067] Call Trace:
>
>[ 6779.245075]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>
>[ 6779.245081]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>
>[ 6779.245088]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>
>[ 6779.245096]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>
>[ 6779.245104]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.245106] Code: 
>[ 6779.245108] 86 
>[ 6779.245109] 38 
>[ 6779.245110] e0 
>[ 6779.245111] ff 
>[ 6779.245113] ff 
>[ 6779.245114] a8 
>[ 6779.245115] 08 
>[ 6779.245116] 75 
>[ 6779.245117] 22 
>[ 6779.245118] 48 
>[ 6779.245120] 8d 
>[ 6779.245121] 41 
>[ 6779.245122] 10 
>[ 6779.245123] 31 
>[ 6779.245124] d2 
>[ 6779.245125] 48 
>[ 6779.245126] 89 
>[ 6779.245128] d1 
>[ 6779.245129] 0f 
>[ 6779.245130] 01 
>[ 6779.245131] c8 
>[ 6779.245132] 0f 
>[ 6779.245133] ae 
>[ 6779.245135] f0 
>[ 6779.245136] 48 
>[ 6779.245137] 8b 
>[ 6779.245138] 86 
>[ 6779.245139] 38 
>[ 6779.245140] e0 
>[ 6779.245141] ff 
>[ 6779.245143] ff 
>[ 6779.245144] a8 
>[ 6779.245145] 08 
>[ 6779.245146] 75 
>[ 6779.245147] 08 
>[ 6779.245148] b1 
>[ 6779.245149] 01 
>[ 6779.245151] 4c 
>[ 6779.245152] 89 
>[ 6779.245153] e0 
>[ 6779.245154] 0f 
>[ 6779.245155] 01 
>[ 6779.245156] c9 
>[ 6779.245158] <85> 
>[ 6779.245159] 1d 
>[ 6779.245160] 7d 
>[ 6779.245161] ae 
>[ 6779.245162] 70 
>[ 6779.245164] 00 
>[ 6779.245165] 75 
>[ 6779.245166] 0f 
>[ 6779.245167] 48 
>[ 6779.245168] 8d 
>[ 6779.245169] 74 
>[ 6779.245170] 24 
>[ 6779.245172] 0c 
>[ 6779.245173] bf 
>[ 6779.245174] 05 
>[ 6779.245175] 00 
>[ 6779.245176] 00 
>[ 6779.245177] 00 
>[ 6779.245178] e8 
>[ 6779.245180] 70 
>[ 6779.245181] 7e 
>
>[ 6779.245185] NMI backtrace for cpu 2
>[ 6779.245192] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 2.331 msecs
>[ 6779.245196] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 3.12.5-gentoo #1
>[ 6779.245198] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.245200] task: ffff88040c4dc380 ti: ffff88040c50e000 task.ti: ffff88040c50e000
>[ 6779.245203] RIP: 0010:[<ffffffff8170a8e0>] 
>[ 6779.245208]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.245210] RSP: 0018:ffff88040c50fe68  EFLAGS: 00000002
>[ 6779.245212] RAX: 0000062a84e578f7 RBX: ffff88041ec97150 RCX: 0000000000000018
>[ 6779.245214] RDX: 0000000225c17d03 RSI: ffff88040c50ffd8 RDI: 000000000009b383
>[ 6779.245216] RBP: 0000000000000004 R08: 0000000000000360 R09: 0000000000000006
>[ 6779.245218] R10: ffff88041ec8d6a0 R11: 0000000000011640 R12: 0000062a84dbc574
>[ 6779.245219] R13: ffff88040c50ffd8 R14: 0000000000000000 R15: 0000000000000000
>[ 6779.245222] FS:  0000000000000000(0000) GS:ffff88041ec80000(0000) knlGS:0000000000000000
>[ 6779.245224] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.245226] CR2: 00007f18705f7000 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6779.245228] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.245229] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.245230] Stack:
>[ 6779.245232]  ffffffff81590829
>[ 6779.245243]  0000000000000010 0000000000000202 ffff88040c50fe98
>[ 6779.245260]  0000000000000018 ffffffff81590822 0000000000000004 ffffffff819ee5b0
>[ 6779.245275]  0000000000000000 ffff88041ec97150 ffffffff819ee5b0 ffff88040c50ffd8
>[ 6779.245278] Call Trace:
>[ 6779.245286]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.245294]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.245301]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.245310]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.245319]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.245439] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.245442] NMI backtrace for cpu 0
>[ 6779.245448] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 2.589 msecs
>[ 6779.245453] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.5-gentoo #1
>[ 6779.245456] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6779.245459] task: ffffffff819a8440 ti: ffffffff81998000 task.ti: ffffffff81998000
>[ 6779.245468] RIP: 0010:[<ffffffff8170a8e0>]  [<ffffffff8170a8e0>] reboot_interrupt+0x70/0x70
>[ 6779.245472] RSP: 0018:ffffffff81999eb8  EFLAGS: 00000012
>[ 6779.245475] RAX: 0000062a84e578f7 RBX: ffff88041ec17150 RCX: 0000000000000018
>[ 6779.245478] RDX: 0000000225c17d03 RSI: ffffffff81999fd8 RDI: 00000000000efb0e
>[ 6779.245481] RBP: 0000000000000005 R08: 00000000000003cf R09: 0000000000000008
>[ 6779.245484] R10: ffff88041ec0d6a0 R11: 0000000000011640 R12: 0000062a84d67de9
>[ 6779.245487] R13: ffffffff81999fd8 R14: 0000000000000001 R15: 00000000c800dc38
>[ 6779.245490] FS:  0000000000000000(0000) GS:ffff88041ec00000(0000) knlGS:0000000000000000
>[ 6779.245495] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6779.245499] CR2: 00007f9ffcba7bdc CR3: 00000000029a3000 CR4: 00000000001407f0
>[ 6779.245504] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6779.245508] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6779.245511] Stack:
>[ 6779.245526]  ffffffff81590829 0000000000000010 0000000000000212 ffffffff81999ee8
>[ 6779.245543]  0000000000000018 ffffffff81590822 0000000000000005 ffffffff819ee5b0
>[ 6779.245558]  0000000000000000 ffff88041ec17150 ffffffff819ee5b0 ffffffff81999fd8
>[ 6779.245561] Call Trace:
>[ 6779.245571]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6779.245580]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6779.245589]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6779.245600]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6779.245610]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6779.245620]  [<ffffffff81a65c60>] ? start_kernel+0x36e/0x379
>[ 6779.245630]  [<ffffffff81a65708>] ? repair_env_string+0x57/0x57
>[ 6779.245633] Code: e0 f7 46 68 03 00 00 00 74 03 0f 01 f8 65 ff 04 25 50 b8 00 00 65 48 0f 44 24 25 58 b8 00 00 56 e8 48 79 91 ff e9 8b ee ff ff 90 <0f> 1f 00 68 10 ff ff ff 48 83 ec 58 fc 48 89 7c 24 50 48 89 74 
>[ 6779.245765] INFO: NMI handler (arch_trigger_all_cpu_backtrace_handler) took too long to run: 2.909 msecs
>[ 6781.432149] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6781.432164] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6781.432175] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6781.432185] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6794.687808] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6794.687825] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6794.687836] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6794.687846] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6807.943466] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6807.943482] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6807.943493] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6807.943503] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6813.162010] hub 2-14:1.0: state 7 ports 2 chg 0000 evt 0002
>[ 6813.162525] hub 2-14:1.0: port 1, status 0100, change 0001, 12 Mb/s
>[ 6813.162819] usb 2-14.1: USB disconnect, device number 10
>[ 6813.162826] usb 2-14.1: unregistering device
>[ 6813.162832] usb 2-14.1: unregistering interface 2-14.1:1.0
>[ 6821.199125] nouveau E[  PGRAPH][0000:01:00.0] TRAP ch -1 [0x027f7e0000 unknown]
>[ 6821.199141] nouveau E[  PGRAPH][0000:01:00.0] ROP0 0x80000000 0x80000001
>[ 6821.199153] nouveau E[  PGRAPH][0000:01:00.0] ROP1 0x80000000 0x80000001
>[ 6821.199163] nouveau E[  PGRAPH][0000:01:00.0] ROP2 0x80000000 0x80000001
>[ 6824.242693] INFO: rcu_sched self-detected stall on CPU { 7}  (t=21000 jiffies g=334586 c=334585 q=228)
>[ 6824.242706] sending NMI to all CPUs:
>[ 6824.242714] NMI backtrace for cpu 7
>[ 6824.242723] CPU: 7 PID: 22305 Comm: kworker/7:0 Not tainted 3.12.5-gentoo #1
>[ 6824.242728] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.242738] Workqueue: pm pm_runtime_work
>[ 6824.242745] task: ffff880407bfe540 ti: ffff8800da9e8000 task.ti: ffff8800da9e8000
>[ 6824.242750] RIP: 0010:[<ffffffff8127bfae>]  [<ffffffff8127bfae>] delay_tsc+0x18/0x46
>[ 6824.242764] RSP: 0018:ffff88041edc3e50  EFLAGS: 00000046
>[ 6824.242770] RAX: 000000007f323333 RBX: 0000000000002710 RCX: 000000007f3232af
>[ 6824.242775] RDX: 0000000000000084 RSI: 0000000000000007 RDI: 0000000000323cf6
>[ 6824.242781] RBP: ffff88041edcd7f0 R08: 0000000000000007 R09: 0000000000000000
>[ 6824.242786] R10: 0000000000000000 R11: 000000000000d500 R12: ffffffff819d4100
>[ 6824.242792] R13: ffff88041edccfb8 R14: ffff8800da9e8000 R15: 0000000000000007
>[ 6824.242799] FS:  0000000000000000(0000) GS:ffff88041edc0000(0000) knlGS:0000000000000000
>[ 6824.242804] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.242810] CR2: 00007f9ffc1e2fc0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.242815] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.242821] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.242824] Stack:
>[ 6824.242829]  ffffffff81025095 ffffffff819d4100 ffffffff810d83f6 00000001810b92f3
>[ 6824.242838]  00000000000000e4 0000000000000020 0000000000000007 ffff88041edc3e80
>[ 6824.242846]  ffff880407bfe540 0000000000000000 0000000000000007 ffff88041edccfb8
>[ 6824.242855] Call Trace:
>[ 6824.242859]  <IRQ> 
>
>[ 6824.242873]  [<ffffffff81025095>] ? arch_trigger_all_cpu_backtrace+0x63/0x6e
>[ 6824.242886]  [<ffffffff810d83f6>] ? rcu_check_callbacks+0x1a0/0x4c2
>[ 6824.242898]  [<ffffffff81088336>] ? update_process_times+0x31/0x5c
>[ 6824.242908]  [<ffffffff810bd786>] ? tick_sched_timer+0x30/0x4c
>[ 6824.242921]  [<ffffffff810988b6>] ? __run_hrtimer.isra.25+0x4b/0xa4
>[ 6824.242930]  [<ffffffff81098e60>] ? hrtimer_interrupt+0xd9/0x1d4
>[ 6824.242939]  [<ffffffff81023fd9>] ? smp_apic_timer_interrupt+0x36/0x46
>[ 6824.242949]  [<ffffffff8170a94a>] ? apic_timer_interrupt+0x6a/0x70
>[ 6824.242953]  <EOI> 
>
>[ 6824.242967]  [<ffffffff813466af>] ? ttm_bo_evict+0x19f/0x2a8
>[ 6824.242977]  [<ffffffff81281b26>] ? ioread32+0xb/0x2c
>[ 6824.242988]  [<ffffffff813f62d2>] ? nouveau_fence_done+0x36/0x7a
>[ 6824.242998]  [<ffffffff813f672d>] ? nouveau_fence_wait+0x9b/0x12a
>[ 6824.243008]  [<ffffffff813f6789>] ? nouveau_fence_wait+0xf7/0x12a
>[ 6824.243018]  [<ffffffff813f698f>] ? nouveau_fence_new+0x55/0x8e
>[ 6824.243028]  [<ffffffff813f513b>] ? nouveau_channel_idle+0x37/0x78
>[ 6824.243037]  [<ffffffff813f3edc>] ? nouveau_do_suspend+0xd8/0x23b
>[ 6824.243047]  [<ffffffff813f4070>] ? nouveau_pmops_runtime_suspend+0x31/0x6b
>[ 6824.243057]  [<ffffffff8129a4a4>] ? pci_pm_runtime_suspend+0x60/0x119
>[ 6824.243069]  [<ffffffff8142f632>] ? __rpm_callback+0x28/0x4c
>[ 6824.243079]  [<ffffffff8142f6a1>] ? rpm_callback+0x4b/0x69
>[ 6824.243089]  [<ffffffff8142fc4d>] ? rpm_suspend+0x2a9/0x3f9
>[ 6824.243100]  [<ffffffff8158eb39>] ? cs_dbs_timer+0xb3/0xcb
>[ 6824.243108]  [<ffffffff814308f5>] ? pm_runtime_work+0x65/0x7b
>[ 6824.243119]  [<ffffffff810914cd>] ? process_one_work+0x1c5/0x2e4
>[ 6824.243129]  [<ffffffff81091a2b>] ? worker_thread+0x1c7/0x2bc
>[ 6824.243140]  [<ffffffff81091864>] ? rescuer_thread+0x253/0x253
>[ 6824.243150]  [<ffffffff8109653a>] ? kthread+0xad/0xb5
>[ 6824.243160]  [<ffffffff8109648d>] ? kthread_freezable_should_stop+0x40/0x40
>[ 6824.243169]  [<ffffffff81709d7c>] ? ret_from_fork+0x7c/0xb0
>[ 6824.243179]  [<ffffffff8109648d>] ? kthread_freezable_should_stop+0x40/0x40
>[ 6824.243183] Code: 00 48 69 d2 fa 00 00 00 f7 e2 48 8d 7a 01 e9 93 ff ff ff 65 8b 34 25 1c b0 00 00 0f 1f 00 0f ae e8 0f 31 89 c1 0f 1f 00 0f ae e8 <0f> 31 89 c2 29 ca 39 fa 73 23 f3 90 65 44 8b 04 25 1c b0 00 00 
>[ 6824.243275] NMI backtrace for cpu 3
>[ 6824.243285] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.5-gentoo #1
>[ 6824.243289] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.243295] task: ffff88040c4dca40 ti: ffff88040c510000 task.ti: ffff88040c510000
>[ 6824.243300] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.243314] RSP: 0018:ffff88040c511e58  EFLAGS: 00000046
>[ 6824.243319] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.243324] RDX: 0000000000000000 RSI: ffff88040c511fd8 RDI: 0000000000000003
>[ 6824.243329] RBP: 0000000000000005 R08: 00000000000003e1 R09: 0000000000000008
>[ 6824.243334] R10: ffff88041eccd6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.243339] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.243345] FS:  0000000000000000(0000) GS:ffff88041ecc0000(0000) knlGS:0000000000000000
>[ 6824.243351] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.243356] CR2: 00007f532036b3b0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.243361] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.243366] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.243369] Stack:
>[ 6824.243373]  0000000000000000 00000003000f2d04 ffffffff81590829 ffff88041ecd7150
>[ 6824.243381]  ffffffff819ee780 00000634ff488062 ffff88040c511fd8 ffffffff8159081b
>[ 6824.243389]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ecd7150
>[ 6824.243397] Call Trace:
>[ 6824.243408]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.243416]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.243425]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.243437]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.243448]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.243453] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.243541] NMI backtrace for cpu 5
>[ 6824.243553] CPU: 5 PID: 0 Comm: swapper/5 Not tainted 3.12.5-gentoo #1
>[ 6824.243559] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.243566] task: ffff88040c4dd7c0 ti: ffff88040c514000 task.ti: ffff88040c514000
>[ 6824.243571] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.243587] RSP: 0018:ffff88040c515e58  EFLAGS: 00000046
>[ 6824.243593] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.243599] RDX: 0000000000000000 RSI: ffff88040c515fd8 RDI: 0000000000000005
>[ 6824.243604] RBP: 0000000000000005 R08: 00000000000003c9 R09: 0000000000000008
>[ 6824.243610] R10: ffff88041ed4d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.243615] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.243622] FS:  0000000000000000(0000) GS:ffff88041ed40000(0000) knlGS:0000000000000000
>[ 6824.243628] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.243634] CR2: 00007f186e1d1e7c CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.243639] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.243644] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.243648] Stack:
>[ 6824.243652]  0000000000000000 00000005000eb0d8 ffffffff81590829 ffff88041ed57150
>[ 6824.243661]  ffffffff819ee780 00000634ff39c96b ffff88040c515fd8 ffffffff8159081b
>[ 6824.243670]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ed57150
>[ 6824.243678] Call Trace:
>[ 6824.243691]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.243700]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.243711]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.243723]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.243733]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.243738] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.243832] NMI backtrace for cpu 6
>[ 6824.243844] CPU: 6 PID: 0 Comm: swapper/6 Not tainted 3.12.5-gentoo #1
>[ 6824.243850] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.243857] task: ffff88040c4dde80 ti: ffff88040c516000 task.ti: ffff88040c516000
>[ 6824.243862] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.243877] RSP: 0018:ffff88040c517e58  EFLAGS: 00000046
>[ 6824.243883] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.243889] RDX: 0000000000000000 RSI: ffff88040c517fd8 RDI: 0000000000000006
>[ 6824.243894] RBP: 0000000000000005 R08: 00000000000003cc R09: 0000000000000008
>[ 6824.243899] R10: ffff88041ed8d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.243904] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.243911] FS:  0000000000000000(0000) GS:ffff88041ed80000(0000) knlGS:0000000000000000
>[ 6824.243918] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.243923] CR2: 00007f1e9b3983b0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.243928] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.243933] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.243937] Stack:
>[ 6824.243941]  0000000000000000 00000006000e959d ffffffff81590829 ffff88041ed97150
>[ 6824.243951]  ffffffff819ee780 00000634ff39e388 ffff88040c517fd8 ffffffff8159081b
>[ 6824.243959]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ed97150
>[ 6824.243968] Call Trace:
>[ 6824.243980]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.243989]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.243999]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.244011]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.244021]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.244026] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.244120] NMI backtrace for cpu 4
>[ 6824.244132] CPU: 4 PID: 0 Comm: swapper/4 Not tainted 3.12.5-gentoo #1
>[ 6824.244138] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.244145] task: ffff88040c4dd100 ti: ffff88040c512000 task.ti: ffff88040c512000
>[ 6824.244150] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.244165] RSP: 0018:ffff88040c513e58  EFLAGS: 00000046
>[ 6824.244171] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.244176] RDX: 0000000000000000 RSI: ffff88040c513fd8 RDI: 0000000000000004
>[ 6824.244182] RBP: 0000000000000005 R08: 00000000000003d0 R09: 0000000000000008
>[ 6824.244187] R10: ffff88041ed0d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.244192] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.244199] FS:  0000000000000000(0000) GS:ffff88041ed00000(0000) knlGS:0000000000000000
>[ 6824.244204] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.244210] CR2: 00007fff54bfdbc8 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.244216] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.244221] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.244224] Stack:
>[ 6824.244228]  0000000000000000 00000004000e9b1d ffffffff81590829 ffff88041ed17150
>[ 6824.244238]  ffffffff819ee780 00000634ff39d774 ffff88040c513fd8 ffffffff8159081b
>[ 6824.244246]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ed17150
>[ 6824.244255] Call Trace:
>[ 6824.244267]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.244276]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.244286]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.244297]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.244308]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.244313] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.244406] NMI backtrace for cpu 1
>[ 6824.244413] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.12.5-gentoo #1
>[ 6824.244416] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.244420] task: ffff88040c4dbcc0 ti: ffff88040c50c000 task.ti: ffff88040c50c000
>[ 6824.244424] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.244433] RSP: 0018:ffff88040c50de58  EFLAGS: 00000046
>[ 6824.244437] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.244440] RDX: 0000000000000000 RSI: ffff88040c50dfd8 RDI: 0000000000000001
>[ 6824.244443] RBP: 0000000000000005 R08: 00000000000003cf R09: 0000000000000008
>[ 6824.244446] R10: ffff88041ec4d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.244449] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.244453] FS:  0000000000000000(0000) GS:ffff88041ec40000(0000) knlGS:0000000000000000
>[ 6824.244457] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.244461] CR2: 00007f68a97b13b0 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.244464] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.244467] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.244469] Stack:
>[ 6824.244471]  0000000000000000 00000001000e8edc ffffffff81590829 ffff88041ec57150
>[ 6824.244477]  ffffffff819ee780 00000634ff39e3e8 ffff88040c50dfd8 ffffffff8159081b
>[ 6824.244482]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ec57150
>[ 6824.244488] Call Trace:
>[ 6824.244496]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.244502]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.244508]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.244516]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.244523]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.244527] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.244587] NMI backtrace for cpu 0
>[ 6824.244595] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.12.5-gentoo #1
>[ 6824.244598] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.244602] task: ffffffff819a8440 ti: ffffffff81998000 task.ti: ffffffff81998000
>[ 6824.244605] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.244620] RSP: 0018:ffffffff81999ea8  EFLAGS: 00000046
>[ 6824.244633] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.244646] RDX: 0000000000000000 RSI: ffffffff81999fd8 RDI: 0000000000000000
>[ 6824.244658] RBP: 0000000000000005 R08: 00000000000003d0 R09: 0000000000000008
>[ 6824.244671] R10: ffff88041ec0d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.244682] R13: 0000000000000004 R14: 0000000000000001 R15: 00000000c800dc38
>[ 6824.244696] FS:  0000000000000000(0000) GS:ffff88041ec00000(0000) knlGS:0000000000000000
>[ 6824.244709] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.244721] CR2: 00007f9ffcdc6000 CR3: 00000000029a3000 CR4: 00000000001407f0
>[ 6824.244733] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.244746] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.244757] Stack:
>[ 6824.244769]  0000000000000000 00000000000eb100 ffffffff81590829 ffff88041ec17150
>[ 6824.244812]  ffffffff819ee780 00000634ff39c7e4 ffffffff81999fd8 ffffffff8159081b
>[ 6824.244855]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ec17150
>[ 6824.244885] Call Trace:
>[ 6824.244892]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.244899]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.244905]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.244914]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.244921]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.244929]  [<ffffffff81a65c60>] ? start_kernel+0x36e/0x379
>[ 6824.244935]  [<ffffffff81a65708>] ? repair_env_string+0x57/0x57
>[ 6824.244938] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6824.244999] NMI backtrace for cpu 2
>[ 6824.245007] CPU: 2 PID: 0 Comm: swapper/2 Not tainted 3.12.5-gentoo #1
>[ 6824.245010] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6824.245013] task: ffff88040c4dc380 ti: ffff88040c50e000 task.ti: ffff88040c50e000
>[ 6824.245017] RIP: 0010:[<ffffffff812e3ac5>]  [<ffffffff812e3ac5>] intel_idle+0xa5/0xc9
>[ 6824.245026] RSP: 0018:ffff88040c50fe58  EFLAGS: 00000046
>[ 6824.245030] RAX: 0000000000000032 RBX: 0000000000000010 RCX: 0000000000000001
>[ 6824.245033] RDX: 0000000000000000 RSI: ffff88040c50ffd8 RDI: 0000000000000002
>[ 6824.245036] RBP: 0000000000000005 R08: 00000000000003cf R09: 0000000000000008
>[ 6824.245039] R10: ffff88041ec8d6a0 R11: 0000000000011640 R12: 0000000000000032
>[ 6824.245042] R13: 0000000000000004 R14: 0000000000000000 R15: 0000000000000000
>[ 6824.245046] FS:  0000000000000000(0000) GS:ffff88041ec80000(0000) knlGS:0000000000000000
>[ 6824.245050] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[ 6824.245053] CR2: 00007f68a976d000 CR3: 00000000029a3000 CR4: 00000000001407e0
>[ 6824.245056] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[ 6824.245060] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[ 6824.245062] Stack:
>[ 6824.245064]  0000000000000000 00000002000e8df5 ffffffff81590829 ffff88041ec97150
>[ 6824.245070]  ffffffff819ee780 00000634ff39e460 ffff88040c50ffd8 ffffffff8159081b
>[ 6824.245075]  0000000000000005 ffffffff819ee5b0 0000000000000000 ffff88041ec97150
>[ 6824.245081] Call Trace:
>[ 6824.245088]  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6824.245094]  [<ffffffff8159081b>] ? cpuidle_enter_state+0x35/0xa6
>[ 6824.245101]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6824.245108]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6824.245114]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6824.245116] Code: 86 38 e0 ff ff a8 08 75 22 48 8d 41 10 31 d2 48 89 d1 0f 01 c8 0f ae f0 48 8b 86 38 e0 ff ff a8 08 75 08 b1 01 4c 89 e0 0f 01 c9 <85> 1d 7d ae 70 00 75 0f 48 8d 74 24 0c bf 05 00 00 00 e8 70 7e 
>[ 6833.243075] nouveau E[     DRM] failed to idle channel 0xcccc0001 [DRM]
>[ 6833.243975] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6833.243984] xhci_hcd 0000:00:14.0: Giveback URB ffff8804058b1c00, len = 18, expected = 96, status = -121
>[ 6833.244011] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6833.244017] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6833.244195] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6833.244200] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6833.244205] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6833.244209] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6833.244213] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6833.244218] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6833.244222] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6833.244227] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d770 (DMA)
>[ 6833.244231] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6833.244237] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d770 (0x409a8d770 dma), new cycle = 1
>[ 6833.244242] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.244265] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6833.244279] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d771
>[ 6833.254138] pci_pm_runtime_suspend(): nouveau_pmops_runtime_suspend+0x0/0x6b returns -16
>[ 6833.261424] usb 2-14.1: usb_disable_device nuking all URBs
>[ 6833.261439] xhci_hcd 0000:00:14.0: xhci_drop_endpoint called for udev ffff8800daa2c000
>[ 6833.261452] xhci_hcd 0000:00:14.0: drop ep 0x81, slot id 10, new drop flags = 0x8, new add flags = 0x0, new slot info = 0xa200001
>[ 6833.261461] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff8800daa2c000
>[ 6833.261468] xhci_hcd 0000:00:14.0: New Input Control Context:
>[ 6833.261477] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000008 - drop flags
>[ 6833.261485] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000001 - add flags
>[ 6833.261493] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6833.261501] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6833.261509] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6833.261516] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6833.261524] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6833.261532] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6833.261538] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.261546] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6833.261554] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6833.261562] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6833.261571] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6833.261578] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6833.261586] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6833.261594] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6833.261602] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6833.261610] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.261618] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6833.261626] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6833.261634] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6833.261642] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6833.261650] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6833.261658] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6833.261666] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6833.261675] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.261911] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[ 6833.261938] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[ 6833.261946] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[ 6833.261952] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.261962] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0xa200001 - dev_info
>[ 6833.261970] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6833.261978] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6833.261987] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x1000000a - dev_state
>[ 6833.261996] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6833.262001] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6833.262006] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6833.262011] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6833.262016] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.262021] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6833.262025] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6833.262030] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850991 - deq
>[ 6833.262035] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6833.262039] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6833.262044] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6833.262049] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6833.262054] xhci_hcd 0000:00:14.0: Cached old ring, 1 ring cached
>[ 6833.262350] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.366429] hub 2-14:1.0: debounce: port 1: total 100ms stable 100ms status 0x301
>[ 6833.366440] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.366478] xhci_hcd 0000:00:14.0: Slot 11 output ctx = 0x40beaa000 (dma)
>[ 6833.366485] xhci_hcd 0000:00:14.0: Slot 11 input ctx = 0x40b554000 (dma)
>[ 6833.366494] xhci_hcd 0000:00:14.0: Set slot id 11 dcbaa entry ffff88040bed9058 to 0x40beaa000
>[ 6833.377429] hub 2-14:1.0: port 1 not reset yet, waiting 10ms
>[ 6833.439402] usb 2-14.1: new low-speed USB device number 11 using xhci_hcd
>[ 6833.439413] xhci_hcd 0000:00:14.0: Set root hub portnum to 14
>[ 6833.439418] xhci_hcd 0000:00:14.0: Set fake root hub portnum to 14
>[ 6833.439423] xhci_hcd 0000:00:14.0: udev->tt = ffff88040bb6fea0
>[ 6833.439428] xhci_hcd 0000:00:14.0: udev->ttport = 0x1
>[ 6833.439432] xhci_hcd 0000:00:14.0: Slot ID 11 Input Context:
>[ 6833.439438] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6833.439443] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000003 - add flags
>[ 6833.439448] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6833.439452] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6833.439457] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6833.439462] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6833.439466] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6833.439471] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6833.439475] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.439479] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6833.439484] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6833.439489] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6833.439494] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6833.439499] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6833.439503] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6833.439508] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6833.439513] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6833.439518] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.439522] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6833.439527] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6833.439532] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6833.439536] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6833.439541] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6833.439546] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6833.439550] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6833.439555] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6833.439560] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6833.439564] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6833.439569] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6833.439574] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6833.439578] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6833.439583] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6833.439587] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6833.439592] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6833.439596] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x000000 - ep_info
>[ 6833.439601] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x000000 - ep_info2
>[ 6833.439605] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x000000 - deq
>[ 6833.439610] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x000000 - tx_info
>[ 6833.439614] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6833.439619] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6833.439624] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6833.439628] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.439863] xhci_hcd 0000:00:14.0: Successful Address Device command
>[ 6833.439869] xhci_hcd 0000:00:14.0: Op regs DCBAA ptr = 0x0000040bed9000
>[ 6833.439875] xhci_hcd 0000:00:14.0: Slot ID 11 dcbaa entry @ffff88040bed9058 = 0x0000040beaa000
>[ 6833.439880] xhci_hcd 0000:00:14.0: Output Context DMA address = 0x40beaa000
>[ 6833.439884] xhci_hcd 0000:00:14.0: Slot ID 11 Input Context:
>[ 6833.439889] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6833.439893] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000003 - add flags
>[ 6833.439898] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6833.439903] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6833.439907] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6833.439912] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6833.439917] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6833.439921] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6833.439925] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.439929] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0xa200001 - dev_info
>[ 6833.439934] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6833.439939] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6833.439943] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6833.439948] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6833.439953] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6833.439957] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6833.439962] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6833.439966] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.439971] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6833.439975] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6833.439980] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6833.439985] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6833.439989] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6833.439994] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6833.439999] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6833.440003] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6833.440008] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6833.440012] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6833.440017] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6833.440021] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6833.440026] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6833.440030] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6833.440035] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6833.440039] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6833.440044] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x000000 - ep_info
>[ 6833.440048] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x000000 - ep_info2
>[ 6833.440068] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x000000 - deq
>[ 6833.440073] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x000000 - tx_info
>[ 6833.440077] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6833.440082] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6833.440086] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6833.440091] xhci_hcd 0000:00:14.0: Slot ID 11 Output Context:
>[ 6833.440094] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.440099] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0xa200001 - dev_info
>[ 6833.440104] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6833.440108] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6833.440113] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x1000000b - dev_state
>[ 6833.440117] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6833.440122] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6833.440127] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6833.440131] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6833.440136] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.440140] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6833.440144] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6833.440149] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850801 - deq
>[ 6833.440153] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6833.440158] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6833.440174] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6833.440187] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6833.440200] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6833.440213] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[ 6833.440227] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x000000 - ep_info2
>[ 6833.440240] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x000000 - deq
>[ 6833.440253] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[ 6833.440267] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[ 6833.440280] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[ 6833.440293] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[ 6833.440306] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6833.440319] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x000000 - ep_info
>[ 6833.440332] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x000000 - ep_info2
>[ 6833.440346] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x000000 - deq
>[ 6833.440359] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x000000 - tx_info
>[ 6833.440372] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[ 6833.440386] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[ 6833.440397] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[ 6833.440402] xhci_hcd 0000:00:14.0: Internal device address = 12
>[ 6833.453690] usb 2-14.1: skipped 1 descriptor after interface
>[ 6833.453959] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6833.454082] usb 2-14.1: default language 0x0409
>[ 6833.454959] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6833.455673] xhci_hcd 0000:00:14.0: Waiting for status stage event
>[ 6833.455784] usb 2-14.1: udev 11, busnum 2, minor = 138
>[ 6833.455791] usb 2-14.1: New USB device found, idVendor=046d, idProduct=c05a
>[ 6833.455797] usb 2-14.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[ 6833.455805] usb 2-14.1: Product: USB Optical Mouse
>[ 6833.455811] usb 2-14.1: Manufacturer: Logitech
>[ 6833.456025] usb 2-14.1: usb_probe_device
>[ 6833.456032] usb 2-14.1: configuration #1 chosen from 1 choice
>[ 6833.456047] usb 2-14.1: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[ 6833.456067] xhci_hcd 0000:00:14.0: add ep 0x81, slot id 11, new drop flags = 0x0, new add flags = 0x8, new slot info = 0x1a200001
>[ 6833.456075] xhci_hcd 0000:00:14.0: xhci_check_bandwidth called for udev ffff8800daa2a000
>[ 6833.456079] xhci_hcd 0000:00:14.0: New Input Control Context:
>[ 6833.456097] xhci_hcd 0000:00:14.0: @ffff88040b554000 (virt) @40b554000 (dma) 0x000000 - drop flags
>[ 6833.456104] xhci_hcd 0000:00:14.0: @ffff88040b554004 (virt) @40b554004 (dma) 0x000009 - add flags
>[ 6833.456110] xhci_hcd 0000:00:14.0: @ffff88040b554008 (virt) @40b554008 (dma) 0x000000 - rsvd2[0]
>[ 6833.456128] xhci_hcd 0000:00:14.0: @ffff88040b55400c (virt) @40b55400c (dma) 0x000000 - rsvd2[1]
>[ 6833.456134] xhci_hcd 0000:00:14.0: @ffff88040b554010 (virt) @40b554010 (dma) 0x000000 - rsvd2[2]
>[ 6833.456139] xhci_hcd 0000:00:14.0: @ffff88040b554014 (virt) @40b554014 (dma) 0x000000 - rsvd2[3]
>[ 6833.456145] xhci_hcd 0000:00:14.0: @ffff88040b554018 (virt) @40b554018 (dma) 0x000000 - rsvd2[4]
>[ 6833.456150] xhci_hcd 0000:00:14.0: @ffff88040b55401c (virt) @40b55401c (dma) 0x000000 - rsvd2[5]
>[ 6833.456156] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.456163] xhci_hcd 0000:00:14.0: @ffff88040b554020 (virt) @40b554020 (dma) 0x1a200001 - dev_info
>[ 6833.456168] xhci_hcd 0000:00:14.0: @ffff88040b554024 (virt) @40b554024 (dma) 0x0e0000 - dev_info2
>[ 6833.456174] xhci_hcd 0000:00:14.0: @ffff88040b554028 (virt) @40b554028 (dma) 0x000102 - tt_info
>[ 6833.456180] xhci_hcd 0000:00:14.0: @ffff88040b55402c (virt) @40b55402c (dma) 0x000000 - dev_state
>[ 6833.456185] xhci_hcd 0000:00:14.0: @ffff88040b554030 (virt) @40b554030 (dma) 0x000000 - rsvd[0]
>[ 6833.456191] xhci_hcd 0000:00:14.0: @ffff88040b554034 (virt) @40b554034 (dma) 0x000000 - rsvd[1]
>[ 6833.456196] xhci_hcd 0000:00:14.0: @ffff88040b554038 (virt) @40b554038 (dma) 0x000000 - rsvd[2]
>[ 6833.456201] xhci_hcd 0000:00:14.0: @ffff88040b55403c (virt) @40b55403c (dma) 0x000000 - rsvd[3]
>[ 6833.456205] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.456212] xhci_hcd 0000:00:14.0: @ffff88040b554040 (virt) @40b554040 (dma) 0x000000 - ep_info
>[ 6833.456217] xhci_hcd 0000:00:14.0: @ffff88040b554044 (virt) @40b554044 (dma) 0x080026 - ep_info2
>[ 6833.456226] xhci_hcd 0000:00:14.0: @ffff88040b554048 (virt) @40b554048 (dma) 0x409850801 - deq
>[ 6833.456230] xhci_hcd 0000:00:14.0: @ffff88040b554050 (virt) @40b554050 (dma) 0x000000 - tx_info
>[ 6833.456237] xhci_hcd 0000:00:14.0: @ffff88040b554054 (virt) @40b554054 (dma) 0x000000 - rsvd[0]
>[ 6833.456240] xhci_hcd 0000:00:14.0: @ffff88040b554058 (virt) @40b554058 (dma) 0x000000 - rsvd[1]
>[ 6833.456243] xhci_hcd 0000:00:14.0: @ffff88040b55405c (virt) @40b55405c (dma) 0x000000 - rsvd[2]
>[ 6833.456250] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6833.456254] xhci_hcd 0000:00:14.0: @ffff88040b554060 (virt) @40b554060 (dma) 0x000000 - ep_info
>[ 6833.456260] xhci_hcd 0000:00:14.0: @ffff88040b554064 (virt) @40b554064 (dma) 0x000000 - ep_info2
>[ 6833.456263] xhci_hcd 0000:00:14.0: @ffff88040b554068 (virt) @40b554068 (dma) 0x000000 - deq
>[ 6833.456267] xhci_hcd 0000:00:14.0: @ffff88040b554070 (virt) @40b554070 (dma) 0x000000 - tx_info
>[ 6833.456273] xhci_hcd 0000:00:14.0: @ffff88040b554074 (virt) @40b554074 (dma) 0x000000 - rsvd[0]
>[ 6833.456277] xhci_hcd 0000:00:14.0: @ffff88040b554078 (virt) @40b554078 (dma) 0x000000 - rsvd[1]
>[ 6833.456284] xhci_hcd 0000:00:14.0: @ffff88040b55407c (virt) @40b55407c (dma) 0x000000 - rsvd[2]
>[ 6833.456288] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6833.456294] xhci_hcd 0000:00:14.0: @ffff88040b554080 (virt) @40b554080 (dma) 0x060000 - ep_info
>[ 6833.456297] xhci_hcd 0000:00:14.0: @ffff88040b554084 (virt) @40b554084 (dma) 0x04003e - ep_info2
>[ 6833.456300] xhci_hcd 0000:00:14.0: @ffff88040b554088 (virt) @40b554088 (dma) 0x40b69d001 - deq
>[ 6833.456307] xhci_hcd 0000:00:14.0: @ffff88040b554090 (virt) @40b554090 (dma) 0x040004 - tx_info
>[ 6833.456311] xhci_hcd 0000:00:14.0: @ffff88040b554094 (virt) @40b554094 (dma) 0x000000 - rsvd[0]
>[ 6833.456317] xhci_hcd 0000:00:14.0: @ffff88040b554098 (virt) @40b554098 (dma) 0x000000 - rsvd[1]
>[ 6833.456320] xhci_hcd 0000:00:14.0: @ffff88040b55409c (virt) @40b55409c (dma) 0x000000 - rsvd[2]
>[ 6833.456325] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.456549] xhci_hcd 0000:00:14.0: Completed config ep cmd
>[ 6833.456570] xhci_hcd 0000:00:14.0: Successful Endpoint Configure command
>[ 6833.456577] xhci_hcd 0000:00:14.0: Output context after successful config ep cmd:
>[ 6833.456583] xhci_hcd 0000:00:14.0: Slot Context:
>[ 6833.456595] xhci_hcd 0000:00:14.0: @ffff88040beaa000 (virt) @40beaa000 (dma) 0x1a200001 - dev_info
>[ 6833.456616] xhci_hcd 0000:00:14.0: @ffff88040beaa004 (virt) @40beaa004 (dma) 0x0e0000 - dev_info2
>[ 6833.456637] xhci_hcd 0000:00:14.0: @ffff88040beaa008 (virt) @40beaa008 (dma) 0x000102 - tt_info
>[ 6833.456655] xhci_hcd 0000:00:14.0: @ffff88040beaa00c (virt) @40beaa00c (dma) 0x1800000b - dev_state
>[ 6833.456674] xhci_hcd 0000:00:14.0: @ffff88040beaa010 (virt) @40beaa010 (dma) 0x000000 - rsvd[0]
>[ 6833.456692] xhci_hcd 0000:00:14.0: @ffff88040beaa014 (virt) @40beaa014 (dma) 0x000000 - rsvd[1]
>[ 6833.456710] xhci_hcd 0000:00:14.0: @ffff88040beaa018 (virt) @40beaa018 (dma) 0x000000 - rsvd[2]
>[ 6833.456728] xhci_hcd 0000:00:14.0: @ffff88040beaa01c (virt) @40beaa01c (dma) 0x000000 - rsvd[3]
>[ 6833.456745] xhci_hcd 0000:00:14.0: IN Endpoint 00 Context (ep_index 00):
>[ 6833.456763] xhci_hcd 0000:00:14.0: @ffff88040beaa020 (virt) @40beaa020 (dma) 0x000001 - ep_info
>[ 6833.456781] xhci_hcd 0000:00:14.0: @ffff88040beaa024 (virt) @40beaa024 (dma) 0x080026 - ep_info2
>[ 6833.456798] xhci_hcd 0000:00:14.0: @ffff88040beaa028 (virt) @40beaa028 (dma) 0x409850801 - deq
>[ 6833.456818] xhci_hcd 0000:00:14.0: @ffff88040beaa030 (virt) @40beaa030 (dma) 0x000000 - tx_info
>[ 6833.456839] xhci_hcd 0000:00:14.0: @ffff88040beaa034 (virt) @40beaa034 (dma) 0x000000 - rsvd[0]
>[ 6833.456860] xhci_hcd 0000:00:14.0: @ffff88040beaa038 (virt) @40beaa038 (dma) 0x000000 - rsvd[1]
>[ 6833.456875] xhci_hcd 0000:00:14.0: @ffff88040beaa03c (virt) @40beaa03c (dma) 0x000000 - rsvd[2]
>[ 6833.456891] xhci_hcd 0000:00:14.0: OUT Endpoint 01 Context (ep_index 01):
>[ 6833.456898] xhci_hcd 0000:00:14.0: @ffff88040beaa040 (virt) @40beaa040 (dma) 0x000000 - ep_info
>[ 6833.456905] xhci_hcd 0000:00:14.0: @ffff88040beaa044 (virt) @40beaa044 (dma) 0x000000 - ep_info2
>[ 6833.456913] xhci_hcd 0000:00:14.0: @ffff88040beaa048 (virt) @40beaa048 (dma) 0x000000 - deq
>[ 6833.456921] xhci_hcd 0000:00:14.0: @ffff88040beaa050 (virt) @40beaa050 (dma) 0x000000 - tx_info
>[ 6833.456929] xhci_hcd 0000:00:14.0: @ffff88040beaa054 (virt) @40beaa054 (dma) 0x000000 - rsvd[0]
>[ 6833.456937] xhci_hcd 0000:00:14.0: @ffff88040beaa058 (virt) @40beaa058 (dma) 0x000000 - rsvd[1]
>[ 6833.456944] xhci_hcd 0000:00:14.0: @ffff88040beaa05c (virt) @40beaa05c (dma) 0x000000 - rsvd[2]
>[ 6833.456952] xhci_hcd 0000:00:14.0: IN Endpoint 01 Context (ep_index 02):
>[ 6833.456960] xhci_hcd 0000:00:14.0: @ffff88040beaa060 (virt) @40beaa060 (dma) 0x060001 - ep_info
>[ 6833.456967] xhci_hcd 0000:00:14.0: @ffff88040beaa064 (virt) @40beaa064 (dma) 0x04003e - ep_info2
>[ 6833.456975] xhci_hcd 0000:00:14.0: @ffff88040beaa068 (virt) @40beaa068 (dma) 0x40b69d001 - deq
>[ 6833.456983] xhci_hcd 0000:00:14.0: @ffff88040beaa070 (virt) @40beaa070 (dma) 0x040004 - tx_info
>[ 6833.456991] xhci_hcd 0000:00:14.0: @ffff88040beaa074 (virt) @40beaa074 (dma) 0x000000 - rsvd[0]
>[ 6833.456999] xhci_hcd 0000:00:14.0: @ffff88040beaa078 (virt) @40beaa078 (dma) 0x000000 - rsvd[1]
>[ 6833.457007] xhci_hcd 0000:00:14.0: @ffff88040beaa07c (virt) @40beaa07c (dma) 0x000000 - rsvd[2]
>[ 6833.457018] xhci_hcd 0000:00:14.0: Endpoint 0x81 not halted, refusing to reset.
>[ 6833.457305] usb 2-14.1: adding 2-14.1:1.0 (config #1, interface 0)
>[ 6833.457382] usbhid 2-14.1:1.0: usb_probe_interface
>[ 6833.457386] usbhid 2-14.1:1.0: usb_probe_interface - got id
>[ 6833.457655] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6833.457660] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6833.457663] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6833.457665] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6833.457671] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6833.457677] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6833.457681] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040bf9c840 (virtual)
>[ 6833.457686] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409850990 (DMA)
>[ 6833.457689] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6833.457695] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040bf9c840 (0x409850800 dma), new deq ptr = ffff880409850990 (0x409850990 dma), new cycle = 1
>[ 6833.457698] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6833.457704] xhci_hcd 0000:00:14.0: Giveback URB ffff88040692e6c0, len = 0, expected = 0, status = -32
>[ 6833.457711] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6833.457716] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409850991
>[ 6833.459397] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb2/2-14/2-14.1/2-14.1:1.0/input/input26
>[ 6833.459643] hid-generic 0003:046D:C05A.0009: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-14.1/input0
>[ 6833.459743] hub 2-14:1.0: state 7 ports 2 chg 0000 evt 0002
>[ 6834.297069] irq 16: nobody cared (try booting with the "irqpoll" option)
>[ 6834.297079] CPU: 4 PID: 0 Comm: swapper/4 Not tainted 3.12.5-gentoo #1
>[ 6834.297083] Hardware name: ASUS All Series/P9D WS, BIOS 1103 06/14/2013
>[ 6834.297087]  0000000000000000 0000000000000000 ffffffff81703004 ffff88040c6eb600
>[ 6834.297094]  ffffffff810b3475 ffff88040c6eb600 0000000000000000 0000000000000010
>[ 6834.297101]  ffffffff810b3814 0000000000004731 0000000000000000 ffff88040c6eb600
>[ 6834.297107] Call Trace:
>[ 6834.297110]  <IRQ>  [<ffffffff81703004>] ? dump_stack+0x41/0x51
>[ 6834.297128]  [<ffffffff810b3475>] ? __report_bad_irq+0x17/0xbb
>[ 6834.297136]  [<ffffffff810b3814>] ? note_interrupt+0x15b/0x1e7
>[ 6834.297144]  [<ffffffff810b1bee>] ? handle_irq_event_percpu+0x103/0x11a
>[ 6834.297151]  [<ffffffff810b1c33>] ? handle_irq_event+0x2e/0x4f
>[ 6834.297158]  [<ffffffff810bd55d>] ? tick_nohz_stop_idle+0x20/0x2f
>[ 6834.297164]  [<ffffffff810b40c9>] ? handle_fasteoi_irq+0x71/0xa3
>[ 6834.297170]  [<ffffffff81003e41>] ? handle_irq+0x15/0x1d
>[ 6834.297175]  [<ffffffff81003aed>] ? do_IRQ+0x41/0xa6
>[ 6834.297184]  [<ffffffff8170976a>] ? common_interrupt+0x6a/0x6a
>[ 6834.297187]  <EOI>  [<ffffffff81590829>] ? cpuidle_enter_state+0x43/0xa6
>[ 6834.297199]  [<ffffffff81590822>] ? cpuidle_enter_state+0x3c/0xa6
>[ 6834.297205]  [<ffffffff81590946>] ? cpuidle_idle_call+0xba/0x109
>[ 6834.297214]  [<ffffffff8100963e>] ? arch_cpu_idle+0x6/0x19
>[ 6834.297221]  [<ffffffff810b1427>] ? cpu_startup_entry+0xa7/0x104
>[ 6834.297225] handlers:
>[ 6834.297230] [<ffffffff813bede0>] nouveau_mc_intr
>[ 6834.297233] Disabling IRQ #16
>[ 6835.742710] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6835.742723] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9a780, len = 18, expected = 96, status = -121
>[ 6835.742770] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6835.742780] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6835.742987] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6835.742997] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6835.743002] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6835.743006] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6835.743010] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6835.743015] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6835.743023] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6835.743038] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7b0 (DMA)
>[ 6835.743042] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6835.743050] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7b0 (0x409a8d7b0 dma), new cycle = 1
>[ 6835.743055] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6835.743071] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6835.743077] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7b1
>[ 6837.790546] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6837.790558] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9a780, len = 18, expected = 96, status = -121
>[ 6837.790603] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6837.790616] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6837.790827] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6837.790840] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6837.790847] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6837.790851] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6837.790856] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6837.790861] xhci_hcd 0000:00:14.0: Cycle state = 0x1
>[ 6837.790866] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122c0 (virtual)
>[ 6837.790870] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d7f0 (DMA)
>[ 6837.790875] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6837.790885] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122c0 (0x409a8d400 dma), new deq ptr = ffff880409a8d7f0 (0x409a8d7f0 dma), new cycle = 1
>[ 6837.790890] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6837.790911] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6837.790919] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d7f1
>[ 6839.838417] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6839.838429] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9a780, len = 18, expected = 96, status = -121
>[ 6839.838473] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6839.838487] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6839.838698] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6839.838707] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6839.838711] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6839.838717] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6839.838723] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6839.838731] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6839.838738] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6839.838746] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d040 (DMA)
>[ 6839.838752] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6839.838763] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d040 (0x409a8d040 dma), new cycle = 0
>[ 6839.838770] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6839.838794] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6839.838824] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d040
>[ 6841.886149] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6841.886155] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5840, len = 18, expected = 96, status = -121
>[ 6841.886188] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6841.886195] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6841.886375] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6841.886379] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6841.886381] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6841.886383] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6841.886386] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6841.886388] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6841.886391] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6841.886393] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d080 (DMA)
>[ 6841.886395] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6841.886399] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d080 (0x409a8d080 dma), new cycle = 0
>[ 6841.886401] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6841.886406] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6841.886412] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6841.886417] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d080
>[ 6843.934052] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6843.934060] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6843.934082] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6843.934088] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6843.934266] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6843.934269] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6843.934272] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6843.934277] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6843.934280] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6843.934283] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6843.934287] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6843.934290] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d0c0 (DMA)
>[ 6843.934293] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6843.934299] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d0c0 (0x409a8d0c0 dma), new cycle = 0
>[ 6843.934302] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6843.934308] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6843.934313] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d0c0
>[ 6845.981884] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6845.981892] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6845.981920] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6845.981925] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6845.982097] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6845.982100] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6845.982103] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6845.982105] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6845.982108] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6845.982111] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6845.982114] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6845.982117] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d100 (DMA)
>[ 6845.982120] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6845.982124] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d100 (0x409a8d100 dma), new cycle = 0
>[ 6845.982127] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6845.982132] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6845.982140] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6845.982144] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d100
>[ 6848.029802] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6848.029811] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6848.029841] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6848.029849] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6848.030050] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6848.030058] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6848.030062] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6848.030065] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6848.030069] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6848.030073] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6848.030077] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6848.030080] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d140 (DMA)
>[ 6848.030084] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6848.030089] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d140 (0x409a8d140 dma), new cycle = 0
>[ 6848.030093] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6848.030107] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6848.030116] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d140
>[ 6850.077632] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6850.077640] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6850.077667] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6850.077672] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6850.077849] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6850.077853] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6850.077857] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6850.077860] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6850.077863] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6850.077867] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6850.077870] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6850.077874] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d180 (DMA)
>[ 6850.077877] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6850.077883] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d180 (0x409a8d180 dma), new cycle = 0
>[ 6850.077886] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6850.077901] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6850.077909] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d180
>[ 6852.125550] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6852.125561] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9ab40, len = 18, expected = 96, status = -121
>[ 6852.125596] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6852.125606] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6852.125812] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6852.125825] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6852.125833] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6852.125840] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6852.125847] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6852.125854] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6852.125860] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6852.125867] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d1c0 (DMA)
>[ 6852.125873] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6852.125881] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d1c0 (0x409a8d1c0 dma), new cycle = 0
>[ 6852.125888] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6852.125907] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6852.125925] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d1c0
>[ 6854.173375] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6854.173386] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6854.173418] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6854.173427] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6854.173621] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6854.173626] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6854.173630] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6854.173634] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6854.173638] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6854.173643] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6854.173648] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6854.173652] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d200 (DMA)
>[ 6854.173656] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6854.173663] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d200 (0x409a8d200 dma), new cycle = 0
>[ 6854.173668] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6854.173676] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6854.173686] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6854.173695] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d200
>[ 6856.221254] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6856.221266] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6856.221298] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6856.221307] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6856.221501] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6856.221506] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6856.221511] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6856.221515] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6856.221520] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6856.221525] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6856.221529] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6856.221534] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d240 (DMA)
>[ 6856.221538] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6856.221545] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d240 (0x409a8d240 dma), new cycle = 0
>[ 6856.221549] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6856.221564] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6856.221572] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d240
>[ 6858.269080] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6858.269092] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6858.269122] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6858.269132] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6858.269327] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6858.269333] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6858.269337] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6858.269341] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6858.269346] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6858.269351] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6858.269355] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6858.269360] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d280 (DMA)
>[ 6858.269364] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6858.269371] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d280 (0x409a8d280 dma), new cycle = 0
>[ 6858.269375] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6858.269389] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6858.269398] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d280
>[ 6860.316957] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6860.316968] xhci_hcd 0000:00:14.0: Giveback URB ffff88040bf9a000, len = 18, expected = 96, status = -121
>[ 6860.317002] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6860.317012] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6860.317195] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6860.317201] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6860.317205] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6860.317209] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6860.317213] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6860.317217] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6860.317222] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6860.317227] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d2c0 (DMA)
>[ 6860.317231] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6860.317237] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d2c0 (0x409a8d2c0 dma), new cycle = 0
>[ 6860.317242] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6860.317250] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6860.317259] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6860.317269] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d2c0
>[ 6862.364804] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6862.364815] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6862.364846] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6862.364857] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6862.365050] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6862.365056] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6862.365060] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6862.365064] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6862.365068] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6862.365073] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6862.365077] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6862.365082] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d300 (DMA)
>[ 6862.365087] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6862.365094] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d300 (0x409a8d300 dma), new cycle = 0
>[ 6862.365099] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6862.365113] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6862.365121] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d300
>[ 6864.412657] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6864.412669] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6864.412701] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6864.412715] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6864.412906] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6864.412911] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6864.412915] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6864.412919] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6864.412923] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6864.412928] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6864.412932] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6864.412937] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d340 (DMA)
>[ 6864.412941] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6864.412947] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d340 (0x409a8d340 dma), new cycle = 0
>[ 6864.412952] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6864.412959] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6864.412971] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6864.412981] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d340
>[ 6866.460525] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6866.460536] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6866.460567] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6866.460577] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6866.460770] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6866.460776] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6866.460780] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6866.460784] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6866.460788] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6866.460792] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6866.460798] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6866.460803] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d380 (DMA)
>[ 6866.460807] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6866.460813] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d380 (0x409a8d380 dma), new cycle = 0
>[ 6866.460818] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6866.460832] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6866.460840] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d380
>[ 6868.508392] xhci_hcd 0000:00:14.0: ep 0x81 - asked for 96 bytes, 78 bytes untransferred
>[ 6868.508403] xhci_hcd 0000:00:14.0: Giveback URB ffff880403ae5480, len = 18, expected = 96, status = -121
>[ 6868.508435] xhci_hcd 0000:00:14.0: Stalled endpoint
>[ 6868.508450] xhci_hcd 0000:00:14.0: Giveback URB ffff88040c5e40c0, len = 0, expected = 13, status = -32
>[ 6868.508641] xhci_hcd 0000:00:14.0: Queueing reset endpoint command
>[ 6868.508647] xhci_hcd 0000:00:14.0: Cleaning up stalled endpoint ring
>[ 6868.508652] xhci_hcd 0000:00:14.0: Finding segment containing stopped TRB.
>[ 6868.508657] xhci_hcd 0000:00:14.0: Finding endpoint context
>[ 6868.508661] xhci_hcd 0000:00:14.0: Finding segment containing last TRB in TD.
>[ 6868.508666] xhci_hcd 0000:00:14.0: Cycle state = 0x0
>[ 6868.508670] xhci_hcd 0000:00:14.0: New dequeue segment = ffff88040c6122a0 (virtual)
>[ 6868.508675] xhci_hcd 0000:00:14.0: New dequeue pointer = 0x409a8d3c0 (DMA)
>[ 6868.508679] xhci_hcd 0000:00:14.0: Queueing new dequeue state
>[ 6868.508685] xhci_hcd 0000:00:14.0: Set TR Deq Ptr cmd, new deq seg = ffff88040c6122a0 (0x409a8d000 dma), new deq ptr = ffff880409a8d3c0 (0x409a8d3c0 dma), new cycle = 0
>[ 6868.508690] xhci_hcd 0000:00:14.0: // Ding dong!
>[ 6868.508697] xhci_hcd 0000:00:14.0: WARN halted endpoint, queueing URB anyway.
>[ 6868.508715] xhci_hcd 0000:00:14.0: Ignoring reset ep completion code of 1
>[ 6868.508723] xhci_hcd 0000:00:14.0: Successful Set TR Deq Ptr cmd, deq = @409a8d3c0

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Attachments on bug 69882: 86731 | 86732 | 86733 | 86735 | 90899 | 90900 | 119484

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