Attachment 95291 Details for Bug 75876 – dmesg

dmesg

dmesg_bdw02_0307.txt (text/plain), 126.63 KB, created by lu hua on 2014-03-07 07:34:04 UTC

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Description:

Filename:

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Creator: lu hua

Created: 2014-03-07 07:34:04 UTC

Size: 126.63 KB

patch

obsolete

>[ 2518.826446] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2518.826662] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2518.826667] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2518.826754] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2518.827017] [drm:i915_gem_open], 
>[ 2518.827041] [drm:i915_gem_open], 
>[ 2518.827062] [drm:i915_gem_open], 
>[ 2518.827076] [drm:i915_gem_open], 
>[ 2518.827216] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2526.815271] [drm] stuck on bsd ring
>[ 2526.819452] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2526.822613] [drm:i915_error_work_func], resetting chip
>[ 2526.822799] [drm] Simulated gpu hang, resetting stop_rings
>[ 2526.825885] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2526.827284] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2526.827294] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2526.827413] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2526.827519] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2526.827637] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2526.827639] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2526.827708] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2526.827918] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2532.813112] [drm] stuck on bsd ring
>[ 2532.817325] [drm] GPU HANG: ecode 1:0xa77ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2532.820803] [drm:i915_error_work_func], resetting chip
>[ 2532.821114] [drm] Simulated gpu hang, resetting stop_rings
>[ 2532.825048] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2532.827145] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2532.827164] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2532.827271] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2532.827374] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2532.827498] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2532.827501] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2532.827568] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2532.827910] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2538.810952] [drm] stuck on bsd ring
>[ 2538.815194] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2538.818428] [drm:i915_error_work_func], resetting chip
>[ 2538.818601] [drm] Simulated gpu hang, resetting stop_rings
>[ 2538.821753] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2538.823982] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2538.823990] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2538.824094] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2538.824190] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2538.824310] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2538.824315] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2538.824384] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2538.824652] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2548.803352] [drm] stuck on bsd ring
>[ 2548.807619] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2548.811117] [drm:i915_error_work_func], resetting chip
>[ 2548.811441] [drm] Simulated gpu hang, resetting stop_rings
>[ 2548.814647] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2548.816355] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2548.816387] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2548.816498] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2548.816602] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2548.816724] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2548.816727] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2548.816796] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2548.817056] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2554.801197] [drm] stuck on bsd ring
>[ 2554.805484] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2554.808878] [drm:i915_error_work_func], resetting chip
>[ 2554.809056] [drm] Simulated gpu hang, resetting stop_rings
>[ 2554.812185] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2554.814216] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2554.814230] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2554.814354] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2554.814457] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2554.814580] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2554.814583] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2554.814652] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2554.814948] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2560.803038] [drm] stuck on bsd ring
>[ 2560.807367] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2560.810940] [drm:i915_error_work_func], resetting chip
>[ 2560.811424] [drm] Simulated gpu hang, resetting stop_rings
>[ 2560.814791] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2560.816056] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2560.816068] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2560.816183] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2560.816288] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2560.816412] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2560.816415] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2560.816483] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2560.816781] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2570.799440] [drm] stuck on bsd ring
>[ 2570.803756] [drm] GPU HANG: ecode 1:0xa77ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2570.807302] [drm:i915_error_work_func], resetting chip
>[ 2570.807818] [drm] Simulated gpu hang, resetting stop_rings
>[ 2570.811672] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2570.813462] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2570.813480] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2570.813585] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2570.813684] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2570.813804] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2570.813807] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2570.813876] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2570.814142] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2576.793279] [drm] stuck on bsd ring
>[ 2576.797605] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2576.801073] [drm:i915_error_work_func], resetting chip
>[ 2576.801428] [drm] Simulated gpu hang, resetting stop_rings
>[ 2576.805446] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2576.807313] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2576.807330] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2576.807443] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2576.807547] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2576.807672] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2576.807675] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2576.807742] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2576.808004] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2586.793685] [drm] stuck on bsd ring
>[ 2586.798003] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2586.801306] [drm:i915_error_work_func], resetting chip
>[ 2586.801514] [drm] Simulated gpu hang, resetting stop_rings
>[ 2586.804894] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2586.806722] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2586.806740] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2586.806846] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2586.806945] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2586.807068] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2586.807071] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2586.807140] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2586.807401] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2592.791529] [drm] stuck on bsd ring
>[ 2592.795848] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2592.799350] [drm:i915_error_work_func], resetting chip
>[ 2592.800649] [drm] Simulated gpu hang, resetting stop_rings
>[ 2592.803862] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2592.805557] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2592.805566] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2592.805669] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2592.805767] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2592.805887] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2592.805890] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2592.805958] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2592.806220] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2602.787930] [drm] stuck on bsd ring
>[ 2602.792242] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2602.795793] [drm:i915_error_work_func], resetting chip
>[ 2602.796225] [drm] Simulated gpu hang, resetting stop_rings
>[ 2602.799515] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2602.800963] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2602.800973] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2602.801077] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2602.801173] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2602.801295] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2602.801298] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2602.801366] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2602.801642] [drm:i915_gem_open], 
>[ 2602.801667] [drm:i915_gem_open], 
>[ 2602.801750] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2608.785771] [drm] stuck on bsd ring
>[ 2608.790092] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2608.793652] [drm:i915_error_work_func], resetting chip
>[ 2608.794207] [drm] Simulated gpu hang, resetting stop_rings
>[ 2608.797486] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2608.798790] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2608.798805] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2608.798912] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2608.799010] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2608.799136] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2608.799138] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2608.799207] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2608.800817] [drm:i915_gem_open], 
>[ 2608.800842] [drm:i915_gem_open], 
>[ 2608.800925] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2612.784334] [drm] stuck on blitter ring
>[ 2612.788673] [drm] GPU HANG: ecode 1:0x277ffffe, reason: Ring hung, action: reset
>[ 2612.792210] [drm:i915_error_work_func], resetting chip
>[ 2612.792717] [drm] Simulated gpu hang, resetting stop_rings
>[ 2612.796568] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2612.798343] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2612.798352] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2612.798472] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2612.798577] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2612.798698] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2612.798701] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2612.798768] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2612.799039] [drm:i915_gem_open], 
>[ 2612.799070] [drm:i915_gem_open], 
>[ 2612.799141] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2613.799165] [drm:i915_gem_open], 
>[ 2613.799211] [drm:i915_gem_open], 
>[ 2614.798833] [drm:i915_gem_open], 
>[ 2614.798869] [drm:i915_gem_open], 
>[ 2620.777451] [drm] stuck on bsd ring
>[ 2620.781737] [drm] GPU HANG: ecode 1:0x277ffffe, reason: Ring hung, action: reset
>[ 2620.785220] [drm:i915_error_work_func], resetting chip
>[ 2620.785547] [drm] Simulated gpu hang, resetting stop_rings
>[ 2620.788633] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2620.790458] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2620.790468] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2620.790582] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2620.790688] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2620.790810] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2620.790813] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2620.790880] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2620.791056] [drm:i915_gem_open], 
>[ 2620.791081] [drm:i915_gem_open], 
>[ 2620.791168] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 2621.791177] [drm:i915_gem_open], 
>[ 2621.791221] [drm:i915_gem_open], 
>[ 2622.790842] [drm:i915_gem_open], 
>[ 2622.790873] [drm:i915_gem_open], 
>[ 2626.775297] [drm] stuck on blitter ring
>[ 2626.779572] [drm] GPU HANG: ecode 2:0xfffffffe, reason: Ring hung, action: reset
>[ 2626.782900] [drm:i915_error_work_func], resetting chip
>[ 2626.783588] [drm] Simulated gpu hang, resetting stop_rings
>[ 2626.786802] [drm:init_status_page], render ring hws offset: 0x008ff000
>[ 2626.788334] [drm:init_pipe_control], render ring pipe control offset: 0x00032000
>[ 2626.788352] [drm:init_status_page], bsd ring hws offset: 0x00033000
>[ 2626.788459] [drm:init_status_page], blitter ring hws offset: 0x00054000
>[ 2626.788556] [drm:init_status_page], video enhancement ring hws offset: 0x00075000
>[ 2626.788682] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2626.788685] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2626.788754] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2626.788997] [drm:i915_gem_open], 
>[ 2626.789038] [drm:i915_gem_open], 
>[ 2626.789065] [drm:i915_gem_open], 
>[ 2626.789082] [drm:i915_gem_open], 
>[ 2626.789097] [drm:i915_gem_open], 
>[ 2626.789113] [drm:i915_gem_open], 
>[ 2626.789126] [drm:i915_gem_open], 
>[ 2626.789141] [drm:i915_gem_open], 
>[ 2626.789238] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2632.773137] [drm] stuck on video enhancement ring
>[ 2632.777393] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2632.780920] [drm:i915_error_work_func], resetting chip
>[ 2632.781281] [drm] Simulated gpu hang, resetting stop_rings
>[ 2632.784635] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2632.786180] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2632.786191] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2632.786318] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2632.786427] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2632.786555] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2632.786558] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2632.786625] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2632.786883] [drm:i915_gem_open], 
>[ 2632.786908] [drm:i915_gem_open], 
>[ 2632.786929] [drm:i915_gem_open], 
>[ 2632.786941] [drm:i915_gem_open], 
>[ 2632.787047] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2640.774260] [drm] stuck on video enhancement ring
>[ 2640.778505] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2640.781715] [drm:i915_error_work_func], resetting chip
>[ 2640.781920] [drm] Simulated gpu hang, resetting stop_rings
>[ 2640.785223] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2640.787284] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2640.787305] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2640.787413] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2640.787513] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2640.787635] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2640.787638] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2640.787708] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2640.787886] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2646.772102] [drm] stuck on video enhancement ring
>[ 2646.776345] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2646.779531] [drm:i915_error_work_func], resetting chip
>[ 2646.779753] [drm] Simulated gpu hang, resetting stop_rings
>[ 2646.783404] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2646.785107] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2646.785115] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2646.785241] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2646.785345] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2646.785467] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2646.785470] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2646.785538] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2646.785812] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2652.765944] [drm] stuck on video enhancement ring
>[ 2652.770198] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2652.773399] [drm:i915_error_work_func], resetting chip
>[ 2652.773617] [drm] Simulated gpu hang, resetting stop_rings
>[ 2652.776874] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2652.778952] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2652.778965] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2652.779081] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2652.779186] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2652.779308] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2652.779312] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2652.779378] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2652.779641] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2658.767785] [drm] stuck on video enhancement ring
>[ 2658.772095] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2658.775357] [drm:i915_error_work_func], resetting chip
>[ 2658.775593] [drm] Simulated gpu hang, resetting stop_rings
>[ 2658.779325] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2658.780811] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2658.780820] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2658.780929] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2658.781058] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2658.781180] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2658.781183] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2658.781252] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2658.781547] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2664.765627] [drm] stuck on video enhancement ring
>[ 2664.769965] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2664.773559] [drm:i915_error_work_func], resetting chip
>[ 2664.773861] [drm] Simulated gpu hang, resetting stop_rings
>[ 2664.777863] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2664.779687] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2664.779696] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2664.779802] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2664.779897] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2664.780024] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2664.780027] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2664.780095] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2664.780395] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2670.759452] [drm] stuck on video enhancement ring
>[ 2670.763831] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2670.767295] [drm:i915_error_work_func], resetting chip
>[ 2670.767603] [drm] Simulated gpu hang, resetting stop_rings
>[ 2670.770804] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2670.772493] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2670.772512] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2670.772631] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2670.772746] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2670.772925] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2670.772928] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2670.772997] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2670.773257] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2680.759871] [drm] stuck on video enhancement ring
>[ 2680.764231] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2680.767816] [drm:i915_error_work_func], resetting chip
>[ 2680.768180] [drm] Simulated gpu hang, resetting stop_rings
>[ 2680.772121] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2680.773909] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2680.773924] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2680.774030] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2680.774120] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2680.774245] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2680.774248] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2680.774315] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2680.774540] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2686.753709] [drm] stuck on video enhancement ring
>[ 2686.758070] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2686.761335] [drm:i915_error_work_func], resetting chip
>[ 2686.761719] [drm] Simulated gpu hang, resetting stop_rings
>[ 2686.764927] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2686.766728] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2686.766740] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2686.766866] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2686.766971] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2686.767090] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2686.767093] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2686.767160] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2686.767846] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2692.755554] [drm] stuck on video enhancement ring
>[ 2692.759890] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2692.763192] [drm:i915_error_work_func], resetting chip
>[ 2692.763350] [drm] Simulated gpu hang, resetting stop_rings
>[ 2692.766490] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2692.768547] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2692.768557] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2692.768659] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2692.768763] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2692.768879] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2692.768882] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2692.768948] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2692.769205] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2698.753394] [drm] stuck on video enhancement ring
>[ 2698.757740] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2698.761294] [drm:i915_error_work_func], resetting chip
>[ 2698.761589] [drm] Simulated gpu hang, resetting stop_rings
>[ 2698.765443] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2698.767403] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2698.767411] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2698.767507] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2698.767604] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2698.767723] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2698.767725] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2698.767791] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2698.767999] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2704.747236] [drm] stuck on video enhancement ring
>[ 2704.751604] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2704.755670] [drm:i915_error_work_func], resetting chip
>[ 2704.755879] [drm] Simulated gpu hang, resetting stop_rings
>[ 2704.759434] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2704.761262] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2704.761281] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2704.761393] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2704.761490] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2704.761608] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2704.761611] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2704.761679] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2704.761931] [drm:i915_gem_open], 
>[ 2704.761965] [drm:i915_gem_open], 
>[ 2704.762038] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2714.743637] [drm] stuck on video enhancement ring
>[ 2714.747987] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5205], reason: Ring hung, action: reset
>[ 2714.751278] [drm:i915_error_work_func], resetting chip
>[ 2714.752638] [drm] Simulated gpu hang, resetting stop_rings
>[ 2714.755773] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2714.757673] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2714.757695] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2714.757802] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2714.757894] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2714.758014] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2714.758017] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2714.758082] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2714.759363] [drm:i915_gem_open], 
>[ 2714.759385] [drm:i915_gem_open], 
>[ 2714.759464] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2720.745482] [drm] stuck on video enhancement ring
>[ 2720.749838] [drm] GPU HANG: ecode 3:0x277ffffe, reason: Ring hung, action: reset
>[ 2720.753083] [drm:i915_error_work_func], resetting chip
>[ 2720.753276] [drm] Simulated gpu hang, resetting stop_rings
>[ 2720.756544] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2720.758486] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2720.758495] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2720.758591] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2720.758683] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2720.758804] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2720.758806] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2720.758874] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2720.759074] [drm:i915_gem_open], 
>[ 2720.759107] [drm:i915_gem_open], 
>[ 2720.759220] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2721.759188] [drm:i915_gem_open], 
>[ 2721.759225] [drm:i915_gem_open], 
>[ 2722.758853] [drm:i915_gem_open], 
>[ 2722.758879] [drm:i915_gem_open], 
>[ 2728.742603] [drm] stuck on video enhancement ring
>[ 2728.746949] [drm] GPU HANG: ecode 3:0xa77ffffe, reason: Ring hung, action: reset
>[ 2728.750420] [drm:i915_error_work_func], resetting chip
>[ 2728.750618] [drm] Simulated gpu hang, resetting stop_rings
>[ 2728.753859] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 2728.755617] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 2728.755625] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 2728.755722] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 2728.755812] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 2728.755924] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2728.755926] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2728.755991] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2728.756132] [drm:i915_gem_open], 
>[ 2728.756153] [drm:i915_gem_open], 
>[ 2728.756239] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 2729.756211] [drm:i915_gem_open], 
>[ 2729.756275] [drm:i915_gem_open], 
>[ 2730.755880] [drm:i915_gem_open], 
>[ 2730.755904] [drm:i915_gem_open], 
>[ 2740.734285] [drm] stuck on video enhancement ring
>[ 2740.738649] [drm] GPU HANG: ecode 3:0xa77ffffe, reason: Ring hung, action: reset
>[ 2740.741813] [drm:i915_error_work_func], resetting chip
>[ 2740.742288] [drm] Simulated gpu hang, resetting stop_rings
>[ 2740.745365] [drm:init_status_page], render ring hws offset: 0x00904000
>[ 2740.747317] [drm:init_pipe_control], render ring pipe control offset: 0x00032000
>[ 2740.747333] [drm:init_status_page], bsd ring hws offset: 0x00033000
>[ 2740.747439] [drm:init_status_page], blitter ring hws offset: 0x00054000
>[ 2740.747537] [drm:init_status_page], video enhancement ring hws offset: 0x00075000
>[ 2740.747654] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 2740.747657] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 2740.747721] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 2740.748855] [drm:intel_crtc_cursor_set], cursor off
>[ 2740.748864] [drm:intel_crtc_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[ 2740.748869] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[ 2740.748874] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 2740.748878] [drm:intel_crtc_cursor_set], cursor off
>[ 2740.748880] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 2740.748883] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[ 2740.748887] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 2740.748889] [drm:intel_crtc_cursor_set], cursor off
>[ 2740.748891] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 2740.748894] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
>[ 2740.748897] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 4710.590920] [drm:i915_gem_open], 
>[ 4710.590965] [drm:intel_crtc_cursor_set], cursor off
>[ 4710.590970] [drm:intel_crtc_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[ 4710.590976] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[ 4710.590980] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 4710.590984] [drm:intel_crtc_cursor_set], cursor off
>[ 4710.590987] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 4710.590990] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[ 4710.590993] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 4710.590995] [drm:intel_crtc_cursor_set], cursor off
>[ 4710.590998] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 4710.591001] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
>[ 4710.591004] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 4710.591017] [drm:i915_gem_open], 
>[ 4710.591243] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4710.591258] [drm:i915_gem_open], 
>[ 4710.591273] [drm:i915_gem_open], 
>[ 4710.591290] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4710.592676] [drm:i915_gem_open], 
>[ 4710.592718] [drm:i915_gem_open], 
>[ 4710.592747] [drm:i915_gem_open], 
>[ 4710.592769] [drm:i915_gem_open], 
>[ 4710.592786] [drm:i915_gem_open], 
>[ 4710.592808] [drm:i915_gem_open], 
>[ 4710.592825] [drm:i915_gem_open], 
>[ 4710.592846] [drm:i915_gem_open], 
>[ 4710.593144] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4717.023119] [drm] stuck on render ring
>[ 4717.027437] [drm] GPU HANG: ecode 0:0xe75ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4717.030946] [drm:i915_error_work_func], resetting chip
>[ 4717.031258] [drm] Simulated gpu hang, resetting stop_rings
>[ 4717.034668] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4717.036142] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4717.036152] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4717.036281] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4717.036388] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4717.036511] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4717.036514] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4717.036582] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4717.036949] [drm:i915_gem_open], 
>[ 4717.036974] [drm:i915_gem_open], 
>[ 4717.036995] [drm:i915_gem_open], 
>[ 4717.037011] [drm:i915_gem_open], 
>[ 4717.037024] [drm:i915_gem_open], 
>[ 4717.037039] [drm:i915_gem_open], 
>[ 4717.037051] [drm:i915_gem_open], 
>[ 4717.037066] [drm:i915_gem_open], 
>[ 4717.037712] [drm:i915_gem_open], 
>[ 4717.037740] [drm:i915_gem_open], 
>[ 4717.037765] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4717.037775] [drm:i915_gem_context_create_ioctl], HW context 2 created
>[ 4717.037780] [drm:i915_gem_context_create_ioctl], HW context 3 created
>[ 4717.037785] [drm:i915_gem_context_create_ioctl], HW context 4 created
>[ 4717.037792] [drm:i915_gem_open], 
>[ 4717.037806] [drm:i915_gem_open], 
>[ 4717.037818] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4717.037823] [drm:i915_gem_context_create_ioctl], HW context 2 created
>[ 4717.037827] [drm:i915_gem_context_create_ioctl], HW context 3 created
>[ 4717.037831] [drm:i915_gem_context_create_ioctl], HW context 4 created
>[ 4717.037836] [drm:i915_gem_open], 
>[ 4717.037849] [drm:i915_gem_open], 
>[ 4717.037861] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4717.037865] [drm:i915_gem_context_create_ioctl], HW context 2 created
>[ 4717.037869] [drm:i915_gem_context_create_ioctl], HW context 3 created
>[ 4717.037874] [drm:i915_gem_context_create_ioctl], HW context 4 created
>[ 4717.037879] [drm:i915_gem_open], 
>[ 4717.037894] [drm:i915_gem_open], 
>[ 4717.037906] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4717.037910] [drm:i915_gem_context_create_ioctl], HW context 2 created
>[ 4717.037915] [drm:i915_gem_context_create_ioctl], HW context 3 created
>[ 4717.037919] [drm:i915_gem_context_create_ioctl], HW context 4 created
>[ 4717.038557] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4723.024950] [drm] stuck on render ring
>[ 4723.029275] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4723.032507] [drm:i915_error_work_func], resetting chip
>[ 4723.032717] [drm] Simulated gpu hang, resetting stop_rings
>[ 4723.035779] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4723.037971] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4723.037982] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4723.038109] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4723.038208] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4723.038329] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4723.038332] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4723.038400] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4723.038635] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4723.038665] [drm:i915_gem_context_destroy_ioctl], HW context 2 destroyed
>[ 4723.038693] [drm:i915_gem_context_destroy_ioctl], HW context 3 destroyed
>[ 4723.038723] [drm:i915_gem_context_destroy_ioctl], HW context 4 destroyed
>[ 4723.038767] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4723.038793] [drm:i915_gem_context_destroy_ioctl], HW context 2 destroyed
>[ 4723.038822] [drm:i915_gem_context_destroy_ioctl], HW context 3 destroyed
>[ 4723.038851] [drm:i915_gem_context_destroy_ioctl], HW context 4 destroyed
>[ 4723.038887] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4723.038946] [drm:i915_gem_context_destroy_ioctl], HW context 2 destroyed
>[ 4723.039001] [drm:i915_gem_context_destroy_ioctl], HW context 3 destroyed
>[ 4723.039044] [drm:i915_gem_context_destroy_ioctl], HW context 4 destroyed
>[ 4723.039103] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4723.039148] [drm:i915_gem_context_destroy_ioctl], HW context 2 destroyed
>[ 4723.039190] [drm:i915_gem_context_destroy_ioctl], HW context 3 destroyed
>[ 4723.039230] [drm:i915_gem_context_destroy_ioctl], HW context 4 destroyed
>[ 4723.039317] [drm:i915_gem_open], 
>[ 4723.039359] [drm:i915_gem_open], 
>[ 4723.039391] [drm:i915_gem_open], 
>[ 4723.039416] [drm:i915_gem_open], 
>[ 4723.039864] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4729.018796] [drm] stuck on render ring
>[ 4729.023127] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4729.026732] [drm:i915_error_work_func], resetting chip
>[ 4729.027986] [drm] Simulated gpu hang, resetting stop_rings
>[ 4729.031154] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4729.032818] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4729.032833] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4729.032939] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4729.033035] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4729.033155] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4729.033157] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4729.033227] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4729.033427] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4735.008635] [drm] stuck on render ring
>[ 4735.012954] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4735.016302] [drm:i915_error_work_func], resetting chip
>[ 4735.016684] [drm] Simulated gpu hang, resetting stop_rings
>[ 4735.020286] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4735.021653] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4735.021662] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4735.021789] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4735.021896] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4735.022023] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4735.022026] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4735.022094] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4735.022398] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4741.006474] [drm] stuck on render ring
>[ 4741.010784] [drm] GPU HANG: ecode 0:0xe75ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4741.014123] [drm:i915_error_work_func], resetting chip
>[ 4741.014358] [drm] Simulated gpu hang, resetting stop_rings
>[ 4741.018072] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4741.019508] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4741.019522] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4741.019634] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4741.019737] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4741.019857] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4741.019860] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4741.019928] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4741.020346] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4751.010882] [drm] stuck on render ring
>[ 4751.015222] [drm] GPU HANG: ecode 0:0xe756fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4751.018532] [drm:i915_error_work_func], resetting chip
>[ 4751.018712] [drm] Simulated gpu hang, resetting stop_rings
>[ 4751.022812] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4751.024901] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4751.024911] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4751.025040] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4751.025141] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4751.025262] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4751.025265] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4751.025333] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4751.025634] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4757.000719] [drm] stuck on render ring
>[ 4757.005068] [drm] GPU HANG: ecode 0:0xe756fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4757.008386] [drm:i915_error_work_func], resetting chip
>[ 4757.008569] [drm] Simulated gpu hang, resetting stop_rings
>[ 4757.012681] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4757.014745] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4757.014756] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4757.014885] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4757.014986] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4757.015108] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4757.015111] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4757.015178] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4757.015448] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4763.006562] [drm] stuck on render ring
>[ 4763.010912] [drm] GPU HANG: ecode 0:0xe756fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4763.014494] [drm:i915_error_work_func], resetting chip
>[ 4763.014848] [drm] Simulated gpu hang, resetting stop_rings
>[ 4763.018846] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4763.020598] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4763.020613] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4763.020723] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4763.020818] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4763.020939] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4763.020941] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4763.021009] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4763.021286] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4769.008401] [drm] stuck on render ring
>[ 4769.012778] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4769.016167] [drm:i915_error_work_func], resetting chip
>[ 4769.016364] [drm] Simulated gpu hang, resetting stop_rings
>[ 4769.019512] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4769.019716] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4769.019731] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4769.019910] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4769.020070] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4769.020251] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4769.020256] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4769.020337] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4769.020917] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4775.006242] [drm] stuck on render ring
>[ 4775.010608] [drm] GPU HANG: ecode 0:0xe75ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4775.014252] [drm:i915_error_work_func], resetting chip
>[ 4775.014690] [drm] Simulated gpu hang, resetting stop_rings
>[ 4775.017979] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4775.019249] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4775.019258] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4775.019380] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4775.019485] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4775.019605] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4775.019608] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4775.019676] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4775.019969] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4781.004083] [drm] stuck on render ring
>[ 4781.008453] [drm] GPU HANG: ecode 0:0xe75ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4781.012139] [drm:i915_error_work_func], resetting chip
>[ 4781.012381] [drm] Simulated gpu hang, resetting stop_rings
>[ 4781.015667] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4781.017114] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4781.017123] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4781.017228] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4781.017352] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4781.017472] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4781.017475] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4781.017543] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4781.017812] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4787.001930] [drm] stuck on render ring
>[ 4787.006333] [drm] GPU HANG: ecode 0:0xe756fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4787.009974] [drm:i915_error_work_func], resetting chip
>[ 4787.010411] [drm] Simulated gpu hang, resetting stop_rings
>[ 4787.013708] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4787.014951] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4787.014969] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4787.015076] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4787.015172] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4787.015290] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4787.015294] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4787.015361] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4787.015652] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4792.999766] [drm] stuck on render ring
>[ 4793.004141] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4793.007816] [drm:i915_error_work_func], resetting chip
>[ 4793.008214] [drm] Simulated gpu hang, resetting stop_rings
>[ 4793.011587] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4793.013806] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4793.013819] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4793.013929] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4793.014025] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4793.014143] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4793.014146] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4793.014214] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4793.014569] [drm:i915_gem_open], 
>[ 4793.014595] [drm:i915_gem_open], 
>[ 4793.014619] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4793.014623] [drm:i915_gem_context_create_ioctl], HW context 2 created
>[ 4793.014965] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4798.997609] [drm] stuck on render ring
>[ 4799.002001] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4799.005638] [drm:i915_error_work_func], resetting chip
>[ 4799.005931] [drm] Simulated gpu hang, resetting stop_rings
>[ 4799.009878] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4799.011648] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4799.011661] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4799.011767] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4799.011862] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4799.011980] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4799.011983] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4799.012050] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4799.012254] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4804.991460] [drm] stuck on render ring
>[ 4804.995884] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4804.999221] [drm:i915_error_work_func], resetting chip
>[ 4804.999829] [drm] Simulated gpu hang, resetting stop_rings
>[ 4805.003230] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4805.004467] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4805.004477] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4805.004596] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4805.004701] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4805.004825] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4805.004828] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4805.004902] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4805.005153] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4805.005170] [drm:i915_gem_context_destroy_ioctl], HW context 2 destroyed
>[ 4805.005273] [drm:i915_gem_open], 
>[ 4805.005296] [drm:i915_gem_open], 
>[ 4805.005772] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4814.987867] [drm] stuck on render ring
>[ 4814.992247] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4814.996939] [drm:i915_error_work_func], resetting chip
>[ 4814.997642] [drm] Simulated gpu hang, resetting stop_rings
>[ 4815.000792] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4815.002873] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4815.002887] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4815.002997] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4815.003100] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4815.003224] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4815.003227] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4815.003295] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4815.004886] [drm:i915_gem_open], 
>[ 4815.004913] [drm:i915_gem_open], 
>[ 4815.004934] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4815.005037] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4820.989704] [drm] stuck on render ring
>[ 4820.994140] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4820.997825] [drm:i915_error_work_func], resetting chip
>[ 4820.998102] [drm] Simulated gpu hang, resetting stop_rings
>[ 4821.002056] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4821.003728] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4821.003747] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4821.003854] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4821.003953] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4821.004073] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4821.004076] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4821.004144] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4821.005641] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4821.005756] [drm:i915_gem_open], 
>[ 4821.005798] [drm:i915_gem_open], 
>[ 4821.005828] [drm:i915_gem_open], 
>[ 4821.005853] [drm:i915_gem_open], 
>[ 4821.005878] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4821.005888] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4821.006037] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4826.983542] [drm] stuck on render ring
>[ 4826.987971] [drm] GPU HANG: ecode 0:0xe757fffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4826.991312] [drm:i915_error_work_func], resetting chip
>[ 4826.991505] [drm] Simulated gpu hang, resetting stop_rings
>[ 4826.994788] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4826.996564] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4826.996578] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4826.996686] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4826.996789] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4826.996917] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4826.996920] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4826.996989] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4826.997269] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4826.997289] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4826.997347] [drm:i915_gem_open], 
>[ 4826.997368] [drm:i915_gem_open], 
>[ 4826.997777] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4834.984661] [drm] stuck on render ring
>[ 4834.989088] [drm] GPU HANG: ecode 0:0xe757fffe, reason: Ring hung, action: reset
>[ 4834.992723] [drm:i915_error_work_func], resetting chip
>[ 4834.993024] [drm] Simulated gpu hang, resetting stop_rings
>[ 4834.996981] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4834.998666] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4834.998677] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4834.998799] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4834.998904] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4834.999026] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4834.999029] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4834.999098] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4834.999383] [drm:i915_gem_open], 
>[ 4834.999412] [drm:i915_gem_open], 
>[ 4834.999438] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 4834.999536] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4834.999543] [drm:i915_gem_context_destroy_ioctl], HW context 1 destroyed
>[ 4840.978514] [drm] stuck on render ring
>[ 4840.982916] [drm] GPU HANG: ecode 0:0xe757fffe, reason: Ring hung, action: reset
>[ 4840.987456] [drm:i915_error_work_func], resetting chip
>[ 4840.987740] [drm] Simulated gpu hang, resetting stop_rings
>[ 4840.990891] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4840.992522] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4840.992532] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4840.992660] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4840.992768] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4840.992896] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4840.992900] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4840.992969] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4840.993244] [drm:i915_gem_open], 
>[ 4840.993283] [drm:i915_gem_open], 
>[ 4840.993454] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4841.993542] [drm:i915_gem_open], 
>[ 4841.993589] [drm:i915_gem_open], 
>[ 4842.993219] [drm:i915_gem_open], 
>[ 4842.993271] [drm:i915_gem_open], 
>[ 4848.975632] [drm] stuck on render ring
>[ 4848.980035] [drm] GPU HANG: ecode 0:0xe757fffe, reason: Ring hung, action: reset
>[ 4848.983559] [drm:i915_error_work_func], resetting chip
>[ 4848.984838] [drm] Simulated gpu hang, resetting stop_rings
>[ 4848.988041] [drm:init_status_page], render ring hws offset: 0x00908000
>[ 4848.989637] [drm:init_pipe_control], render ring pipe control offset: 0x00929000
>[ 4848.989646] [drm:init_status_page], bsd ring hws offset: 0x0092a000
>[ 4848.989767] [drm:init_status_page], blitter ring hws offset: 0x00032000
>[ 4848.989871] [drm:init_status_page], video enhancement ring hws offset: 0x00053000
>[ 4848.989992] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4848.989995] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4848.990063] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4848.990257] [drm:i915_gem_open], 
>[ 4848.990282] [drm:i915_gem_open], 
>[ 4848.990434] [drm:i915_ring_stop_set], Stopping rings 0x00000001
>[ 4849.990442] [drm:i915_gem_open], 
>[ 4849.990490] [drm:i915_gem_open], 
>[ 4850.990114] [drm:i915_gem_open], 
>[ 4850.990147] [drm:i915_gem_open], 
>[ 4856.976755] [drm] stuck on render ring
>[ 4856.981157] [drm] GPU HANG: ecode 0:0xe757fffe, reason: Ring hung, action: reset
>[ 4856.984692] [drm:i915_error_work_func], resetting chip
>[ 4856.985236] [drm] Simulated gpu hang, resetting stop_rings
>[ 4856.988900] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4856.990757] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4856.990766] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4856.990870] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4856.990995] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4856.991123] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4856.991126] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4856.991194] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4856.991475] [drm:i915_gem_open], 
>[ 4856.991503] [drm:i915_gem_open], 
>[ 4856.991526] [drm:i915_gem_open], 
>[ 4856.991542] [drm:i915_gem_open], 
>[ 4856.991556] [drm:i915_gem_open], 
>[ 4856.991570] [drm:i915_gem_open], 
>[ 4856.991584] [drm:i915_gem_open], 
>[ 4856.991599] [drm:i915_gem_open], 
>[ 4856.991760] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4862.970586] [drm] stuck on blitter ring
>[ 4862.974927] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4862.978227] [drm:i915_error_work_func], resetting chip
>[ 4862.978412] [drm] Simulated gpu hang, resetting stop_rings
>[ 4862.981634] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4862.983619] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4862.983630] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4862.983742] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4862.983867] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4862.983991] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4862.983993] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4862.984062] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4862.984334] [drm:i915_gem_open], 
>[ 4862.984358] [drm:i915_gem_open], 
>[ 4862.984379] [drm:i915_gem_open], 
>[ 4862.984393] [drm:i915_gem_open], 
>[ 4862.984490] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4868.972427] [drm] stuck on blitter ring
>[ 4868.976778] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4868.980407] [drm:i915_error_work_func], resetting chip
>[ 4868.980689] [drm] Simulated gpu hang, resetting stop_rings
>[ 4868.984052] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4868.985448] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4868.985459] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4868.985580] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4868.985685] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4868.985809] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4868.985812] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4868.985881] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4868.986058] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4874.970280] [drm] stuck on blitter ring
>[ 4874.974610] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4874.978175] [drm:i915_error_work_func], resetting chip
>[ 4874.978523] [drm] Simulated gpu hang, resetting stop_rings
>[ 4874.981885] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4874.983281] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4874.983291] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4874.983412] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4874.983517] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4874.983644] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4874.983647] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4874.983716] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4874.983990] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4880.964121] [drm] stuck on blitter ring
>[ 4880.968467] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4880.973080] [drm:i915_error_work_func], resetting chip
>[ 4880.973872] [drm] Simulated gpu hang, resetting stop_rings
>[ 4880.976994] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4880.979138] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4880.979149] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4880.979257] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4880.979384] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4880.979505] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4880.979508] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4880.979576] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4880.980536] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4886.961968] [drm] stuck on blitter ring
>[ 4886.966322] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4886.970915] [drm:i915_error_work_func], resetting chip
>[ 4886.971269] [drm] Simulated gpu hang, resetting stop_rings
>[ 4886.974412] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4886.975994] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4886.976007] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4886.976125] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4886.976259] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4886.976386] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4886.976389] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4886.976457] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4886.976752] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4896.958358] [drm] stuck on blitter ring
>[ 4896.962694] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4896.966371] [drm:i915_error_work_func], resetting chip
>[ 4896.966803] [drm] Simulated gpu hang, resetting stop_rings
>[ 4896.970083] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4896.971396] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4896.971410] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4896.971521] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4896.971621] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4896.971744] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4896.971746] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4896.971815] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4896.972079] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4902.960195] [drm] stuck on blitter ring
>[ 4902.964534] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4902.968150] [drm:i915_error_work_func], resetting chip
>[ 4902.969581] [drm] Simulated gpu hang, resetting stop_rings
>[ 4902.972789] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4902.974209] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4902.974218] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4902.974339] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4902.974444] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4902.974564] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4902.974566] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4902.974635] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4902.974899] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4908.958039] [drm] stuck on blitter ring
>[ 4908.962382] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4908.965919] [drm:i915_error_work_func], resetting chip
>[ 4908.967324] [drm] Simulated gpu hang, resetting stop_rings
>[ 4908.970734] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4908.972073] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4908.972082] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4908.972187] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4908.972316] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4908.972440] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4908.972442] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4908.972511] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4908.972797] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4914.955893] [drm] stuck on blitter ring
>[ 4914.960236] [drm] GPU HANG: ecode 2:0xe77ffff6, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4914.963823] [drm:i915_error_work_func], resetting chip
>[ 4914.964154] [drm] Simulated gpu hang, resetting stop_rings
>[ 4914.967720] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4914.968883] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4914.968895] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4914.969009] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4914.969114] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4914.969237] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4914.969240] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4914.969309] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4914.969609] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4928.950854] [drm] stuck on blitter ring
>[ 4928.955194] [drm] GPU HANG: ecode 2:0xe77ffff6, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4928.958791] [drm:i915_error_work_func], resetting chip
>[ 4928.959318] [drm] Simulated gpu hang, resetting stop_rings
>[ 4928.963056] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4928.964871] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4928.964880] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4928.964986] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4928.965113] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4928.965232] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4928.965235] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4928.965303] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4928.965574] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4934.944703] [drm] stuck on blitter ring
>[ 4934.949058] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4934.952361] [drm:i915_error_work_func], resetting chip
>[ 4934.952538] [drm] Simulated gpu hang, resetting stop_rings
>[ 4934.955760] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4934.957724] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4934.957739] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4934.957857] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4934.957994] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4934.958118] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4934.958121] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4934.958188] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4934.958453] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4948.943647] [drm] stuck on blitter ring
>[ 4948.947993] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4948.951590] [drm:i915_error_work_func], resetting chip
>[ 4948.951900] [drm] Simulated gpu hang, resetting stop_rings
>[ 4948.955697] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4948.957681] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4948.957697] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4948.957804] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4948.957903] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4948.958027] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4948.958030] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4948.958097] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4948.958378] [drm:i915_gem_open], 
>[ 4948.958406] [drm:i915_gem_open], 
>[ 4948.958499] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4958.936066] [drm] stuck on blitter ring
>[ 4958.940407] [drm] GPU HANG: ecode 2:0xe77ffff2, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4958.943693] [drm:i915_error_work_func], resetting chip
>[ 4958.943892] [drm] Simulated gpu hang, resetting stop_rings
>[ 4958.947114] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4958.949086] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4958.949107] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4958.949218] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4958.949321] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4958.949446] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4958.949449] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4958.949517] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4958.950996] [drm:i915_gem_open], 
>[ 4958.951042] [drm:i915_gem_open], 
>[ 4958.951181] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4968.936452] [drm] stuck on blitter ring
>[ 4968.940803] [drm] GPU HANG: ecode 2:0xe77ffff2, reason: Ring hung, action: reset
>[ 4968.944547] [drm:i915_error_work_func], resetting chip
>[ 4968.944880] [drm] Simulated gpu hang, resetting stop_rings
>[ 4968.948191] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4968.949456] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4968.949466] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4968.949582] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4968.949686] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4968.949809] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4968.949811] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4968.949880] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4968.950274] [drm:i915_gem_open], 
>[ 4968.950303] [drm:i915_gem_open], 
>[ 4968.950371] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4969.950393] [drm:i915_gem_open], 
>[ 4969.950439] [drm:i915_gem_open], 
>[ 4970.950059] [drm:i915_gem_open], 
>[ 4970.950098] [drm:i915_gem_open], 
>[ 4976.929591] [drm] stuck on bsd ring
>[ 4976.932637] [drm] stuck on blitter ring
>[ 4976.936968] [drm] GPU HANG: ecode 1:0xfefffffe, reason: Ring hung, action: reset
>[ 4976.941455] [drm:i915_error_work_func], resetting chip
>[ 4976.941731] [drm] Simulated gpu hang, resetting stop_rings
>[ 4976.944812] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4976.946584] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4976.946594] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4976.946721] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4976.946827] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4976.946950] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4976.946953] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4976.947022] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4976.947209] [drm:i915_gem_open], 
>[ 4976.947242] [drm:i915_gem_open], 
>[ 4976.947378] [drm:i915_ring_stop_set], Stopping rings 0x00000002
>[ 4977.947405] [drm:i915_gem_open], 
>[ 4977.947452] [drm:i915_gem_open], 
>[ 4978.947058] [drm:i915_gem_open], 
>[ 4978.947094] [drm:i915_gem_open], 
>[ 4984.930696] [drm] stuck on blitter ring
>[ 4984.934998] [drm] GPU HANG: ecode 2:0xe77ffff2, reason: Ring hung, action: reset
>[ 4984.938474] [drm:i915_error_work_func], resetting chip
>[ 4984.938811] [drm] Simulated gpu hang, resetting stop_rings
>[ 4984.942647] [drm:init_status_page], render ring hws offset: 0x0090d000
>[ 4984.944720] [drm:init_pipe_control], render ring pipe control offset: 0x00032000
>[ 4984.944729] [drm:init_status_page], bsd ring hws offset: 0x00033000
>[ 4984.944863] [drm:init_status_page], blitter ring hws offset: 0x00054000
>[ 4984.944987] [drm:init_status_page], video enhancement ring hws offset: 0x00075000
>[ 4984.945106] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4984.945109] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4984.945178] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4984.945440] [drm:i915_gem_open], 
>[ 4984.945465] [drm:i915_gem_open], 
>[ 4984.945486] [drm:i915_gem_open], 
>[ 4984.945504] [drm:i915_gem_open], 
>[ 4984.945520] [drm:i915_gem_open], 
>[ 4984.945536] [drm:i915_gem_open], 
>[ 4984.945548] [drm:i915_gem_open], 
>[ 4984.945565] [drm:i915_gem_open], 
>[ 4984.945664] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 4990.924538] [drm] stuck on bsd ring
>[ 4990.928741] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4990.931910] [drm:i915_error_work_func], resetting chip
>[ 4990.932148] [drm] Simulated gpu hang, resetting stop_rings
>[ 4990.935706] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4990.937551] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4990.937561] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4990.937686] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4990.937792] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4990.937915] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4990.937918] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4990.937986] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4990.938297] [drm:i915_gem_open], 
>[ 4990.938335] [drm:i915_gem_open], 
>[ 4990.938359] [drm:i915_gem_open], 
>[ 4990.938375] [drm:i915_gem_open], 
>[ 4990.938469] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 4996.922380] [drm] stuck on bsd ring
>[ 4996.926592] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 4996.930067] [drm:i915_error_work_func], resetting chip
>[ 4996.930386] [drm] Simulated gpu hang, resetting stop_rings
>[ 4996.933661] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 4996.935418] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 4996.935429] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 4996.935558] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 4996.935663] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 4996.935852] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 4996.935856] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 4996.935923] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 4996.936098] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5002.920223] [drm] stuck on bsd ring
>[ 5002.924447] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5002.927977] [drm:i915_error_work_func], resetting chip
>[ 5002.928306] [drm] Simulated gpu hang, resetting stop_rings
>[ 5002.931564] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5002.933237] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5002.933248] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5002.933371] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5002.933479] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5002.933601] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5002.933604] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5002.933673] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5002.933913] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5008.922064] [drm] stuck on bsd ring
>[ 5008.926289] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5008.929516] [drm:i915_error_work_func], resetting chip
>[ 5008.929700] [drm] Simulated gpu hang, resetting stop_rings
>[ 5008.935127] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5008.937067] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5008.937078] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5008.937198] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5008.937306] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5008.937430] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5008.937433] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5008.937502] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5008.938422] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5014.919904] [drm] stuck on bsd ring
>[ 5014.924157] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5014.927433] [drm:i915_error_work_func], resetting chip
>[ 5014.927609] [drm] Simulated gpu hang, resetting stop_rings
>[ 5014.933165] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5014.934919] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5014.934930] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5014.935059] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5014.935169] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5014.935294] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5014.935297] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5014.935366] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5014.936267] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5022.917026] [drm] stuck on bsd ring
>[ 5022.921317] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5022.924864] [drm:i915_error_work_func], resetting chip
>[ 5022.925364] [drm] Simulated gpu hang, resetting stop_rings
>[ 5022.928631] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5022.930054] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5022.930072] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5022.930179] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5022.930275] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5022.930397] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5022.930399] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5022.930468] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5022.930732] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5028.914867] [drm] stuck on bsd ring
>[ 5028.919185] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5028.922742] [drm:i915_error_work_func], resetting chip
>[ 5028.923237] [drm] Simulated gpu hang, resetting stop_rings
>[ 5028.927111] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5028.928909] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5028.928923] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5028.929030] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5028.929130] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5028.929252] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5028.929255] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5028.929322] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5028.929592] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5036.907993] [drm] stuck on bsd ring
>[ 5036.912323] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5036.915857] [drm:i915_error_work_func], resetting chip
>[ 5036.916236] [drm] Simulated gpu hang, resetting stop_rings
>[ 5036.919604] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5036.921016] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5036.921026] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5036.921141] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5036.921250] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5036.921375] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5036.921378] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5036.921446] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5036.921743] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5042.905833] [drm] stuck on bsd ring
>[ 5042.910145] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5042.914730] [drm:i915_error_work_func], resetting chip
>[ 5042.915088] [drm] Simulated gpu hang, resetting stop_rings
>[ 5042.918294] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5042.919843] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5042.919852] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5042.919980] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5042.920084] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5042.920206] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5042.920209] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5042.920277] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5042.920576] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5048.907673] [drm] stuck on bsd ring
>[ 5048.912000] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5048.915557] [drm:i915_error_work_func], resetting chip
>[ 5048.915868] [drm] Simulated gpu hang, resetting stop_rings
>[ 5048.919814] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5048.921682] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5048.921691] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5048.921815] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5048.921920] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5048.922041] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5048.922044] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5048.922114] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5048.922385] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5054.901519] [drm] stuck on bsd ring
>[ 5054.905836] [drm] GPU HANG: ecode 1:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5054.909388] [drm:i915_error_work_func], resetting chip
>[ 5054.909702] [drm] Simulated gpu hang, resetting stop_rings
>[ 5054.912834] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5054.914534] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5054.914552] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5054.914713] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5054.914820] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5054.914949] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5054.914952] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5054.915020] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5054.915315] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5066.897199] [drm] stuck on bsd ring
>[ 5066.901507] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5066.905089] [drm:i915_error_work_func], resetting chip
>[ 5066.905604] [drm] Simulated gpu hang, resetting stop_rings
>[ 5066.908971] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5066.910224] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5066.910234] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5066.910349] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5066.910453] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5066.910576] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5066.910579] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5066.910647] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5066.910957] [drm:i915_gem_open], 
>[ 5066.910985] [drm:i915_gem_open], 
>[ 5066.911065] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5080.892162] [drm] stuck on bsd ring
>[ 5080.896499] [drm] GPU HANG: ecode 1:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5080.901065] [drm:i915_error_work_func], resetting chip
>[ 5080.901332] [drm] Simulated gpu hang, resetting stop_rings
>[ 5080.904536] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5080.906199] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5080.906208] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5080.906339] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5080.906444] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5080.906567] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5080.906570] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5080.906637] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5080.908272] [drm:i915_gem_open], 
>[ 5080.908299] [drm:i915_gem_open], 
>[ 5080.908384] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5084.890729] [drm] stuck on blitter ring
>[ 5084.895070] [drm] GPU HANG: ecode 1:0x277ffffe, reason: Ring hung, action: reset
>[ 5084.899596] [drm:i915_error_work_func], resetting chip
>[ 5084.900013] [drm] Simulated gpu hang, resetting stop_rings
>[ 5084.903161] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5084.904749] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5084.904766] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5084.904875] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5084.904987] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5084.905110] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5084.905113] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5084.905181] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5084.905438] [drm:i915_gem_open], 
>[ 5084.905463] [drm:i915_gem_open], 
>[ 5084.905534] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5085.905542] [drm:i915_gem_open], 
>[ 5085.905591] [drm:i915_gem_open], 
>[ 5086.905207] [drm:i915_gem_open], 
>[ 5086.905242] [drm:i915_gem_open], 
>[ 5092.891845] [drm] stuck on bsd ring
>[ 5092.896143] [drm] GPU HANG: ecode 1:0x277ffffe, reason: Ring hung, action: reset
>[ 5092.899632] [drm:i915_error_work_func], resetting chip
>[ 5092.899943] [drm] Simulated gpu hang, resetting stop_rings
>[ 5092.903939] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5092.905883] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5092.905893] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5092.905997] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5092.906120] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5092.906244] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5092.906247] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5092.906317] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5092.906497] [drm:i915_gem_open], 
>[ 5092.906523] [drm:i915_gem_open], 
>[ 5092.906616] [drm:i915_ring_stop_set], Stopping rings 0x00000004
>[ 5093.906638] [drm:i915_gem_open], 
>[ 5093.906680] [drm:i915_gem_open], 
>[ 5094.906313] [drm:i915_gem_open], 
>[ 5094.906352] [drm:i915_gem_open], 
>[ 5098.885692] [drm] stuck on blitter ring
>[ 5098.889982] [drm] GPU HANG: ecode 1:0x277ffffe, reason: Ring hung, action: reset
>[ 5098.893523] [drm:i915_error_work_func], resetting chip
>[ 5098.893901] [drm] Simulated gpu hang, resetting stop_rings
>[ 5098.896965] [drm:init_status_page], render ring hws offset: 0x00912000
>[ 5098.898728] [drm:init_pipe_control], render ring pipe control offset: 0x00032000
>[ 5098.898753] [drm:init_status_page], bsd ring hws offset: 0x00033000
>[ 5098.898873] [drm:init_status_page], blitter ring hws offset: 0x00054000
>[ 5098.899002] [drm:init_status_page], video enhancement ring hws offset: 0x00075000
>[ 5098.899129] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5098.899132] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5098.899200] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5098.899412] [drm:i915_gem_open], 
>[ 5098.899448] [drm:i915_gem_open], 
>[ 5098.899478] [drm:i915_gem_open], 
>[ 5098.899502] [drm:i915_gem_open], 
>[ 5098.899522] [drm:i915_gem_open], 
>[ 5098.899546] [drm:i915_gem_open], 
>[ 5098.899565] [drm:i915_gem_open], 
>[ 5098.899589] [drm:i915_gem_open], 
>[ 5098.899780] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5104.883530] [drm] stuck on video enhancement ring
>[ 5104.887769] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5104.890987] [drm:i915_error_work_func], resetting chip
>[ 5104.891228] [drm] Simulated gpu hang, resetting stop_rings
>[ 5104.894517] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5104.896570] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5104.896587] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5104.896701] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5104.896804] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5104.896928] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5104.896931] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5104.896999] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5104.897299] [drm:i915_gem_open], 
>[ 5104.897335] [drm:i915_gem_open], 
>[ 5104.897367] [drm:i915_gem_open], 
>[ 5104.897391] [drm:i915_gem_open], 
>[ 5104.897575] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5110.881371] [drm] stuck on video enhancement ring
>[ 5110.885610] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5110.889154] [drm:i915_error_work_func], resetting chip
>[ 5110.889491] [drm] Simulated gpu hang, resetting stop_rings
>[ 5110.892847] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5110.894412] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5110.894422] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5110.894549] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5110.894655] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5110.894784] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5110.894787] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5110.894856] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5110.895021] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5120.881774] [drm] stuck on video enhancement ring
>[ 5120.885997] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5120.889475] [drm:i915_error_work_func], resetting chip
>[ 5120.889797] [drm] Simulated gpu hang, resetting stop_rings
>[ 5120.893160] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5120.894837] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5120.894847] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5120.894956] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5120.895081] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5120.895201] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5120.895204] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5120.895273] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5120.895570] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5126.879616] [drm] stuck on video enhancement ring
>[ 5126.883857] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5126.887072] [drm:i915_error_work_func], resetting chip
>[ 5126.887302] [drm] Simulated gpu hang, resetting stop_rings
>[ 5126.890971] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5126.892644] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5126.892653] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5126.892761] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5126.892891] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5126.893018] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5126.893021] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5126.893088] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5126.893365] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5132.873459] [drm] stuck on video enhancement ring
>[ 5132.877768] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5132.881027] [drm:i915_error_work_func], resetting chip
>[ 5132.881260] [drm] Simulated gpu hang, resetting stop_rings
>[ 5132.884957] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5132.886486] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5132.886496] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5132.886608] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5132.886733] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5132.886861] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5132.886864] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5132.886933] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5132.887235] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5138.871300] [drm] stuck on video enhancement ring
>[ 5138.875634] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5138.878947] [drm:i915_error_work_func], resetting chip
>[ 5138.879179] [drm] Simulated gpu hang, resetting stop_rings
>[ 5138.882882] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5138.884293] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5138.884302] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5138.884438] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5138.884542] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5138.884672] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5138.884675] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5138.884742] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5138.885043] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5150.866980] [drm] stuck on video enhancement ring
>[ 5150.871344] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5150.874658] [drm:i915_error_work_func], resetting chip
>[ 5150.874874] [drm] Simulated gpu hang, resetting stop_rings
>[ 5150.878604] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5150.880007] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5150.880017] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5150.880149] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5150.880257] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5150.880382] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5150.880385] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5150.880452] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5150.880753] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5156.864825] [drm] stuck on video enhancement ring
>[ 5156.869181] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5156.872499] [drm:i915_error_work_func], resetting chip
>[ 5156.872718] [drm] Simulated gpu hang, resetting stop_rings
>[ 5156.876451] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5156.877849] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5156.877866] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5156.877976] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5156.878078] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5156.878208] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5156.878212] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5156.878280] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5156.878574] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5162.862667] [drm] stuck on video enhancement ring
>[ 5162.867040] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5162.870541] [drm:i915_error_work_func], resetting chip
>[ 5162.870803] [drm] Simulated gpu hang, resetting stop_rings
>[ 5162.874456] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5162.875701] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5162.875711] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5162.875838] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5162.875948] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5162.876076] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5162.876079] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5162.876146] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5162.876413] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5172.863067] [drm] stuck on video enhancement ring
>[ 5172.867434] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5172.870761] [drm:i915_error_work_func], resetting chip
>[ 5172.870927] [drm] Simulated gpu hang, resetting stop_rings
>[ 5172.874193] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5172.876102] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5172.876124] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5172.876231] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5172.876329] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5172.876453] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5172.876456] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5172.876524] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5172.876795] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5178.856912] [drm] stuck on video enhancement ring
>[ 5178.861281] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5178.865876] [drm:i915_error_work_func], resetting chip
>[ 5178.866134] [drm] Simulated gpu hang, resetting stop_rings
>[ 5178.869356] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5178.870926] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5178.870937] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5178.871058] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5178.871167] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5178.871290] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5178.871293] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5178.871362] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5178.872391] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5188.853312] [drm] stuck on video enhancement ring
>[ 5188.857685] [drm] GPU HANG: ecode 3:0xa77ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5188.861384] [drm:i915_error_work_func], resetting chip
>[ 5188.861668] [drm] Simulated gpu hang, resetting stop_rings
>[ 5188.865033] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5188.866357] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5188.866371] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5188.866486] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5188.866618] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5188.866746] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5188.866749] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5188.866818] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5188.867088] [drm:i915_gem_open], 
>[ 5188.867114] [drm:i915_gem_open], 
>[ 5188.867199] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5194.855154] [drm] stuck on video enhancement ring
>[ 5194.859491] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5544], reason: Ring hung, action: reset
>[ 5194.862801] [drm:i915_error_work_func], resetting chip
>[ 5194.862985] [drm] Simulated gpu hang, resetting stop_rings
>[ 5194.866653] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5194.868180] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5194.868189] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5194.868287] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5194.868382] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5194.868498] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5194.868500] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5194.868569] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5194.870098] [drm:i915_gem_open], 
>[ 5194.870138] [drm:i915_gem_open], 
>[ 5194.870248] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5208.850118] [drm] stuck on video enhancement ring
>[ 5208.854473] [drm] GPU HANG: ecode 3:0xa77ffffe, reason: Ring hung, action: reset
>[ 5208.857755] [drm:i915_error_work_func], resetting chip
>[ 5208.858159] [drm] Simulated gpu hang, resetting stop_rings
>[ 5208.861593] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5208.863278] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5208.863287] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5208.863385] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5208.863490] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5208.863606] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5208.863609] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5208.863677] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5208.863914] [drm:i915_gem_open], 
>[ 5208.863940] [drm:i915_gem_open], 
>[ 5208.864018] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5209.864012] [drm:i915_gem_open], 
>[ 5209.864054] [drm:i915_gem_open], 
>[ 5210.863675] [drm:i915_gem_open], 
>[ 5210.863704] [drm:i915_gem_open], 
>[ 5216.843239] [drm] stuck on video enhancement ring
>[ 5216.847615] [drm] GPU HANG: ecode 3:0x277ffffe, reason: Ring hung, action: reset
>[ 5216.851103] [drm:i915_error_work_func], resetting chip
>[ 5216.852312] [drm] Simulated gpu hang, resetting stop_rings
>[ 5216.855424] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5216.857248] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5216.857257] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5216.857381] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5216.857487] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5216.857608] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5216.857610] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5216.857679] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5216.857828] [drm:i915_gem_open], 
>[ 5216.857850] [drm:i915_gem_open], 
>[ 5216.857933] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5217.857947] [drm:i915_gem_open], 
>[ 5217.857985] [drm:i915_gem_open], 
>[ 5218.857588] [drm:i915_gem_open], 
>[ 5218.857616] [drm:i915_gem_open], 
>[ 5224.840362] [drm] stuck on video enhancement ring
>[ 5224.844659] [drm] GPU HANG: ecode 3:0x277ffffe, reason: Ring hung, action: reset
>[ 5224.849087] [drm:i915_error_work_func], resetting chip
>[ 5224.849279] [drm] Simulated gpu hang, resetting stop_rings
>[ 5224.852343] [drm:init_status_page], render ring hws offset: 0x00917000
>[ 5224.854370] [drm:init_pipe_control], render ring pipe control offset: 0x00032000
>[ 5224.854378] [drm:init_status_page], bsd ring hws offset: 0x00033000
>[ 5224.854502] [drm:init_status_page], blitter ring hws offset: 0x00054000
>[ 5224.854607] [drm:init_status_page], video enhancement ring hws offset: 0x00075000
>[ 5224.854724] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5224.854727] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5224.854794] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5224.855788] [drm:intel_crtc_cursor_set], cursor off
>[ 5224.855798] [drm:intel_crtc_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[ 5224.855806] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[ 5224.855812] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5224.855818] [drm:intel_crtc_cursor_set], cursor off
>[ 5224.855822] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 5224.855826] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[ 5224.855833] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5224.855837] [drm:intel_crtc_cursor_set], cursor off
>[ 5224.855841] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 5224.855845] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
>[ 5224.855850] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5319.531905] [drm:i915_gem_open], 
>[ 5319.531944] [drm:intel_crtc_cursor_set], cursor off
>[ 5319.531950] [drm:intel_crtc_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[ 5319.531956] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[ 5319.531960] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5319.531965] [drm:intel_crtc_cursor_set], cursor off
>[ 5319.531967] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 5319.531971] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[ 5319.531974] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5319.531977] [drm:intel_crtc_cursor_set], cursor off
>[ 5319.531979] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 5319.531983] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
>[ 5319.531986] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5319.531999] [drm:i915_gem_open], 
>[ 5319.532231] [drm:i915_gem_context_create_ioctl], HW context 1 created
>[ 5319.532458] [drm:i915_gem_open], 
>[ 5319.532488] [drm:i915_gem_open], 
>[ 5319.532511] [drm:i915_gem_open], 
>[ 5319.532532] [drm:i915_gem_open], 
>[ 5319.532673] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5325.808030] [drm] stuck on video enhancement ring
>[ 5325.812266] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5325.815715] [drm:i915_error_work_func], resetting chip
>[ 5325.815988] [drm] Simulated gpu hang, resetting stop_rings
>[ 5325.819821] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5325.821043] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5325.821053] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5325.821172] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5325.821275] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5325.821391] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5325.821393] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5325.821461] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5325.821662] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5331.805871] [drm] stuck on video enhancement ring
>[ 5331.810129] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5331.813560] [drm:i915_error_work_func], resetting chip
>[ 5331.813814] [drm] Simulated gpu hang, resetting stop_rings
>[ 5331.817602] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5331.818880] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5331.818889] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5331.818988] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5331.819109] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5331.819222] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5331.819225] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5331.819292] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5331.819519] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5337.799709] [drm] stuck on video enhancement ring
>[ 5337.804014] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5337.807180] [drm:i915_error_work_func], resetting chip
>[ 5337.807368] [drm] Simulated gpu hang, resetting stop_rings
>[ 5337.810575] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5337.812732] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5337.812743] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5337.812861] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5337.812965] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5337.813082] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5337.813085] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5337.813150] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5337.813358] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5351.798677] [drm] stuck on video enhancement ring
>[ 5351.802892] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5351.806707] [drm:i915_error_work_func], resetting chip
>[ 5351.806902] [drm] Simulated gpu hang, resetting stop_rings
>[ 5351.810148] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5351.811709] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5351.811731] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5351.811838] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5351.811931] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5351.812050] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5351.812053] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5351.812120] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5351.813114] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5361.791081] [drm] stuck on video enhancement ring
>[ 5361.795347] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5361.798931] [drm:i915_error_work_func], resetting chip
>[ 5361.799201] [drm] Simulated gpu hang, resetting stop_rings
>[ 5361.802500] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5361.804094] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5361.804103] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5361.804208] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5361.804334] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5361.804453] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5361.804456] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5361.804523] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5361.804759] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5373.786762] [drm] stuck on video enhancement ring
>[ 5373.791053] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5373.794641] [drm:i915_error_work_func], resetting chip
>[ 5373.794987] [drm] Simulated gpu hang, resetting stop_rings
>[ 5373.798309] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5373.799774] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5373.799783] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5373.799907] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5373.800010] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5373.800133] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5373.800136] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5373.800202] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5373.800405] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5379.788603] [drm] stuck on video enhancement ring
>[ 5379.792940] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5379.796196] [drm:i915_error_work_func], resetting chip
>[ 5379.796376] [drm] Simulated gpu hang, resetting stop_rings
>[ 5379.799985] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5379.801608] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5379.801617] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5379.801712] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5379.801804] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5379.801919] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5379.801922] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5379.801987] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5379.802206] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5385.786445] [drm] stuck on video enhancement ring
>[ 5385.790998] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5385.795362] [drm:i915_error_work_func], resetting chip
>[ 5385.795664] [drm] Simulated gpu hang, resetting stop_rings
>[ 5385.798816] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5385.800450] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5385.800458] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5385.800555] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5385.800646] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5385.800758] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5385.800761] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5385.800824] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5385.801043] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5391.780285] [drm] stuck on video enhancement ring
>[ 5391.784982] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5391.788539] [drm:i915_error_work_func], resetting chip
>[ 5391.788778] [drm] Simulated gpu hang, resetting stop_rings
>[ 5391.792077] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5391.793299] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5391.793307] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5391.793408] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5391.793530] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5391.793644] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5391.793646] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5391.793707] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5391.793908] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5397.782128] [drm] stuck on video enhancement ring
>[ 5397.786498] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5397.790010] [drm:i915_error_work_func], resetting chip
>[ 5397.790272] [drm] Simulated gpu hang, resetting stop_rings
>[ 5397.794063] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5397.796132] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5397.796140] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5397.796236] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5397.796327] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5397.796441] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5397.796443] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5397.796506] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5397.796699] [drm:i915_ring_stop_set], Stopping rings 0x00000008
>[ 5407.774528] [drm] stuck on video enhancement ring
>[ 5407.779213] [drm] GPU HANG: ecode 3:0x277ffffe, in gem_reset_stats [5885], reason: Ring hung, action: reset
>[ 5407.783314] [drm:i915_error_work_func], resetting chip
>[ 5407.783702] [drm] Simulated gpu hang, resetting stop_rings
>[ 5407.786920] [drm:init_status_page], render ring hws offset: 0x00012000
>[ 5407.788539] [drm:init_pipe_control], render ring pipe control offset: 0x00033000
>[ 5407.788547] [drm:init_status_page], bsd ring hws offset: 0x00034000
>[ 5407.788648] [drm:init_status_page], blitter ring hws offset: 0x00055000
>[ 5407.788741] [drm:init_status_page], video enhancement ring hws offset: 0x00076000
>[ 5407.788854] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe B
>[ 5407.788857] [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe C
>[ 5407.788917] [drm:ironlake_update_plane], Writing base 00097000 00000000 0 0 7680
>[ 5407.789732] [drm:intel_crtc_cursor_set], cursor off
>[ 5407.789741] [drm:intel_crtc_set_config], [CRTC:3] [FB:23] #connectors=1 (x y) (0 0)
>[ 5407.789749] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
>[ 5407.789755] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5407.789761] [drm:intel_crtc_cursor_set], cursor off
>[ 5407.789765] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
>[ 5407.789770] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[ 5407.789775] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
>[ 5407.789780] [drm:intel_crtc_cursor_set], cursor off
>[ 5407.789783] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
>[ 5407.789788] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
>[ 5407.789793] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]

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Attachments on bug 75876: 95291 | 95904

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