Attachment 97303 Details for Bug 77368 – Log by "reproducer"

Log by "reproducer"

intel-debug.txt (text/plain), 28.73 KB, created by Florian Echtler on 2014-04-13 10:56:36 UTC

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Creator: Florian Echtler

Created: 2014-04-13 10:56:36 UTC

Size: 28.73 KB

patch

obsolete

>bo_create: buf 3 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=0, open=1, limit=-1
>bo_map: 3 (batchbuffer), map_count=1
>bo_map: 3 (batchbuffer) -> 0x7fcd2f67e000
>bo_create: buf 4 (pipe_control workaround) 4096b
>bo_create: buf 5 (program cache) 4096b
>drm_intel_gem_bo_purge_vma_cache: cached=0, open=2, limit=-1
>bo_map: 4 (pipe_control workaround), map_count=1
>bo_map: 4 (pipe_control workaround) -> 0x7fcd2f67d000
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>../../../../../../../src/mesa/drivers/dri/i965/intel_extensions.c:86: Batchbuffer flush with   60b (pkt) +    0b (state) =   60b (0.2%)
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>BO 4 (pipe_control workaround) migrated: 0x00000000 -> 0x07d78000
>BO 3 (batchbuffer) migrated: 0x00000000 -> 0x07d79000
> 0: 4 (pipe_control workaround)
> 1: 3 (batchbuffer)@0x00000038 -> 4 (pipe_control workaround)@0x07d78000 + 0x00000190
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fcd2f67e000
>0x07d79000:      0x00000000: MI_NOOP
>0x07d79004:      0x61020000: STATE_SIP
>0x07d79008:      0x00000000:    dword 1
>0x07d7900c:      0x00000001: MI_NOOP
>0x07d79010:      0x11000001: MI_LOAD_REGISTER_IMM
>0x07d79014:      0x00005280:    dword 1
>0x07d79018:      0x1337d0d0:    dword 2
>0x07d7901c:      0x7a000003: PIPE_CONTROL
>0x07d79020:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x07d79024:      0x00000000:    destination address
>0x07d79028:      0x00000000:    immediate dword low
>0x07d7902c:      0x00000000:    immediate dword high
>0x07d79030:      0x12000001: MI_STORE_REGISTER_MEM
>0x07d79034:      0x00005280:    dword 1
>0x07d79038:      0x07d78190:    dword 2
>0x07d7903c:      0x05000000: MI_BATCH_BUFFER_END
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fcd2f67e000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>waiting for idle
>bo_create: buf 6 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer), map_count=1
>bo_map: 6 (batchbuffer) -> 0x7fcd2f674000
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fcd2f67d000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fcd2f67d000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>../../../../../../../src/mesa/drivers/dri/i965/intel_extensions.c:144: Batchbuffer flush with   76b (pkt) +    0b (state) =   76b (0.2%)
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>BO 6 (batchbuffer) migrated: 0x00000000 -> 0x07d92000
> 0: 4 (pipe_control workaround)
> 1: 6 (batchbuffer)@0x00000028 -> 4 (pipe_control workaround)@0x07d78000 + 0x000001b8
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fcd2f674000
>Monitors: (OA users = 0)
>0x07d92000:      0x11000001: MI_LOAD_REGISTER_IMM
>0x07d92004:      0x00002360:    dword 1
>0x07d92008:      0x31337000:    dword 2
>0x07d9200c:      0x7a000003: PIPE_CONTROL
>0x07d92010:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x07d92014:      0x00000000:    destination address
>0x07d92018:      0x00000000:    immediate dword low
>0x07d9201c:      0x00000000:    immediate dword high
>0x07d92020:      0x12000001: MI_STORE_REGISTER_MEM
>0x07d92024:      0x00002360:    dword 1
>0x07d92028:      0x07d781b8:    dword 2
>0x07d9202c:      0x7a000003: PIPE_CONTROL
>0x07d92030:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x07d92034:      0x00000000:    destination address
>0x07d92038:      0x00000000:    immediate dword low
>0x07d9203c:      0x00000000:    immediate dword high
>0x07d92040:      0x11000001: MI_LOAD_REGISTER_IMM
>0x07d92044:      0x00002360:    dword 1
>0x07d92048:      0x00000000:    dword 2
>0x07d9204c:      0x05000000: MI_BATCH_BUFFER_END
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fcd2f674000
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>waiting for idle
>bo_create: buf 7 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=1, limit=-1
>bo_map: 7 (batchbuffer), map_count=1
>bo_map: 7 (batchbuffer) -> 0x7fcd2f66c000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fcd2f67d000
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=1, limit=-1
>bo_create: buf 8 (shader time) 262144b
>enter intel_update_renderbuffers, drawable 0x1547f00
>enter intel_update_dri2_buffers, drawable 0x1547f00
>attaching buffer 77, at 1, cpp 4, pitch 4096
>bo_create_from_handle: 77 (dri2 back buffer)
>bo_create: buf 10 (region) 16777216b
>bo_create: buf 11 (region) 2097152b
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=2, limit=-1
>bo_map_gtt: mmap 11 (region), map_count=1
>bo_map_gtt: 11 (region) -> 0x7fcd287d1000
>drm_intel_gem_bo_purge_vma_cache: cached=4, open=1, limit=-1
>bo_create: buf 12 (region) 16777216b
>bo_create: buf 13 (region) 16777216b
>bo_create: buf 14 (region) 4194304b
>before glBufferData(GL_PIXEL_UNPACK_BUFFER_EXT, size, NULL, GL_STREAM_DRAW)
>bo_create: buf 15 (bufferobj) 2097152b
>after glBufferData(GL_PIXEL_UNPACK_BUFFER_EXT, size, NULL, GL_STREAM_DRAW)
>Monitors: (OA users = 0)
>intel_region_alloc_internal <-- 0x123d4b0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x1808bf0
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x1808ea0
>intel_miptree_set_level_info level 0 size: 1024,512,8 offset 0,0
>intel_miptree_set_image_offset level 0 img 0 pos 0,0
>intel_miptree_set_image_offset level 0 img 1 pos 0,512
>intel_miptree_set_image_offset level 0 img 2 pos 0,1024
>intel_miptree_set_image_offset level 0 img 3 pos 0,1536
>intel_miptree_set_image_offset level 0 img 4 pos 0,2048
>intel_miptree_set_image_offset level 0 img 5 pos 0,2560
>intel_miptree_set_image_offset level 0 img 6 pos 0,3072
>intel_miptree_set_image_offset level 0 img 7 pos 0,3584
>brw_miptree_layout: 1024x4096x4
>intel_region_alloc_internal <-- 0x16221a0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_R_UINT32 level 0..0 <-- 0x1809320
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intel_region_alloc_internal <-- 0x1624010
>intel_region_release 0x123d4b0 0
>intel_alloc_renderbuffer_storage: GL_DEPTH_COMPONENT: MESA_FORMAT_Z24_UNORM_X8_UINT (1024x512)
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_Z24_UNORM_X8_UINT level 0..0 <-- 0x18096d0
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x4
>intel_region_alloc_internal <-- 0x123d4b0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_Z24_UNORM_X8_UINT level 0..0 <-- 0x1809a80
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x4
>intel_region_alloc_internal <-- 0x1623560
>intel_alloc_renderbuffer_storage: GL_STENCIL_INDEX: MESA_FORMAT_S_UINT8 (1024x512)
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_S_UINT8 level 0..0 <-- 0x1809e30
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x1
>intel_region_alloc_internal <-- 0x1603140
>bo_create: buf 3 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=0, open=1, limit=-1
>bo_map: 3 (batchbuffer), map_count=1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>bo_create: buf 4 (pipe_control workaround) 4096b
>bo_create: buf 5 (program cache) 4096b
>drm_intel_gem_bo_purge_vma_cache: cached=0, open=2, limit=-1
>bo_map: 4 (pipe_control workaround), map_count=1
>bo_map: 4 (pipe_control workaround) -> 0x7fe10722b000
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>../../../../../../../src/mesa/drivers/dri/i965/intel_extensions.c:86: Batchbuffer flush with   60b (pkt) +    0b (state) =   60b (0.2%)
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>BO 4 (pipe_control workaround) migrated: 0x00000000 -> 0x156ce000
>BO 3 (batchbuffer) migrated: 0x00000000 -> 0x156cf000
> 0: 4 (pipe_control workaround)
> 1: 3 (batchbuffer)@0x00000038 -> 4 (pipe_control workaround)@0x156ce000 + 0x00000190
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>0x156cf000:      0x00000000: MI_NOOP
>0x156cf004:      0x61020000: STATE_SIP
>0x156cf008:      0x00000000:    dword 1
>0x156cf00c:      0x00000001: MI_NOOP
>0x156cf010:      0x11000001: MI_LOAD_REGISTER_IMM
>0x156cf014:      0x00005280:    dword 1
>0x156cf018:      0x1337d0d0:    dword 2
>0x156cf01c:      0x7a000003: PIPE_CONTROL
>0x156cf020:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x156cf024:      0x00000000:    destination address
>0x156cf028:      0x00000000:    immediate dword low
>0x156cf02c:      0x00000000:    immediate dword high
>0x156cf030:      0x12000001: MI_STORE_REGISTER_MEM
>0x156cf034:      0x00005280:    dword 1
>0x156cf038:      0x156ce190:    dword 2
>0x156cf03c:      0x05000000: MI_BATCH_BUFFER_END
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=0, limit=-1
>waiting for idle
>bo_create: buf 6 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer), map_count=1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fe10722b000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=1, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fe10722b000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>../../../../../../../src/mesa/drivers/dri/i965/intel_extensions.c:144: Batchbuffer flush with   76b (pkt) +    0b (state) =   76b (0.2%)
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>BO 6 (batchbuffer) migrated: 0x00000000 -> 0x18da2000
> 0: 4 (pipe_control workaround)
> 1: 6 (batchbuffer)@0x00000028 -> 4 (pipe_control workaround)@0x156ce000 + 0x000001b8
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>Monitors: (OA users = 0)
>0x18da2000:      0x11000001: MI_LOAD_REGISTER_IMM
>0x18da2004:      0x00002360:    dword 1
>0x18da2008:      0x31337000:    dword 2
>0x18da200c:      0x7a000003: PIPE_CONTROL
>0x18da2010:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x18da2014:      0x00000000:    destination address
>0x18da2018:      0x00000000:    immediate dword low
>0x18da201c:      0x00000000:    immediate dword high
>0x18da2020:      0x12000001: MI_STORE_REGISTER_MEM
>0x18da2024:      0x00002360:    dword 1
>0x18da2028:      0x156ce1b8:    dword 2
>0x18da202c:      0x7a000003: PIPE_CONTROL
>0x18da2030:      0x00101c11:    no write, cs stall, render target cache flush, instruction cache invalidate, texture cache invalidate, vf fetch invalidate, depth cache flush, 
>0x18da2034:      0x00000000:    destination address
>0x18da2038:      0x00000000:    immediate dword low
>0x18da203c:      0x00000000:    immediate dword high
>0x18da2040:      0x11000001: MI_LOAD_REGISTER_IMM
>0x18da2044:      0x00002360:    dword 1
>0x18da2048:      0x00000000:    dword 2
>0x18da204c:      0x05000000: MI_BATCH_BUFFER_END
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=0, limit=-1
>waiting for idle
>bo_create: buf 7 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=1, limit=-1
>bo_map: 7 (batchbuffer), map_count=1
>bo_map: 7 (batchbuffer) -> 0x7fe10721a000
>drm_intel_gem_bo_purge_vma_cache: cached=2, open=2, limit=-1
>bo_map: 4 (pipe_control workaround) -> 0x7fe10722b000
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=1, limit=-1
>bo_create: buf 8 (shader time) 262144b
>enter intel_update_renderbuffers, drawable 0x202df00
>enter intel_update_dri2_buffers, drawable 0x202df00
>attaching buffer 77, at 1, cpp 4, pitch 4096
>bo_create_from_handle: 77 (dri2 back buffer)
>bo_create: buf 10 (region) 16777216b
>bo_create: buf 11 (region) 2097152b
>drm_intel_gem_bo_purge_vma_cache: cached=3, open=2, limit=-1
>bo_map_gtt: mmap 11 (region), map_count=1
>bo_map_gtt: 11 (region) -> 0x7fe10037f000
>drm_intel_gem_bo_purge_vma_cache: cached=4, open=1, limit=-1
>bo_create: buf 12 (region) 16777216b
>bo_create: buf 13 (region) 16777216b
>bo_create: buf 14 (region) 4194304b
>before glBufferData(GL_PIXEL_UNPACK_BUFFER_EXT, size, NULL, GL_STREAM_DRAW)
>bo_create: buf 15 (bufferobj) 2097152b
>after glBufferData(GL_PIXEL_UNPACK_BUFFER_EXT, size, NULL, GL_STREAM_DRAW)
>before glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>drm_intel_gem_bo_purge_vma_cache: cached=4, open=2, limit=-1
>bo_map_gtt: mmap 15 (bufferobj), map_count=1
>bo_map_gtt: 15 (bufferobj) -> 0x7fe0fff7e000
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=1, limit=-1
>after glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>before glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>Monitors: (OA users = 0)
>intel_region_alloc_internal <-- 0x1d234b0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x22eebf0
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x22eeea0
>intel_miptree_set_level_info level 0 size: 1024,512,8 offset 0,0
>intel_miptree_set_image_offset level 0 img 0 pos 0,0
>intel_miptree_set_image_offset level 0 img 1 pos 0,512
>intel_miptree_set_image_offset level 0 img 2 pos 0,1024
>intel_miptree_set_image_offset level 0 img 3 pos 0,1536
>intel_miptree_set_image_offset level 0 img 4 pos 0,2048
>intel_miptree_set_image_offset level 0 img 5 pos 0,2560
>intel_miptree_set_image_offset level 0 img 6 pos 0,3072
>intel_miptree_set_image_offset level 0 img 7 pos 0,3584
>brw_miptree_layout: 1024x4096x4
>intel_region_alloc_internal <-- 0x21081a0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_R_UINT32 level 0..0 <-- 0x22ef320
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intel_region_alloc_internal <-- 0x210a010
>intel_region_release 0x1d234b0 0
>intel_alloc_renderbuffer_storage: GL_DEPTH_COMPONENT: MESA_FORMAT_Z24_UNORM_X8_UINT (1024x512)
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_Z24_UNORM_X8_UINT level 0..0 <-- 0x22ef6d0
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x4
>intel_region_alloc_internal <-- 0x1d234b0
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_Z24_UNORM_X8_UINT level 0..0 <-- 0x22efa80
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x4
>intel_region_alloc_internal <-- 0x2109560
>intel_alloc_renderbuffer_storage: GL_STENCIL_INDEX: MESA_FORMAT_S_UINT8 (1024x512)
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_S_UINT8 level 0..0 <-- 0x22efe30
>intel_miptree_set_level_info level 0 size: 4096,1024,1 offset 0,0
>brw_miptree_layout: 4096x1024x1
>intel_region_alloc_internal <-- 0x20e9140
>GLSL IR for native fragment shader 0:
>(
>(declare (shader_in ) vec4 gl_Color)
>(declare (shader_out ) vec4 gl_FragColor)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (xyzw) (var_ref gl_FragColor)  (var_ref gl_Color) ) 
>    ))
>
>)
>
>
>)
>
>Native code for fragment shader 0 (SIMD8 dispatch):
>   START B0
>   shader time start
>0x00000000: mov(8)          g6<1>UD         ARF192<0,1,0>UD                 { align1 WE_all 1Q };
>   (declare (shader_in ) vec4 gl_Color)
>0x00000010: pln.sat(8)      g113<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q };
>0x00000020: pln.sat(8)      g114<1>F        g4.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q };
>0x00000030: pln.sat(8)      g115<1>F        g5<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q };
>0x00000040: pln.sat(8)      g116<1>F        g5.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q };
>   shader time end
>0x00000050: mov(8)          g11<1>UD        ARF192<0,1,0>UD                 { align1 WE_all 1Q };
>0x00000060: and.e.f0(8)     null            g11.2<0,1,0>UD  0x00000001UD    { align1 WE_normal 1Q };
>0x00000070: (+f0) if(8) 0 0                 null            0x00000000UD    { align1 WE_normal 1Q switch };
>   END B0 ->B1 ->B2
>   START B1 <-B0
>0x00000080: add(8)          g12<1>UD        -g6<0,1,0>UD    g11<0,1,0>UD    { align1 WE_normal 1Q };
>0x00000090: mov(1)          g9<1>D          64D                             { align1 WE_all };
>0x000000a0: mov(1)          g10<1>UD        0x00000001UD                    { align1 WE_all };
>0x000000b0: send(1)         null            g9<0,1,0>F
>                data (1, 7, 6) mlen 2 rlen 0                    { align1 WE_all };
>0x000000c0: add(8)          g12<1>UD        g12<8,8,1>UD    0xfffffffeUD    { align1 WE_normal 1Q };
>0x000000d0: mov(1)          g7<1>D          0D                              { align1 WE_all };
>0x000000e0: mov(1)          g8<1>UD         g12<0,1,0>UD        
>bo_create: buf 16 (program cache) 4096b
>bo_unreference final: 5 (program cache)
>drm_check_space: total 18464kb vs bufgr 2083012kb
>after glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>before glXSwapBuffers(dpy, w)
>../../../../../../../src/mesa/drivers/dri/i965/intel_screen.c:190: Batchbuffer flush with  104b (pkt) +    0b (state) =  104b (0.3%)
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=0, limit=-1
>BO 10 (region) migrated: 0x00000000 -> 0x1922e000
>BO 15 (bufferobj) migrated: 0x00000000 -> 0x0f20a000
>BO 7 (batchbuffer) migrated: 0x00000000 -> 0x1a22e000
> 0: 10 (region)
> 1: 15 (bufferobj)
> 2: 7 (batchbuffer)@0x0000002c -> 10 (region)@0x1922e000 + 0x00000000
> 2: 7 (batchbuffer)@0x00000038 -> 15 (bufferobj)@0x0f20a000 + 0x00000000
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=1, limit=-1
>bo_map: 7 (batchbuffer) -> 0x7fe10721a000
>            { align1 WE_all };
>0x000000f0: send(1)         null            g7<0,1,0>F
>                data (1, 7, 6) mlen 2 rlen 0                    { align1 WE_all };
>0x00000100: else(8) 0                       null            0x00000000UD    { align1 WE_normal 1Q switch };
>   END B1 ->B3
>   START B2 <-B0
>0x00000110: mov(1)          g13<1>D         128D                            { align1 WE_all };
>0x00000120: mov(1)          g14<1>UD        0x00000001UD                    { align1 WE_all };
>0x00000130: send(1)         null            g13<0,1,0>F
>                data (1, 7, 6) mlen 2 rlen 0                    { align1 WE_all };
>   END B2 ->B3
>   START B3 <-B2 <-B1
>0x00000140: endif(8) 2                      null            0x00000002UD    { align1 WE_normal 1Q switch };
>0x00000150: sendc(8)        null            g113<8,8,1>F
>                render ( RT write, 0, 4, 12) mlen 4 rlen 0      { align1 WE_normal 1Q EOT };
>   END B3
>
>do_blit_drawpixels
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x230a9b0
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intelEmitCopyBlit src:buf(0x22f1570)/-4096+0 0,0 dst:buf(0x22ef220)/4096+0 0,0 sz:1024x512
>intel_miptree_release 0x230a9b0 refcount will be 0
>intel_miptree_release deleting 0x230a9b0
>intel_region_release 0x1f89b40 0
>do_blit_drawpixels: success
>0x1a22e000:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x1a22e004:      0x00000000:    address
>0x1a22e008:      0x00000000:    dword
>0x1a22e00c:      0x00000000:    upper dword
>0x1a22e010:      0x11000001: MI_LOAD_REGISTER_IMM
>0x1a22e014:      0x00022200:    dword 1
>0x1a22e018:      0x00030002:    dword 2
>0x1a22e01c:      0x54f00806: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 0, dst tile 1)
>0x1a22e020:      0x03cc0400:    format 8888, pitch 1024, rop 0xcc, clipping disabled,  
>0x1a22e024:      0x00000000:    dst (0,0)
>0x1a22e028:      0x02000400:    dst (1024,512)
>0x1a22e02c:      0x1922e000:    dst offset 0x1922e000
>0x1a22e030:      0x00000000:    src (0,0)
>0x1a22e034:      0x0000f000:    src pitch -4096
>0x1a22e038:      0x0f20a000:    src offset 0x0f20a000
>0x1a22e03c:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x1a22e040:      0x00000000:    address
>0x1a22e044:      0x00000000:    dword
>0x1a22e048:      0x00000000:    upper dword
>0x1a22e04c:      0x11000001: MI_LOAD_REGISTER_IMM
>0x1a22e050:      0x00022200:    dword 1
>0x1a22e054:      0x00030000:    dword 2
>0x1a22e058:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x1a22e05c:      0x00000000:    address
>0x1a22e060:      0x00000000:    dword
>0x1a22e064:      0x00000000:    upper dword
>0x1a22e068:      0x05000000: MI_BATCH_BUFFER_END
>0x1a22e06c:      0x00000000:    
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=1, limit=-1
>bo_map: 7 (batchbuffer) -> 0x7fe10721a000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=0, limit=-1
>waiting for idle
>bo_unreference final: 6 (batchbuffer)
>bo_create: buf 6 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=2, limit=-1
>bo_map: 8 (shader time), map_count=1
>bo_map: 8 (shader time) -> 0x7fe107152000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>after glXSwapBuffers(dpy, w)
>before glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>after glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>before glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>enter intel_update_renderbuffers, drawable 0x202df00
>enter intel_update_dri2_buffers, drawable 0x202df00
>bo_unreference final: 3 (batchbuffer)
>drm_check_space: total 18464kb vs bufgr 2083012kb
>after glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>before glXSwapBuffers(dpy, w)
>../../../../../../../src/mesa/drivers/dri/i965/intel_screen.c:190: Batchbuffer flush with  104b (pkt) +    0b (state) =  104b (0.3%)
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
> 0: 10 (region)
> 1: 15 (bufferobj)
> 2: 6 (batchbuffer)@0x0000002c -> 10 (region)@0x1922e000 + 0x00000000
> 2: 6 (batchbuffer)@0x00000038 -> 15 (bufferobj)@0x0f20a000 + 0x00000000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>Monitors: (OA users = 0)
>do_blit_drawpixels
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x230a9b0
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intelEmitCopyBlit src:buf(0x22f1570)/-4096+0 0,0 dst:buf(0x22ef220)/4096+0 0,0 sz:1024x512
>intel_miptree_release 0x230a9b0 refcount will be 0
>intel_miptree_release deleting 0x230a9b0
>intel_region_release 0x1eef880 0
>do_blit_drawpixels: success
>0x18da2000:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x18da2004:      0x00000000:    address
>0x18da2008:      0x00000000:    dword
>0x18da200c:      0x00000000:    upper dword
>0x18da2010:      0x11000001: MI_LOAD_REGISTER_IMM
>0x18da2014:      0x00022200:    dword 1
>0x18da2018:      0x00030002:    dword 2
>0x18da201c:      0x54f00806: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 0, dst tile 1)
>0x18da2020:      0x03cc0400:    format 8888, pitch 1024, rop 0xcc, clipping disabled,  
>0x18da2024:      0x00000000:    dst (0,0)
>0x18da2028:      0x02000400:    dst (1024,512)
>0x18da202c:      0x1922e000:    dst offset 0x1922e000
>0x18da2030:      0x00000000:    src (0,0)
>0x18da2034:      0x0000f000:    src pitch -4096
>0x18da2038:      0x0f20a000:    src offset 0x0f20a000
>0x18da203c:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x18da2040:      0x00000000:    address
>0x18da2044:      0x00000000:    dword
>0x18da2048:      0x00000000:    upper dword
>0x18da204c:      0x11000001: MI_LOAD_REGISTER_IMM
>0x18da2050:      0x00022200:    dword 1
>0x18da2054:      0x00030000:    dword 2
>0x18da2058:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x18da205c:      0x00000000:    address
>0x18da2060:      0x00000000:    dword
>0x18da2064:      0x00000000:    upper dword
>0x18da2068:      0x05000000: MI_BATCH_BUFFER_END
>0x18da206c:      0x00000000:    
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 6 (batchbuffer) -> 0x7fe107222000
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
>waiting for idle
>bo_unreference final: 7 (batchbuffer)
>bo_create: buf 3 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=2, limit=-1
>bo_map: 8 (shader time) -> 0x7fe107152000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>after glXSwapBuffers(dpy, w)
>before glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>after glBufferSubData(GL_PIXEL_UNPACK_BUFFER_EXT, 0, size - i * 4, pixeldata + i)
>before glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>enter intel_update_renderbuffers, drawable 0x202df00
>enter intel_update_dri2_buffers, drawable 0x202df00
>drm_check_space: total 18464kb vs bufgr 2083012kb
>after glDrawPixels(width, height, GL_BGRA, GL_UNSIGNED_BYTE, NULL)
>before glXSwapBuffers(dpy, w)
>../../../../../../../src/mesa/drivers/dri/i965/intel_screen.c:190: Batchbuffer flush with  104b (pkt) +    0b (state) =  104b (0.3%)
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
> 0: 10 (region)
> 1: 15 (bufferobj)
> 2: 3 (batchbuffer)@0x0000002c -> 10 (region)@0x1922e000 + 0x00000000
> 2: 3 (batchbuffer)@0x00000038 -> 15 (bufferobj)@0x0f20a000 + 0x00000000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>Monitors: (OA users = 0)
>do_blit_drawpixels
>intel_miptree_create_layout target GL_TEXTURE_2D format MESA_FORMAT_B8G8R8A8_SRGB level 0..0 <-- 0x230a9b0
>intel_miptree_set_level_info level 0 size: 1024,512,1 offset 0,0
>brw_miptree_layout: 1024x512x4
>intelEmitCopyBlit src:buf(0x22f1570)/-4096+0 0,0 dst:buf(0x22ef220)/4096+0 0,0 sz:1024x512
>intel_miptree_release 0x230a9b0 refcount will be 0
>intel_miptree_release deleting 0x230a9b0
>intel_region_release 0x1f4f7c0 0
>do_blit_drawpixels: success
>0x156cf000:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x156cf004:      0x00000000:    address
>0x156cf008:      0x00000000:    dword
>0x156cf00c:      0x00000000:    upper dword
>0x156cf010:      0x11000001: MI_LOAD_REGISTER_IMM
>0x156cf014:      0x00022200:    dword 1
>0x156cf018:      0x00030002:    dword 2
>0x156cf01c:      0x54f00806: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 0, dst tile 1)
>0x156cf020:      0x03cc0400:    format 8888, pitch 1024, rop 0xcc, clipping disabled,  
>0x156cf024:      0x00000000:    dst (0,0)
>0x156cf028:      0x02000400:    dst (1024,512)
>0x156cf02c:      0x1922e000:    dst offset 0x1922e000
>0x156cf030:      0x00000000:    src (0,0)
>0x156cf034:      0x0000f000:    src pitch -4096
>0x156cf038:      0x0f20a000:    src offset 0x0f20a000
>0x156cf03c:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x156cf040:      0x00000000:    address
>0x156cf044:      0x00000000:    dword
>0x156cf048:      0x00000000:    upper dword
>0x156cf04c:      0x11000001: MI_LOAD_REGISTER_IMM
>0x156cf050:      0x00022200:    dword 1
>0x156cf054:      0x00030000:    dword 2
>0x156cf058:      0x13000002: MI_FLUSH_DW post_sync_op='no write' 
>0x156cf05c:      0x00000000:    address
>0x156cf060:      0x00000000:    dword
>0x156cf064:      0x00000000:    upper dword
>0x156cf068:      0x05000000: MI_BATCH_BUFFER_END
>0x156cf06c:      0x00000000:    
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 3 (batchbuffer) -> 0x7fe10722c000
>drm_intel_gem_bo_purge_vma_cache: cached=7, open=0, limit=-1
>waiting for idle
>bo_unreference final: 6 (batchbuffer)
>bo_create: buf 7 (batchbuffer) 32768b
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>bo_map: 7 (batchbuffer) -> 0x7fe10721a000
>drm_intel_gem_bo_purge_vma_cache: cached=5, open=2, limit=-1
>bo_map: 8 (shader time) -> 0x7fe107152000
>drm_intel_gem_bo_purge_vma_cache: cached=6, open=1, limit=-1
>after glXSwapBuffers(dpy, w)
>Monitors: (OA users = 0)

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Attachments on bug 77368: 97258 | 97303

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