Attachment 97635 Details for Bug 76520 – intel_reg_dumper_before_good.txt

intel_reg_dumper_before_good.txt

intel_reg_dumper_before_good.txt (text/plain), 13.56 KB, created by Tim Richardson on 2014-04-20 07:13:11 UTC

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Creator: Tim Richardson

Created: 2014-04-20 07:13:11 UTC

Size: 13.56 KB

patch

obsolete

>                           DCC: 0x000f0002 (dual channel interleaved, XOR randomization: enabled, XOR bit: 11)
>                     CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>                        C0DRB0: 0x000f0002 (0x0002)
>                        C0DRB1: 0x0000000f (0x000f)
>                        C0DRB2: 0x00000000 (0x0000)
>                        C0DRB3: 0x0e000000 (0x0000)
>                        C1DRB0: 0x17cbe000 (0xe000)
>                        C1DRB1: 0x000017cb (0x17cb)
>                        C1DRB2: 0x00000000 (0x0000)
>                        C1DRB3: 0x00000000 (0x0000)
>                       C0DRA01: 0x00030e00 (0x0e00)
>                       C0DRA23: 0x000c0003 (0x0003)
>                       C1DRA01: 0x00000000 (0x0000)
>                       C1DRA23: 0x00000000 (0x0000)
>                    PGETBL_CTL: 0xbff80001
>             VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>             VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>                 VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>                     DPLL_TEST: 0x00010001 ()
>                  CACHE_MODE_0: 0x00006800
>                       D_STATE: 0x00000000
>                 DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>                RENCLK_GATE_D1: 0x20000000
>                RENCLK_GATE_D2: 0x00000000
>                         SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>                         SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>                       SDVOUDI: 0x00000000
>                        DSPARB: 0x00001d9c
>                        DSPFW1: 0xd8080808
>                        DSPFW2: 0x00000808
>                        DSPFW3: 0x20000000
>                          ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync)
>                          LVDS: 0x82300300 (enabled, pipe A, 18 bit, 1 channel)
>                          DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                          DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>                          DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>                   DVOA_SRCDIM: 0x00000000
>                   DVOB_SRCDIM: 0x00000000
>                   DVOC_SRCDIM: 0x00000000
>                   BLC_PWM_CTL: 0x00000000
>                  BLC_PWM_CTL2: 0x80000000
>                    PP_CONTROL: 0xabcd0003 (power target: on)
>                     PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                  PP_ON_DELAYS: 0x02580fa0
>                 PP_OFF_DELAYS: 0x01f407d0
>                    PP_DIVISOR: 0x0031cd05
>                  PFIT_CONTROL: 0x00000000
>               PFIT_PGM_RATIOS: 0x0f5c0ccd
>               PORT_HOTPLUG_EN: 0x04000220
>             PORT_HOTPLUG_STAT: 0x00000000
>                      DSPACNTR: 0xd8000400 (enabled, pipe A)
>                    DSPASTRIDE: 0x00001400 (5120 bytes)
>                       DSPAPOS: 0x00000000 (0, 0)
>                      DSPASIZE: 0x00000000 (1, 1)
>                      DSPABASE: 0x00000000
>                      DSPASURF: 0x03793000
>                   DSPATILEOFF: 0x00000000
>                     PIPEACONF: 0xc0000000 (enabled, active, progressive)
>                      PIPEASRC: 0x04ff031f (1280, 800)
>                     PIPEASTAT: 0x08440200 (status: GMBUS_EVENT_ENABLE LBLC_EVENT_ENABLE SVBLANK_INT_ENABLE VSYNC_INT_STATUS)
>             PIPEA_GMCH_DATA_M: 0x00000000
>             PIPEA_GMCH_DATA_N: 0x00000000
>               PIPEA_DP_LINK_M: 0x00000000
>               PIPEA_DP_LINK_N: 0x00000000
>                 CURSOR_A_BASE: 0x00000000
>              CURSOR_A_CONTROL: 0x00000000
>             CURSOR_A_POSITION: 0x007900b4
>                          FPA0: 0x00020d06 (n = 2, m1 = 13, m2 = 6)
>                          FPA1: 0x00020d06 (n = 2, m1 = 13, m2 = 6)
>                        DPLL_A: 0x98026c00 (enabled, non-dvo, unknown clock, LVDS mode, p1 = 2, p2 = 14)
>                     DPLL_A_MD: 0x00000000
>                      HTOTAL_A: 0x059f04ff (1280 active, 1440 total)
>                      HBLANK_A: 0x059f04ff (1280 start, 1440 end)
>                       HSYNC_A: 0x054f052f (1328 start, 1360 end)
>                      VTOTAL_A: 0x0336031f (800 active, 823 total)
>                      VBLANK_A: 0x0336031f (800 start, 823 end)
>                       VSYNC_A: 0x03280322 (803 start, 809 end)
>                     BCLRPAT_A: 0x00000000
>                  VSYNCSHIFT_A: 0x00000000
>                      DSPBCNTR: 0x01000000 (disabled, pipe B)
>                    DSPBSTRIDE: 0x00000000 (0 bytes)
>                       DSPBPOS: 0x00000000 (0, 0)
>                      DSPBSIZE: 0x00000000 (1, 1)
>                      DSPBBASE: 0x00000000
>                      DSPBSURF: 0x00000000
>                   DSPBTILEOFF: 0x00000000
>                     PIPEBCONF: 0x00000000 (disabled, inactive, progressive)
>                      PIPEBSRC: 0x027f018f (640, 400)
>                     PIPEBSTAT: 0x00400000 (status: LBLC_EVENT_ENABLE)
>             PIPEB_GMCH_DATA_M: 0x00000000
>             PIPEB_GMCH_DATA_N: 0x00000000
>               PIPEB_DP_LINK_M: 0x00000000
>               PIPEB_DP_LINK_N: 0x00000000
>                 CURSOR_B_BASE: 0x00000000
>              CURSOR_B_CONTROL: 0x00000000
>             CURSOR_B_POSITION: 0x00000000
>                          FPB0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
>                          FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>                        DPLL_B: 0x18046a00 (disabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14)
>                     DPLL_B_MD: 0x00000003
>                      HTOTAL_B: 0x059f04ff (1280 active, 1440 total)
>                      HBLANK_B: 0x059f04ff (1280 start, 1440 end)
>                       HSYNC_B: 0x054f052f (1328 start, 1360 end)
>                      VTOTAL_B: 0x0336031f (800 active, 823 total)
>                      VBLANK_B: 0x0336031f (800 start, 823 end)
>                       VSYNC_B: 0x03280322 (803 start, 809 end)
>                     BCLRPAT_B: 0x00000000
>                  VSYNCSHIFT_B: 0x00000000
>             VCLK_DIVISOR_VGA0: 0x00031108
>             VCLK_DIVISOR_VGA1: 0x00031406
>                 VCLK_POST_DIV: 0x00020002
>                      VGACNTRL: 0x80000000 (disabled)
>                        TV_CTL: 0x00000000
>                        TV_DAC: 0x70000000
>                      TV_CSC_Y: 0x00000000
>                     TV_CSC_Y2: 0x00000000
>                      TV_CSC_U: 0x00000000
>                     TV_CSC_U2: 0x00000000
>                      TV_CSC_V: 0x00000000
>                     TV_CSC_V2: 0x00000000
>                  TV_CLR_KNOBS: 0x00000000
>                  TV_CLR_LEVEL: 0x00000000
>                    TV_H_CTL_1: 0x00000000
>                    TV_H_CTL_2: 0x00000000
>                    TV_H_CTL_3: 0x00000000
>                    TV_V_CTL_1: 0x00000000
>                    TV_V_CTL_2: 0x00000000
>                    TV_V_CTL_3: 0x00000000
>                    TV_V_CTL_4: 0x00000000
>                    TV_V_CTL_5: 0x00000000
>                    TV_V_CTL_6: 0x00000000
>                    TV_V_CTL_7: 0x00000000
>                   TV_SC_CTL_1: 0x00000000
>                   TV_SC_CTL_2: 0x00000000
>                   TV_SC_CTL_3: 0x00000000
>                    TV_WIN_POS: 0x00000000
>                   TV_WIN_SIZE: 0x00000000
>               TV_FILTER_CTL_1: 0x00000000
>               TV_FILTER_CTL_2: 0x00000000
>               TV_FILTER_CTL_3: 0x00000000
>                 TV_CC_CONTROL: 0x00000000
>                    TV_CC_DATA: 0x00000000
>                   TV_H_LUMA_0: 0x00000000
>                  TV_H_LUMA_59: 0x00000000
>                 TV_H_CHROMA_0: 0x00000000
>                TV_H_CHROMA_59: 0x00000000
>                  FBC_CFB_BASE: 0x00000000
>                   FBC_LL_BASE: 0x00000000
>                   FBC_CONTROL: 0x00000000
>                   FBC_COMMAND: 0x00000000
>                    FBC_STATUS: 0x20000000
>                  FBC_CONTROL2: 0x00000000
>                 FBC_FENCE_OFF: 0x00000000
>                   FBC_MOD_NUM: 0x00000000
>                       MI_MODE: 0x00000240
>                  MI_ARB_STATE: 0x00000044
>                MI_RDRET_STATE: 0x00000000
>                       ECOSKPD: 0x00000307
>                          DP_B: 0x00000000
>                DPB_AUX_CH_CTL: 0x00000000
>              DPB_AUX_CH_DATA1: 0x00000000
>              DPB_AUX_CH_DATA2: 0x00000000
>              DPB_AUX_CH_DATA3: 0x00000000
>              DPB_AUX_CH_DATA4: 0x00000000
>              DPB_AUX_CH_DATA5: 0x00000000
>                          DP_C: 0x00000000
>                DPC_AUX_CH_CTL: 0x00000000
>              DPC_AUX_CH_DATA1: 0x00000000
>              DPC_AUX_CH_DATA2: 0x00000000
>              DPC_AUX_CH_DATA3: 0x00000000
>              DPC_AUX_CH_DATA4: 0x00000000
>              DPC_AUX_CH_DATA5: 0x00000000
>                          DP_D: 0x00000000
>                DPD_AUX_CH_CTL: 0x00000000
>              DPD_AUX_CH_DATA1: 0x00000000
>              DPD_AUX_CH_DATA2: 0x00000000
>              DPD_AUX_CH_DATA3: 0x00000000
>              DPD_AUX_CH_DATA4: 0x00000000
>              DPD_AUX_CH_DATA5: 0x00000000
>                    AUD_CONFIG: 0x00000000
>              AUD_HDMIW_STATUS: 0x00000000
>                AUD_CONV_CHCNT: 0x00000000
>                 VIDEO_DIP_CTL: 0x00000600
>                 AUD_PINW_CNTR: 0x00000140
>                   AUD_CNTL_ST: 0x00001800
>                   AUD_PIN_CAP: 0x00000094
>                  AUD_PINW_CAP: 0x004013b5
>            AUD_PINW_UNSOLRESP: 0x00000000
>              AUD_OUT_DIG_CNVT: 0x00000001
>                 AUD_OUT_CWCAP: 0x00000219
>                   AUD_GRP_CAP: 0x00000004
>                      FENCE  0: 0x00000000 (disabled)
>                      FENCE  1: 0x00000000 (disabled)
>                      FENCE  2: 0x00000000 (disabled)
>                      FENCE  3: 0x00000000 (disabled)
>                      FENCE  4: 0x00000000 (disabled)
>                      FENCE  5: 0x00000000 (disabled)
>                      FENCE  6: 0x00000000 (disabled)
>                      FENCE  7: 0x00000000 (disabled)
>                      FENCE  8: 0x06ce000d (disabled)
>                      FENCE  9: 0x06ce4000 (disabled)
>                     FENCE  10: 0x06cd100d (disabled)
>                     FENCE  11: 0x06cd5000 (disabled)
>                     FENCE  12: 0x0781600d (disabled)
>                     FENCE  13: 0x0781a000 (disabled)
>                     FENCE  14: 0x0888300d (disabled)
>                     FENCE  15: 0x08886000 (disabled)
>                 FENCE START 0: 0x06ce000d ( enabled, X tile walk,  512 pitch, 0x06ce0000 start)
>                   FENCE END 0: 0x06ce4000 (                                   0x06ce4000 end)
>                 FENCE START 1: 0x06cd100d ( enabled, X tile walk,  512 pitch, 0x06cd1000 start)
>                   FENCE END 1: 0x06cd5000 (                                   0x06cd5000 end)
>                 FENCE START 2: 0x0781600d ( enabled, X tile walk,  512 pitch, 0x07816000 start)
>                   FENCE END 2: 0x0781a000 (                                   0x0781a000 end)
>                 FENCE START 3: 0x0888300d ( enabled, X tile walk,  512 pitch, 0x08883000 start)
>                   FENCE END 3: 0x08886000 (                                   0x08886000 end)
>                 FENCE START 4: 0x0084809d ( enabled, X tile walk, 5120 pitch, 0x00848000 start)
>                   FENCE END 4: 0x00c2f000 (                                   0x00c2f000 end)
>                 FENCE START 5: 0x06cc700d ( enabled, X tile walk,  512 pitch, 0x06cc7000 start)
>                   FENCE END 5: 0x06ccb000 (                                   0x06ccb000 end)
>                 FENCE START 6: 0x06ccc00d ( enabled, X tile walk,  512 pitch, 0x06ccc000 start)
>                   FENCE END 6: 0x06cd0000 (                                   0x06cd0000 end)
>                 FENCE START 7: 0x077fd00d ( enabled, X tile walk,  512 pitch, 0x077fd000 start)
>                   FENCE END 7: 0x07801000 (                                   0x07801000 end)
>                 FENCE START 8: 0x06cbd00d ( enabled, X tile walk,  512 pitch, 0x06cbd000 start)
>                   FENCE END 8: 0x06cc6000 (                                   0x06cc6000 end)
>                 FENCE START 9: 0x0379309d ( enabled, X tile walk, 5120 pitch, 0x03793000 start)
>                   FENCE END 9: 0x03b7a000 (                                   0x03b7a000 end)
>                FENCE START 10: 0x06cd600d ( enabled, X tile walk,  512 pitch, 0x06cd6000 start)
>                  FENCE END 10: 0x06cda000 (                                   0x06cda000 end)
>                FENCE START 11: 0x01fd705d ( enabled, X tile walk, 3072 pitch, 0x01fd7000 start)
>                  FENCE END 11: 0x023be000 (                                   0x023be000 end)
>                FENCE START 12: 0x0633105d ( enabled, X tile walk, 3072 pitch, 0x06331000 start)
>                  FENCE END 12: 0x06348000 (                                   0x06348000 end)
>                FENCE START 13: 0x06cdb00d ( enabled, X tile walk,  512 pitch, 0x06cdb000 start)
>                  FENCE END 13: 0x06cdf000 (                                   0x06cdf000 end)
>                FENCE START 14: 0x06ce500d ( enabled, X tile walk,  512 pitch, 0x06ce5000 start)
>                  FENCE END 14: 0x06ce6000 (                                   0x06ce6000 end)
>                FENCE START 15: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 15: 0x00000000 (                                   0x00000000 end)
>                       INST_PM: 0x00000000
>pipe A dot 74107 n 2 m1 13 m2 6 p1 2 p2 14
>SDVO phase shift 5 out of range -- probobly not an issue.
>pipe B dot 103333 n 1 m1 15 m2 6 p1 3 p2 10

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Attachments on bug 76520: 96282 | 97635 | 97636 | 97637 | 98841 | 100625 | 100674 | 100699 | 100714 | 100715 | 100718 | 100733

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