Attachment 99169 Details for Bug 75276 – VGPR spilling work-around

[patch] VGPR spilling work-around

0002-VER-5-emit-Error-when-attempting-to-spill-or-load-a-.patch (text/plain), 4.12 KB, created by Tom Stellard on 2014-05-16 19:27:02 UTC

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Creator: Tom Stellard

Created: 2014-05-16 19:27:02 UTC

Size: 4.12 KB

patch

obsolete

>From 1ed00e79c13adbc3479544de74ae6cd02fefa491 Mon Sep 17 00:00:00 2001
>From: Darren <darren.powell@amd.com>
>Date: Mon, 28 Apr 2014 13:38:14 -0400
>Subject: [PATCH 2/3] [VER 5] emit Error when attempting to spill or load a
> spilled VGPR
>
>---
> lib/Target/R600/SIInstrInfo.cpp | 41 +++++++++++++++++++++++++++++------------
> 1 file changed, 29 insertions(+), 12 deletions(-)
>
>diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
>index 0d6650d..44bf7eb 100644
>--- a/lib/Target/R600/SIInstrInfo.cpp
>+++ b/lib/Target/R600/SIInstrInfo.cpp
>@@ -192,18 +192,26 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
>                                       int FrameIndex,
>                                       const TargetRegisterClass *RC,
>                                       const TargetRegisterInfo *TRI) const {
>-  SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
>+  MachineFunction *MF = MBB.getParent();
>+  SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
>+  MachineRegisterInfo &MRI = MF->getRegInfo();
>   DebugLoc DL = MBB.findDebugLoc(MI);
>   unsigned KillFlag = isKill ? RegState::Kill : 0;
>-  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
> 
>-  if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
>-    unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent());
>+  if (RI.hasVGPRs(RC)) {
>+    LLVMContext &Ctx = MF->getFunction()->getContext();
>+    //const char *name = RC->getName();
>+    Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
>+    insertNOPs(MI, 1);
>+
>+  } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
>+    unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
>+    unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
> 
>-    BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), MFI->SpillTracker.LaneVGPR)
>+    BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
>             .addReg(SrcReg, KillFlag)
>             .addImm(Lane);
>-    MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR, Lane);
>+    MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
>   } else if (RI.isSGPRClass(RC)) {
>     // We are only allowed to create one new instruction when spilling
>     // registers, so we need to use pseudo instruction for vector
>@@ -212,8 +220,7 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
>     // Reserve a spot in the spill tracker for each sub-register of
>     // the vector register.
>     unsigned NumSubRegs = RC->getSize() / 4;
>-    unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent(),
>-                                                        NumSubRegs);
>+    unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
>     MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
>                                     FirstLane);
> 
>@@ -239,11 +246,21 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
>                                        unsigned DestReg, int FrameIndex,
>                                        const TargetRegisterClass *RC,
>                                        const TargetRegisterInfo *TRI) const {
>-  SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
>+  MachineFunction *MF = MBB.getParent();
>+  SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
>+  MachineRegisterInfo &MRI = MF->getRegInfo();
>   DebugLoc DL = MBB.findDebugLoc(MI);
>-  if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
>-    SIMachineFunctionInfo::SpilledReg Spill =
>-        MFI->SpillTracker.getSpilledReg(FrameIndex);
>+
>+  if (RI.hasVGPRs(RC)) {
>+    LLVMContext &Ctx = MF->getFunction()->getContext();
>+    //const char *name = RC->getName();
>+    Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
>+    insertNOPs(MI, 1);
>+
>+  } else if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
>+    SIMachineFunctionInfo::SpilledReg Spill;
>+    Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
>+
>     assert(Spill.VGPR);
>     BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
>             .addReg(Spill.VGPR)
>-- 
>1.8.3.2
>

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Attachments on bug 75276: 94675 | 98982 | 99169 | 99186 | 99187 | 99236 | 99254 | 103583 | 106527 | 106569 | 112178 | 112179

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