Summary: | [SKL] Enable UMD to control GPGPU EUs slice number in static/dynamic way | ||
---|---|---|---|
Product: | DRI | Reporter: | Dmitry Rogozhkin <dmitry.v.rogozhkin> |
Component: | DRM/Intel | Assignee: | Dmitry Rogozhkin <dmitry.v.rogozhkin> |
Status: | RESOLVED MOVED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
Severity: | enhancement | ||
Priority: | medium | CC: | intel-gfx-bugs, joonas.lahtinen |
Version: | unspecified | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | ReadyForDev | ||
i915 platform: | BDW, SKL | i915 features: | display/Other |
Description
Dmitry Rogozhkin
2017-05-02 00:29:27 UTC
Hmm, since the slice/eu masks are stored in the context, is userspace unable to adjustment via LRI? If it can, job done. If not, then we need a context param to allow unprivileged adjustment for the users own contexts. Is it a good recommendation for all non-GPGPU workloads to set subslice_mask = 0? Hi Chris, Userspace could adjust it via LRI, if only i915 whitelists GEN8_R_PWR_CLK_STATE (this configuration from userspace via LRI is the preferred way for newer platforms, and I was suggesting Dmitry the same thing could be done from BDW onwards). Just letting you know that letting userspace directly change this configuration through LRI might corrupt the data coming from the OA unit. I think Chris' patchset to set the userspace control this through a context ioctl is the best solution. That way we can do something sensible in the kernel when the OA unit is enabled. (In reply to Lionel Landwerlin from comment #4) > Just letting you know that letting userspace directly change this > configuration through LRI might corrupt the data coming from the OA unit. > I think Chris' patchset to set the userspace control this through a context > ioctl is the best solution. That way we can do something sensible in the > kernel when the OA unit is enabled. Good afternoon, is the problem still present or the patchset fixed it?? With inline GEN8_R_PWR_CLK_STATE programming we are getting reset of per-slice registers including MOCS, this can lead to functional and performance regressions. From the other hand with the i915 KMD level programming we can reprogram the state we lost. Thus, we probably will follow with the KMD level slice programming. Here are the related patches: * https://patchwork.freedesktop.org/series/29715/ - patch series to enable slice programming for Gen8+ (most recent respin) * https://patchwork.freedesktop.org/series/29564/ - patch series to fix conflict with OA NOA programming And slice programming IGT test: https://patchwork.freedesktop.org/patch/174839/ First of all. Sorry about spam. This is mass update for our bugs. Sorry if you feel this annoying but with this trying to understand if bug still valid or not. If bug investigation still in progress, please ignore this and I apologize! If you think this is not anymore valid, please comment to the bug that can be closed. If you haven't tested with our latest pre-upstream tree(drm-tip), can you do that also to see if issue is valid there still and if you cannot see issue there, please comment to the bug. Dmitry, Chris, is this still valid issue? Yes, it is still valid. Is media stack still interested in having this for performance reasons? Are there patches available against some userspace component? -- GitLab Migration Automatic Message -- This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity. You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/intel/issues/36. |
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