| Summary: | [BXT] gles asserts in cts | ||
|---|---|---|---|
| Product: | Mesa | Reporter: | Mirlan <mirlan.ax.tokonbekov> |
| Component: | Drivers/DRI/i965 | Assignee: | Anuj Phogat <anuj.phogat> |
| Status: | RESOLVED FIXED | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
| Severity: | normal | ||
| Priority: | medium | CC: | anuj.phogat |
| Version: | git | ||
| Hardware: | Other | ||
| OS: | All | ||
| Whiteboard: | |||
| i915 platform: | i915 features: | ||
A quick look in to this failure points to an exposed bug in our driver due to my commit 0d576fb. We were programming the same URB size for both bxt 2x6 and bxt 3x6 configs. But the gfxspecs suggests different sizes. I'm looking in to fixing it properly so that we follow the similar approach for future hardware too. bxt is disabled in jenkins, because this affects half of our test pool. This bug also has affected bxt performance, with dramatic swings to several benchmarks. This bug is fixed by below commit on master: commit 8d02916e0c083f57bc7dfd886333f099763bd998 Author: Anuj Phogat <anuj.phogat@gmail.com> Date: Tue Jun 6 16:14:19 2017 -0700 intel: Fix broxton 2x6 way size computation This patch is undoing the changes to way size computation in broxton 2x6, made by below commit: Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 Author: Anuj Phogat <anuj.phogat@gmail.com> i965: Simplify l3 way size computations By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306 Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Mark Janes <mark.a.janes@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> As mentioned by Anuj, issue should be resolved. |
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ES31-CTS.functional.compute.shared_var.basic_type.mat4_highp.bxtm64 ES31-CTS.functional.compute.shared_var.basic_type.mat4x2_mediump.bxtm64 ES31-CTS.functional.compute.shared_var.basic_type.mat4_mediump.bxtm64 ES31-CTS.functional.compute.shared_var.basic_type.uint_highp.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.add.mediump_uint.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.add.highp_uint.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.compswap.lowp_int.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.compswap.highp_uint.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.compswap.mediump_int.bxtm64 ES31-CTS.functional.compute.shared_var.atomic.compswap.highp_int.bxtm64 ES31-CTS.functional.compute.shared_var.work_group_size.mat4_1_128_1.bxtm64 ES31-CTS.functional.compute.shared_var.work_group_size.mat4_1_1_1.bxtm64 glcts: /home/jenkins/workspace/Leeroy_3/repos/mesa/src/intel/common/gen_urb_config.c:151: gen_get_urb_config: Assertion `total_needs <= urb_chunks' failed. bisected to: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 Author: Anuj Phogat <anuj.phogat@gmail.com> i965: Simplify l3 way size computations By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. V2: Keep the get_l3_way_size() function. Suggested-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>