| Summary: | DP@Cherryview → CH7517 → VGA: interlaced modes broken | ||||||
|---|---|---|---|---|---|---|---|
| Product: | DRI | Reporter: | Dennis Vshivkov <awesome.walrus+bugzilla> | ||||
| Component: | DRM/Intel | Assignee: | Ville Syrjala <ville.syrjala> | ||||
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
| Severity: | normal | ||||||
| Priority: | medium | CC: | intel-gfx-bugs | ||||
| Version: | unspecified | ||||||
| Hardware: | x86-64 (AMD64) | ||||||
| OS: | Linux (All) | ||||||
| Whiteboard: | PatchSubmitted | ||||||
| i915 platform: | BSW/CHT | i915 features: | display/DP | ||||
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Hmm. Indeed looks like DP+interlaced is totally hosed on CHV (and probably VLV too, perhaps even g4x?). I tested it on an external DP monitor here, and I get very corrupted output. I wasn't able to find anything in the docs suggesting that we're doing anything wrong, nor that we're missing some important register setting. I even found one chicken bit called 'Flip_MSA_vertical_total_in_interlace_mode' which suggests that at least someone gave *some* thought to DP+interlaced in the hardware design. Frobbing with any of the relevant looking bits didn't help. My display does correctly identify the mode as 1080i though, so I assume at least some parts of the MSA packet must be correct. Sad way to "fix" this, but apparently there's no other option: https://patchwork.freedesktop.org/patch/191072/ commit 050213893307e661933a315a3c6e82658a68ffee Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Nov 29 20:08:47 2017 +0200 drm/i915: Interlaced DP output doesn't work on VLV/CHV Hello Dennis, could you confirm is fixed by comment 3. Thank you. Well, the patch from comment 3 doesn't implement a fix as such — AFAIU, Intel hardware here isn't capable, not the driver, — it simply disables interlaced modes on DP+CHV/VLV. Do you want me to patch the driver and verify whether interlaced DP modes are now disabled rather than broken on my problematic setup? IMHO anyone owning a CHV/VLV with a DP output can verify that, it's not specific to my system. But please let me know. (BTW, I've since moved on to working 1080i off the HDMI output of my new video source plus an HDMI→VGA converter.) (In reply to Dennis Vshivkov from comment #5) > Well, the patch from comment 3 doesn't implement a fix as such — AFAIU, > Intel hardware here isn't capable, not the driver, — it simply disables > interlaced modes on DP+CHV/VLV. > > Do you want me to patch the driver and verify whether interlaced DP modes > are now disabled rather than broken on my problematic setup? IMHO anyone > owning a CHV/VLV with a DP output can verify that, it's not specific to my > system. But please let me know. > > (BTW, I've since moved on to working 1080i off the HDMI output of my new > video source plus an HDMI→VGA converter.) No need to. I believe I have the HW to test it, I'll check it later. Thanks a lot for your time Dennis. Closing, please re-open if still occurs. |
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Created attachment 135733 [details] DRM driver debug output Attempted upgrading a video source for a full HD screen system (consumes 720p and 1080i @50/60Hz via VGA→RGBHV cable, previously served by an nVidia Ion platform for years). The new system is built on Celeron N3150, i.e., uses Cherryview Braswell (Gen8LP) i915 graphics (PCI ID 8086:22b1, rev 0x21). Problem: interlaced modes do not work, only progressive do. Specifically, as found with an oscilloscope, there are no requisite half-lines between odd and even interlaced fields — vsync start always aligns with hsync start, as opposed to proper interlaced modes output by the former source, where vsync starts mid-scanline on every other field, and which work fine. All other timings seem OK: e.g., half the scanlines configured are used between vsyncs, vsync duration is also half-long, etc. More specifics: - OS: Debian 8.8, kernel 4.13.0-0.bpo.1-amd64 (from stretch-backports); - the new system has its VGA port appear as “DP2” to the driver; there's also a CH7517A chip on board (a DisplayPort to VGA translator), which adds up; - an example problematic mode (tried many, though): Modeline "1920x1080@50i" 74.250 1920 2448 2492 2640 1080 1085 1095 1125 Interlace - messed with the driver to verify that VSYNCSHIFT gets set to 1128 (for the mode above) and PIPEACONF gets 0b101 in bits 23:21 (and tried every other way of requesting interlaced mode via those bits — to no avail); - debug logging from the driver setting the aforementioned mode is attached. Is there any hope?