Bug 104923

Summary: anv: Dota2 rendering corruption
Product: Mesa Reporter: Scott D Phillips <scott.d.phillips>
Component: Drivers/Vulkan/intelAssignee: Jason Ekstrand <jason>
Status: RESOLVED FIXED QA Contact: Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity: normal    
Priority: medium CC: currojerez, jason, mattst88
Version: git   
Hardware: Other   
OS: All   
i915 platform: i915 features:
Bug Depends on:    
Bug Blocks: 104757    
Attachments: Screenshot
Broken shader with post-RA scheduling enabled
"fixed" shader with post-RA scheduling disabled

Description Scott D Phillips 2018-02-03 05:24:54 UTC
Created attachment 137146 [details]

Starting with ("4c7af87fb92 anv: Enable UBO pushing"), I'm seeing some corrupted rendering in Dota 2 with anv on my kbl_gt2. I'm seeing this by watching the recording of MatchID 3372726385. At about 1:10 in the recording the little guy pops up at the bottom and has some bad vertices.
Comment 1 Jason Ekstrand 2018-02-07 01:40:31 UTC
Created attachment 137203 [details]
Broken shader with post-RA scheduling enabled
Comment 2 Jason Ekstrand 2018-02-07 01:40:55 UTC
Created attachment 137204 [details]
"fixed" shader with post-RA scheduling disabled
Comment 3 Jason Ekstrand 2018-02-07 01:41:30 UTC
I've narrowed this down quite a bit now.  This branch contains a patch which can help pin-point the exact shader:


Anything which perturbs instructions seems to fix it.  I think it's actually a bug in post-RA scheduling.  If I disable post-ra scheduling everything goes back to passing.
Comment 4 Jason Ekstrand 2018-03-01 06:24:02 UTC
Patch is on the list:

Comment 5 Jason Ekstrand 2018-03-01 23:15:17 UTC
This has been fixed by the following commit in master:

commit ff4726077d86800d33520581f154a27dac408588
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Wed Feb 28 19:57:44 2018 -0800

    intel/fs: Set up sampler message headers in the visitor on gen7+
    This gives the scheduler visibility into the headers which should
    improve scheduling.  More importantly, however, it lets the scheduler
    know that the header gets written.  As-is, the scheduler thinks that a
    texture instruction only reads it's payload and is unaware that it may
    write to the first register so it may reorder it with respect to a read
    from that register.  This is causing issues in a couple of Dota 2 vertex
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104923
    Cc: mesa-stable@lists.freedesktop.org
    Reviewed-by: Francisco Jerez <currojerez@riseup.net>

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