Bug 105286

Summary: [CI] igt@perf_pmu@busy-vcs0 - fail - Failed assertion: (double)(val) <= (1.0 + (tolerance)) * (double)(flags & (1) ? slept : 0.f) && (double)(val) >= (1.0 - (tolerance)) * (double)(flags & (1) ? slept : 0.f)
Product: DRI Reporter: Martin Peres <martin.peres>
Component: DRM/IntelAssignee: Intel GFX Bugs mailing list <intel-gfx-bugs>
Status: CLOSED WORKSFORME QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: normal    
Priority: medium CC: intel-gfx-bugs
Version: XOrg git   
Hardware: Other   
OS: All   
Whiteboard: ReadyForDev
i915 platform: SNB i915 features: Perf/PMU

Description Martin Peres 2018-02-28 10:09:00 UTC 
(perf_pmu:1972) CRITICAL: Test assertion failure function single, file perf_pmu.c:211:
(perf_pmu:1972) CRITICAL: Failed assertion: (double)(val) <= (1.0 + (tolerance)) * (double)(flags & (1) ? slept : 0.f) && (double)(val) >= (1.0 - (tolerance)) * (double)(flags & (1) ? slept : 0.f)
(perf_pmu:1972) CRITICAL: 'val' != 'flags & (1) ? slept : 0.f' (470000000.000000 not within +5.000000%/-5.000000% tolerance of 500071392.000000)
Subtest busy-vcs0 failed.

https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4306/shard-snb2/igt@perf_pmu@busy-vcs0.html
Comment 1 Chris Wilson 2018-05-11 21:20:35 UTC 
We think this should be fixed by

commit d502f055ac4500cada758876a512ac4f14b34851
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date:   Wed Apr 4 10:51:52 2018 +0100

    tests/perf_pmu: Avoid RT thread for accuracy test
    
    Realtime scheduling interferes with execlists submission (tasklet) so try
    to simplify the PWM loop in a few ways:
    
     * Drop RT.
     * Longer batches for smaller systematic error.
     * More truthful test duration calculation.
     * Less clock queries.
     * No self-adjust - instead just report the achieved cycle and let the
       parent check against it.
     * Report absolute cycle error.
Comment 2 Martin Peres 2018-05-22 20:55:08 UTC 
No changes... We still see the problem every single run...
Comment 3 Chris Wilson 2018-09-06 08:29:18 UTC 
Lots more tuning of the test since.
Comment 4 Martin Peres 2018-09-07 17:37:00 UTC 
(In reply to Chris Wilson from comment #3)
> Lots more tuning of the test since.

Not seen since drmtip_56 (3 months / 49 runs ago). Closing!

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