Bug 105771

After the timeout things seem to work correctly, the same PHY enabling will succeed afterwards. Since the timeout isn't actually specified by BSpec, we should just try increasing it:

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index c8e9e44e5981..00b3ab656b06 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 	 * all 1s.  Eventually they become accessible as they power up, then
 	 * the reserved bit will give the default 0.  Poll on the reserved bit
 	 * becoming 0 to find when the PHY is accessible.
-	 * HW team confirmed that the time to reach phypowergood status is
-	 * anywhere between 50 us and 100us.
+	 * The flag should get set in 100us according to the HW team, but
+	 * use 1ms due to occasional timeouts observed with that.
 	 */
-	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
-		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
+	if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+				       PHY_RESERVED | PHY_POWER_GOOD,
+				       PHY_POWER_GOOD,
+				       1))
 		DRM_ERROR("timeout during PHY%d power on\n", phy);
-	}
 
 	/* Program PLL Rcomp code offset */
 	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));

Also on drmtip runs:
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_16/fi-glk-j4005/igt@gem_ctx_isolation@bcs0-s3.html

reference: https://patchwork.freedesktop.org/series/41366/

Fix merged to drm-tip.

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4040/shard-glk5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

[  172.683710] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0 power on

The patch was integrated to CI_DRM_4039, so it doean't seem that the fix is enough.

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4043/shard-glk5/igt@gem_exec_suspend@basic-s3.html

[  148.463532] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0 power on

Hm, the logs don't seem to match the change in the fix:

(In reply to Marta Löfstedt from comment #5)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4040/shard-glk5/
> igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
> [  172.683710] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
> power on
> 
> The patch was integrated to CI_DRM_4039, so it doesn't seem that the fix is
> enough.

<7>[  172.683181] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
<3>[  172.683710] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0 power on

The wait here was maximum ~600usec, as opposed to the minimum of 1msec we should have after the fix.

(In reply to Marta Löfstedt from comment #6)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4043/shard-glk5/
> igt@gem_exec_suspend@basic-s3.html
> 
> [  148.463532] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0
> power on

<7>[  148.463053] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
<3>[  148.463532] [drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0 power on

The wait here was maximum ~500usec instead of the minimum of 1msec. 

The only explanation for this I have is that either that the system clock is off somehow, or that these CI runs were without the fix applied.

This time on glk3

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4045/shard-glk3/igt@gem_eio@in-flight-suspend.html

glk3 again:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4046/shard-glk3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

and here goes glk1:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4045/shard-glk1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4050/shard-glk3/igt@gem_softpin@noreloc-s3.html

[  158.579450] [drm:bxt_ddi_pll_enable [i915]] *ERROR* PLL 1 not locked

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4054/shard-glk4/igt@drv_suspend@fence-restore-tiled2untiled.html
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4054/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4054/shard-glk3/igt@drv_suspend@debugfs-reader.html

*** Bug 103774 has been marked as a duplicate of this bug. ***

Both

[drm:_bxt_ddi_phy_init [i915]] *ERROR* timeout during PHY0 power on
and
[drm:bxt_ddi_pll_enable [i915]] *ERROR* PLL 1 not locked

should be fixed by

commit 3085982c6b45d7d22f76e3aa018affbc143a7370
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date:   Mon Apr 23 14:37:53 2018 +0300

    drm/i915: Use ktime on wait_for

Was this fixed in CI?

(In reply to Jani Saarinen from comment #14)
> Was this fixed in CI?

This will take a couple of weeks to be sure.

This looks fixed.