|Summary:||Cirrus bpp and clock detection|
|Product:||xorg||Reporter:||Samuel Thibault <samuel.thibault>|
|Component:||Driver/cirrus||Assignee:||Xorg Project Team <xorg-team>|
|Status:||RESOLVED FIXED||QA Contact:||Xorg Project Team <xorg-team>|
|i915 platform:||i915 features:|
|Bug Depends on:|
Description Samuel Thibault 2007-04-22 08:32:19 UTC
Hi, I'm trying to run X.org with qemu's cirrus GD5446 virtual board, and it didn't work at first: Xorg.0.log was telling me "bad mode clock/interlace/doublescan" for all modes, most probably becase there was also "Max pixel clock is 0 Mhz" loggued above. By looking at the source code, the Max pixel clock value is indeed 0 for 32bpp depth (gd5446_MaxClocks). I hence had to add DefaultDepth 24 in the screen section (there was none before) for making it work. Shouldn't the cirrus driver be able to set bpp to what the device can handle? Samuel
Comment 1 Adam Jackson 2007-06-28 13:51:40 UTC
32 isn't a real depth. Unless you're doing like, r10g12b10. But you aren't.
Comment 2 Samuel Thibault 2007-06-28 15:54:40 UTC
Well, maybe, but it was set to this by default, it's not me who chose that depth
Comment 3 Adam Jackson 2008-03-24 11:55:29 UTC
Fixed in git, I believe.