Summary: | [CI][BAT] igt@drv_selftest@live_coherency - dmesg-fail - Value[9/31] mismatch, (overwrite with gtt) wrote [gpu] fcf5ab91 read [cpu] 30a546e (inverse 30a546e), at offset cc | ||
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Product: | DRI | Reporter: | Martin Peres <martin.peres> |
Component: | DRM/Intel | Assignee: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
Severity: | normal | ||
Priority: | medium | CC: | intel-gfx-bugs |
Version: | XOrg git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | ReadyForDev | ||
i915 platform: | i915 features: |
Description
Martin Peres
2018-08-07 12:27:25 UTC
This may already be a duplicate of https://bugs.freedesktop.org/show_bug.cgi?id=107435. commit f6844a85e0c96a55c61fa3e611f414999b11e4de Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Jul 30 08:53:51 2018 +0100 drm/i915/selftests: Replace opencoded clflush with drm_clflush_virt_range We occasionally see that the clflush prior to a read of GPU data is returning stale data, reminiscent of much earlier bugs fixed by adding a second clflush for serialisation. As drm_clflush_virt_range() already supplies the workaround, use it rather than open code the clflush instruction. References: 396f5d62d1a5 ("drm: Restore double clflush on the last partial cacheline") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180730075351.15569-3-chris@chris-wilson.co.uk Test is now all green on fi-byt-j1900, closing (In reply to James Ausmus from comment #3) > Test is now all green on fi-byt-j1900, closing You are assuming that failures are consistent ;) In this particular case, the reproduction rate is lower than .5%... or it has been fixed immediately... hard to tell since Chris has been so faaaastt! Anyway, I will trust Chris and archive the bug. It's down to an irregular fail with gdg (107164). I feel like I've exhausted all the likely suspects... Perhaps my delay is not quite enough. |
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