Bug 109469

Summary: [CI][SHARDS] igt@gem_mmap_gtt@hang - fail - Failed assertion: !control->error
Product: DRI Reporter: Martin Peres <martin.peres>
Component: DRM/IntelAssignee: Intel GFX Bugs mailing list <intel-gfx-bugs>
Status: CLOSED FIXED QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: normal    
Priority: high CC: intel-gfx-bugs
Version: XOrg git   
Hardware: Other   
OS: All   
Whiteboard: ReadyForDev
i915 platform: ALL i915 features: GEM/Other

Description Martin Peres 2019-01-28 09:21:36 UTC 
https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4791/shard-iclb5/igt@gem_mmap_gtt@hang.html

(gem_mmap_gtt:4820) WARNING: child[0] found (aaaaaaaa, 0), expecting 0
(gem_mmap_gtt:4819) CRITICAL: Test assertion failure function test_hang, file ../tests/i915/gem_mmap_gtt.c:455:
(gem_mmap_gtt:4819) CRITICAL: Failed assertion: !control->error
Subtest hang failed.
Comment 1 CI Bug Log 2019-01-28 09:22:18 UTC 
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* All machines: igt@gem_mmap_gtt@hang - fail - Failed assertion: !control-&gt;error
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3705/shard-apl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3705/shard-glk9/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3705/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3705/shard-kbl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3705/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3707/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3707/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3707/shard-hsw1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3707/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3707/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3708/shard-apl8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3708/shard-glk2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3708/shard-hsw7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3708/shard-kbl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3708/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3710/shard-apl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3710/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3710/shard-hsw8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3710/shard-kbl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3710/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12038/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12038/shard-glk4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12038/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12038/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12038/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-apl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-glk2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-hsw2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-iclb1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-kbl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-skl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5484/shard-snb7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2295/shard-apl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2295/shard-glk6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2295/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2295/shard-kbl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2295/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3711/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3711/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3711/shard-hsw7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3711/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12042/shard-apl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12042/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12042/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12042/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12042/shard-snb6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-apl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-glk3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-iclb7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-skl10/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5485/shard-snb6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-apl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-glk1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-iclb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-kbl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-skl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5486/shard-snb7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12043/shard-apl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12043/shard-glk9/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12043/shard-hsw8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12043/shard-kbl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12043/shard-snb1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12044/shard-apl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12044/shard-glk2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12044/shard-hsw1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12044/shard-kbl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12044/shard-snb1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12045/shard-apl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12045/shard-glk1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12045/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12045/shard-kbl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12045/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-apl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-glk7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-hsw8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-iclb6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-kbl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-skl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5487/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-apl8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-glk5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-hsw8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-iclb1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-kbl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-skl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5488/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12046/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12046/shard-glk3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12046/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12046/shard-kbl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12046/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12047/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12047/shard-glk6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12047/shard-hsw1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12047/shard-kbl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12047/shard-snb7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3713/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3713/shard-glk4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3713/shard-hsw3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3713/shard-kbl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3713/shard-snb6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3714/shard-apl7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3714/shard-glk1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3714/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3714/shard-kbl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3714/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3715/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3715/shard-glk1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3715/shard-hsw3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3715/shard-kbl3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3715/shard-snb7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3716/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3716/shard-glk6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3716/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3716/shard-kbl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3716/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2296/shard-apl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2296/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2296/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2296/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12048/shard-apl8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12048/shard-glk5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12048/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12048/shard-kbl4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12048/shard-snb4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12049/shard-apl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12049/shard-glk8/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12049/shard-hsw5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12049/shard-kbl1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12049/shard-snb2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12050/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12050/shard-glk8/igt@gem_mmap_gtt@hang.html
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  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12050/shard-kbl1/igt@gem_mmap_gtt@hang.html
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  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3717/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3717/shard-glk7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3717/shard-hsw7/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3717/shard-kbl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3717/shard-snb5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12051/shard-apl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12051/shard-glk9/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12051/shard-hsw3/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12051/shard-kbl6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12051/shard-snb4/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3718/shard-apl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3718/shard-hsw6/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3718/shard-kbl2/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3718/shard-snb1/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3719/shard-apl5/igt@gem_mmap_gtt@hang.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_3719/shard-glk7/igt@gem_mmap_gtt@hang.html
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Comment 2 Chris Wilson 2019-01-28 09:36:26 UTC 
This was a deliberate regression in our GPU reset handling -- accepting that we cannot serialise user memory access without a magic recursive mutex.

commit eb8d0f5af4ec2d172baf8b4b9a2199cd916b4e54
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Jan 25 13:22:28 2019 +0000

    drm/i915: Remove GPU reset dependence on struct_mutex
    
    Now that the submission backends are controlled via their own spinlocks,
    with a wave of a magic wand we can lift the struct_mutex requirement
    around GPU reset. That is we allow the submission frontend (userspace)
    to keep on submitting while we process the GPU reset as we can suspend
    the backend independently.
    
    The major change is around the backoff/handoff strategy for performing
    the reset. With no mutex deadlock, we no longer have to coordinate with
    any waiter, and just perform the reset immediately.
    
    Testcase: igt/gem_mmap_gtt/hang # regresses
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190125132230.22221-3-chris@chris-wilson.co.uk


We think we might be able to do a "light stop_machine()" to suspend affected userspace (along the lines of SIGSTOP) while we do the reset -- which should avoid the recursion from inside the pagefault handlers. Actual user impact should be low, temporary visual glitch (userspace image shown with incorrect tiling) on older machines should the GPU hang (so after already being unresponsive for 10s), machine stability unaffected.
Comment 3 Chris Wilson 2019-02-01 12:18:42 UTC 
Light coming our way in the tunnel, https://patchwork.freedesktop.org/series/56042/
Comment 4 CI Bug Log 2019-02-05 07:55:25 UTC 
A CI Bug Log filter associated to this bug has been updated:

{- All machines: igt@gem_mmap_gtt@hang - fail - Failed assertion: !control-&gt;error -}
{+ All machines: igt@gem_mmap_gtt@hang - fail/dmesg-fail - Failed assertion: !control-&gt;error +}

 No new failures caught with the new filter
Comment 5 Chris Wilson 2019-02-08 22:08:25 UTC 
commit 2caffbf1176256cc4f8d4e5c3c524fc689cb9876
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Feb 8 15:37:03 2019 +0000

    drm/i915: Revoke mmaps and prevent access to fence registers across reset
    
    Previously, we were able to rely on the recursive properties of
    struct_mutex to allow us to serialise revoking mmaps and reacquiring the
    FENCE registers with them being clobbered over a global device reset.
    I then proceeded to throw out the baby with the bath water in order to
    pursue a struct_mutex-less reset.
    
    Perusing LWN for alternative strategies, the dilemma on how to serialise
    access to a global resource on one side was answered by
    https://lwn.net/Articles/202847/ -- Sleepable RCU:
    
        1  int readside(void) {
        2      int idx;
        3      rcu_read_lock();
        4      if (nomoresrcu) {
        5          rcu_read_unlock();
        6          return -EINVAL;
        7      }
        8      idx = srcu_read_lock(&ss);
        9      rcu_read_unlock();
        10     /* SRCU read-side critical section. */
        11     srcu_read_unlock(&ss, idx);
        12     return 0;
        13 }
        14
        15 void cleanup(void)
        16 {
        17     nomoresrcu = 1;
        18     synchronize_rcu();
        19     synchronize_srcu(&ss);
        20     cleanup_srcu_struct(&ss);
        21 }
    
    No more worrying about stop_machine, just an uber-complex mutex,
    optimised for reads, with the overhead pushed to the rare reset path.
    
    However, we do run the risk of a deadlock as we allocate underneath the
    SRCU read lock, and the allocation may require a GPU reset, causing a
    dependency cycle via the in-flight requests. We resolve that by declaring
    the driver wedged and cancelling all in-flight rendering.
    
    v2: Use expedited rcu barriers to match our earlier timing
    characteristics.
    v3: Try to annotate locking contexts for sparse
    v4: Reduce selftest lock duration to avoid a reset deadlock with fences
    v5: s/srcu/reset_backoff_srcu/
    v6: Remove more stale comments
    
    Testcase: igt/gem_mmap_gtt/hang
    Fixes: eb8d0f5af4ec ("drm/i915: Remove GPU reset dependence on struct_mutex")
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Mika Kuoppala <mika.kuoppala@intel.com>
    Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190208153708.20023-2-chris@chris-wilson.co.uk
Comment 6 Martin Peres 2019-03-06 18:42:36 UTC 
(In reply to Chris Wilson from comment #5)
> commit 2caffbf1176256cc4f8d4e5c3c524fc689cb9876
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Fri Feb 8 15:37:03 2019 +0000
> 
>     drm/i915: Revoke mmaps and prevent access to fence registers across reset
>     
>     Previously, we were able to rely on the recursive properties of
>     struct_mutex to allow us to serialise revoking mmaps and reacquiring the
>     FENCE registers with them being clobbered over a global device reset.
>     I then proceeded to throw out the baby with the bath water in order to
>     pursue a struct_mutex-less reset.
>     
>     Perusing LWN for alternative strategies, the dilemma on how to serialise
>     access to a global resource on one side was answered by
>     https://lwn.net/Articles/202847/ -- Sleepable RCU:
>     
>         1  int readside(void) {
>         2      int idx;
>         3      rcu_read_lock();
>         4      if (nomoresrcu) {
>         5          rcu_read_unlock();
>         6          return -EINVAL;
>         7      }
>         8      idx = srcu_read_lock(&ss);
>         9      rcu_read_unlock();
>         10     /* SRCU read-side critical section. */
>         11     srcu_read_unlock(&ss, idx);
>         12     return 0;
>         13 }
>         14
>         15 void cleanup(void)
>         16 {
>         17     nomoresrcu = 1;
>         18     synchronize_rcu();
>         19     synchronize_srcu(&ss);
>         20     cleanup_srcu_struct(&ss);
>         21 }
>     
>     No more worrying about stop_machine, just an uber-complex mutex,
>     optimised for reads, with the overhead pushed to the rare reset path.
>     
>     However, we do run the risk of a deadlock as we allocate underneath the
>     SRCU read lock, and the allocation may require a GPU reset, causing a
>     dependency cycle via the in-flight requests. We resolve that by declaring
>     the driver wedged and cancelling all in-flight rendering.
>     
>     v2: Use expedited rcu barriers to match our earlier timing
>     characteristics.
>     v3: Try to annotate locking contexts for sparse
>     v4: Reduce selftest lock duration to avoid a reset deadlock with fences
>     v5: s/srcu/reset_backoff_srcu/
>     v6: Remove more stale comments
>     
>     Testcase: igt/gem_mmap_gtt/hang
>     Fixes: eb8d0f5af4ec ("drm/i915: Remove GPU reset dependence on
> struct_mutex")
>     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>     Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>     Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>     Link:
> https://patchwork.freedesktop.org/patch/msgid/20190208153708.20023-2-
> chris@chris-wilson.co.uk

It did the trick! Used to be seen every run, but not anymore for the past 3.5 weeks! Closing :)
Comment 7 CI Bug Log 2019-03-06 18:42:44 UTC 
The CI Bug Log issue associated to this bug has been archived.

New failures matching the above filters will not be associated to this bug anymore.

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