Bug 110208

Summary:	New GPU sysfs Power State Interface for custom pp_od_clk_voltage
Product:	DRI	Reporter:	famo <richard.llom>
Component:	DRM/AMDgpu	Assignee:	Default DRI bug account <dri-devel>
Status:	RESOLVED MOVED	QA Contact:
Severity:	normal
Priority:	medium
Version:	unspecified
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:		i915 features:

Description famo 2019-03-20 11:48:27 UTC

In order to use a custom pp_od_clk_voltage one has to set power_dpm_force_performance_level to manual.

However this way it is not possible to use custom pp_od_clk_voltage and force - for instance - high or peak performance levels.


The forcing of different performance levels doesn't (and shouldn't) relate to custom clocks/voltages. Putting this setting in the same interface is a poor choice and (unnecessarily) restricts the possibilities.


Please add a new sysfs interface for *solely* choosing between default and custom pp_od_clk_voltage.

Comment 1 famo 2019-03-20 11:50:50 UTC

Link to  documentation:
https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html#power-dpm-force-performance-level

Quote:
pp_od_clk_voltage

The amdgpu driver provides a sysfs API for adjusting the clocks and voltages in each power level within a power state. The pp_od_clk_voltage is used for this.

< For Vega10 and previous ASICs >

Reading the file will display:

    a list of engine clock levels and voltages labeled OD_SCLK
    a list of memory clock levels and voltages labeled OD_MCLK
    a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE

To manually adjust these settings, first select manual using power_dpm_force_performance_level. ...

Comment 2 Martin Peres 2019-11-19 09:17:55 UTC

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