Bug 110347

Summary: pp_od_clk_voltage mV cap ignored
Product: DRI Reporter: bednarczyk.pawel
Component: DRM/AMDgpuAssignee: Default DRI bug account <dri-devel>
Status: RESOLVED DUPLICATE QA Contact:
Severity: normal    
Priority: medium CC: bednarczyk.pawel, johan.gardhage, t.clastres
Version: XOrg git   
Hardware: x86-64 (AMD64)   
OS: Linux (All)   
Whiteboard:
i915 platform: i915 features:
Attachments:
Description Flags
Xorg log
none
dmesg none

Description bednarczyk.pawel 2019-04-07 12:01:38 UTC 
Hi all,

I have a Gigabyte Radeon RX Vega 64 GAMING OC 8GB and I have been playing with undervolting/overclocking the card for a better performance/power draw ratio.

I have set the voltages/frequency as follows: https://gist.github.com/Bednar87/eeeee4fea34b03b96b2833e2900d3405 with voltage capped @ 950V

Now of course prior to doing that I added the amdgpu.ppffeaturemask parameter to the boot line with value 0xfffd7fff.

Looking at sudo watch -n 0.5 cat /sys/kernel/debug/dri/0/amdgpu_pm_info shows that the voltage is at 1200mV (VDDGFX). The power draw is also not reduced as one could expect from undervolting the clocks but instead shoots up to 320W and maintains this value under stress (50% power limit was also enabled). 

The frequency on the clocks seems to work fine and the settings seem to be honoured but the voltage value seems to be ignored.

cat /sys/class/drm/card0/device/pp_od_clk_voltage

OD_SCLK:
0:        852Mhz        800mV
1:        991Mhz        825mV
2:       1084Mhz        850mV
3:       1138Mhz        875mV
4:       1250Mhz        900mV
5:       1370Mhz        925mV
6:       1475Mhz        950mV
7:       1575Mhz        950mV
OD_MCLK:
0:        167Mhz        800mV
1:        500Mhz        825mV
2:        800Mhz        865mV
3:       1050Mhz        950mV
OD_RANGE:
SCLK:     852MHz       2400MHz
MCLK:     167MHz       1500MHz
VDDC:     800mV        1200mV

I am on Arch Linux kernel 5.0.6 MESA 19.0.1
Comment 1 bednarczyk.pawel 2019-04-07 12:27:22 UTC 
I am able to work around the voltage issue by setting P6 frequency = P7 Frequency. In this case the voltage sits at the pre-defined value of 950mV, but I run into another problem. Memory Pstate is stuck at 0 (167 MHZ) so the overall performance goes down significantly. It seems there's an issue when the card goes into P7 with respect to voltages.
Comment 2 bednarczyk.pawel 2019-04-07 18:28:53 UTC 
Created attachment 143887 [details]
Xorg log
Comment 3 bednarczyk.pawel 2019-04-07 18:29:42 UTC 
Created attachment 143888 [details]
dmesg
Comment 4 bednarczyk.pawel 2019-04-09 19:39:22 UTC 
For whatever reason the below configuration works fine:

OD_SCLK:
0:        852Mhz        800mV
1:        979Mhz        825mV
2:       1106Mhz        850mV
3:       1233Mhz        875mV
4:       1360Mhz        900mV
5:       1485Mhz        925mV
6:       1575Mhz       1000mV
7:       1631Mhz       1050mV
OD_MCLK:
0:        167Mhz        800mV
1:        500Mhz        825mV
2:        800Mhz        865mV
3:       1000Mhz       1000mV

Note, I am never hitting P7. Oddly enough, if I leave everything else constant and change memory state 3 from 3: 1000Mhz 1000mV to 3: 1025Mhz 1000mV, I am hitting the same issue with memory pstate getting stuck @ 0 (167Mhz).
Comment 5 Térence Clastres 2019-07-24 17:08:12 UTC 
Hi, Wouldn't this change merged to linux 5.3-rc1 related to this issue? 
https://github.com/torvalds/linux/commit/7d59c41b5150d0641203f91cfcaa0f9af5999cce ?
Comment 6 bednarczyk.pawel 2019-07-24 17:24:17 UTC 
just tried against the latest kernel git master with AMD's latest AMD GPU tree baked on top of that and my voltage is still shooting up to 1200m when the card raches P7:

OD_SCLK:
0:        852Mhz        800mV
1:        991Mhz        900mV
2:       1084Mhz        910mV
3:       1138Mhz        920mV
4:       1195Mhz        925mV
5:       1250Mhz        935mV
6:       1425Mhz        940mV
7:       1475Mhz        950mV
OD_MCLK:
0:        167Mhz        800mV
1:        500Mhz        850mV
2:        800Mhz        910mV
3:       1025Mhz        950mV
OD_RANGE:
SCLK:     852MHz       2400MHz
MCLK:     167MHz       1500MHz
VDDC:     800mV        1200mV


If I cheat and set P6=P7 as follows:

OD_SCLK:
0:        852Mhz        800mV
1:        991Mhz        900mV
2:       1084Mhz        910mV
3:       1138Mhz        920mV
4:       1195Mhz        925mV
5:       1250Mhz        935mV
6:       1425Mhz        940mV
7:       1425Mhz        950mV
OD_MCLK:
0:        167Mhz        800mV
1:        500Mhz        850mV
2:        800Mhz        910mV
3:       1025Mhz        950mV
OD_RANGE:
SCLK:     852MHz       2400MHz
MCLK:     167MHz       1500MHz
VDDC:     800mV        1200mV

then voltage stays at 950mV as it should. There's a problem somewhere when the card switches to P7.
Comment 7 Stefan Springer 2019-10-23 14:41:21 UTC 

*** This bug has been marked as a duplicate of bug 109887 ***

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.