Bug 110647

Summary:	[CI][RESUME] igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait - skip - Primary plane cannot be disabled separately from output, SKIP
Product:	DRI	Reporter:	Lakshmi <lakshminarayana.vudum>
Component:	DRM/Intel	Assignee:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Status:	RESOLVED DUPLICATE	QA Contact:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity:	normal
Priority:	high	CC:	intel-gfx-bugs
Version:	DRI git
Hardware:	Other
OS:	All
Whiteboard:	ReadyForDev
i915 platform:	ICL	i915 features:	display/Other

Description Lakshmi 2019-05-08 15:40:31 UTC

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6052/re-icl-u/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html

	
Starting subtest: plane-primary-toggle-with-vblank-wait
Test requirement not met in function run_primary_test, file ../tests/kms_atomic_transition.c:69:
Test requirement: !(ret == -EINVAL)
Primary plane cannot be disabled separately from output
Last errno: 22, Invalid argument
Subtest plane-primary-toggle-with-vblank-wait: SKIP (6.288s)


Dmesg-Warnings	
<3> [520.953781] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
<3> [522.771336] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
<3> [523.199836] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
<3> [523.658894] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
<3> [526.112734] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to start channel equalization
<3> [526.283277] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
<3> [526.530617] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
<3> [527.006135] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
<3> [527.627563] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
<3> [528.458230] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
<3> [528.471846] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun

Comment 1 CI Bug Log 2019-05-08 15:41:16 UTC

The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* ICL: igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait - skip - Primary plane cannot be disabled separately from output, SKIP
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6052/re-icl-u/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html

Comment 2 Jani Saarinen 2019-05-08 16:35:20 UTC

Isn't this https://bugs.freedesktop.org/show_bug.cgi?id=107724?

Comment 3 Ville Syrjala 2019-05-08 17:14:11 UTC

This seems to be about

Test requirement: !(ret == -EINVAL)
Primary plane cannot be disabled separately from output
Last errno: 22, Invalid argument

which is caused by

<3> [526.112734] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to start channel equalization
<7> [526.112788] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:196:DP-1] Link Training failed at link rate = 270000, lane count = 1
...
<7> [527.190380] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 1 max rate 162000 max bpp 24 pixel clock 108000KHz
<7> [527.190545] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [527.190623] [drm:intel_atomic_check [i915]] Encoder config failure: -22

Comment 4 Jani Saarinen 2019-05-08 17:17:57 UTC

So this system has chamelium on both HDMI and DP. 
So then we have already exisiting bug https://bugs.freedesktop.org/show_bug.cgi?id=110390 according to cibuglog.

Comment 5 Lakshmi 2019-05-09 06:04:33 UTC

(In reply to Jani Saarinen from comment #4)
> So this system has chamelium on both HDMI and DP. 
> So then we have already exisiting bug
> https://bugs.freedesktop.org/show_bug.cgi?id=110390 according to cibuglog.

CI bug log filter is updated to catch this failure. Closing this as duplicate of Bug 110390.

*** This bug has been marked as a duplicate of bug 110390 ***

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