Bug 110840

Summary:	[CI][SHARDS] igt@gem_ctx_shared@q-independent-vebox - fail - Failed assertion: (int32_t)(handle[HI] - handle[LO]) < 0
Product:	DRI	Reporter:	Martin Peres <martin.peres>
Component:	DRM/Intel	Assignee:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Status:	RESOLVED FIXED	QA Contact:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity:	normal
Priority:	high	CC:	intel-gfx-bugs
Version:	XOrg git
Hardware:	Other
OS:	All
Whiteboard:	ReadyForDev
i915 platform:	ICL	i915 features:	GEM/Other

Description Martin Peres 2019-06-05 07:04:31 UTC

https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5033/shard-iclb5/igt@gem_ctx_shared@q-independent-vebox.html

Starting subtest: Q-independent-vebox
(gem_ctx_shared:1149) CRITICAL: Test assertion failure function independent, file ../tests/i915/gem_ctx_shared.c:592:
(gem_ctx_shared:1149) CRITICAL: Failed assertion: (int32_t)(handle[HI] - handle[LO]) < 0

Comment 1 CI Bug Log 2019-06-05 07:05:02 UTC

The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* ICL: igt@gem_ctx_shared@q-independent-vebox - fail - Failed assertion: (int32_t)(handle[HI] - handle[LO]) &lt; 0
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5033/shard-iclb5/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6183/shard-iclb2/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3098/shard-iclb7/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3099/shard-iclb5/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5034/shard-iclb6/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6184/shard-iclb3/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3097/shard-iclb1/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13165/shard-iclb1/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5035/shard-iclb5/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/TrybotIGT_25/shard-iclb1/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5036/shard-iclb5/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6185/shard-iclb6/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3101/shard-iclb2/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5037/shard-iclb4/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3102/shard-iclb8/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6187/re-icl-u/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6186/shard-iclb2/igt@gem_ctx_shared@q-independent-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3100/shard-iclb8/igt@gem_ctx_shared@q-independent-vebox.html

Comment 2 Tvrtko Ursulin 2019-06-06 08:07:46 UTC

Fix posted at https://patchwork.freedesktop.org/series/61698/

Comment 3 Chris Wilson 2019-06-06 09:21:12 UTC

commit 3e2b20817b68ab41377c1b86207a1e7309fc3779 (upstream/master, origin/master, origin/HEAD)
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Jun 4 17:27:26 2019 +0100

    i915/gem_ctx_shared: Fixup vecs0 mmio base for icl
    
    I told vecs0 to use vecs1 registers...
    
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>

Comment 4 Martin Peres 2019-08-14 13:52:01 UTC

(In reply to Chris Wilson from comment #3)
> commit 3e2b20817b68ab41377c1b86207a1e7309fc3779 (upstream/master,
> origin/master, origin/HEAD)
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Tue Jun 4 17:27:26 2019 +0100
> 
>     i915/gem_ctx_shared: Fixup vecs0 mmio base for icl
>     
>     I told vecs0 to use vecs1 registers...
>     
>     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>     Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>

Well, that might explain the issue :D It was seen 32 times in a row and now nothing for 2 months. Thanks!

Comment 5 CI Bug Log 2019-08-14 13:52:12 UTC

The CI Bug Log issue associated to this bug has been archived.

New failures matching the above filters will not be associated to this bug anymore.

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.