Summary: | crash calling AMDGPU_INFO_READ_MMR_REG with count set to -1 | ||||||||
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Product: | DRI | Reporter: | Trek <trek00> | ||||||
Component: | DRM/AMDgpu | Assignee: | Default DRI bug account <dri-devel> | ||||||
Status: | RESOLVED FIXED | QA Contact: | |||||||
Severity: | normal | ||||||||
Priority: | medium | ||||||||
Version: | DRI git | ||||||||
Hardware: | x86-64 (AMD64) | ||||||||
OS: | Linux (All) | ||||||||
Whiteboard: | |||||||||
i915 platform: | i915 features: | ||||||||
Attachments: |
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Description
Trek
2019-07-31 19:11:59 UTC
Created attachment 145226 [details] [review] possible fix The proposed fix is tested on latest git. I'm unsure if 65536 is a good limit: it could be small as 64, but even if the longest consecutive registers are 48, may be in the future they are increased and no one remember to higher that limit. Anyway it should not be larger than the PCI BAR area for memory mapped registers, that on my KAVERI is 256K, thus 65536 registers. ciao! Created attachment 145229 [details] [review] possible fix v2 Thanks to agd5f_, here the patch with updated limit fixed to 128. Applied. thanks! |
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