Summary: | [CI][RESUME] igt@runner@aborted - fail - Previous test: kms_atomic_transition (plane-toggle-modeset-transition) | ||
---|---|---|---|
Product: | DRI | Reporter: | Martin Peres <martin.peres> |
Component: | DRM/Intel | Assignee: | Ankit <ankit.k.nautiyal> |
Status: | RESOLVED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
Severity: | critical | ||
Priority: | high | CC: | intel-gfx-bugs |
Version: | XOrg git | ||
Hardware: | Other | ||
OS: | All | ||
Whiteboard: | |||
i915 platform: | TGL | i915 features: | display/Other |
Description
Martin Peres
2019-09-11 05:43:27 UTC
The CI Bug Log issue associated to this bug has been updated. ### New filters associated * TGL: igt@kms_atomic_transition@plane-toggle-modeset-transition - fail - cursor D assertion failure (expected on, current off) (No new failures associated) * TGL: igt@runner@aborted - fail - Previous test: kms_atomic_transition (plane-toggle-modeset-transition) (No new failures associated) Assessment: Reproducible : 100% . Can be reproduced always when enabling cursor plane on Pipe D. Currently seen only on TGL platform. Impact : High What does the sub-test do: The test enables pipes sequentially and does a modeset. All planes are then enabled. This is followed by disable of the pipes and planes. The issue: The test itself passes, but there is WARNING in the dmesg, that the cursor plane for Pipe D is expected to be enabled but actually is disabled. This assert is during the atomic_tail commit after the pipe gets enabled and the plane state is verified. The state verification of cursor plane fails, resulting in assert failure. On some initial debug, it is observed, that the issue is reproducing exclusively on PIPE D with cursor plane. After the test is run, the screen is observed to be blank, affecting subsequent tests. Raising the importance to 'Critical'. CUR_CTL register is missing for Pipe D, due to which the plane-state checking fails in intel_atomic_commit_tail, while enabling the cursor plane. Need to add the register offset for PIPE D Cursor. A CI Bug Log filter associated to this bug has been updated: {- TGL: igt@kms_atomic_transition@plane-toggle-modeset-transition - fail - cursor D assertion failure (expected on, current off) -} {+ TGL: igt@kms_atomic_transition@plane-toggle-modeset-transition - fail - cursor D assertion failure (expected on, current off) +} New failures caught by the filter: * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html Patch sent : https://patchwork.freedesktop.org/series/67144/ to add the register CUR_CTL_D. Patch merged in drm-tip. With this the issue should be resolved. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6960/shard-tglb6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html The issue is not observed any more, as patch is already merged. Closing the issue. fix : Added CUR_D_CTL register merged. https://patchwork.freedesktop.org/patch/332601/ Issue not seen anymore:https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6960/shard-tglb6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html So this was on build? https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6951/git-log-oneline.txt As I understand, TGL machines were not in shards for the build CI_DRM_6951, and this issue would be observed on TGL only, since only it has PIPE D enabled. Now I can see the TGL systems are added to shards for running all IGT, and since the patch is merged, this issue is not seen in dmesgs. Thanks a lot Ankit, you did a great job assessing and driving this bug down :) The CI Bug Log issue associated to this bug has been archived. New failures matching the above filters will not be associated to this bug anymore. |
Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.