Bug 111746

Summary:	[CI][DRMTIP]igt@i915_selftest@live_mman - incomplete
Product:	DRI	Reporter:	Lakshmi <lakshminarayana.vudum>
Component:	DRM/Intel	Assignee:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Status:	RESOLVED MOVED	QA Contact:	Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity:	normal
Priority:	medium	CC:	intel-gfx-bugs
Version:	DRI git
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:	TGL	i915 features:	GEM/Other
Bug Depends on:	111880
Bug Blocks:

Description Lakshmi 2019-09-19 10:03:38 UTC

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6916/fi-tgl-u2/igt@i915_selftest@live_mman.html
6> [418.276440] [IGT] i915_selftest: executing
<6> [418.282437] [IGT] i915_selftest: starting subtest live_mman
<5> [418.330769] Setting dangerous option live_selftests - tainting kernel
<6> [418.353130] [drm] i915.alpha_support is deprecated, use i915.force_probe=9a49 instead
<7> [418.353303] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 2048K
<7> [418.353359] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no)
<7> [418.353529] [drm:intel_pch_type [i915]] Found Tiger Lake LP PCH
<7> [418.353573] [drm:intel_power_domains_init [i915]] Allowed DC state mask 0b
<7> [418.354052] [drm:intel_device_info_init_mmio [i915]] vdbox enable: 0000, instances: 0000
<7> [418.354083] [drm:intel_device_info_init_mmio [i915]] vebox enable: 0000, instances: 0000
<7> [418.354373] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M
<7> [418.354417] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
<7> [418.354472] [drm:i915_ggtt_probe_hw [i915]] DSM size = 60M
<6> [418.354487] i915 0000:00:02.0: vgaarb: deactivate vga console
<7> [418.354702] [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED = 0x000000004f2000c7
<7> [418.354744] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 61440K, usable: 59392K
<7> [418.355072] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
<7> [418.355147] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x44962018
<7> [418.355300] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.1.0
<7> [418.355349] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
<7> [418.355396] [drm:intel_opregion_setup [i915]] SWSCI supported
<7> [418.378069] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300583
<7> [418.378117] [drm:intel_opregion_setup [i915]] ASLE supported
<7> [418.378184] [drm:intel_opregion_setup [i915]] ASLE extension supported
<7> [418.378221] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
<7> [418.378260] [drm:i915_driver_probe [i915]] DRAM type: DDR4
<7> [418.378295] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 8 GB, width: X8, ranks: 1, 16Gb DIMMs: no
<7> [418.378323] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no
<7> [418.378347] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 1, 16Gb DIMMs: no
<7> [418.378372] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no
<7> [418.378395] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no
<7> [418.378419] [drm:skl_dram_get_channel_info [i915]] CH1 not populated
<7> [418.378441] [drm:i915_driver_probe [i915]] Memory configuration is symmetric? no
<7> [418.378462] [drm:i915_driver_probe [i915]] DRAM bandwidth: 17066672 kBps, channels: 1
<7> [418.378481] [drm:i915_driver_probe [i915]] DRAM ranks: 1, 16Gb DIMMs: no
<7> [418.378523] [drm:intel_bios_init [i915]] Skipping VBT init due to disabled display.
<7> [418.378827] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
<7> [418.378928] [drm:i915_driver_probe [i915]] rawclk rate: 19200 kHz
<7> [418.378973] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
<7> [418.379049] [drm:intel_combo_phy_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [418.379102] [drm:intel_combo_phy_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [418.379212] [drm:intel_power_well_enable [i915]] enabling power well 1
<7> [418.379308] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 172800 kHz, VCO 345600 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [418.379374] [drm:intel_power_well_enable [i915]] enabling always-on
<7> [418.379418] [drm:intel_power_well_enable [i915]] enabling DC off
<7> [418.379453] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
<7> [418.379555] [drm:intel_combo_phy_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [418.379636] [drm:intel_combo_phy_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [418.379678] [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [418.379733] [drm:intel_power_well_enable [i915]] enabling power well 3
<7> [418.379807] [drm:intel_power_well_enable [i915]] enabling power well 4
<7> [418.379838] [drm:intel_power_well_enable [i915]] enabling power well 5
<7> [418.379952] [drm:intel_csr_ucode_init [i915]] Loading i915/tgl_dmc_ver2_04.bin
<7> [418.381074] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
<7> [418.381247] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
<7> [418.381300] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 59 (59.0 usec)
<7> [418.381329] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 68 (68.0 usec)
<7> [418.381353] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 72 (72.0 usec)
<7> [418.381376] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 103 (103.0 usec)
<7> [418.381400] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 117 (117.0 usec)
<7> [418.381422] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 123 (123.0 usec)
<7> [418.381445] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 139 (139.0 usec)
<7> [418.381493] [drm:intel_modeset_init [i915]] 4 display pipes available.
<7> [418.381544] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 172800 kHz, VCO 345600 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<6> [418.381673] mei_hdcp mei::b638ab7e-94e2-4ea2-a552-d1c54b627f04:01: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
<6> [418.381675] [drm] Finished loading DMC firmware i915/tgl_dmc_ver2_04.bin (v2.4)
<7> [418.381768] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 652800 kHz
<7> [418.381807] [drm:intel_modeset_init [i915]] Max dotclock rate: 1305600 kHz
<7> [418.382245] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 0
<7> [418.382283] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
<7> [418.382318] [drm:intel_modeset_setup_hw_state [i915]] TBT PLL hw state readout: crtc_mask 0x00000000, on 0
<7> [418.382579] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
<7> [418.383113] [drm:i915_gem_contexts_init [i915]] logical context support initialized
<7> [418.385556] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0
<6> [418.386550] [drm] Initialized i915 1.6.0 20190822 for 0000:00:02.0 on minor 0
<7> [418.387177] [drm:intel_power_well_disable [i915]] disabling power well 5
<7> [418.387294] [drm:intel_power_well_disable [i915]] disabling power well 4
<7> [418.387345] [drm:intel_power_well_disable [i915]] disabling power well 3
<7> [418.387427] [drm:intel_power_well_disable [i915]] disabling power well 2
<7> [418.387478] [drm:intel_power_well_disable [i915]] disabling DC off
<7> [418.387528] [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [418.387575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [418.388640] [drm:intel_power_well_disable [i915]] disabling always-on
<7> [418.389750] i915 device info: pciid=0x9a49 rev=0x00 platform=TIGERLAKE (subplatform=0x0) gen=12
<7> [418.389753] i915 device info: is_mobile: no
<7> [418.389755] i915 device info: is_lp: no
<7> [418.389757] i915 device info: require_force_probe: yes
<7> [418.389758] i915 device info: has_64bit_reloc: yes
<7> [418.389760] i915 device info: gpu_reset_clobbers_display: no
<7> [418.389762] i915 device info: has_reset_engine: yes
<7> [418.389764] i915 device info: has_fpga_dbg: yes
<7> [418.389766] i915 device info: has_global_mocs: yes
<7> [418.389768] i915 device info: has_gt_uc: yes
<7> [418.389770] i915 device info: has_l3_dpf: no
<7> [418.389771] i915 device info: has_llc: yes
<7> [418.389773] i915 device info: has_logical_ring_contexts: yes
<7> [418.389775] i915 device info: has_logical_ring_elsq: yes
<7> [418.389777] i915 device info: has_logical_ring_preemption: yes
<7> [418.389779] i915 device info: has_pooled_eu: no
<7> [418.389781] i915 device info: has_rc6: yes
<7> [418.389783] i915 device info: has_rc6p: no
<7> [418.389785] i915 device info: has_rps: yes
<7> [418.389787] i915 device info: has_runtime_pm: yes
<7> [418.389788] i915 device info: has_snoop: no
<7> [418.389790] i915 device info: has_coherent_ggtt: no
<7> [418.389792] i915 device info: unfenced_needs_alignment: no
<7> [418.389794] i915 device info: hws_needs_physical: no
<7> [418.389796] i915 device info: cursor_needs_physical: no
<7> [418.389797] i915 device info: has_csr: yes
<7> [418.389799] i915 device info: has_ddi: yes
<7> [418.389801] i915 device info: has_dp_mst: yes
<7> [418.389803] i915 device info: has_fbc: yes
<7> [418.389805] i915 device info: has_gmch: no
<7> [418.389806] i915 device info: has_hotplug: yes
<7> [418.389808] i915 device info: has_ipc: yes
<7> [418.389810] i915 device info: has_modular_fia: yes
<7> [418.389812] i915 device info: has_overlay: no
<7> [418.389814] i915 device info: has_psr: yes
<7> [418.389816] i915 device info: overlay_needs_physical: no
<7> [418.389817] i915 device info: supports_tv: no
<7> [418.389819] i915 device info: slice total: 1, mask=0001
<7> [418.389821] i915 device info: subslice total: 2
<7> [418.389824] i915 device info: slice0: 2 subslices, mask=000000c0
<7> [418.389826] i915 device info: EU total: 16
<7> [418.389827] i915 device info: EU per subslice: 8
<7> [418.389829] i915 device info: has slice power gating: yes
<7> [418.389831] i915 device info: has subslice power gating: yes
<7> [418.389833] i915 device info: has EU power gating: yes
<7> [418.389835] i915 device info: CS timestamp frequency: 19200 kHz
<6> [418.389837] [drm] DRM_I915_DEBUG enabled
<6> [418.389838] [drm] DRM_I915_DEBUG_GEM enabled
<6> [418.389840] [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
<6> [418.389844] i915: Performing live selftests with st_random_seed=0x9d8151b1 st_timeout=1000
<6> [418.389846] i915: Running mman
<6> [418.389861] i915: Running i915_gem_mman_live_selftests/igt_partial_tiling
<7> [419.419128] check_partial_mappings: timed out after tiling=0 stride=0
<7> [420.420124] check_partial_mappings: timed out after tiling=1 stride=262144
<7> [421.421402] check_partial_mappings: timed out after tiling=2 stride=262144
<6> [421.421477] i915: Running i915_gem_mman_live_selftests/igt_smoke_tiling

Comment 1 CI Bug Log 2019-09-19 10:04:55 UTC

The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@i915_selftest@live_mman - incomplete 
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6916/fi-tgl-u2/igt@i915_selftest@live_mman.html

Comment 2 Francesco Balestrieri 2019-10-02 05:22:57 UTC

Seen once (but again, does it fall in the same bucket as the rest of the incompletes?)

Comment 3 prathap.kumar.valsan 2019-10-19 16:23:24 UTC

Test is passing on local solo runs. Must fall in to the same bucket as other incompleteness.

Comment 4 EdwardsS 2019-10-21 19:27:24 UTC

Fantastic that you have resolved these bugs. I am surprised to visit https://www.toptenwritingservices.com/time4writing-com-review/ that how you do this in such a short time and above this you any solution never failed. You really exert in your field and come with appropriate solutions.

Comment 5 Martin Peres 2019-11-29 19:32:29 UTC

-- GitLab Migration Automatic Message --

This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity.

You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/intel/issues/434.

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